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1. awesome-zewei-Agile-IC-PythonHDL awesome-zewei-Agile-IC-PythonHDL Public

   List of awesome open source SoC Projects, generators, and Python HDL

2. awesome-zewei-hdl awesome-zewei-hdl Public

   Forked from drom/awesome-hdl

   HDL，Python HDL，and DSL

3. caravel caravel Public

   Forked from chipfoundry/caravel

   Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.

   Verilog

4. chipgen chipgen Public

   Forked from vowstar/qsoc

   QSoC - Quick System on Chip Studio

   C++

5. caravel_user_project caravel_user_project Public template

   Forked from efabless/caravel_user_project

   https://caravel-user-project.readthedocs.io

   Verilog

6. pulp_soc_full pulp_soc_full Public

   Forked from pulp-platform/carfield

   A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

   Tcl