From 56df802b6a648fbbfc7567c1517aee94eb712957 Mon Sep 17 00:00:00 2001 From: Gao-xt Date: Thu, 1 Aug 2024 18:42:02 +0800 Subject: [PATCH] Cru: update system register and support clock select for k1matrix 64c --- arch/riscv/include/asm/mach-k1matrix/cru.h | 300 +++++++++++++++++++++ arch/riscv/include/asm/mach-k1matrix/reg.h | 199 ++++++++++++++ arch/riscv/mach-k1matrix/cru_clk_fake.c | 197 +++++++++++++- 3 files changed, 688 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/mach-k1matrix/cru.h b/arch/riscv/include/asm/mach-k1matrix/cru.h index c36815a8..72340c81 100644 --- a/arch/riscv/include/asm/mach-k1matrix/cru.h +++ b/arch/riscv/include/asm/mach-k1matrix/cru.h @@ -315,6 +315,306 @@ #define CRU_PERI_TBU_SW_RESET CRU_REG(0x29F0) #define CRU_PERI_TBU_ADB_SW_RESET CRU_REG(0x29F4) +#ifdef CONFIG_K1MATRIX_64C + +#define CRU_COMPLL_CTL CRU_REG(0x000) +#define CRU_COMPLL_CFG1 CRU_REG(0x004) +#define CRU_COMPLL_CFG2 CRU_REG(0x008) +#define CRU_MESH_PLL_CTL CRU_REG(0x00C) +#define CRU_MESH_PLL_CFG1 CRU_REG(0x010) +#define CRU_MESH_PLL_CFG2 CRU_REG(0x014) +#define CRU_PERI_PLL_CTL CRU_REG(0x018) +#define CRU_PERI_PLL_CFG1 CRU_REG(0x01C) +#define CRU_PERI_PLL_CFG2 CRU_REG(0x020) +#define CRU_DDR0_PLL_CTL CRU_REG(0x024) +#define CRU_DDR0_PLL_CFG1 CRU_REG(0x028) +#define CRU_DDR0_PLL_CFG2 CRU_REG(0x02C) +#define CRU_DDR1_PLL_CTL CRU_REG(0x030) +#define CRU_DDR1_PLL_CFG1 CRU_REG(0x034) +#define CRU_DDR1_PLL_CFG2 CRU_REG(0x038) +#define CRU_CPU0_PLL_CTL CRU_REG(0x03C) +#define CRU_CPU0_PLL_CFG1 CRU_REG(0x040) +#define CRU_CPU0_PLL_CFG2 CRU_REG(0x044) +#define CRU_CPU1_PLL_CTL CRU_REG(0x048) +#define CRU_CPU1_PLL_CFG1 CRU_REG(0x04C) +#define CRU_CPU1_PLL_CFG2 CRU_REG(0x050) +#define CRU_CPU_CLK_CTL CRU_REG(0x100) +#define CRU_CPU_NIC_CLK_CTL CRU_REG(0x104) +#define CRU_CPU_HAP_CLK_CTL CRU_REG(0x108) + +#define CRU_LTOP_CFG_CLK_CTL CRU_REG(0x110) +#define CRU_LTOP_PCIE_CFG_CLK_CTL CRU_REG(0x120) +#define CRU_LTOP_PCIE_AUX_CLK_CTL CRU_REG(0x124) +#define CRU_LTOP_PCIE_TFR_CLK_CTL CRU_REG(0x128) +#define CRU_LTOP_PHY_FW_CLK_CTL CRU_REG(0x12C) +#define CRU_RTOP_CFG_CLK_CTL CRU_REG(0x130) +#define CRU_RTOP_PCIE_CFG_CLK_CTL CRU_REG(0x134) +#define CRU_RTOP_PCIE_AUX_CLK_CTL CRU_REG(0x138) +#define CRU_RTOP_PCIE_TFR_CLK_CTL CRU_REG(0x13C) +#define CRU_RTOP_PHY_FW_CLK_CTL CRU_REG(0x140) +#define CRU_BOT_CFG_CLK_CTL CRU_REG(0x144) +#define CRU_BOT_PCIE_CFG_CLK_CTL CRU_REG(0x148) +#define CRU_BOT_PCIE_AUX_CLK_CTL CRU_REG(0x14C) +#define CRU_BOT_PCIE_TFR_CLK_CTL CRU_REG(0x150) +#define CRU_BOT_PHY_FW_CLK_CTL CRU_REG(0x154) +#define CRU_TPERI_SUB_SCLK_CTL CRU_REG(0x158) +#define CRU_TPERI_SUB_MCLK_CTL CRU_REG(0x15C) +#define CRU_MESH_SUB_CLK_CTL CRU_REG(0x160) +#define CRU_DDR_CFG_CLK_CTL CRU_REG(0x170) +#define CRU_DDR_SUB_CLK_CTL CRU_REG(0x174) +#define CRU_DDRAB_SUB_CLK_CTL CRU_REG(0x178) +#define CRU_DDRCD_SUB_CLK_CTL CRU_REG(0x17C) +#define CRU_DDREF_SUB_CLK_CTL CRU_REG(0x180) +#define CRU_DDRGH_SUB_CLK_CTL CRU_REG(0x184) +#define CRU_TRMU_IOPMP_CFG_CLK_CTL CRU_REG(0x188) +#define CRU_HNI_PERI_CFG_CLK_CTL CRU_REG(0x190) +#define CRU_CLUSTER0_CLK_CTL CRU_REG(0x200) +#define CRU_CLUSTER1_CLK_CTL CRU_REG(0x204) +#define CRU_CLUSTER2_CLK_CTL CRU_REG(0x208) +#define CRU_CLUSTER3_CLK_CTL CRU_REG(0x20C) +#define CRU_CLUSTER4_CLK_CTL CRU_REG(0x210) +#define CRU_CLUSTER5_CLK_CTL CRU_REG(0x214) +#define CRU_CLUSTER6_CLK_CTL CRU_REG(0x218) +#define CRU_CLUSTER7_CLK_CTL CRU_REG(0x21C) +#define CRU_CLUSTER8_CLK_CTL CRU_REG(0x220) +#define CRU_CLUSTER9_CLK_CTL CRU_REG(0x224) +#define CRU_CLUSTER10_CLK_CTL CRU_REG(0x228) +#define CRU_CLUSTER11_CLK_CTL CRU_REG(0x22C) +#define CRU_CLUSTER12_CLK_CTL CRU_REG(0x230) +#define CRU_CLUSTER13_CLK_CTL CRU_REG(0x234) +#define CRU_CLUSTER14_CLK_CTL CRU_REG(0x238) +#define CRU_CLUSTER15_CLK_CTL CRU_REG(0x23C) +#define CRU_SYS_APB_CLK_CTL CRU_REG(0x240) +#define CRU_APIC_CLK_CTL CRU_REG(0x244) +#define CRU_IMSIC_CLK_CTL CRU_REG(0x248) +#define CRU_MESH_CXS40_CLK_CTL CRU_REG(0x24C) +#define CRU_MESH_CXS360_CLK_CTL CRU_REG(0x250) +#define CRU_RMU_AXI_CLK_DIV CRU_REG(0x300) +#define CRU_RMU_AHB_CLK_DIV CRU_REG(0x304) +#define CRU_RMU_APB_CLK_DIV CRU_REG(0x308) +#define CRU_RMU_LPC_CLK_DIV CRU_REG(0x30C) +#define CRU_RMU_CLK_SEL CRU_REG(0x310) +#define CRU_RMU_PVTC_CLK_SEL CRU_REG(0x314) +#define CRU_RMU_SRAM_CLK_EN CRU_REG(0x320) +#define CRU_RMU_QSPI_CLK_EN CRU_REG(0x324) +#define CRU_RMU_eFuse_NS_CLK_EN CRU_REG(0x328) +#define CRU_RMU_LPC_IO_CLK_CTL CRU_REG(0x32C) +#define CRU_RMU_LPC_LCLK_CTL CRU_REG(0x330) +#define CRU_RMU_LPC_CLK_EN CRU_REG(0x334) +#define CRU_RMU_eSPI_CLK_EN CRU_REG(0x338) +#define CRU_RMU_UART0_CLK_EN CRU_REG(0x33C) +#define CRU_RMU_UART1_CLK_EN CRU_REG(0x340) +#define CRU_RMU_UART2_CLK_EN CRU_REG(0x344) +#define CRU_RMU_Timer_S_CLK_EN CRU_REG(0x348) +#define CRU_RMU_Spinlock_CLK_EN CRU_REG(0x34C) +#define CRU_RMU_Mailbox_S_CLK_EN CRU_REG(0x350) +#define CRU_RMU_Mailbox_NS_CLK_EN CRU_REG(0x354) +#define CRU_RMU_SRAM_MAILBOX_S_CLK_EN CRU_REG(0x358) +#define CRU_RMU_SRAM_MAILBOX_NS_CLK_EN CRU_REG(0x35C) + + +#define CRU_RMU_PIC_CLK_EN CRU_REG(0x358) +#define CRU_RMU_HAP_CLK_EN CRU_REG(0x35C) +#define CRU_PCIE0_BUS_CLK_CTL CRU_REG(0x400) +#define CRU_PCIE1_BUS_CLK_CTL CRU_REG(0x404) +#define CRU_PCIE2_BUS_CLK_CTL CRU_REG(0x408) +#define CRU_PCIE3_BUS_CLK_CTL CRU_REG(0x40C) +#define CRU_PCIE0_AXI_CLK_CTL CRU_REG(0x410) +#define CRU_PCIE1_AXI_CLK_CTL CRU_REG(0x414) +#define CRU_PCIE2_AXI_CLK_CTL CRU_REG(0x418) +#define CRU_PCIE3_AXI_CLK_CTL CRU_REG(0x41C) +#define CRU_MPHY0_CLK_CTL CRU_REG(0x420) +#define CRU_MPHY1_CLK_CTL CRU_REG(0x424) +#define CRU_MPHY2_CLK_CTL CRU_REG(0x428) +#define CRU_TCU0_CLK_CTL CRU_REG(0x430) +#define CRU_TCU1_CLK_CTL CRU_REG(0x434) +#define CRU_PCIE4_BUS_CLK_CTL CRU_REG(0x600) +#define CRU_PCIE5_BUS_CLK_CTL CRU_REG(0x604) +#define CRU_PCIE6_BUS_CLK_CTL CRU_REG(0x608) +#define CRU_PCIE7_BUS_CLK_CTL CRU_REG(0x60C) +#define CRU_PCIE8_BUS_CLK_CTL CRU_REG(0x610) +#define CRU_PCIE9_BUS_CLK_CTL CRU_REG(0x614) +#define CRU_PCIE4_AUX_CLK_CTL CRU_REG(0x618) +#define CRU_PCIE5_AUX_CLK_CTL CRU_REG(0x61C) +#define CRU_PCIE6_AUX_CLK_CTL CRU_REG(0x620) +#define CRU_PCIE7_AUX_CLK_CTL CRU_REG(0x624) +#define CRU_PCIE8_AUX_CLK_CTL CRU_REG(0x628) +#define CRU_PCIE9_AUX_CLK_CTL CRU_REG(0x62C) +#define CRU_PCIE_TCU2_CLK_CTL CRU_REG(0x630) +#define CRU_PCIE_SUBLINK_CLK_CTL CRU_REG(0x634) +#define CRU_PCIE_SYS_CLK_CTL CRU_REG(0x638) +#define CRU_COMBPHY3_CLK_CTL CRU_REG(0x63C) +#define CRU_COMBPHY4_CLK_CTL CRU_REG(0x640) +#define CRU_COMBPHY5_CLK_CTL CRU_REG(0x644) +#define CRU_PERI_AHB_CLK_CTL CRU_REG(0x810) +#define CRU_PERI_SPI0_CLK_CTL CRU_REG(0x820) +#define CRU_PERI_SPI1_CLK_CTL CRU_REG(0x824) +#define CRU_PERI_SPI2_CLK_CTL CRU_REG(0x828) +#define CRU_PERI_SPI3_CLK_CTL CRU_REG(0x82C) +#define CRU_PERI_SMBUS0_CLK_CTL CRU_REG(0x840) +#define CRU_PERI_SMBUS1_CLK_CTL CRU_REG(0x844) +#define CRU_PERI_I3C0_CLK_CTL CRU_REG(0x860) +#define CRU_PERI_I3C1_CLK_CTL CRU_REG(0x864) +#define CRU_PERI_I2C0_CLK_CTL CRU_REG(0x880) +#define CRU_PERI_I2C1_CLK_CTL CRU_REG(0x884) +#define CRU_PERI_I2C2_CLK_CTL CRU_REG(0x888) +#define CRU_PERI_I2C3_CLK_CTL CRU_REG(0x88C) +#define CRU_PERI_I2C4_CLK_CTL CRU_REG(0x890) +#define CRU_PERI_I2C5_CLK_CTL CRU_REG(0x894) +#define CRU_PERI_UART0_CLK_CTL CRU_REG(0x8A0) +#define CRU_PERI_UART1_CLK_CTL CRU_REG(0x8A4) +#define CRU_PERI_UART2_CLK_CTL CRU_REG(0x8A8) +#define CRU_PERI_UART3_CLK_CTL CRU_REG(0x8AC) +#define CRU_PERI_GPIO0_CLK_CTL CRU_REG(0x8C0) +#define CRU_PERI_GPIO1_CLK_CTL CRU_REG(0x8C4) +#define CRU_PERI_GPIO2_CLK_CTL CRU_REG(0x8C8) +#define CRU_PERI_GPIO3_CLK_CTL CRU_REG(0x8CC) +#define CRU_PERI_GPIO4_CLK_CTL CRU_REG(0x8D0) +#define CRU_PERI_WDT0_CLK_CTL CRU_REG(0x8E0) +#define CRU_PERI_WDT1_CLK_CTL CRU_REG(0x8E4) +#define CRU_PERI_WDT2_CLK_CTL CRU_REG(0x8E8) +#define CRU_PERI_WDT3_CLK_CTL CRU_REG(0x8EC) +#define CRU_PERI_WDT4_CLK_CTL CRU_REG(0x8F0) +#define CRU_PERI_WDT5_CLK_CTL CRU_REG(0x8F4) +#define CRU_PERI_WDT6_CLK_CTL CRU_REG(0x8F8) +#define CRU_PERI_WDT7_CLK_CTL CRU_REG(0x8FC) +#define CRU_PERI_TIMER0_CLK_CTL CRU_REG(0x900) +#define CRU_PERI_TIMER1_CLK_CTL CRU_REG(0x904) +#define CRU_PERI_TIMER2_CLK_CTL CRU_REG(0x908) +#define CRU_PERI_TIMER3_CLK_CTL CRU_REG(0x90C) +#define CRU_PERI_TIMER4_CLK_CTL CRU_REG(0x910) +#define CRU_PERI_TIMER5_CLK_CTL CRU_REG(0x914) +#define CRU_PERI_TIMER6_CLK_CTL CRU_REG(0x918) +#define CRU_PERI_TIMER7_CLK_CTL CRU_REG(0x91C) +#define CRU_PERI_TIMER8_CLK_CTL CRU_REG(0x920) +#define CRU_PERI_TIMER9_CLK_CTL CRU_REG(0x924) +#define CRU_PERI_TIMER10_CLK_CTL CRU_REG(0x928) +#define CRU_PERI_TIMER11_CLK_CTL CRU_REG(0x92C) +#define CRU_PERI_TIMER12_CLK_CTL CRU_REG(0x930) +#define CRU_PERI_TIMER13_CLK_CTL CRU_REG(0x934) +#define CRU_PERI_TIMER14_CLK_CTL CRU_REG(0x938) +#define CRU_PERI_TIMER15_CLK_CTL CRU_REG(0x93C) +#define CRU_PERI_TIMER16_CLK_CTL CRU_REG(0x940) +#define CRU_PERI_TIMER17_CLK_CTL CRU_REG(0x944) +#define CRU_PERI_TIMER18_CLK_CTL CRU_REG(0x948) +#define CRU_PERI_TIMER19_CLK_CTL CRU_REG(0x94C) +#define CRU_PERI_TIMER20_CLK_CTL CRU_REG(0x950) +#define CRU_PERI_TIMER21_CLK_CTL CRU_REG(0x954) +#define CRU_PERI_TIMER22_CLK_CTL CRU_REG(0x958) +#define CRU_PERI_TIMER23_CLK_CTL CRU_REG(0x95C) +#define CRU_PERI_TIMER24_CLK_CTL CRU_REG(0x960) +#define CRU_PERI_TIMER25_CLK_CTL CRU_REG(0x964) +#define CRU_PERI_TIMER26_CLK_CTL CRU_REG(0x968) +#define CRU_PERI_TIMER27_CLK_CTL CRU_REG(0x96C) +#define CRU_PERI_TIMER28_CLK_CTL CRU_REG(0x970) +#define CRU_PERI_TIMER29_CLK_CTL CRU_REG(0x974) +#define CRU_PERI_TIMER30_CLK_CTL CRU_REG(0x978) +#define CRU_PERI_TIMER31_CLK_CTL CRU_REG(0x97C) +#define CRU_PERI_DMAC_CLK_CTL CRU_REG(0x9C0) +#define CRU_PERI_GMAC_CLK_CTL CRU_REG(0x9E0) +#define CRU_CPU_SUB_SW_RESET CRU_REG(0x2100) +#define CRU_PCIE_TOP_SW_RESET CRU_REG(0x2104) +#define CRU_PCIE_BOT_SW_RESET CRU_REG(0x2108) +#define CRU_PERI_SUB_SW_RESET CRU_REG(0x210C) +#define CRU_MESH_SUB_SW_RESET CRU_REG(0x2110) +#define CRU_DDR_SUB_SW_RESET CRU_REG(0x2114) +#define CRU_CLUSTER0_SW_RESET CRU_REG(0x2200) +#define CRU_CLUSTER0_COREX_SW_RESET CRU_REG(0x2204) +#define CRU_CLUSTER1_SW_RESET CRU_REG(0x2208) +#define CRU_CLUSTER1_COREX_SW_RESET CRU_REG(0x220C) +#define CRU_CLUSTER2_SW_RESET CRU_REG(0x2210) +#define CRU_CLUSTER2_COREX_SW_RESET CRU_REG(0x2214) +#define CRU_CLUSTER3_SW_RESET CRU_REG(0x2218) +#define CRU_CLUSTER3_COREX_SW_RESET CRU_REG(0x221C) +#define CRU_CLUSTER4_SW_RESET CRU_REG(0x2220) +#define CRU_CLUSTER4_COREX_SW_RESET CRU_REG(0x2224) +#define CRU_CLUSTER5_SW_RESET CRU_REG(0x2228) +#define CRU_CLUSTER5_COREX_SW_RESET CRU_REG(0x222C) +#define CRU_CLUSTER6_SW_RESET CRU_REG(0x2230) +#define CRU_CLUSTER6_COREX_SW_RESET CRU_REG(0x2234) +#define CRU_CLUSTER7_SW_RESET CRU_REG(0x2238) +#define CRU_CLUSTER7_COREX_SW_RESET CRU_REG(0x223C) + +#define CRU_CPU_RAS_SW_RESET CRU_REG(0x2240) +#define CRU_CPU_SW_RESET CRU_REG(0X2250) +#define CRU_RMU_SRAM_SW_RSTN CRU_REG(0x2320) +#define CRU_RMU_QSPI_SW_RSTN CRU_REG(0x2324) +#define CRU_RMU_eFuse_NS_SW_RSTN CRU_REG(0x2328) +#define CRU_RMU_LPC_SW_RSTN CRU_REG(0x2334) +#define CRU_RMU_eSPI_SW_RSTN CRU_REG(0x2338) +#define CRU_RMU_PVTC_SW_RSTN CRU_REG(0x233C) +#define CRU_RMU_UART0_SW_RSTN CRU_REG(0x2340) +#define CRU_RMU_UART1_SW_RSTN CRU_REG(0x2344) +#define CRU_RMU_Timer_S_SW_RSTN CRU_REG(0x2348) +#define CRU_RMU_Spinlock_SW_RSTN CRU_REG(0x234C) +#define CRU_RMU_Mailbox_S_SW_RSTN CRU_REG(0x2350) +#define CRU_RMU_Mailbox_NS_SW_RSTN CRU_REG(0x2354) +#define CRU_RMU_PIC_SW_RSTN CRU_REG(0x2358) +#define CRU_PCIE0_SW_RESET CRU_REG(0x2400) +#define CRU_PCIE1_SW_RESET CRU_REG(0x2404) +#define CRU_PCIE2_SW_RESET CRU_REG(0x2408) +#define CRU_PCIE3_SW_RESET CRU_REG(0x240C) +#define CRU_MPHY0_SW_RESET CRU_REG(0x2420) +#define CRU_MPHY1_SW_RESET CRU_REG(0x2424) +#define CRU_MPHY2_SW_RESET CRU_REG(0x2428) +#define CRU_TCU0_SW_RESET CRU_REG(0x2430) +#define CRU_TCU1_SW_RESET CRU_REG(0x2434) +#define CRU_PCIE4_SW_RESET CRU_REG(0x2600) +#define CRU_PCIE5_SW_RESET CRU_REG(0x2604) +#define CRU_PCIE6_SW_RESET CRU_REG(0x2608) +#define CRU_PCIE7_SW_RESET CRU_REG(0x260C) +#define CRU_PCIE8_SW_RESET CRU_REG(0x2610) +#define CRU_PCIE9_SW_RESET CRU_REG(0x2614) +#define CRU_PCIE_TCU2_SW_RESET CRU_REG(0x2634) +#define CRU_PCIE_SUBLINK_SW_RESET CRU_REG(0x2638) +#define CRU_PCIE_SYS_SW_RESET CRU_REG(0x263C) +#define CRU_COMBPHY3_APB_SW_RESET CRU_REG(0x2640) +#define CRU_COMBPHY4_APB_SW_RESET CRU_REG(0x2644) +#define CRU_COMBPHY5_APB_SW_RESET CRU_REG(0x2648) +#define CRU_COMBPHY3_PHYRESETN_SW_RESET CRU_REG(0x264C) +#define CRU_COMBPHY4_PHYRESETN_SW_RESET CRU_REG(0x2650) +#define CRU_COMBPHY5_PHYRESETN_SW_RESET CRU_REG(0x2654) +#define CRU_PERI_SPI0_SW_RESET CRU_REG(0x2820) +#define CRU_PERI_SPI1_SW_RESET CRU_REG(0x2824) +#define CRU_PERI_SPI2_SW_RESET CRU_REG(0x2828) +#define CRU_PERI_SPI3_SW_RESET CRU_REG(0x282C) +#define CRU_PERI_SMBUS0_SW_RESET CRU_REG(0x2840) +#define CRU_PERI_SMBUS1_SW_RESET CRU_REG(0x2844) +#define CRU_PERI_I3C0_SW_RESET CRU_REG(0x2860) +#define CRU_PERI_I3C1_SW_RESET CRU_REG(0x2864) +#define CRU_PERI_I2C0_SW_RESET CRU_REG(0x2880) +#define CRU_PERI_I2C1_SW_RESET CRU_REG(0x2884) +#define CRU_PERI_I2C2_SW_RESET CRU_REG(0x2888) +#define CRU_PERI_I2C3_SW_RESET CRU_REG(0x288C) +#define CRU_PERI_I2C4_SW_RESET CRU_REG(0x2890) +#define CRU_PERI_I2C5_SW_RESET CRU_REG(0x2894) +#define CRU_PERI_UART0_SW_RESET CRU_REG(0x28A0) +#define CRU_PERI_UART1_SW_RESET CRU_REG(0x28A4) +#define CRU_PERI_UART2_SW_RESET CRU_REG(0x28A8) +#define CRU_PERI_UART3_SW_RESET CRU_REG(0x28AC) +#define CRU_PERI_GPIO0_SW_RESET CRU_REG(0x28C0) +#define CRU_PERI_GPIO1_SW_RESET CRU_REG(0x28C4) +#define CRU_PERI_GPIO2_SW_RESET CRU_REG(0x28C8) +#define CRU_PERI_GPIO3_SW_RESET CRU_REG(0x28CC) +#define CRU_PERI_GPIO4_SW_RESET CRU_REG(0x28D0) +#define CRU_PERI_WDT0_SW_RESET CRU_REG(0x28E0) +#define CRU_PERI_WDT1_SW_RESET CRU_REG(0x28E4) +#define CRU_PERI_WDT2_SW_RESET CRU_REG(0x28E8) +#define CRU_PERI_WDT3_SW_RESET CRU_REG(0x28EC) +#define CRU_PERI_WDT4_SW_RESET CRU_REG(0x28F0) +#define CRU_PERI_WDT5_SW_RESET CRU_REG(0x28F4) +#define CRU_PERI_WDT6_SW_RESET CRU_REG(0x28F8) +#define CRU_PERI_WDT7_SW_RESET CRU_REG(0x28FC) +#define CRU_PERI_GTIMER0_SW_RESET CRU_REG(0x2900) +#define CRU_PERI_GTIMER1_SW_RESET CRU_REG(0x2920) +#define CRU_PERI_GTIMER2_SW_RESET CRU_REG(0x2940) +#define CRU_PERI_GTIMER3_SW_RESET CRU_REG(0x2960) +#define CRU_PERI_DMAC_SW_RESET CRU_REG(0x29C0) +#define CRU_PERI_GMAC_SW_RESET CRU_REG(0x29E0) +#define CRU_PERI_TBU_SW_RESET CRU_REG(0x29F0) +#define CRU_PERI_TBU_ADB_SW_RESET CRU_REG(0x29F4) +#endif + /* XXX_CLK_CTL */ #define CRU_CLKENABLE(n) _BV(n) #define CRU_CLKDIV0_OFFSET 4 diff --git a/arch/riscv/include/asm/mach-k1matrix/reg.h b/arch/riscv/include/asm/mach-k1matrix/reg.h index a801d7cc..6f4a4862 100644 --- a/arch/riscv/include/asm/mach-k1matrix/reg.h +++ b/arch/riscv/include/asm/mach-k1matrix/reg.h @@ -202,6 +202,205 @@ extern unsigned long k1matrix_die_base; #define __IOMMU_CRTL2_CFG_BASE ULL(0x04F80000000) #define __IOMMU_CRTL3_CFG_BASE ULL(0x04F80200000) +#ifdef CONFIG_K1MATRIX_64C + +#define DIE0_BASE ULL(0x00000000000) +#define DIE1_BASE ULL(0x05000000000) +#define __DIE_BASE(die) ((uint64_t)(die) << 39) +#define DIE_BASE k1matrix_die_base + +#define __DDR_BASE ULL(0x00000000000) +#define __DRAM_SIZE ULL(0x02000000000) + +#define __RMU_QSPI_XIP_BASE ULL(0x00400000000) +#define __RMU_BROM_BASE ULL(0x00410000000) +#define __RMU_RAM_BASE ULL(0x00410100000) +#define __RMU_MAILBOX_EHSM_BASE ULL(0x00420000000) +#define __RMU_EFUSE_S_BASE ULL(0x00420010000) +#define __RMU_QSPI_0_BASE ULL(0x00420420000) +#define __RMU_WDT_BASE ULL(0x00420710000) +#define __RMU_TIMER0_3_BASE ULL(0x00420720000) +#define __RMU_REG_BASE ULL(0x00420730000) +#define __RMU_PLIC_BASE ULL(0x00528000000) +#define __RMU_CLINT_BASE ULL(0x00530000000) +#define __RMU_SRAM_MAILBOX_S_BASE ULL(0x00538000000) +#define __RMU_LS_DMA_BASE ULL(0x00538010000) +#define __RMU_MAILBOX_EHSM_ALIAS_BASE ULL(0x00539000000) +#define __RMU_EFUSE_S_ALIAS_BASE ULL(0x00539000000) +#define __RMU_QSPI_0_ALIAS_BASE ULL(0x00539020000) +#define __RMU_REG_ALIAS_BASE ULL(0x00539030000) +#define __RMU_R_SPI_M_0_BASE ULL(0x0053A000000) +#define __RMU_R_SPI_S_0_BASE ULL(0x0053A010000) +#define __RMU_R_SMBUS_0_BASE ULL(0x0053A100000) +#define __RMU_R_SMBUS_1_BASE ULL(0x0053A110000) +#define __RMU_R_SMBUS_2_BASE ULL(0x0053A120000) +#define __RMU_R_SMBUS_3_BASE ULL(0x0053A130000) +#define __RMU_R_SMBUS_4_BASE ULL(0x0053A140000) +#define __RMU_R_I2C_0_BASE ULL(0x0053A200000) +#define __RMU_R_I2C_1_BASE ULL(0x0053A210000) +#define __RMU_R_I2C_2_BASE ULL(0x0053A220000) +#define __RMU_R_GPIOA_BASE ULL(0x0053A300000) +#define __RMU_R_GPIOB_BASE ULL(0x0053A310000) +#define __RMU_R_GPIOC_BASE ULL(0x0053A320000) +#define __RMU_UART_S_0_BASE ULL(0x0053C000000) +#define __RMU_UART_S_1_BASE ULL(0x0053C010000) +#define __RMU_UART_S_2_BASE ULL(0x0053C020000) +#define __RMU_MAILBOX_S_BASE ULL(0x0053C030000) +#define __RMU_TIMER_S_BASE ULL(0x0053C050000) +#define __RMU_STM_BASE ULL(0x0053C060000) +#define __RMU_SYS_REG_BASE ULL(0x0053C070000) +#define __RMU_SYS_CRU_BASE ULL(0x0053C080000) +#define __RMU_PVT_CRTL_0_BASE ULL(0x0053C100000) +#define __RMU_PVT_CRTL_1_BASE ULL(0x0053C110000) +#define __RMU_PVT_CRTL_2_BASE ULL(0x0053C120000) +#define __RMU_ACTIVE_SHIELD_BASE ULL(0x0053C130000) +#define __RMU_LCP_CFG_BASE ULL(0x0053E000000) +#define __RMU_ESPI_CFG_BASE ULL(0x0053E010000) +#define __RMU_SPINLOCK_BASE ULL(0x0053E200000) +#define __RMU_MAILBOX_NS_BASE ULL(0x0053E210000) +#define __RMU_EFUSE_NS_BASE ULL(0x0053E230000) +#define __RMU_SRAM_MAILBOX_BASE ULL(0x0053F000000) +#define __RMU_LPC_IO_BASE ULL(0x0053FE00000) +#define __RMU_ESPI_IO_BASE ULL(0x0053FE10000) +#define __RMU_IOPMP_DEFAULT_SLV_NID0_BASE ULL(0x0053FFF0000) + +#define __SPI0_M_0_BASE ULL(0x00552000000) +#define __SPI1_M_1_BASE ULL(0x00552010000) +#define __I3C_0_BASE ULL(0x00552180000) +#define __I3C_1_BASE ULL(0x00552190000) +#define __I3C_2_BASE ULL(0x005521A0000) +#define __I3C_3_BASE ULL(0x005521B0000) +#define __I2C_0_BASE ULL(0x00552200000) +#define __I2C_1_BASE ULL(0x00552210000) +#define __I2C_2_BASE ULL(0x00552220000) +#define __I2C_3_BASE ULL(0x00552230000) +#define __I2C_4_BASE ULL(0x00552240000) +#define __I2C_5_BASE ULL(0x00552250000) +#define __UART_0_BASE ULL(0x00552300000) +#define __UART_1_BASE ULL(0x00552310000) +#define __A_GPIOA_BASE ULL(0x00552400000) +#define __A_GPIOB_BASE ULL(0x00552410000) +#define __A_GPIOC_BASE ULL(0x00552420000) +#define __WDT_BASE ULL(0x00552500000) +#define __TIMER_NS_BASE ULL(0x00552700000) +#define __HS_DMA_BASE ULL(0x00554C00000) +#define __GMAC_BASE ULL(0x00554C20000) +#define __SRAM_GMAC_BASE ULL(0x00554C40000) +#define __S_ACLINT_HARTX_SSIP_BASE ULL(0x00558400000) +#define __S_APLIC_S_DOMAIN_CFG_BASE ULL(0x00558500000) +#define __S_MODE_MSI_BASE ULL(0x00558600000) +#define __M_ACLINT_HARTX_MSIP_BASE ULL(0x0055A000000) +#define __M_ACLINT_HARTX_MTIP_BASE ULL(0x0055A004000) +#define __M_APLIC_M_DOMAIN_CFG_BASE ULL(0x0055A200000) +#define __M_MODE_MSI_BASE ULL(0x0055A300000) + +#define __RMU_IOPMP_S0_NID4 ULL(0x0055C000000) +#define __PERI_IOPMP_S1_NID4 ULL(0x0055C010000) +#define __PCIE0_IOPMP_S0_NID68 ULL(0x0055C020000) +#define __PCIE1_IOPMP_S1_NID68 ULL(0x0055C030000) +#define __PCIE2_IOPMP_S2_NID68 ULL(0x0055C040000) +#define __PCIE3_IOPMP_S0_NID132 ULL(0x0055C050000) +#define __PCIE4_IOPMP_S1_NID132 ULL(0x0055C060000) +#define __PCIE5_IOPMP_S0_NID196 ULL(0x0055C070000) +#define __IOMMU_CTRL0_IOPMP_S1_NID196 ULL(0x0055C080000) +#define __IOMMU_CTRL1_IOPMP_S0_NID260 ULL(0x0055C090000) +#define __PCIE6_IOPMP_S1_NID260 ULL(0x0055C0A0000) +#define __PCIE7_IOPMP_S1_NID324 ULL(0x0055C0B0000) +#define __PCIE8_IOPMP_S2_NID324 ULL(0x0055C0C0000) +#define __PCIE9_IOPMP_S0_NID300 ULL(0x00560000000) +#define __PCIE10_IOPMP_S0_NID364 ULL(0x00560010000) +#define __IOMMU_CTRL2_IOPMP_S1_NID364 ULL(0x00560020000) +#define __PCIE11_IOPMP_S0_NID108 ULL(0x00568000000) +#define __PCIE12_IOPMP_S1_NID44 ULL(0x00568010000) +#define __IOMMU_CTRL3_IOPMP_S2_NID44 ULL(0x00568020000) + +#define __DDR_CH_C_PHY_BASE ULL(0x0056C000000) +#define __DDR_CH_C_CRTL_BASE ULL(0x0056D000000) +#define __DDR_CH_C_LSC_BASE ULL(0x0056D800000) +#define __DDR_CH_D_PHY_BASE ULL(0x0056E000000) +#define __DDR_CH_D_CRTL_BASE ULL(0x0056F000000) +#define __DDR_CH_D_LSC_BASE ULL(0x0056F800000) +#define __DDR_CH_A_PHY_BASE ULL(0x00570000000) +#define __DDR_CH_A_CRTL_BASE ULL(0x00571000000) +#define __DDR_CH_A_LSC_BASE ULL(0x00571800000) +#define __DDR_CH_B_PHY_BASE ULL(0x00572000000) +#define __DDR_CH_B_CRTL_BASE ULL(0x00573000000) +#define __DDR_CH_B_LSC_BASE ULL(0x00573800000) +#define __DDR_CH_E_PHY_BASE ULL(0x00574000000) +#define __DDR_CH_E_CRTL_BASE ULL(0x00575000000) +#define __DDR_CH_E_LSC_BASE ULL(0x00575800000) +#define __DDR_CH_F_PHY_BASE ULL(0x00576000000) +#define __DDR_CH_F_CRTL_BASE ULL(0x00577000000) +#define __DDR_CH_F_LSC_BASE ULL(0x00577800000) +#define __DDR_CH_G_PHY_BASE ULL(0x00578000000) +#define __DDR_CH_G_CRTL_BASE ULL(0x00579000000) +#define __DDR_CH_G_LSC_BASE ULL(0x00579800000) +#define __DDR_CH_H_PHY_BASE ULL(0x0057A000000) +#define __DDR_CH_H_CRTL_BASE ULL(0x0057B000000) +#define __DDR_CH_H_LSC_BASE ULL(0x0057B800000) +#define __ACPU_RAS_SPACE_BASE ULL(0x00580000000) + +#define __N100_CFG_BASE ULL(0x005C8000000) +#define __N100_OCM_BASE ULL(0x005CC000000) +#define __LPC_FLASH_BASE ULL(0x005E0000000) +#define __ESPI_FLASH_BASE ULL(0x005E2000000) +#define __XIP_FLASH_ALIAS_BASE ULL(0x005F0000000) + +#define __PCIE0_SLV_BASE ULL(0x04000000000) +#define __PCIE1_SLV_BASE ULL(0x04100000000) +#define __PCIE2_SLV_BASE ULL(0x04200000000) +#define __PCIE3_SLV_BASE ULL(0x04300000000) +#define __PCIE4_SLV_BASE ULL(0x04400000000) +#define __PCIE5_SLV_BASE ULL(0x04500000000) +#define __IOPMP_DEFAULT_SLV_NID192 ULL(0x046FFFF0000) +#define __PCIE0_DBI_BASE ULL(0x04700000000) +#define __PCIE0_APP_BASE ULL(0x04700400000) +#define __PCIE1_DBI_BASE ULL(0x04700800000) +#define __PCIE1_APP_BASE ULL(0x04700C00000) +#define __PCIE2_DBI_BASE ULL(0x04701000000) +#define __PCIE2_APP_BASE ULL(0x04701400000) +#define __PCIE_4L_COMBPHY0_BASE ULL(0x04701800000) +#define __PCIE3_DBI_BASE ULL(0x04702000000) +#define __PCIE3_APP_BASE ULL(0x04702400000) +#define __PCIE_4L_COMBPHY1_BASE ULL(0x04703800000) +#define __PCIE4_DBI_BASE ULL(0x04704000000) +#define __PCIE4_APP_BASE ULL(0x04704400000) +#define __PCIE_4L_COMBPHY2_BASE ULL(0x04705800000) +#define __PCIE5_DBI_BASE ULL(0x04706000000) +#define __PCIE5_APP_BASE ULL(0x04706400000) +#define __PCIE_4L_COMBPHY3_BASE ULL(0x04707800000) +#define __IOMMU_CRTL0_CFG_BASE ULL(0x04780000000) +#define __PCIE6_SLV_BASE ULL(0x04800000000) +#define __PCIE7_SLV_BASE ULL(0x04900000000) +#define __PCIE8_SLV_BASE ULL(0x04A00000000) +#define __PCIE6_DBI_BASE ULL(0x04F00000000) +#define __PCIE6_APP_BASE ULL(0x04F00400000) +#define __PCIE7_DBI_BASE ULL(0x04F00800000) +#define __PCIE7_APP_BASE ULL(0x04F00C00000) +#define __PCIE8_DBI_BASE ULL(0x04F01000000) +#define __PCIE8_APP_BASE ULL(0x04F01400000) +#define __PCIE_16L_COMBPHY4_BASE ULL(0x04F01800000) +#define __IOMMU_CRTL1_CFG_BASE ULL(0x04F80000000) +#define __PCIE9_SLV_BASE ULL(0x05000000000) +#define __PCIE10_SLV_BASE ULL(0x05100000000) +#define __PCIE9_DBI_BASE ULL(0x05700000000) +#define __PCIE9_APP_BASE ULL(0x05700400000) +#define __PCIE10_DBI_BASE ULL(0x05700800000) +#define __PCIE10_APP_BASE ULL(0x05700C00000) +#define __PCIE_16L_COMBPHY5_BASE ULL(0x05701800000) +#define __IOPMP_DEFAULT_SLV_NID296 ULL(0x0577FFF0000) +#define __IOMMU_CRTL2_CFG_BASE ULL(0x05780000000) +#define __PCIE11_SLV_BASE ULL(0x05800000000) +#define __PCIE12_SLV_BASE ULL(0x05900000000) +#define __PCIE11_DBI_BASE ULL(0x05F00000000) +#define __PCIE11_APP_BASE ULL(0x05F00400000) +#define __PCIE12_DBI_BASE ULL(0x05F00800000) +#define __PCIE12_APP_BASE ULL(0x05F00C00000) +#define __PCIE_16L_COMBPHY6_BASE ULL(0x05F01800000) +#define __IOPMP_DEFAULT_SLV_NID104 ULL(0x05F7FFF0000) +#define __IOMMU_CRTL3_CFG_BASE ULL(0x05F80000000) +#endif + #define UART0_BASE __RMU_UART0_BASE #define ACLINT_BASE __RMU_CLINT_BASE diff --git a/arch/riscv/mach-k1matrix/cru_clk_fake.c b/arch/riscv/mach-k1matrix/cru_clk_fake.c index 20114542..b86dca36 100644 --- a/arch/riscv/mach-k1matrix/cru_clk_fake.c +++ b/arch/riscv/mach-k1matrix/cru_clk_fake.c @@ -106,6 +106,13 @@ struct div_clk { }; +#ifdef CONFIG_K1MATRIX_64C +struct div_clk div_clks[] = { + + +} +#endif + struct div_clk div_clks[] = { [CPU_NIC_CLKDIV] = { .reg = CRU_CPU_NIC_CLK_CTL, @@ -391,7 +398,7 @@ struct div_clk div_clks[] = { }, }; -#ifdef CONFIG_CLK_MNEMONICS + const char *div_clk_names[NR_DIV_CLKS] = { [CPU_NIC_CLKDIV] = "cpu_nic_clkdiv", [CPU_HAP_CLKDIV] = "cpu_hap_clkdiv", @@ -433,6 +440,7 @@ const char *div_clk_names[NR_DIV_CLKS] = { [RMU_LPC_CLK_DIV] = "rmu_lpc_clk_div", }; +#ifdef CONFIG_CLK_MNEMONICS const char *get_div_name(clk_clk_t clk) { if (clk >= NR_DIV_CLKS) @@ -533,7 +541,7 @@ struct sel_clk { cru_flags_t flags; }; -clk_t cpu_nic_clksels[] = { +clk_t fout1ph0_clksels[] = { osc_clk, com_pll_fout1ph0, }; @@ -543,7 +551,7 @@ clk_t pcie_peri_xclksels[] = { peri_pll_foutpostdiv, }; -clk_t pcie_com_xclksels[] = { +clk_t com_clksels[] = { osc_clk, com_pll_foutpostdiv, }; @@ -560,14 +568,14 @@ clk_t peri_gmac_tx_clksels[] = { struct sel_clk sel_clks[] = { [RMU_CLKSEL] = { - .clksels = cpu_nic_clksels, + .clksels = fout1ph0_clksels, .reg = CRU_RMU_CLK_SEL, .nr_clksels = 2, .sel = 1, .flags = 0, }, [CPU_NIC_CLKSEL] = { - .clksels = cpu_nic_clksels, + .clksels = fout1ph0_clksels, .reg = CRU_CPU_NIC_CLK_CTL, .nr_clksels = 2, .sel = 1, @@ -588,14 +596,14 @@ struct sel_clk sel_clks[] = { .flags = 0, }, [PCIE_TOP_CFG_CLKSEL] = { - .clksels = pcie_com_xclksels, + .clksels = com_clksels, .reg = CRU_PCIE_TOP_CFGCLK_CTL, .nr_clksels = 2, .sel = 1, .flags = 0, }, [PCIE_BOT_CFG_CLKSEL] = { - .clksels = pcie_com_xclksels, + .clksels = com_clksels, .reg = CRU_PCIE_BOT_CFGCLK_CTL, .nr_clksels = 2, .sel = 1, @@ -629,9 +637,158 @@ struct sel_clk sel_clks[] = { .sel = 1, .flags = CRU_CLKEN, }, +#ifdef CONFIG_K1MATRIX_64C + [LTOP_CFG_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_LTOP_CFG_CLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = CRU_CLKEN, + }, + [LTOP_PCIE_CFG_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_LTOP_PCIE_CFG_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = CRU_CLKEN, + }, + [LTOP_PCIE_AUX_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_LTOP_PCIE_AUX_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = 0, + } + [LTOP_PCIE_TFR_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_LTOP_PCIE_TFR_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = 0, + } + [LTOP_PHY_FW_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_LTOP_PHY_FW_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = CRU_CLKEN, + } + [RTOP_CFG_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_RTOP_CFG_CLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = CRU_CLKEN, + }, + [RTOP_PCIE_CFG_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_RTOP_PCIE_CFG_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = CRU_CLKEN, + }, + [RTOP_PCIE_AUX_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_RTOP_PCIE_AUX_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = 0, + }, + [RTOP_PCIE_TFR_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_RTOP_PCIE_TFR_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = 0, + }, + [BOT_PHY_FW_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_BOT_PHY_FW_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = CRU_CLKEN, + }, + [BOT_CFG_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_BOT_CFG_CLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = CRU_CLKEN, + }, + [BOT_PCIE_CFG_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_BOT_PCIE_CFG_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = CRU_CLKEN, + }, + [BOT_PCIE_AUX_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_BOT_PCIE_AUX_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = 0, + }, + [BOT_PCIE_TFR_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_BOT_PCIE_TFR_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = 0, + }, + [BOT_PHY_FW_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_BOT_PHY_FW_CLK_CTL, + .nr_clksels = 2, + .sel =1, + .flags = CRU_CLKEN, + }, + [CPU_NIC_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_CPU_NIC_CLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = 0, + }, + [TRMU_IOPMP_CFG_CLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_TRMU_IOPMP_CFG_CLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = CRU_CLKEN, + }, + [DDR_CFG_CLKSEL] = { + .clksels = com_clksels, + .reg = CRU_DDR_CFG_CLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = 0, + }, + [TPERI_SUB_MCLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_TPERI_SUB_MCLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = CRU_CLKEN, + }, + [TPERI_SUB_SCLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_TPERI_SUB_SCLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = CRU_CLKEN, + }, + [HNI_PERI_CFG_SCLKSEL] = { + .clksels = fout1ph0_clksels, + .reg = CRU_HNI_PERI_CFG_CLK_CTL, + .nr_clksels = 2, + .sel = 1, + .flags = CRU_CLKEN, + }, +#endif }; -#ifdef CONFIG_CLK_MNEMONICS + const char *sel_clk_names[NR_SEL_CLKS] = { [RMU_CLKSEL] = "rmu_clksel", [CPU_NIC_CLKSEL] = "cpu_nic_clksel", @@ -643,8 +800,32 @@ const char *sel_clk_names[NR_SEL_CLKS] = { [PCIE_BOT_XCLKSEL] = "pcie_bot_xclksel", [PERI_SUB_CLKSEL] = "peri_sub_clksel", [PERI_GMAC_TXCLK_SEL] = "peri_gmac_txclk_sel", + #ifdef CONFIG_K1MATRIX_64C + [LTOP_CFG_CLKSEL] = "ltop_cfg_clksel", + [LTOP_PCIE_CFG_CLKSEL] = "ltop_pcie_cfg_clksel", + [LTOP_PCIE_AUX_CLKSEL] = "ltop_pcie_aux_clksel", + [LTOP_PCIE_TFR_CLKSEL] = "ltop_pcie_tfr_clksel", + [LTOP_PHY_FW_CLKSEL] = "ltop_phy_fw_clksel", + [RTOP_CFG_CLKSEL] = "rtop_cfg_clksel", + [RTOP_PCIE_CFG_CLKSEL] = "rtop_pcie_cfg_clksel", + [RTOP_PCIE_AUX_CLKSEL] = "rtop_pcie_aux_clksel", + [RTOP_PCIE_TFR_CLKSEL] = "rtop_pcie_tfr_clksel", + [RTOP_PHY_FW_CLKSEL] = "rtop_phy_fw_clksel", + [BOT_CFG_CLKSEL] = "bot_cfg_clksel", + [BOT_PCIE_CFG_CLKSEL] = "bot_pcie_cfg_clksel", + [BOT_PCIE_AUX_CLKSEL] = "bot_pcie_aux_clksel", + [BOT_PCIE_TFR_CLKSEL] = "bot_pcie_tfr_clksel", + [BOT_PHY_FW_CLKSEL] = "bot_phy_fw_clksel", + [CPU_NIC_CLKSEL] = "cpu_nic_clksel", + [TRMU_IOPMP_CFG_CLKSEL] = "trmu_iopmp_cfg_clksel", + [DDR_CFG_CLKSEL] = "ddr_cfg_clksel", + [TPERI_SUB_MCLKSEL] = "tperi_sub_mclksel", + [TPERI_SUB_SCLKSEL] = "tperi_sub_sclksel", + [HNI_PERI_CFG_SCLKSEL] = "hni_peri_cfg_sclksel", + #endif }; +#ifdef CONFIG_CLK_MNEMONICS static const char *get_sel_name(clk_clk_t sel) { if (sel >= NR_SEL_CLKS)