-
Notifications
You must be signed in to change notification settings - Fork 0
/
clk-si5341.c
1845 lines (1585 loc) · 46.5 KB
/
clk-si5341.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
* Copyright (C) 2019 Topic Embedded Products
* Author: Mike Looijmans <mike.looijmans@topic.nl>
*
* The Si5341 has 10 outputs and 5 synthesizers.
* The Si5340 is a smaller version of the Si5341 with only 4 outputs.
* The Si5345 is similar to the Si5341, with the addition of fractional input
* dividers and automatic input selection.
* The Si5342 and Si5344 are smaller versions of the Si5345.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/gcd.h>
#include <linux/math64.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <asm/unaligned.h>
#define SI5341_NUM_INPUTS 4
#define SI5340_MAX_NUM_OUTPUTS 4
#define SI5341_MAX_NUM_OUTPUTS 10
#define SI5342_MAX_NUM_OUTPUTS 2
#define SI5344_MAX_NUM_OUTPUTS 4
#define SI5345_MAX_NUM_OUTPUTS 10
#define SI5340_NUM_SYNTH 4
#define SI5341_NUM_SYNTH 5
#define SI5342_NUM_SYNTH 2
#define SI5344_NUM_SYNTH 4
#define SI5345_NUM_SYNTH 5
/* Range of the synthesizer fractional divider */
#define SI5341_SYNTH_N_MIN 10
#define SI5341_SYNTH_N_MAX 4095
/* The chip can get its input clock from 3 input pins or an XTAL */
/* There is one PLL running at 13500–14256 MHz */
#define SI5341_PLL_VCO_MIN 13500000000ull
#define SI5341_PLL_VCO_MAX 14256000000ull
/* The 5 frequency synthesizers obtain their input from the PLL */
struct clk_si5341_synth {
struct clk_hw hw;
struct clk_si5341 *data;
u8 index;
};
#define to_clk_si5341_synth(_hw) \
container_of(_hw, struct clk_si5341_synth, hw)
/* The output stages can be connected to any synth (full mux) */
struct clk_si5341_output {
struct clk_hw hw;
struct clk_si5341 *data;
struct regulator *vddo_reg;
u8 index;
};
#define to_clk_si5341_output(_hw) \
container_of(_hw, struct clk_si5341_output, hw)
struct clk_si5341 {
struct clk_hw hw;
struct regmap *regmap;
struct i2c_client *i2c_client;
struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
struct clk *input_clk[SI5341_NUM_INPUTS];
const char *input_clk_name[SI5341_NUM_INPUTS];
const u16 *reg_output_offset;
const u16 *reg_rdiv_offset;
u64 freq_vco; /* 13500–14256 MHz */
u8 num_outputs;
u8 num_synth;
u16 chip_id;
bool xaxb_ext_clk;
bool iovdd_33;
};
#define to_clk_si5341(_hw) container_of(_hw, struct clk_si5341, hw)
struct clk_si5341_output_config {
u8 out_format_drv_bits;
u8 out_cm_ampl_bits;
u8 vdd_sel_bits;
bool synth_master;
bool always_on;
};
#define SI5341_PAGE 0x0001
#define SI5341_PN_BASE 0x0002
#define SI5341_DEVICE_REV 0x0005
#define SI5341_STATUS 0x000C
#define SI5341_LOS 0x000D
#define SI5341_STATUS_STICKY 0x0011
#define SI5341_LOS_STICKY 0x0012
#define SI5341_SOFT_RST 0x001C
#define SI5341_IN_SEL 0x0021
#define SI5341_DEVICE_READY 0x00FE
#define SI5341_XAXB_CFG 0x090E
#define SI5341_IO_VDD_SEL 0x0943
#define SI5341_IN_EN 0x0949
#define SI5341_INX_TO_PFD_EN 0x094A
/* Status bits */
#define SI5341_STATUS_SYSINCAL BIT(0)
#define SI5341_STATUS_LOSXAXB BIT(1)
#define SI5341_STATUS_LOSREF BIT(2)
#define SI5341_STATUS_LOL BIT(3)
/* Input selection */
#define SI5341_IN_SEL_MASK 0x06
#define SI5341_IN_SEL_SHIFT 1
#define SI5341_IN_SEL_REGCTRL 0x01
#define SI5341_INX_TO_PFD_SHIFT 4
/* XTAL config bits */
#define SI5341_XAXB_CFG_EXTCLK_EN BIT(0)
#define SI5341_XAXB_CFG_PDNB BIT(1)
/* Input dividers (48-bit) */
#define SI5341_IN_PDIV(x) (0x0208 + ((x) * 10))
#define SI5341_IN_PSET(x) (0x020E + ((x) * 10))
#define SI5341_PX_UPD 0x0230
/* PLL configuration */
#define SI5341_PLL_M_NUM 0x0235
#define SI5341_PLL_M_DEN 0x023B
/* Output configuration */
#define SI5341_OUT_CONFIG(output) \
((output)->data->reg_output_offset[(output)->index])
#define SI5341_OUT_FORMAT(output) (SI5341_OUT_CONFIG(output) + 1)
#define SI5341_OUT_CM(output) (SI5341_OUT_CONFIG(output) + 2)
#define SI5341_OUT_MUX_SEL(output) (SI5341_OUT_CONFIG(output) + 3)
#define SI5341_OUT_R_REG(output) \
((output)->data->reg_rdiv_offset[(output)->index])
#define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
/* Synthesize N divider */
#define SI5341_SYNTH_N_NUM(x) (0x0302 + ((x) * 11))
#define SI5341_SYNTH_N_DEN(x) (0x0308 + ((x) * 11))
#define SI5341_SYNTH_N_UPD(x) (0x030C + ((x) * 11))
/* Synthesizer output enable, phase bypass, power mode */
#define SI5341_SYNTH_N_CLK_TO_OUTX_EN 0x0A03
#define SI5341_SYNTH_N_PIBYP 0x0A04
#define SI5341_SYNTH_N_PDNB 0x0A05
#define SI5341_SYNTH_N_CLK_DIS 0x0B4A
#define SI5341_REGISTER_MAX 0xBFF
/* SI5341_OUT_CONFIG bits */
#define SI5341_OUT_CFG_PDN BIT(0)
#define SI5341_OUT_CFG_OE BIT(1)
#define SI5341_OUT_CFG_RDIV_FORCE2 BIT(2)
/* Static configuration (to be moved to firmware) */
struct si5341_reg_default {
u16 address;
u8 value;
};
static const char * const si5341_input_clock_names[] = {
"in0", "in1", "in2", "xtal"
};
/* Output configuration registers 0..9 are not quite logically organized */
/* Also for si5345 */
static const u16 si5341_reg_output_offset[] = {
0x0108,
0x010D,
0x0112,
0x0117,
0x011C,
0x0121,
0x0126,
0x012B,
0x0130,
0x013A,
};
/* for si5340, si5342 and si5344 */
static const u16 si5340_reg_output_offset[] = {
0x0112,
0x0117,
0x0126,
0x012B,
};
/* The location of the R divider registers */
static const u16 si5341_reg_rdiv_offset[] = {
0x024A,
0x024D,
0x0250,
0x0253,
0x0256,
0x0259,
0x025C,
0x025F,
0x0262,
0x0268,
};
static const u16 si5340_reg_rdiv_offset[] = {
0x0250,
0x0253,
0x025C,
0x025F,
};
/*
* Programming sequence from ClockBuilder, settings to initialize the system
* using only the XTAL input, without pre-divider.
* This also contains settings that aren't mentioned anywhere in the datasheet.
* The "known" settings like synth and output configuration are done later.
*/
static const struct si5341_reg_default si5341_reg_defaults[] = {
{ 0x0017, 0x3A }, /* INT mask (disable interrupts) */
{ 0x0018, 0xFF }, /* INT mask */
{ 0x0021, 0x0F }, /* Select XTAL as input */
{ 0x0022, 0x00 }, /* Not in datasheet */
{ 0x002B, 0x02 }, /* SPI config */
{ 0x002C, 0x20 }, /* LOS enable for XTAL */
{ 0x002D, 0x00 }, /* LOS timing */
{ 0x002E, 0x00 },
{ 0x002F, 0x00 },
{ 0x0030, 0x00 },
{ 0x0031, 0x00 },
{ 0x0032, 0x00 },
{ 0x0033, 0x00 },
{ 0x0034, 0x00 },
{ 0x0035, 0x00 },
{ 0x0036, 0x00 },
{ 0x0037, 0x00 },
{ 0x0038, 0x00 }, /* LOS setting (thresholds) */
{ 0x0039, 0x00 },
{ 0x003A, 0x00 },
{ 0x003B, 0x00 },
{ 0x003C, 0x00 },
{ 0x003D, 0x00 }, /* LOS setting (thresholds) end */
{ 0x0041, 0x00 }, /* LOS0_DIV_SEL */
{ 0x0042, 0x00 }, /* LOS1_DIV_SEL */
{ 0x0043, 0x00 }, /* LOS2_DIV_SEL */
{ 0x0044, 0x00 }, /* LOS3_DIV_SEL */
{ 0x009E, 0x00 }, /* Not in datasheet */
{ 0x0102, 0x01 }, /* Enable outputs */
{ 0x013F, 0x00 }, /* Not in datasheet */
{ 0x0140, 0x00 }, /* Not in datasheet */
{ 0x0141, 0x40 }, /* OUT LOS */
{ 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
{ 0x0203, 0x00 },
{ 0x0204, 0x00 },
{ 0x0205, 0x00 },
{ 0x0206, 0x00 }, /* PXAXB (2^x) */
{ 0x0208, 0x00 }, /* Px divider setting (usually 0) */
{ 0x0209, 0x00 },
{ 0x020A, 0x00 },
{ 0x020B, 0x00 },
{ 0x020C, 0x00 },
{ 0x020D, 0x00 },
{ 0x020E, 0x00 },
{ 0x020F, 0x00 },
{ 0x0210, 0x00 },
{ 0x0211, 0x00 },
{ 0x0212, 0x00 },
{ 0x0213, 0x00 },
{ 0x0214, 0x00 },
{ 0x0215, 0x00 },
{ 0x0216, 0x00 },
{ 0x0217, 0x00 },
{ 0x0218, 0x00 },
{ 0x0219, 0x00 },
{ 0x021A, 0x00 },
{ 0x021B, 0x00 },
{ 0x021C, 0x00 },
{ 0x021D, 0x00 },
{ 0x021E, 0x00 },
{ 0x021F, 0x00 },
{ 0x0220, 0x00 },
{ 0x0221, 0x00 },
{ 0x0222, 0x00 },
{ 0x0223, 0x00 },
{ 0x0224, 0x00 },
{ 0x0225, 0x00 },
{ 0x0226, 0x00 },
{ 0x0227, 0x00 },
{ 0x0228, 0x00 },
{ 0x0229, 0x00 },
{ 0x022A, 0x00 },
{ 0x022B, 0x00 },
{ 0x022C, 0x00 },
{ 0x022D, 0x00 },
{ 0x022E, 0x00 },
{ 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
{ 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
{ 0x026C, 0x00 },
{ 0x026D, 0x00 },
{ 0x026E, 0x00 },
{ 0x026F, 0x00 },
{ 0x0270, 0x00 },
{ 0x0271, 0x00 },
{ 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
{ 0x0339, 0x1F }, /* N_FSTEP_MSK */
{ 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
{ 0x033C, 0x00 },
{ 0x033D, 0x00 },
{ 0x033E, 0x00 },
{ 0x033F, 0x00 },
{ 0x0340, 0x00 },
{ 0x0341, 0x00 },
{ 0x0342, 0x00 },
{ 0x0343, 0x00 },
{ 0x0344, 0x00 },
{ 0x0345, 0x00 },
{ 0x0346, 0x00 },
{ 0x0347, 0x00 },
{ 0x0348, 0x00 },
{ 0x0349, 0x00 },
{ 0x034A, 0x00 },
{ 0x034B, 0x00 },
{ 0x034C, 0x00 },
{ 0x034D, 0x00 },
{ 0x034E, 0x00 },
{ 0x034F, 0x00 },
{ 0x0350, 0x00 },
{ 0x0351, 0x00 },
{ 0x0352, 0x00 },
{ 0x0353, 0x00 },
{ 0x0354, 0x00 },
{ 0x0355, 0x00 },
{ 0x0356, 0x00 },
{ 0x0357, 0x00 },
{ 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
{ 0x0359, 0x00 }, /* Nx_DELAY */
{ 0x035A, 0x00 },
{ 0x035B, 0x00 },
{ 0x035C, 0x00 },
{ 0x035D, 0x00 },
{ 0x035E, 0x00 },
{ 0x035F, 0x00 },
{ 0x0360, 0x00 },
{ 0x0361, 0x00 },
{ 0x0362, 0x00 }, /* Nx_DELAY end */
{ 0x0802, 0x00 }, /* Not in datasheet */
{ 0x0803, 0x00 }, /* Not in datasheet */
{ 0x0804, 0x00 }, /* Not in datasheet */
{ 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
{ 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
{ 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
{ 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
{ 0x0A02, 0x00 }, /* Not in datasheet */
{ 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
{ 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
{ 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
};
/* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
u64 *val1, u32 *val2)
{
int err;
u8 r[10];
err = regmap_bulk_read(regmap, reg, r, 10);
if (err < 0)
return err;
*val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
(get_unaligned_le32(r));
*val2 = get_unaligned_le32(&r[6]);
return 0;
}
static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
u64 n_num, u32 n_den)
{
u8 r[10];
/* Shift left as far as possible without overflowing */
while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
n_num <<= 1;
n_den <<= 1;
}
/* 44 bits (6 bytes) numerator */
put_unaligned_le32(n_num, r);
r[4] = (n_num >> 32) & 0xff;
r[5] = (n_num >> 40) & 0x0f;
/* 32 bits denominator */
put_unaligned_le32(n_den, &r[6]);
/* Program the fraction */
return regmap_bulk_write(regmap, reg, r, sizeof(r));
}
/* VCO, we assume it runs at a constant frequency */
static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_si5341 *data = to_clk_si5341(hw);
int err;
u64 res;
u64 m_num;
u32 m_den;
unsigned int shift;
/* Assume that PDIV is not being used, just read the PLL setting */
err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
&m_num, &m_den);
if (err < 0)
return 0;
if (!m_num || !m_den)
return 0;
/*
* Though m_num is 64-bit, only the upper bits are actually used. While
* calculating m_num and m_den, they are shifted as far as possible to
* the left. To avoid 96-bit division here, we just shift them back so
* we can do with just 64 bits.
*/
shift = 0;
res = m_num;
while (res & 0xffff00000000ULL) {
++shift;
res >>= 1;
}
res *= parent_rate;
do_div(res, (m_den >> shift));
/* We cannot return the actual frequency in 32 bit, store it locally */
data->freq_vco = res;
/* Report kHz since the value is out of range */
do_div(res, 1000);
return (unsigned long)res;
}
static int si5341_clk_get_selected_input(struct clk_si5341 *data)
{
int err;
u32 val;
err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
if (err < 0)
return err;
return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
}
static u8 si5341_clk_get_parent(struct clk_hw *hw)
{
struct clk_si5341 *data = to_clk_si5341(hw);
int res = si5341_clk_get_selected_input(data);
if (res < 0)
return 0; /* Apparently we cannot report errors */
return res;
}
static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
{
int err;
u8 val;
val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
/* Enable register-based input selection */
val |= SI5341_IN_SEL_REGCTRL;
err = regmap_update_bits(data->regmap,
SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
if (err < 0)
return err;
if (index < 3) {
/* Enable input buffer for selected input */
err = regmap_update_bits(data->regmap,
SI5341_IN_EN, 0x07, BIT(index));
if (err < 0)
return err;
/* Enables the input to phase detector */
err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
0x7 << SI5341_INX_TO_PFD_SHIFT,
BIT(index + SI5341_INX_TO_PFD_SHIFT));
if (err < 0)
return err;
/* Power down XTAL oscillator and buffer */
err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
SI5341_XAXB_CFG_PDNB, 0);
if (err < 0)
return err;
/*
* Set the P divider to "1". There's no explanation in the
* datasheet of these registers, but the clockbuilder software
* programs a "1" when the input is being used.
*/
err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
if (err < 0)
return err;
err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
if (err < 0)
return err;
/* Set update PDIV bit */
err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
if (err < 0)
return err;
} else {
/* Disable all input buffers */
err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
if (err < 0)
return err;
/* Disable input to phase detector */
err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
if (err < 0)
return err;
/* Power up XTAL oscillator and buffer, select clock mode */
err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN,
SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ?
SI5341_XAXB_CFG_EXTCLK_EN : 0));
if (err < 0)
return err;
}
return 0;
}
static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_si5341 *data = to_clk_si5341(hw);
return si5341_clk_reparent(data, index);
}
static const struct clk_ops si5341_clk_ops = {
.set_parent = si5341_clk_set_parent,
.get_parent = si5341_clk_get_parent,
.recalc_rate = si5341_clk_recalc_rate,
};
/* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
/* The synthesizer is on if all power and enable bits are set */
static int si5341_synth_clk_is_on(struct clk_hw *hw)
{
struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
int err;
u32 val;
u8 index = synth->index;
err = regmap_read(synth->data->regmap,
SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
if (err < 0)
return 0;
if (!(val & BIT(index)))
return 0;
err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
if (err < 0)
return 0;
if (!(val & BIT(index)))
return 0;
/* This bit must be 0 for the synthesizer to receive clock input */
err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
if (err < 0)
return 0;
return !(val & BIT(index));
}
static void si5341_synth_clk_unprepare(struct clk_hw *hw)
{
struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
u8 index = synth->index; /* In range 0..5 */
u8 mask = BIT(index);
/* Disable output */
regmap_update_bits(synth->data->regmap,
SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
/* Power down */
regmap_update_bits(synth->data->regmap,
SI5341_SYNTH_N_PDNB, mask, 0);
/* Disable clock input to synth (set to 1 to disable) */
regmap_update_bits(synth->data->regmap,
SI5341_SYNTH_N_CLK_DIS, mask, mask);
}
static int si5341_synth_clk_prepare(struct clk_hw *hw)
{
struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
int err;
u8 index = synth->index;
u8 mask = BIT(index);
/* Power up */
err = regmap_update_bits(synth->data->regmap,
SI5341_SYNTH_N_PDNB, mask, mask);
if (err < 0)
return err;
/* Enable clock input to synth (set bit to 0 to enable) */
err = regmap_update_bits(synth->data->regmap,
SI5341_SYNTH_N_CLK_DIS, mask, 0);
if (err < 0)
return err;
/* Enable output */
return regmap_update_bits(synth->data->regmap,
SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
}
/* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
u64 f;
u64 n_num;
u32 n_den;
int err;
err = si5341_decode_44_32(synth->data->regmap,
SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
if (err < 0)
return err;
/* Check for bogus/uninitialized settings */
if (!n_num || !n_den)
return 0;
/*
* n_num and n_den are shifted left as much as possible, so to prevent
* overflow in 64-bit math, we shift n_den 4 bits to the right
*/
f = synth->data->freq_vco;
f *= n_den >> 4;
/* Now we need to do 64-bit division: f/n_num */
/* And compensate for the 4 bits we dropped */
f = div64_u64(f, (n_num >> 4));
return f;
}
static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
u64 f;
/* The synthesizer accuracy is such that anything in range will work */
f = synth->data->freq_vco;
do_div(f, SI5341_SYNTH_N_MAX);
if (rate < f)
return f;
f = synth->data->freq_vco;
do_div(f, SI5341_SYNTH_N_MIN);
if (rate > f)
return f;
return rate;
}
static int si5341_synth_program(struct clk_si5341_synth *synth,
u64 n_num, u32 n_den, bool is_integer)
{
int err;
u8 index = synth->index;
err = si5341_encode_44_32(synth->data->regmap,
SI5341_SYNTH_N_NUM(index), n_num, n_den);
err = regmap_update_bits(synth->data->regmap,
SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
if (err < 0)
return err;
return regmap_write(synth->data->regmap,
SI5341_SYNTH_N_UPD(index), 0x01);
}
static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
u64 n_num;
u32 n_den;
u32 r;
u32 g;
bool is_integer;
n_num = synth->data->freq_vco;
/* see if there's an integer solution */
r = do_div(n_num, rate);
is_integer = (r == 0);
if (is_integer) {
/* Integer divider equal to n_num */
n_den = 1;
} else {
/* Calculate a fractional solution */
g = gcd(r, rate);
n_den = rate / g;
n_num *= n_den;
n_num += r / g;
}
dev_dbg(&synth->data->i2c_client->dev,
"%s(%u): n=0x%llx d=0x%x %s\n", __func__,
synth->index, n_num, n_den,
is_integer ? "int" : "frac");
return si5341_synth_program(synth, n_num, n_den, is_integer);
}
static const struct clk_ops si5341_synth_clk_ops = {
.is_prepared = si5341_synth_clk_is_on,
.prepare = si5341_synth_clk_prepare,
.unprepare = si5341_synth_clk_unprepare,
.recalc_rate = si5341_synth_clk_recalc_rate,
.round_rate = si5341_synth_clk_round_rate,
.set_rate = si5341_synth_clk_set_rate,
};
static int si5341_output_clk_is_on(struct clk_hw *hw)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
int err;
u32 val;
err = regmap_read(output->data->regmap,
SI5341_OUT_CONFIG(output), &val);
if (err < 0)
return err;
/* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
return (val & 0x03) == SI5341_OUT_CFG_OE;
}
/* Disables and then powers down the output */
static void si5341_output_clk_unprepare(struct clk_hw *hw)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
regmap_update_bits(output->data->regmap,
SI5341_OUT_CONFIG(output),
SI5341_OUT_CFG_OE, 0);
regmap_update_bits(output->data->regmap,
SI5341_OUT_CONFIG(output),
SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
}
/* Powers up and then enables the output */
static int si5341_output_clk_prepare(struct clk_hw *hw)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
int err;
err = regmap_update_bits(output->data->regmap,
SI5341_OUT_CONFIG(output),
SI5341_OUT_CFG_PDN, 0);
if (err < 0)
return err;
return regmap_update_bits(output->data->regmap,
SI5341_OUT_CONFIG(output),
SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
}
static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
int err;
u32 val;
u32 r_divider;
u8 r[3];
err = regmap_read(output->data->regmap,
SI5341_OUT_CONFIG(output), &val);
if (err < 0)
return err;
/* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
if (val & SI5341_OUT_CFG_RDIV_FORCE2)
return parent_rate / 2;
err = regmap_bulk_read(output->data->regmap,
SI5341_OUT_R_REG(output), r, 3);
if (err < 0)
return err;
/* Calculate value as 24-bit integer*/
r_divider = r[2] << 16 | r[1] << 8 | r[0];
/* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
if (!r_divider)
return 0;
/* Divider is 2*(Rx_REG+1) */
r_divider += 1;
r_divider <<= 1;
return parent_rate / r_divider;
}
static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
unsigned long r;
if (!rate)
return 0;
r = *parent_rate >> 1;
/* If rate is an even divisor, no changes to parent required */
if (r && !(r % rate))
return (long)rate;
if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
if (rate > 200000000) {
/* minimum r-divider is 2 */
r = 2;
} else {
/* Take a parent frequency near 400 MHz */
r = (400000000u / rate) & ~1;
}
*parent_rate = r * rate;
} else {
/* We cannot change our parent's rate, report what we can do */
r /= rate;
rate = *parent_rate / (r << 1);
}
return rate;
}
static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
u32 r_div;
int err;
u8 r[3];
if (!rate)
return -EINVAL;
/* Frequency divider is (r_div + 1) * 2 */
r_div = (parent_rate / rate) >> 1;
if (r_div <= 1)
r_div = 0;
else if (r_div >= BIT(24))
r_div = BIT(24) - 1;
else
--r_div;
/* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
err = regmap_update_bits(output->data->regmap,
SI5341_OUT_CONFIG(output),
SI5341_OUT_CFG_RDIV_FORCE2,
(r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
if (err < 0)
return err;
/* Always write Rx_REG, because a zero value disables the divider */
r[0] = r_div ? (r_div & 0xff) : 1;
r[1] = (r_div >> 8) & 0xff;
r[2] = (r_div >> 16) & 0xff;
err = regmap_bulk_write(output->data->regmap,
SI5341_OUT_R_REG(output), r, 3);
return 0;
}
static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
{
return regmap_update_bits(output->data->regmap,
SI5341_OUT_MUX_SEL(output), 0x07, index);
}
static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
if (index >= output->data->num_synth)
return -EINVAL;
return si5341_output_reparent(output, index);
}
static u8 si5341_output_get_parent(struct clk_hw *hw)
{
struct clk_si5341_output *output = to_clk_si5341_output(hw);
u32 val;
regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
return val & 0x7;
}
static const struct clk_ops si5341_output_clk_ops = {
.is_prepared = si5341_output_clk_is_on,
.prepare = si5341_output_clk_prepare,
.unprepare = si5341_output_clk_unprepare,
.recalc_rate = si5341_output_clk_recalc_rate,
.round_rate = si5341_output_clk_round_rate,
.set_rate = si5341_output_clk_set_rate,
.set_parent = si5341_output_set_parent,
.get_parent = si5341_output_get_parent,
};
/*
* The chip can be bought in a pre-programmed version, or one can program the
* NVM in the chip to boot up in a preset mode. This routine tries to determine
* if that's the case, or if we need to reset and program everything from
* scratch. Returns negative error, or true/false.
*/
static int si5341_is_programmed_already(struct clk_si5341 *data)
{
int err;
u8 r[4];
/* Read the PLL divider value, it must have a non-zero value */
err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
r, ARRAY_SIZE(r));
if (err < 0)
return err;
return !!get_unaligned_le32(r);
}
static struct clk_hw *
of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
{
struct clk_si5341 *data = _data;
unsigned int idx = clkspec->args[1];
unsigned int group = clkspec->args[0];
switch (group) {
case 0:
if (idx >= data->num_outputs) {
dev_err(&data->i2c_client->dev,
"invalid output index %u\n", idx);
return ERR_PTR(-EINVAL);
}
return &data->clk[idx].hw;
case 1:
if (idx >= data->num_synth) {
dev_err(&data->i2c_client->dev,
"invalid synthesizer index %u\n", idx);
return ERR_PTR(-EINVAL);
}
return &data->synth[idx].hw;
case 2:
if (idx > 0) {
dev_err(&data->i2c_client->dev,
"invalid PLL index %u\n", idx);
return ERR_PTR(-EINVAL);
}
return &data->hw;
default:
dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
return ERR_PTR(-EINVAL);
}
}
static int si5341_probe_chip_id(struct clk_si5341 *data)
{
int err;
u8 reg[4];
u16 model;
err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
ARRAY_SIZE(reg));