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drivers: ethernet: Add Xilinx AXI Enet driver #73986

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The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs. This patch adds a driver and device tree bindings for the Ethernet MAC core.
The driver was tested on a RISC-V softcore in an FPGA design, with an RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree bindings match the device tree generated by Vitis hsi. Note that Vitis generates one of the two included compatible strings depending on version.
Please not that TX checksum offloading depends on #73985.

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Note that the Ethernet MAC driver depends on the Ethernet MDIO and the AXI DMA drivers.

@WorldofJARcraft WorldofJARcraft force-pushed the xilinx-axienet-mac branch 2 times, most recently from 75a28a2 to e59f91a Compare June 17, 2024 08:49
bool "Xilinx AXI Ethernet Driver"
default y
depends on DT_HAS_XLNX_AXI_ETHERNET_7_2_ENABLED || DT_HAS_XLNX_AXI_ETHERNET_1_00_A_ENABLED
depends on DT_HAS_XLNX_ETH_DMA_ENABLED && XILINX_AXI_DMA

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Is XILINX_AXI_DMA supposed to be DMA_XILINX_AXI_DMA? @WorldofJARcraft

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Yes, it seems like I forgot to change this in this pull request.

decsny
decsny previously requested changes Aug 1, 2024
depends on DT_HAS_XLNX_ETH_DMA_ENABLED && DMA_XILINX_AXI_DMA
help
Enable Xilinx 1G / 2.5G AXI Ethernet driver,
commonly found on FPGAs. Depends on Xilinx AXI DMA.
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very minor nit but the dependency should already be visible in the menu, don't think it's needed to clarify in the help string.

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OK, removed it.

@@ -0,0 +1,577 @@

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missing license (and potentially copyright, but license is the big thing)

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License added.

#define LOG_MODULE_NAME eth_xilinx_axienet
#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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nit but please do the log module register as one line (it can take two arguments for the name and level, dont need to define macros)

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Done

#define XILINX_AXIENET_UNICAST_ADDRESS_WORD_0_OFFSET 0x00000700
#define XILINX_AXIENET_UNICAST_ADDRESS_WORD_1_OFFSET 0x00000704

#define ETH_ALEN 6
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NET_ETH_ADDR_LEN macro already exists, please use that

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Done, must have overlooked this.

(void)ethdev;
if (status < 0) {
LOG_ERR("DMA RX error: %d", status);
k_panic();
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is a dma error code worth causing a kernel panic?

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I do not insist on the panic.
The Xilinx DMA only errors when it was configured incorrectly (e.g., invalid address), so I found this helpful in debugging.
Is there some define I can guard this with?


if (!pkt) {
LOG_ERR("Could not allocate a packet!");
} else {
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same comment about the else block

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Panic removed.

LOG_ERR("Could not write RX buffer into packet!");
k_panic();
net_pkt_unref(pkt);
} else {
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ditto else block

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Guard with ifdef?

if (net_recv_data(data->interface, pkt) < 0) {
LOG_ERR("Coult not receive packet data!");
net_pkt_unref(pkt);
} else {
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ditto else block

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Guard with ifdef?

} else {
if (net_pkt_write(pkt, data->rx_buffer, packet_size)) {
LOG_ERR("Could not write RX buffer into packet!");
k_panic();
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ditto kernel panic question, and for all other occurrences in the file

struct device *ethdev = (struct device *)user_data;
struct xilinx_axienet_data *data = ethdev->data;

(void)data;
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what does this accomplish

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Removed.

@decsny decsny dismissed their stale review August 14, 2024 20:29

removing change request because the comments mostly addressed, the panic still seems like a bad idea to me but I don't have a stake in this driver so it's up to author

@henrikbrixandersen henrikbrixandersen removed their request for review August 20, 2024 08:10
@WorldofJARcraft WorldofJARcraft force-pushed the xilinx-axienet-mac branch 2 times, most recently from 789595f to b1c0676 Compare August 20, 2024 16:10
@saizen408
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saizen408 commented Aug 27, 2024

@WorldofJARcraft Is it on purpose that zephyr_library_sources_ifdef(CONFIG_XILINX_AXI_ENET eth_xilinx_axi_enet.c) is not included in zephyr/drivers/ethernet/CMakeLists.txt ?

I'm fairly new to zephyr so forgive if I am missing something.

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CI failure is expected as long as the DMA (#73926) has not been merged. As the DMA has uses outside of the Ethernet subsystem (e.g., with custom AXI-Stream IP), I think it should be a separate PR.

The Xilinx AXI Ethernet subsystem is commonly found in FPGA designs.
This patch adds a driver and device tree bindings for the Ethernet MAC
core and its MDIO controller.
The driver was tested on a RISC-V softcore in an FPGA design, with an
RGMII phy and Ethernet subsystem version 7.2 Rev. 14. Device tree
bindings match the device tree generated by Vitis hsi. Note that Vitis
generates one of the two included compatible strings depending on
version.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
@WorldofJARcraft
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I have removed the kernel panics from the driver, relying on error messages and appropriate return codes instead.

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4 participants