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added 2 commits
November 1, 2016 17:32
Signed-off-by: Prasanna Karthik <pkarthik@intrinsyc.com>
Signed-off-by: Prasanna Karthik <pkarthik@intrinsyc.com>
zephyr-github
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Mar 15, 2017
The current implementation of stm32_gpio_set() uses the GPIO output data register to change the state of individual GPIOs. The generated assembler needs at least 3 instructions: load / modify / store. This opens a small race window, for example if a thread and an interrupt both try to change the state of the same GPIO bank. Use the GPIO bit set/reset register to perform the atomic change without locking. This also has the benefit of a more optimised implementation, which can be useful for GPIO-intensive work. Compare the new version: 08000c98 <stm32_gpio_set>: 8000c98: f001 010f and.w r1, r1, #15 8000c9c: 2301 movs r3, #1 8000c9e: b902 cbnz r2, 8000ca2 <stm32_gpio_set+0xa> 8000ca0: 3110 adds r1, #16 8000ca2: 408b lsls r3, r1 8000ca4: 6183 str r3, [r0, #24] 8000ca6: 2000 movs r0, #0 8000ca8: 4770 bx lr and the old one: 08000c98 <stm32_gpio_set>: 8000c98: 2301 movs r3, #1 8000c9a: f001 010f and.w r1, r1, #15 8000c9e: fa03 f101 lsl.w r1, r3, r1 8000ca2: 6943 ldr r3, [r0, #20] 8000ca4: b10a cbz r2, 8000caa <stm32_gpio_set+0x12> 8000ca6: 4319 orrs r1, r3 8000ca8: e001 b.n 8000cae <stm32_gpio_set+0x16> 8000caa: ea23 0101 bic.w r1, r3, r1 8000cae: 6141 str r1, [r0, #20] 8000cb0: 2000 movs r0, #0 8000cb2: 4770 bx lr Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
zephyr-github
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Mar 17, 2017
The current implementation of stm32_gpio_set() uses the GPIO output data register to change the state of individual GPIOs. The generated assembler needs at least 3 instructions: load / modify / store. This opens a small race window, for example if a thread and an interrupt both try to change the state of the same GPIO bank. Use the GPIO bit set/reset register to perform the atomic change without locking. This also has the benefit of a more optimised implementation, which can be useful for GPIO-intensive work. Compare the new version: 08000c98 <stm32_gpio_set>: 8000c98: f001 010f and.w r1, r1, #15 8000c9c: 2301 movs r3, #1 8000c9e: b902 cbnz r2, 8000ca2 <stm32_gpio_set+0xa> 8000ca0: 3110 adds r1, #16 8000ca2: 408b lsls r3, r1 8000ca4: 6183 str r3, [r0, #24] 8000ca6: 2000 movs r0, #0 8000ca8: 4770 bx lr and the old one: 08000c98 <stm32_gpio_set>: 8000c98: 2301 movs r3, #1 8000c9a: f001 010f and.w r1, r1, #15 8000c9e: fa03 f101 lsl.w r1, r3, r1 8000ca2: 6943 ldr r3, [r0, #20] 8000ca4: b10a cbz r2, 8000caa <stm32_gpio_set+0x12> 8000ca6: 4319 orrs r1, r3 8000ca8: e001 b.n 8000cae <stm32_gpio_set+0x16> 8000caa: ea23 0101 bic.w r1, r3, r1 8000cae: 6141 str r1, [r0, #20] 8000cb0: 2000 movs r0, #0 8000cb2: 4770 bx lr Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
zephyr-github
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Mar 21, 2017
The current implementation of stm32_gpio_set() uses the GPIO output data register to change the state of individual GPIOs. The generated assembler needs at least 3 instructions: load / modify / store. This opens a small race window, for example if a thread and an interrupt both try to change the state of the same GPIO bank. Use the GPIO bit set/reset register to perform the atomic change without locking. This also has the benefit of a more optimised implementation, which can be useful for GPIO-intensive work. Compare the new version: 08000c98 <stm32_gpio_set>: 8000c98: f001 010f and.w r1, r1, #15 8000c9c: 2301 movs r3, #1 8000c9e: b902 cbnz r2, 8000ca2 <stm32_gpio_set+0xa> 8000ca0: 3110 adds r1, #16 8000ca2: 408b lsls r3, r1 8000ca4: 6183 str r3, [r0, #24] 8000ca6: 2000 movs r0, #0 8000ca8: 4770 bx lr and the old one: 08000c98 <stm32_gpio_set>: 8000c98: 2301 movs r3, #1 8000c9a: f001 010f and.w r1, r1, #15 8000c9e: fa03 f101 lsl.w r1, r3, r1 8000ca2: 6943 ldr r3, [r0, #20] 8000ca4: b10a cbz r2, 8000caa <stm32_gpio_set+0x12> 8000ca6: 4319 orrs r1, r3 8000ca8: e001 b.n 8000cae <stm32_gpio_set+0x16> 8000caa: ea23 0101 bic.w r1, r3, r1 8000cae: 6141 str r1, [r0, #20] 8000cb0: 2000 movs r0, #0 8000cb2: 4770 bx lr Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
zephyr-github
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Mar 27, 2017
The current implementation of stm32_gpio_set() uses the GPIO output data register to change the state of individual GPIOs. The generated assembler needs at least 3 instructions: load / modify / store. This opens a small race window, for example if a thread and an interrupt both try to change the state of the same GPIO bank. Use the GPIO bit set/reset register to perform the atomic change without locking. This also has the benefit of a more optimised implementation, which can be useful for GPIO-intensive work. Compare the new version: 08000c98 <stm32_gpio_set>: 8000c98: f001 010f and.w r1, r1, #15 8000c9c: 2301 movs r3, #1 8000c9e: b902 cbnz r2, 8000ca2 <stm32_gpio_set+0xa> 8000ca0: 3110 adds r1, #16 8000ca2: 408b lsls r3, r1 8000ca4: 6183 str r3, [r0, #24] 8000ca6: 2000 movs r0, #0 8000ca8: 4770 bx lr and the old one: 08000c98 <stm32_gpio_set>: 8000c98: 2301 movs r3, #1 8000c9a: f001 010f and.w r1, r1, #15 8000c9e: fa03 f101 lsl.w r1, r3, r1 8000ca2: 6943 ldr r3, [r0, #20] 8000ca4: b10a cbz r2, 8000caa <stm32_gpio_set+0x12> 8000ca6: 4319 orrs r1, r3 8000ca8: e001 b.n 8000cae <stm32_gpio_set+0x16> 8000caa: ea23 0101 bic.w r1, r3, r1 8000cae: 6141 str r1, [r0, #20] 8000cb0: 2000 movs r0, #0 8000cb2: 4770 bx lr Change-Id: Ie5800d1c345016028d1b9a099f5d74cac35f592a Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
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kartben
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May 19, 2025
Current code does not build on Cortex-M0, seems like it does not like subs: Error: instruction not supported in Thumb16 mode -- `subs r3,#1' Adding a unified assembler language declaration in the snippet seems to fix the problem, also add an M0+ board so this is tested in CI. Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
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avolmat-st
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Jun 18, 2025
Add possibility to perform crop and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
avolmat-st
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Jun 19, 2025
Add possibility to perform crop and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
avolmat-st
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Jun 20, 2025
Add possibility to perform crop on all pipes and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Jun 20, 2025
Add possibility to perform crop on all pipes and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Jun 20, 2025
Add possibility to perform crop on all pipes and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Jun 23, 2025
Add possibility to perform crop on all pipes and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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seyoungjeong
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Jul 11, 2025
Add possibility to perform crop on all pipes and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Chenhongren
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Jul 23, 2025
Add possibility to perform crop on all pipes and compose (downscale) on pixel pipes (endpoint zephyrproject-rtos#1 and endpoint zephyrproject-rtos#2). Rework the code in order to move the downscale control from the set_fmt into the set_selection (compose). (cherry picked from commit 0b9a069) Original-Signed-off-by: Alain Volmat <alain.volmat@foss.st.com> GitOrigin-RevId: 0b9a069 Cr-Build-Id: 8710889529668111169 Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8710889529668111169 Copybot-Job-Name: zephyr-main-copybot-downstream Change-Id: I747c4939c5f8f5b5505b9a01ad1c0253ec657e2f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/6684469 Bot-Commit: ChromeOS Copybot <copybot@chops-service-accounts.iam.gserviceaccount.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org> Commit-Queue: ChromeOS Copybot <copybot@chops-service-accounts.iam.gserviceaccount.com> Tested-by: ChromeOS Copybot <copybot@chops-service-accounts.iam.gserviceaccount.com>
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Aug 4, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Aug 5, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Aug 7, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Aug 14, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Sep 10, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Sep 11, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Sep 11, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main #1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Sep 16, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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Sep 17, 2025
Add support for NV12/NV21, NV16/NV61 and YUV420/YVU420 (semi)planar formats which can be output by the main zephyrproject-rtos#1 pipe. Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
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