tests: dma: chan_blen_transfer: test breaks if DMA cannot access flash

[mathieuchopstm]

Describe the bug

In tests/drivers/dma/chan_blen_transfer, the tx_data buffer is declared const:

zephyr/tests/drivers/dma/chan_blen_transfer/src/test_dma.c

Line 25 in b82b5b0

static __aligned(32) const char tx_data[] = "It is harder to be kind than to be wise........";

As a result, this buffer is placed in .rodata and ends up in FLASH region. This causes the test to fail on SoCs equipped with a DMA controller that cannot access flash memory, such as STM32WB09 MCUs.

Expected behavior
Test should succeed on SoCs with a DMA as long as it can perform memory -> memory (i.e., RAM -> RAM) transfers, regardless of flash -> memory transfer capabilities.

A possible fix is to remove the const qualifier on tx_data - without the qualifier, the buffer seems to be placed in RAM, and the test succeeds.

Logs and console output

Test log:

Running TESTSUITE dma_m2m
===================================================================
START - test_tst_dma0_m2m_chan0_burst16
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=7, BURST_LEN=2
Starting the transfer


    Assertion failed at WEST_TOPDIR/zephyr/tests/drivers/dma/chan_blen_transfer/src/test_dma.c:137: dma_m2m_test_tst_dma0_m2m_chan0_burst16: (test_task(dma, CONFIG_DMA_TRANSFER_CHANNEL_NR_0, 16) == TC_PASS) is false

 FAIL - test_tst_dma0_m2m_chan0_burst16 in 2.028 seconds
===================================================================
START - test_tst_dma0_m2m_chan0_burst8
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=7, BURST_LEN=1
Starting the transfer
E: dma stream 7 is busy.
E: cannot configure the dmamux.
ERROR: transfer

    Assertion failed at WEST_TOPDIR/zephyr/tests/drivers/dma/chan_blen_transfer/src/test_dma.c:137: dma_m2m_test_tst_dma0_m2m_chan0_burst8: (test_task(dma, CONFIG_DMA_TRANSFER_CHANNEL_NR_0, 8) == TC_PASS) is false

 FAIL - test_tst_dma0_m2m_chan0_burst8 in 0.034 seconds
===================================================================
START - test_tst_dma0_m2m_chan1_burst16
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=6, BURST_LEN=2
Starting the transfer


    Assertion failed at WEST_TOPDIR/zephyr/tests/drivers/dma/chan_blen_transfer/src/test_dma.c:137: dma_m2m_test_tst_dma0_m2m_chan1_burst16: (test_task(dma, CONFIG_DMA_TRANSFER_CHANNEL_NR_1, 16) == TC_PASS) is false

 FAIL - test_tst_dma0_m2m_chan1_burst16 in 2.028 seconds
===================================================================
START - test_tst_dma0_m2m_chan1_burst8
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=6, BURST_LEN=1
Starting the transfer
E: dma stream 6 is busy.
E: cannot configure the dmamux.
ERROR: transfer

    Assertion failed at WEST_TOPDIR/zephyr/tests/drivers/dma/chan_blen_transfer/src/test_dma.c:137: dma_m2m_test_tst_dma0_m2m_chan1_burst8: (test_task(dma, CONFIG_DMA_TRANSFER_CHANNEL_NR_1, 8) == TC_PASS) is false

 FAIL - test_tst_dma0_m2m_chan1_burst8 in 0.034 seconds
===================================================================
TESTSUITE dma_m2m failed.

------ TESTSUITE SUMMARY START ------

SUITE FAIL -   0.00% [dma_m2m]: pass = 0, fail = 4, skip = 0, total = 4 duration = 4.124 seconds
 - FAIL - [dma_m2m.test_tst_dma0_m2m_chan0_burst16] duration = 2.028 seconds
 - FAIL - [dma_m2m.test_tst_dma0_m2m_chan0_burst8] duration = 0.034 seconds
 - FAIL - [dma_m2m.test_tst_dma0_m2m_chan1_burst16] duration = 2.028 seconds
 - FAIL - [dma_m2m.test_tst_dma0_m2m_chan1_burst8] duration = 0.034 seconds

------ TESTSUITE SUMMARY END ------

===================================================================
PROJECT EXECUTION FAILED

Test log, after removing the const storage qualifier of tx_data:

Running TESTSUITE dma_m2m
===================================================================
START - test_tst_dma0_m2m_chan0_burst16
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=7, BURST_LEN=2
Starting the transfer
DMA transfer done
It is harder to be kind than to be wise........
 PASS - test_tst_dma0_m2m_chan0_burst16 in 2.015 seconds
===================================================================
START - test_tst_dma0_m2m_chan0_burst8
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=7, BURST_LEN=1
Starting the transfer
DMA transfer done
It is harder to be kind than to be wise........
 PASS - test_tst_dma0_m2m_chan0_burst8 in 2.015 seconds
===================================================================
START - test_tst_dma0_m2m_chan1_burst16
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=6, BURST_LEN=2
Starting the transfer
DMA transfer done
It is harder to be kind than to be wise........
 PASS - test_tst_dma0_m2m_chan1_burst16 in 2.015 seconds
===================================================================
START - test_tst_dma0_m2m_chan1_burst8
Preparing DMA Controller: Name=dmamux@48800000, Chan_ID=6, BURST_LEN=1
Starting the transfer
DMA transfer done
It is harder to be kind than to be wise........
 PASS - test_tst_dma0_m2m_chan1_burst8 in 2.015 seconds
===================================================================
TESTSUITE dma_m2m succeeded

------ TESTSUITE SUMMARY START ------

SUITE PASS - 100.00% [dma_m2m]: pass = 4, fail = 0, skip = 0, total = 4 duration = 8.060 seconds
 - PASS - [dma_m2m.test_tst_dma0_m2m_chan0_burst16] duration = 2.015 seconds
 - PASS - [dma_m2m.test_tst_dma0_m2m_chan0_burst8] duration = 2.015 seconds
 - PASS - [dma_m2m.test_tst_dma0_m2m_chan1_burst16] duration = 2.015 seconds
 - PASS - [dma_m2m.test_tst_dma0_m2m_chan1_burst8] duration = 2.015 seconds

------ TESTSUITE SUMMARY END ------

===================================================================
PROJECT EXECUTION SUCCESSFUL

[teburd]

Please send a patch with the const qualifier removed since you've already done the work and tested it.

There's still going to be some part that fails at some point though because not all RAM is equal for all DMAs and SoCs.

We should use instead dts defined memory attributes and buffer placement at some point https://docs.zephyrproject.org/latest/services/mem_mgmt/index.html#memory-attributes to provide correct static buffer placements (e.g. place the buffer in a region that is useable by DMA).

[mathieuchopstm]

PR open: #75245