drivers: clock_control: Kconfig.stm32xxx PLL div range for each serie

[ABOSTM]

Describe the bug
PLL configuration for series L4, L5 and WB are currently common, but in their respective reference manual, those configuration are different.
For example CLOCK_STM32_PLL_N_MULTIPLIER :

• L4 --> 8 -- 86
• L5 --> 8 -- 126
• WB --> 6 -- 127

Expected behavior
Kconfig need to match with possible values available in Reference Manual.