From 171f687136fe3cb1d6eadb4d86a5692479398731 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 11 Sep 2024 17:52:38 +0200 Subject: [PATCH 001/269] samples: tfm_integration: use zephyr:code-sample directive MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds missing code-sample directive to all the tfm_integration samples in preparation for upcoming changes to the Zephyr documentation that will be leveraging the provided description and metadata. Signed-off-by: Benjamin Cabé --- samples/tfm_integration/psa_crypto/README.rst | 6 +++--- .../tfm_integration/psa_protected_storage/README.rst | 8 ++++---- samples/tfm_integration/tfm_ipc/README.rst | 6 +++--- samples/tfm_integration/tfm_psa_test/README.rst | 4 ++-- samples/tfm_integration/tfm_regression_test/README.rst | 4 ++-- .../tfm_integration/tfm_secure_partition/README.rst | 10 +++++----- 6 files changed, 19 insertions(+), 19 deletions(-) diff --git a/samples/tfm_integration/psa_crypto/README.rst b/samples/tfm_integration/psa_crypto/README.rst index 68ff38245c53916..a403e6064d37617 100644 --- a/samples/tfm_integration/psa_crypto/README.rst +++ b/samples/tfm_integration/psa_crypto/README.rst @@ -1,7 +1,7 @@ -.. _tfm_psa_crypto: +.. zephyr:code-sample:: tfm_psa_crypto + :name: TF-M PSA crypto -TF-M PSA crypto -################ + Use the PSA Crypto API for cryptography and device certificate signing requests. Overview ******** diff --git a/samples/tfm_integration/psa_protected_storage/README.rst b/samples/tfm_integration/psa_protected_storage/README.rst index 67c72440b1b9fac..66c834ffc29bfdd 100644 --- a/samples/tfm_integration/psa_protected_storage/README.rst +++ b/samples/tfm_integration/psa_protected_storage/README.rst @@ -1,7 +1,7 @@ -.. psa_protected_storage: +.. zephyr:code-sample:: psa_protected_storage + :name: TF-M PSA Protected Storage -PSA Protected Storage -##################### + Use the Protected Storage (PS) API to store encrypted data. Overview ******** @@ -41,7 +41,7 @@ run as the overwrite protection will not be removed with a power reset. On QEMU ======== -Refer to :ref:`tfm_ipc` for detailed instructions. +Refer to :zephyr:code-sample:`tfm_ipc` for detailed instructions. Following is an example based on ``west build`` .. code-block:: bash diff --git a/samples/tfm_integration/tfm_ipc/README.rst b/samples/tfm_integration/tfm_ipc/README.rst index 17c0142088060a9..e105be87615513f 100644 --- a/samples/tfm_integration/tfm_ipc/README.rst +++ b/samples/tfm_integration/tfm_ipc/README.rst @@ -1,7 +1,7 @@ -.. _tfm_ipc: +.. zephyr:code-sample:: tfm_ipc + :name: TF-M IPC -TF-M IPC -######## + Implement communication between the secure and non-secure images using IPC. Overview ******** diff --git a/samples/tfm_integration/tfm_psa_test/README.rst b/samples/tfm_integration/tfm_psa_test/README.rst index 73944b6ec656aa1..62ae6fa9af1dbab 100644 --- a/samples/tfm_integration/tfm_psa_test/README.rst +++ b/samples/tfm_integration/tfm_psa_test/README.rst @@ -40,12 +40,12 @@ Note that not all test suites are valid on all boards. On Target ========= -Refer to :ref:`tfm_ipc` for detailed instructions. +Refer to :zephyr:code-sample:`tfm_ipc` for detailed instructions. On QEMU: ======== -Refer to :ref:`tfm_ipc` for detailed instructions. +Refer to :zephyr:code-sample:`tfm_ipc` for detailed instructions. Following is an example based on ``west build`` .. code-block:: bash diff --git a/samples/tfm_integration/tfm_regression_test/README.rst b/samples/tfm_integration/tfm_regression_test/README.rst index 2257414344f02b3..047bd79b2216487 100644 --- a/samples/tfm_integration/tfm_regression_test/README.rst +++ b/samples/tfm_integration/tfm_regression_test/README.rst @@ -24,12 +24,12 @@ Tests for both the secure and non-secure domain are enabled by default, controll On Target ========= -Refer to :ref:`tfm_ipc` for detailed instructions. +Refer to :zephyr:code-sample:`tfm_ipc` for detailed instructions. On QEMU: ======== -Refer to :ref:`tfm_ipc` for detailed instructions. +Refer to :zephyr:code-sample:`tfm_ipc` for detailed instructions. Following is an example based on ``west build`` .. code-block:: bash diff --git a/samples/tfm_integration/tfm_secure_partition/README.rst b/samples/tfm_integration/tfm_secure_partition/README.rst index 94158ef06d857db..8150fead862a56f 100644 --- a/samples/tfm_integration/tfm_secure_partition/README.rst +++ b/samples/tfm_integration/tfm_secure_partition/README.rst @@ -1,7 +1,7 @@ -.. _tfm_secure_partition: +.. zephyr:code-sample:: tfm_secure_partition + :name: TF-M Secure Partition -TF-M Secure Partition Sample -############################ + Create a secure partition that exposes secure services. Overview ******** @@ -38,12 +38,12 @@ This sample can be built with or without CONFIG_TFM_IPC, since it contains code On Target ========= -Refer to :ref:`tfm_ipc` for detailed instructions. +Refer to :zephyr:code-sample:`tfm_ipc` for detailed instructions. On QEMU ======= -Refer to :ref:`tfm_ipc` for detailed instructions. +Refer to :zephyr:code-sample:`tfm_ipc` for detailed instructions. Sample Output ============= From 9cb349076266b4f83f8eee327f80b7ec81b8f2aa Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Wed, 11 Sep 2024 16:21:15 +0300 Subject: [PATCH 002/269] samples: net: http_server: Add information about overlays Enhance documentation and add overlay information to readme file. Signed-off-by: Jukka Rissanen --- samples/net/sockets/http_server/README.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/samples/net/sockets/http_server/README.rst b/samples/net/sockets/http_server/README.rst index 9c039f4a8540caa..33c2f2874e45c4a 100644 --- a/samples/net/sockets/http_server/README.rst +++ b/samples/net/sockets/http_server/README.rst @@ -20,6 +20,20 @@ Requirement Building and running the server ------------------------------- +There are configuration files for various setups in the +:zephyr_file:`samples/net/sockets/http_server` directory: + +.. list-table:: + + * - :zephyr_file:`prj.conf ` + - This is the standard default config. + + * - :zephyr_file:`ieee802154-overlay.conf ` + - This overlay config can be added for IEEE 802.15.4 support. + + * - :zephyr_file:`overlay-netusb.conf ` + - This overlay config can be added for connecting via network USB. + To build and run the application: .. code-block:: bash From aa3dd674a97b60fe6a829942e3b21618070f56ab Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Tue, 10 Sep 2024 10:22:46 -0300 Subject: [PATCH 003/269] soc: esp32xx: update flash initialization Rework how flash is initialized in esp32 SoC. "esp_flash_app_init()" will make sure proper cache handling will be set in place.i Fixes #77551 Signed-off-by: Sylvio Alves --- soc/espressif/esp32/soc.c | 19 +++++-------------- soc/espressif/esp32c2/soc.c | 21 ++++----------------- soc/espressif/esp32c3/soc.c | 21 ++++----------------- soc/espressif/esp32c6/soc.c | 7 ++++--- soc/espressif/esp32s2/soc.c | 17 ++++------------- soc/espressif/esp32s3/soc.c | 27 ++++++++++++--------------- west.yml | 2 +- 7 files changed, 34 insertions(+), 80 deletions(-) diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c index ad50f3210a462d8..3a1fa2041d1ca5e 100644 --- a/soc/espressif/esp32/soc.c +++ b/soc/espressif/esp32/soc.c @@ -13,6 +13,7 @@ #include #include #include +#include #if CONFIG_ESP_SPIRAM #include "psram.h" #endif @@ -141,26 +142,16 @@ void IRAM_ATTR __esp_platform_start(void) esp_start_appcpu(); #endif - esp_mmu_map_init(); - -#ifdef CONFIG_SOC_FLASH_ESP32 esp_mspi_pin_init(); - spi_flash_init_chip_state(); -#endif + + esp_flash_app_init(); + + esp_mmu_map_init(); #if CONFIG_ESP_SPIRAM esp_init_psram(); #endif /* CONFIG_ESP_SPIRAM */ -/* Scheduler is not started at this point. Hence, guard functions - * must be initialized after esp_spiram_init_cache which internally - * uses guard functions. Setting guard functions before SPIRAM - * cache initialization will result in a crash. - */ -#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif - #endif /* !CONFIG_MCUBOOT */ esp_intr_initialize(); diff --git a/soc/espressif/esp32c2/soc.c b/soc/espressif/esp32c2/soc.c index c1cc3e3e8065987..9ed4bbcb4370ffa 100644 --- a/soc/espressif/esp32c2/soc.c +++ b/soc/espressif/esp32c2/soc.c @@ -21,6 +21,7 @@ #include #include #include "esp_private/esp_mmu_map_private.h" +#include #include @@ -66,28 +67,14 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN); SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); -#ifdef CONFIG_SOC_FLASH_ESP32 + esp_timer_early_init(); + esp_mspi_pin_init(); - /** - * This function initialise the Flash chip to the user-defined settings. - * - * In bootloader, we only init Flash (and MSPI) to a preliminary - * state, for being flexible to different chips. - * In this stage, we re-configure the Flash (and MSPI) to required configuration - */ - spi_flash_init_chip_state(); + esp_flash_app_init(); esp_mmu_map_init(); -#endif /*CONFIG_SOC_FLASH_ESP32*/ - - esp_timer_early_init(); - -#if CONFIG_SOC_FLASH_ESP32 - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif - #endif /* !CONFIG_MCUBOOT */ /*Initialize the esp32c2 interrupt controller */ diff --git a/soc/espressif/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c index 61a4cb4c83ff791..aa21357e72876ab 100644 --- a/soc/espressif/esp32c3/soc.c +++ b/soc/espressif/esp32c3/soc.c @@ -21,6 +21,7 @@ #include #include #include "esp_private/esp_mmu_map_private.h" +#include #include @@ -66,28 +67,14 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN); SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); -#ifdef CONFIG_SOC_FLASH_ESP32 + esp_timer_early_init(); + esp_mspi_pin_init(); - /** - * This function initialise the Flash chip to the user-defined settings. - * - * In bootloader, we only init Flash (and MSPI) to a preliminary - * state, for being flexible to different chips. - * In this stage, we re-configure the Flash (and MSPI) to required configuration - */ - spi_flash_init_chip_state(); + esp_flash_app_init(); esp_mmu_map_init(); -#endif /*CONFIG_SOC_FLASH_ESP32*/ - - esp_timer_early_init(); - -#if CONFIG_SOC_FLASH_ESP32 - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif - #endif /* !CONFIG_MCUBOOT */ /*Initialize the esp32c3 interrupt controller */ diff --git a/soc/espressif/esp32c6/soc.c b/soc/espressif/esp32c6/soc.c index 2a30fe457310f39..1c8877d85416a47 100644 --- a/soc/espressif/esp32c6/soc.c +++ b/soc/espressif/esp32c6/soc.c @@ -19,6 +19,7 @@ #include #include #include "esp_private/esp_mmu_map_private.h" +#include #include @@ -58,9 +59,9 @@ void IRAM_ATTR __esp_platform_start(void) esp_timer_early_init(); -#if CONFIG_SOC_FLASH_ESP32 - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif + esp_mspi_pin_init(); + + esp_flash_app_init(); esp_mmu_map_init(); diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c index 6414bc23928ff12..02a6d1b4dc6fbb8 100644 --- a/soc/espressif/esp32s2/soc.c +++ b/soc/espressif/esp32s2/soc.c @@ -96,10 +96,11 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_config_data_cache_mode(); esp_rom_Cache_Enable_DCache(0); -#ifdef CONFIG_SOC_FLASH_ESP32 + esp_timer_early_init(); + esp_mspi_pin_init(); - spi_flash_init_chip_state(); -#endif /* CONFIG_SOC_FLASH_ESP32 */ + + esp_flash_app_init(); esp_mmu_map_init(); @@ -107,16 +108,6 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) esp_init_psram(); #endif /* CONFIG_ESP_SPIRAM */ - esp_timer_early_init(); - - /* Scheduler is not started at this point. Hence, guard functions - * must be initialized after esp_spiram_init_cache which internally - * uses guard functions. Setting guard functions before SPIRAM - * cache initialization will result in a crash. - */ -#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif #endif /* !CONFIG_MCUBOOT */ esp_intr_initialize(); diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c index 079a879326c3836..538a811aa6fc7a8 100644 --- a/soc/espressif/esp32s3/soc.c +++ b/soc/espressif/esp32s3/soc.c @@ -145,18 +145,6 @@ void IRAM_ATTR __esp_platform_start(void) */ esp_config_data_cache_mode(); - esp_mspi_pin_init(); - - spi_flash_init_chip_state(); - - mspi_timing_flash_tuning(); - - esp_mmu_map_init(); - -#if CONFIG_ESP_SPIRAM - esp_init_psram(); -#endif /* CONFIG_ESP_SPIRAM */ - /* Apply SoC patches */ esp_errata(); @@ -174,14 +162,23 @@ void IRAM_ATTR __esp_platform_start(void) esp_timer_early_init(); + esp_mspi_pin_init(); + + esp_flash_app_init(); + + mspi_timing_flash_tuning(); + + esp_mmu_map_init(); + +#if CONFIG_ESP_SPIRAM + esp_init_psram(); +#endif /* CONFIG_ESP_SPIRAM */ + #if CONFIG_SOC_ENABLE_APPCPU /* start the ESP32S3 APP CPU */ esp_start_appcpu(); #endif -#if CONFIG_SOC_FLASH_ESP32 - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif #endif /* !CONFIG_MCUBOOT */ esp_intr_initialize(); diff --git a/west.yml b/west.yml index af1df50dc33a6f3..87c90565d468acf 100644 --- a/west.yml +++ b/west.yml @@ -157,7 +157,7 @@ manifest: groups: - hal - name: hal_espressif - revision: a79e607333bbd115a16e801ba49840a80c852253 + revision: aa6a967d1ab4077691aa046229a782102960218a path: modules/hal/espressif west-commands: west/west-commands.yml groups: From 49bd80828d38edf3692f5dded47f4fd90d885225 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 11 Sep 2024 11:40:03 +0200 Subject: [PATCH 004/269] Bluetooth: VOCS: Replace bools with atomic Replace the booleans used by the VOCS client to use an atomic value instead. The flags are modified to be used in a way that prevents race conditions. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/vocs_client.c | 98 ++++++++++++++------------ subsys/bluetooth/audio/vocs_internal.h | 17 +++-- 2 files changed, 65 insertions(+), 50 deletions(-) diff --git a/subsys/bluetooth/audio/vocs_client.c b/subsys/bluetooth/audio/vocs_client.c index e08b8cb3729e1bf..b9f9f56bc37e645 100644 --- a/subsys/bluetooth/audio/vocs_client.c +++ b/subsys/bluetooth/audio/vocs_client.c @@ -44,9 +44,8 @@ static struct bt_vocs_client *lookup_vocs_by_handle(struct bt_conn *conn, uint16 for (int i = 0; i < ARRAY_SIZE(insts); i++) { if (insts[i].conn == conn && - insts[i].active && - insts[i].start_handle <= handle && - insts[i].end_handle >= handle) { + atomic_test_bit(insts[i].flags, BT_VOCS_CLIENT_FLAG_ACTIVE) && + insts[i].start_handle <= handle && insts[i].end_handle >= handle) { return &insts[i]; } } @@ -134,7 +133,7 @@ static uint8_t vocs_client_read_offset_state_cb(struct bt_conn *conn, uint8_t er } LOG_DBG("Inst %p: err: 0x%02X", inst, err); - inst->busy = false; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); if (cb_err) { LOG_DBG("Offset state read failed: %d", err); @@ -175,7 +174,7 @@ static uint8_t vocs_client_read_location_cb(struct bt_conn *conn, uint8_t err, } LOG_DBG("Inst %p: err: 0x%02X", inst, err); - inst->busy = false; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); if (cb_err) { LOG_DBG("Offset state read failed: %d", err); @@ -226,7 +225,7 @@ static uint8_t internal_read_volume_offset_state_cb(struct bt_conn *conn, uint8_ inst->state.change_counter); /* clear busy flag to reuse function */ - inst->busy = false; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); write_err = bt_vocs_client_state_set(inst, inst->cp.offset); if (write_err) { cb_err = BT_ATT_ERR_UNLIKELY; @@ -242,7 +241,7 @@ static uint8_t internal_read_volume_offset_state_cb(struct bt_conn *conn, uint8_ } if (cb_err) { - inst->busy = false; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); if (inst->cb && inst->cb->set_offset) { inst->cb->set_offset(&inst->vocs, err); @@ -272,7 +271,8 @@ static void vocs_client_write_vocs_cp_cb(struct bt_conn *conn, uint8_t err, * change counter has been read, we restart the applications write request. If it fails * the second time, we return an error to the application. */ - if (cb_err == BT_VOCS_ERR_INVALID_COUNTER && inst->cp_retried) { + if (cb_err == BT_VOCS_ERR_INVALID_COUNTER && + atomic_test_bit(inst->flags, BT_VOCS_CLIENT_FLAG_CP_RETRIED)) { cb_err = BT_ATT_ERR_UNLIKELY; } else if (cb_err == BT_VOCS_ERR_INVALID_COUNTER && inst->state_handle) { LOG_DBG("Invalid change counter. Reading volume offset state from server."); @@ -281,18 +281,19 @@ static void vocs_client_write_vocs_cp_cb(struct bt_conn *conn, uint8_t err, inst->read_params.handle_count = 1; inst->read_params.single.handle = inst->state_handle; + atomic_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_CP_RETRIED); + cb_err = bt_gatt_read(conn, &inst->read_params); if (cb_err) { LOG_WRN("Could not read Volume offset state: %d", cb_err); } else { - inst->cp_retried = true; /* Wait for read callback */ return; } } - inst->busy = false; - inst->cp_retried = false; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_CP_RETRIED); + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); if (inst->cb && inst->cb->set_offset) { inst->cb->set_offset(&inst->vocs, cb_err); @@ -315,7 +316,7 @@ static uint8_t vocs_client_read_output_desc_cb(struct bt_conn *conn, uint8_t err } LOG_DBG("Inst %p: err: 0x%02X", inst, err); - inst->busy = false; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); if (cb_err) { LOG_DBG("Description read failed: %d", err); @@ -358,7 +359,7 @@ static uint8_t vocs_discover_func(struct bt_conn *conn, const struct bt_gatt_att if (!attr) { LOG_DBG("Discovery complete for VOCS %p", inst); - inst->busy = false; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); (void)memset(params, 0, sizeof(*params)); if (inst->cb && inst->cb->discover) { @@ -393,7 +394,7 @@ static uint8_t vocs_discover_func(struct bt_conn *conn, const struct bt_gatt_att sub_params = &inst->location_sub_params; } if (chrc->properties & BT_GATT_CHRC_WRITE_WITHOUT_RESP) { - inst->location_writable = true; + atomic_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_LOC_WRITABLE); } } else if (!bt_uuid_cmp(chrc->uuid, BT_UUID_VOCS_CONTROL)) { LOG_DBG("Control point"); @@ -405,7 +406,7 @@ static uint8_t vocs_discover_func(struct bt_conn *conn, const struct bt_gatt_att sub_params = &inst->desc_sub_params; } if (chrc->properties & BT_GATT_CHRC_WRITE_WITHOUT_RESP) { - inst->desc_writable = true; + atomic_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_DESC_WRITABLE); } } @@ -455,8 +456,8 @@ int bt_vocs_client_state_get(struct bt_vocs_client *inst) return -EINVAL; } - if (inst->busy) { - LOG_DBG("Handle not set"); + if (atomic_test_and_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY)) { + LOG_DBG("Instance is busy"); return -EBUSY; } @@ -466,8 +467,8 @@ int bt_vocs_client_state_get(struct bt_vocs_client *inst) inst->read_params.single.offset = 0U; err = bt_gatt_read(inst->conn, &inst->read_params); - if (!err) { - inst->busy = true; + if (err != 0) { + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); } return err; @@ -493,13 +494,16 @@ int bt_vocs_client_location_set(struct bt_vocs_client *inst, uint32_t location) if (!inst->location_handle) { LOG_DBG("Handle not set"); return -EINVAL; - } else if (inst->busy) { - return -EBUSY; - } else if (!inst->location_writable) { + } else if (!atomic_test_bit(inst->flags, BT_VOCS_CLIENT_FLAG_LOC_WRITABLE)) { LOG_DBG("Location is not writable on peer service instance"); return -EPERM; + } else if (atomic_test_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY)) { + LOG_DBG("Instance is busy"); + return -EBUSY; } + /* When using write without response we do not set the busy flag */ + return bt_gatt_write_without_response(inst->conn, inst->location_handle, &location, sizeof(location), @@ -523,7 +527,8 @@ int bt_vocs_client_location_get(struct bt_vocs_client *inst) if (!inst->location_handle) { LOG_DBG("Handle not set"); return -EINVAL; - } else if (inst->busy) { + } else if (atomic_test_and_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY)) { + LOG_DBG("Instance is busy"); return -EBUSY; } @@ -533,8 +538,8 @@ int bt_vocs_client_location_get(struct bt_vocs_client *inst) inst->read_params.single.offset = 0U; err = bt_gatt_read(inst->conn, &inst->read_params); - if (!err) { - inst->busy = true; + if (err != 0) { + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); } return err; @@ -562,7 +567,8 @@ int bt_vocs_client_state_set(struct bt_vocs_client *inst, int16_t offset) if (!inst->control_handle) { LOG_DBG("Handle not set"); return -EINVAL; - } else if (inst->busy) { + } else if (atomic_test_and_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY)) { + LOG_DBG("Instance is busy"); return -EBUSY; } @@ -577,8 +583,8 @@ int bt_vocs_client_state_set(struct bt_vocs_client *inst, int16_t offset) inst->write_params.func = vocs_client_write_vocs_cp_cb; err = bt_gatt_write(inst->conn, &inst->write_params); - if (!err) { - inst->busy = true; + if (err != 0) { + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); } return err; @@ -601,7 +607,8 @@ int bt_vocs_client_description_get(struct bt_vocs_client *inst) if (!inst->desc_handle) { LOG_DBG("Handle not set"); return -EINVAL; - } else if (inst->busy) { + } else if (atomic_test_and_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY)) { + LOG_DBG("Instance is busy"); return -EBUSY; } @@ -611,8 +618,8 @@ int bt_vocs_client_description_get(struct bt_vocs_client *inst) inst->read_params.single.offset = 0U; err = bt_gatt_read(inst->conn, &inst->read_params); - if (!err) { - inst->busy = true; + if (err != 0) { + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); } return err; @@ -634,13 +641,16 @@ int bt_vocs_client_description_set(struct bt_vocs_client *inst, if (!inst->desc_handle) { LOG_DBG("Handle not set"); return -EINVAL; - } else if (inst->busy) { - return -EBUSY; - } else if (!inst->desc_writable) { + } else if (!atomic_test_bit(inst->flags, BT_VOCS_CLIENT_FLAG_DESC_WRITABLE)) { LOG_DBG("Description is not writable on peer service instance"); return -EPERM; + } else if (atomic_test_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY)) { + LOG_DBG("Instance is busy"); + return -EBUSY; } + /* When using write without response we do not set the busy flag */ + return bt_gatt_write_without_response(inst->conn, inst->desc_handle, description, @@ -650,9 +660,8 @@ int bt_vocs_client_description_set(struct bt_vocs_client *inst, struct bt_vocs *bt_vocs_client_free_instance_get(void) { for (int i = 0; i < ARRAY_SIZE(insts); i++) { - if (!insts[i].active) { + if (!atomic_test_and_set_bit(insts[i].flags, BT_VOCS_CLIENT_FLAG_ACTIVE)) { insts[i].vocs.client_instance = true; - insts[i].active = true; return &insts[i].vocs; } } @@ -689,9 +698,11 @@ int bt_vocs_client_conn_get(const struct bt_vocs *vocs, struct bt_conn **conn) static void vocs_client_reset(struct bt_vocs_client *inst) { memset(&inst->state, 0, sizeof(inst->state)); - inst->location_writable = 0; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_LOC_WRITABLE); + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_DESC_WRITABLE); + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_CP_RETRIED); + inst->location = 0; - inst->desc_writable = 0; inst->start_handle = 0; inst->end_handle = 0; inst->state_handle = 0; @@ -733,12 +744,10 @@ int bt_vocs_discover(struct bt_conn *conn, struct bt_vocs *vocs, inst = CONTAINER_OF(vocs, struct bt_vocs_client, vocs); - CHECKIF(!inst->active) { + if (!atomic_test_bit(inst->flags, BT_VOCS_CLIENT_FLAG_ACTIVE)) { LOG_DBG("Inactive instance"); return -EINVAL; - } - - if (inst->busy) { + } else if (atomic_test_and_set_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY)) { LOG_DBG("Instance is busy"); return -EBUSY; } @@ -752,10 +761,9 @@ int bt_vocs_discover(struct bt_conn *conn, struct bt_vocs *vocs, inst->discover_params.func = vocs_discover_func; err = bt_gatt_discover(conn, &inst->discover_params); - if (err) { + if (err != 0) { LOG_DBG("Discover failed (err %d)", err); - } else { - inst->busy = true; + atomic_clear_bit(inst->flags, BT_VOCS_CLIENT_FLAG_BUSY); } return err; diff --git a/subsys/bluetooth/audio/vocs_internal.h b/subsys/bluetooth/audio/vocs_internal.h index 2acbf1c84546cdf..0e79201b4c5d3d6 100644 --- a/subsys/bluetooth/audio/vocs_internal.h +++ b/subsys/bluetooth/audio/vocs_internal.h @@ -42,13 +42,20 @@ struct bt_vocs { bool client_instance; }; +enum bt_vocs_client_flag { + BT_VOCS_CLIENT_FLAG_BUSY, + BT_VOCS_CLIENT_FLAG_CP_RETRIED, + BT_VOCS_CLIENT_FLAG_DESC_WRITABLE, + BT_VOCS_CLIENT_FLAG_LOC_WRITABLE, + BT_VOCS_CLIENT_FLAG_ACTIVE, + + BT_VOCS_CLIENT_FLAG_NUM_FLAGS, /* keep as last */ +}; + struct bt_vocs_client { struct bt_vocs vocs; struct bt_vocs_state state; - bool location_writable; uint32_t location; - bool desc_writable; - bool active; uint16_t start_handle; uint16_t end_handle; @@ -59,15 +66,15 @@ struct bt_vocs_client { struct bt_gatt_subscribe_params state_sub_params; struct bt_gatt_subscribe_params location_sub_params; struct bt_gatt_subscribe_params desc_sub_params; - bool cp_retried; - bool busy; struct bt_vocs_control cp; struct bt_gatt_write_params write_params; struct bt_gatt_read_params read_params; struct bt_vocs_cb *cb; struct bt_gatt_discover_params discover_params; struct bt_conn *conn; + + ATOMIC_DEFINE(flags, BT_VOCS_CLIENT_FLAG_NUM_FLAGS); }; enum bt_vocs_notify { From df294e34e15d15e2320e1ba09dc700f830669fe3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Tue, 10 Sep 2024 19:51:57 +0200 Subject: [PATCH 005/269] doc: sphinx-lint: fix bad usage of "default role" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes bad usage of single backticks in lieu of double backticks for rendering inline literals, or simple '*' for italics. When appropriate, a better construct than double backticks has been selected (ex. :file:, :kconfig:option:, :c:func:, ...), or proper :ref: have been used if the original intention was to have a link. Signed-off-by: Benjamin Cabé --- .../adafruit/feather_nrf52840/doc/index.rst | 4 +-- boards/adafruit/kb2040/doc/index.rst | 2 +- boards/adafruit/qt_py_rp2040/doc/index.rst | 2 +- boards/ambiq/apollo3_evb/doc/index.rst | 2 +- boards/ambiq/apollo3p_evb/doc/index.rst | 2 +- .../ambiq/apollo4p_blue_kxr_evb/doc/index.rst | 2 +- boards/ambiq/apollo4p_evb/doc/index.rst | 2 +- boards/arduino/nano_33_ble/doc/index.rst | 2 +- .../arm/fvp_base_revc_2xaemv8a/doc/index.rst | 2 +- boards/circuitdojo/feather/doc/index.rst | 2 +- boards/ct/ctcc/doc/index.rst | 4 +-- .../enjoydigital/litex_vexriscv/doc/index.rst | 2 +- boards/intel/rpl/doc/index.rst | 2 +- .../intel/socfpga/agilex5_socdk/doc/index.rst | 2 +- boards/m5stack/m5stack_core2/doc/index.rst | 2 +- boards/native/doc/arch_soc.rst | 8 +++--- boards/native/doc/bsim_boards_design.rst | 24 +++++++++--------- boards/nxp/lpcxpresso54114/doc/index.rst | 4 +-- boards/nxp/lpcxpresso55s69/doc/index.rst | 2 +- boards/nxp/mimxrt1040_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1170_evk/doc/index.rst | 6 ++--- boards/nxp/rd_rw612_bga/doc/index.rst | 2 +- boards/nxp/s32z2xxdc2/doc/index.rst | 2 +- boards/phytec/phyboard_electra/doc/index.rst | 8 +++--- .../doc/phyboard_lyra_am62xx_m4.rst | 11 +++++--- boards/rak/rak11720/doc/index.rst | 2 +- boards/raspberrypi/rpi_5/doc/index.rst | 11 ++++---- boards/raspberrypi/rpi_pico/doc/index.rst | 25 ++++++++++--------- boards/renesas/rzt2m_starterkit/doc/index.rst | 4 +-- boards/seeed/xiao_ble/doc/index.rst | 6 ++--- boards/seeed/xiao_esp32c3/doc/index.rst | 2 +- .../mikroe_mcp2518fd_click/doc/index.rst | 2 +- .../rpi_pico_uno_flexypin/doc/index.rst | 11 ++++---- boards/silabs/dev_kits/sltb010a/doc/index.rst | 2 +- .../dev_kits/xg27_dk2602a/doc/index.rst | 6 ++--- boards/sparkfun/micromod/doc/index.rst | 3 ++- .../sparkfun/pro_micro_rp2040/doc/index.rst | 4 +-- boards/sparkfun/thing_plus/doc/index.rst | 2 +- boards/st/b_u585i_iot02a/doc/index.rst | 4 +-- .../st/nucleo_l552ze_q/doc/nucleol552ze_q.rst | 6 ++--- boards/st/stm32l562e_dk/doc/index.rst | 4 +-- boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst | 4 +-- boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst | 4 +-- boards/telink/tlsr9518adk80d/doc/index.rst | 2 +- boards/ti/sk_am62/doc/index.rst | 10 +++++--- boards/wiznet/w5500_evb_pico/doc/index.rst | 24 +++++++++--------- .../api/audio/bluetooth-le-audio-arch.rst | 24 +++++++++--------- .../bluetooth/bluetooth-shell.rst | 2 +- .../networking/api/coap_client.rst | 8 +++--- .../networking/api/tls_credentials_shell.rst | 2 +- doc/connectivity/networking/api/wifi.rst | 11 ++++---- .../usb/device_next/usb_device.rst | 2 +- doc/contribute/index.rst | 2 +- doc/develop/debug/index.rst | 2 +- doc/develop/manifest/index.rst | 4 +-- doc/develop/modules.rst | 6 ++--- doc/develop/test/pytest.rst | 2 +- doc/develop/test/twister.rst | 20 +++++++-------- doc/develop/test/ztest.rst | 2 +- doc/develop/tools/vscode.rst | 2 +- doc/develop/west/sign.rst | 2 +- doc/glossary.rst | 2 +- doc/hardware/arch/risc-v.rst | 6 ++--- doc/hardware/emulator/bus_emulators.rst | 2 +- doc/hardware/peripherals/uart.rst | 6 ++--- doc/kernel/object_cores/index.rst | 2 +- doc/kernel/services/interrupts.rst | 8 +++--- doc/project/release_process.rst | 2 +- doc/releases/index.rst | 2 +- doc/releases/migration-guide-4.0.rst | 10 ++++---- doc/releases/release-notes-4.0.rst | 4 +-- doc/security/standards/etsi-303645.rst | 2 +- doc/services/device_mgmt/ec_host_cmd.rst | 8 +++--- .../device_mgmt/smp_groups/smp_group_0.rst | 2 +- doc/services/device_mgmt/smp_transport.rst | 4 +-- doc/services/input/gpio-kbd.rst | 2 +- doc/services/llext/build.rst | 8 +++--- doc/services/llext/config.rst | 2 +- doc/services/logging/index.rst | 2 +- doc/services/mem_mgmt/index.rst | 4 +-- doc/services/pm/device_runtime.rst | 2 +- .../portability/posix/conformance/index.rst | 4 ++- doc/services/storage/flash_map/flash_map.rst | 2 +- doc/services/tracing/index.rst | 2 +- doc/services/zbus/index.rst | 7 +++--- .../bluetooth/bap_broadcast_sink/README.rst | 10 ++++---- .../bluetooth/bap_broadcast_source/README.rst | 4 +-- .../bluetooth/bap_unicast_client/README.rst | 4 +-- .../bluetooth/bap_unicast_server/README.rst | 4 +-- .../bluetooth/broadcaster_multiple/README.rst | 4 +-- samples/bluetooth/cap_acceptor/README.rst | 2 +- samples/bluetooth/cap_initiator/README.rst | 2 +- .../encrypted_advertising/README.rst | 2 +- samples/bluetooth/extended_adv/README.rst | 2 +- samples/bluetooth/hci_uart/README.rst | 4 +-- samples/bluetooth/hci_uart_3wire/README.rst | 4 +-- samples/bluetooth/hci_uart_async/README.rst | 4 +-- samples/bluetooth/iso_broadcast/README.rst | 2 +- samples/bluetooth/iso_receive/README.rst | 2 +- samples/bluetooth/observer/README.rst | 2 +- .../pbp_public_broadcast_sink/README.rst | 4 +-- .../pbp_public_broadcast_source/README.rst | 4 +-- samples/bluetooth/peripheral_hids/README.rst | 2 +- .../espressif/flash_memory_mapped/README.rst | 2 +- .../boards/espressif/spiram_test/README.rst | 4 +-- samples/boards/espressif/xt_wdt/README.rst | 2 +- samples/boards/nxp/s32/netc/README.rst | 6 ++--- samples/boards/st/uart/single_wire/README.rst | 2 +- samples/drivers/auxdisplay/README.rst | 4 +-- samples/drivers/dac/README.rst | 3 +-- .../drivers/fpga/fpga_controller/README.rst | 8 +++--- samples/drivers/led/is31fl3733/README.rst | 2 +- samples/drivers/mspi/mspi_async/README.rst | 2 +- samples/drivers/mspi/mspi_flash/README.rst | 2 +- samples/fuel_gauge/max17048/README.rst | 2 +- .../tflite-micro/hello_world/README.rst | 2 +- samples/philosophers/README.rst | 2 +- samples/subsys/dap/README.rst | 4 +-- samples/subsys/fs/format/README.rst | 3 ++- samples/subsys/fs/littlefs/README.rst | 18 ++++++------- samples/subsys/llext/shell_loader/README.rst | 6 ++--- samples/subsys/usb/shell/README.rst | 2 +- samples/sysbuild/with_mcuboot/README.rst | 2 +- .../pylib/pytest-twister-harness/README.rst | 4 +-- snippets/xen_dom0/README.rst | 14 +++++++---- .../boards/espressif_esp32/rtc_clk/README.rst | 2 +- tests/ztest/fail/README.rst | 2 +- 127 files changed, 304 insertions(+), 285 deletions(-) diff --git a/boards/adafruit/feather_nrf52840/doc/index.rst b/boards/adafruit/feather_nrf52840/doc/index.rst index e4e62c0556efbda..7ab630978d43a6b 100644 --- a/boards/adafruit/feather_nrf52840/doc/index.rst +++ b/boards/adafruit/feather_nrf52840/doc/index.rst @@ -181,8 +181,8 @@ but does not support debugging the device. #. If using UF2, connect the board to your host computer using USB. #. Tap the reset button twice quickly to enter bootloader mode. - A mass storage device named `FTHR840BOOT` for (Express) or - `FTHRSNSBOOT` (Sense) should appear on the host. Ensure this is + A mass storage device named ``FTHR840BOOT`` for (Express) or + ``FTHRSNSBOOT`` (Sense) should appear on the host. Ensure this is mounted. #. Flash the image. diff --git a/boards/adafruit/kb2040/doc/index.rst b/boards/adafruit/kb2040/doc/index.rst index 09d5bfb096011e2..58b53aec81518bc 100644 --- a/boards/adafruit/kb2040/doc/index.rst +++ b/boards/adafruit/kb2040/doc/index.rst @@ -117,7 +117,7 @@ Using UF2 Since it doesn't expose the SWD pins, you must flash the Adafruit KB2040 with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the KB2040 is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the KB2040 is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the KB2040. diff --git a/boards/adafruit/qt_py_rp2040/doc/index.rst b/boards/adafruit/qt_py_rp2040/doc/index.rst index 19b5a832223a583..bf081c029b74a0c 100644 --- a/boards/adafruit/qt_py_rp2040/doc/index.rst +++ b/boards/adafruit/qt_py_rp2040/doc/index.rst @@ -116,7 +116,7 @@ Using UF2 Since it doesn't expose the SWD pins, you must flash the Adafruit QT Py RP2040 with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the QT Py RP2040 is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the QT Py RP2040 is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the QT Py RP2040. diff --git a/boards/ambiq/apollo3_evb/doc/index.rst b/boards/ambiq/apollo3_evb/doc/index.rst index 12990d0c9fec1c8..1982236becf7546 100644 --- a/boards/ambiq/apollo3_evb/doc/index.rst +++ b/boards/ambiq/apollo3_evb/doc/index.rst @@ -69,7 +69,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/ambiq/apollo3p_evb/doc/index.rst b/boards/ambiq/apollo3p_evb/doc/index.rst index 9d56556d69c55fb..58b354288d2580e 100644 --- a/boards/ambiq/apollo3p_evb/doc/index.rst +++ b/boards/ambiq/apollo3p_evb/doc/index.rst @@ -69,7 +69,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst index 214b5d4c2ef3a8b..33a68ce8875937e 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -77,7 +77,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst index 7c5cd174cf6f5e9..662b6c41515a514 100644 --- a/boards/ambiq/apollo4p_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_evb/doc/index.rst @@ -72,7 +72,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/arduino/nano_33_ble/doc/index.rst b/boards/arduino/nano_33_ble/doc/index.rst index 05c0605b4645068..2b5ede0ea114fef 100644 --- a/boards/arduino/nano_33_ble/doc/index.rst +++ b/boards/arduino/nano_33_ble/doc/index.rst @@ -160,7 +160,7 @@ That license ties to Arduino Nano 33 BLE hardware serial number, it also works with the ZephyrRTOS. Follow the instruction of the tutorial for Arduino -`Lauterbach TRACE32 GDB Front-End Debugger for Nano 33 BLE` +`Lauterbach TRACE32 GDB Front-End Debugger for Nano 33 BLE`_ to install the TRACE32. After installing the TRACE32, You should set the environmental variable ``T32_DIR``. diff --git a/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst index 495b7ad11f46930..81a098b3ae1d297 100644 --- a/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst +++ b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst @@ -99,7 +99,7 @@ Checkout and Build the TF-A: cd trusted-firmware-a/ make PLAT=fvp PRELOADED_BL33_BASE="0x88000000" all fip -then export the ``ARMFVP_BL1_FILE` and ``ARMFVP_FIP_FILE`` environment variables: +then export the :envvar:`ARMFVP_BL1_FILE` and :envvar:`ARMFVP_FIP_FILE` environment variables: .. code-block:: console diff --git a/boards/circuitdojo/feather/doc/index.rst b/boards/circuitdojo/feather/doc/index.rst index 1988a00e98f5c28..998cfbcfdac774a 100644 --- a/boards/circuitdojo/feather/doc/index.rst +++ b/boards/circuitdojo/feather/doc/index.rst @@ -100,7 +100,7 @@ or Nordic based examples. Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board. Some of the examples do not use secure mode, so they do not require the -``ns`` suffix. A great example of this is the `hello_world` below. +``ns`` suffix. A great example of this is the ``hello_world`` below. Flashing ======== diff --git a/boards/ct/ctcc/doc/index.rst b/boards/ct/ctcc/doc/index.rst index 38987822b6e920f..914df63b3aae428 100644 --- a/boards/ct/ctcc/doc/index.rst +++ b/boards/ct/ctcc/doc/index.rst @@ -172,7 +172,7 @@ As an example we'll use the :zephyr:code-sample:`usb-cdc-acm-console` sample. .. note:: - In all examples it is assumed to use default `root-rsa-2048.pem` file from ``mcuboot/boot`` + In all examples it is assumed to use default :file:`root-rsa-2048.pem` file from ``mcuboot/boot`` directory. Providing certificate in build args produces signed binary automatically. Do not use this certificate in your production firmware! @@ -180,7 +180,7 @@ As an example we'll use the :zephyr:code-sample:`usb-cdc-acm-console` sample. and plug such adapter to USB port. You should see ``NordicSemiconductor MCUBOOT`` or ``NordicSemiconductor Zephyr DFU sample`` - (if you flashed `dfu` sample to slot0) device once plugging it into host + (if you flashed ``dfu`` sample to slot0) device once plugging it into host USB port. You can check that on Linux system by entering ``lsusb`` command. To check if DFU device is visible you can enter ``sudo dfu-util -l`` command. Once the diff --git a/boards/enjoydigital/litex_vexriscv/doc/index.rst b/boards/enjoydigital/litex_vexriscv/doc/index.rst index 2946802be5e0405..f9764907eb449a0 100644 --- a/boards/enjoydigital/litex_vexriscv/doc/index.rst +++ b/boards/enjoydigital/litex_vexriscv/doc/index.rst @@ -184,7 +184,7 @@ Use `ecpprog `_ to upload the bitstream t ecpprog -S antmicro_sdi_mipi_video_converter.bit -You can boot from a serial port using litex_term (replace `ttyUSBX` with your device) , e.g.: +You can boot from a serial port using litex_term (replace ``ttyUSBX`` with your device) , e.g.: .. code-block:: bash diff --git a/boards/intel/rpl/doc/index.rst b/boards/intel/rpl/doc/index.rst index 4c078ab765ec011..e6bc4015256fe6d 100644 --- a/boards/intel/rpl/doc/index.rst +++ b/boards/intel/rpl/doc/index.rst @@ -23,7 +23,7 @@ please refer to `RPL`_. Raptor Lake Customer Reference Board (RPL CRB) is an example implementation of a compact single board computer with high performance for IoT edge devices. The -supported boards are `intel_rpl_s_crb` and `intel_rpl_p_crb`. +supported boards are ``intel_rpl_s_crb`` and ``intel_rpl_p_crb``. These board configurations enable kernel support for the supported Raptor Lake boards. diff --git a/boards/intel/socfpga/agilex5_socdk/doc/index.rst b/boards/intel/socfpga/agilex5_socdk/doc/index.rst index 006ca06625167d1..4208d8b70be04df 100644 --- a/boards/intel/socfpga/agilex5_socdk/doc/index.rst +++ b/boards/intel/socfpga/agilex5_socdk/doc/index.rst @@ -45,7 +45,7 @@ hardware features: NOTE: TODO, more details on dev kit will be updated as and when available. The default configuration can be found in the defconfig file: - `boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig` +:zephyr_file:`boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig`. Programming and Debugging ************************* diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst index 3e492af3532c915..c7a907a3e3433c0 100644 --- a/boards/m5stack/m5stack_core2/doc/index.rst +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -79,7 +79,7 @@ of the M5Stack Core2 board. | MPU6886 | combines a 3-axis gyroscope and a 3-axis accelerometer. | | | | For details please refer to :ref:`m5stack_core2_ext` | | +------------------+--------------------------------------------------------------------------+-----------+ -| Grove port | Note: Grove port requires 5V to be enabled via `bus_5v` regulator | supported | +| Grove port | Note: Grove port requires 5V to be enabled via ``bus_5v`` regulator | supported | +------------------+--------------------------------------------------------------------------+-----------+ | Built-in | The `SPM-1423`_ I2S driven microphone. | todo | | microphone | | | diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst index 36fd1b01ecf67cf..d07a9c589a2c9aa 100644 --- a/boards/native/doc/arch_soc.rst +++ b/boards/native/doc/arch_soc.rst @@ -183,7 +183,7 @@ Currently, these are the most significant features which are not supported in th * Stack checks: :kconfig:option:`CONFIG_HW_STACK_PROTECTION`, :kconfig:option:`CONFIG_STACK_CANARIES`, and :kconfig:option:`CONFIG_THREAD_ANALYZER`. - This is due to how Zephyr allocated threads' stacks are not `actually` being used like they are + This is due to how Zephyr allocated threads' stacks are not *actually* being used like they are in other architectures. Check :ref:`the architecture section's architecture layer paragraph ` for more information. @@ -355,7 +355,7 @@ while this newly created thread will be the first "SW" thread and start executing the boot of the embedded code (including the POSIX arch code). During this MCU boot process, the Zephyr kernel will be initialized and -eventually this will call into the embedded application `main()`, +eventually this will call into the embedded application ``main()``, just like in the embedded target. As the embedded SW execution progresses, more Zephyr threads may be spawned, and for each the POSIX architecture will create a dedicated pthread. @@ -413,7 +413,7 @@ Busy waits Busy waits work thanks to provided board functionality. This does not need to be the same for all boards, but both native_sim and the nrf52_bsim board work similarly thru the combination of a board specific -`arch_busy_wait()` and a special fake HW timer (provided by the board). +:c:func:`arch_busy_wait()` and a special fake HW timer (provided by the board). When a SW thread wants to busy wait, this fake timer will be programmed in the future time corresponding to the end of the busy wait and the CPU will @@ -422,7 +422,7 @@ When this fake HW timer expires the CPU will be waken with a special non-maskable phony interrupt which does not have a corresponding interrupt handler but will resume the busy_wait SW execution. Note that other interrupts may arrive while the busy wait is in progress, -which may delay the `k_busy_wait()` return just like in real life. +which may delay the :c:func:`k_busy_wait()` return just like in real life. Interrupts may be locked out or masked during this time, but the special fake-timer non-maskable interrupt will wake the CPU nonetheless. diff --git a/boards/native/doc/bsim_boards_design.rst b/boards/native/doc/bsim_boards_design.rst index 7fef9d1b5228bdb..a8d45a5d7058057 100644 --- a/boards/native/doc/bsim_boards_design.rst +++ b/boards/native/doc/bsim_boards_design.rst @@ -16,7 +16,7 @@ Bsim boards This page covers the design, architecture and rationale, of the nrf5x_bsim boards and other similar bsim boards. -These boards are postfixed with `_bsim` as they use BabbleSim_ +These boards are postfixed with ``_bsim`` as they use BabbleSim_ (shortened bsim), to simulate the radio environment. These boards use the `native simulator`_ and the :ref:`POSIX architecture` to build and execute the embedded code natively on Linux. @@ -135,13 +135,13 @@ The basic architecture layering of these boards is as follows: simulation specific ones. - The architecture (arch) is the Zephyr :ref:`POSIX architecture` layer. - The SOC layer is `inf_clock`. And the board layer is dependent on + The SOC layer is ``inf_clock``. And the board layer is dependent on the specific device we are simulating. - The POSIX architecture provides an adaptation from the Zephyr arch API (which handles mostly the thread context switching) to the native simulator CPU thread emulation. See :ref:`POSIX arch architecture` -- The SOC `inf_clock` layer provides an adaptation to the native simulator CPU "simulation" +- The SOC ``inf_clock`` layer provides an adaptation to the native simulator CPU "simulation" and the handling of control between the "CPU simulation" (Zephyr threads) and the HW models thread ( See `Threading`_ ). - The board layer provides all SOC/ IC specific content, including @@ -149,13 +149,13 @@ The basic architecture layering of these boards is as follows: busy wait API (see :ref:`posix_busy_wait`), and Zephyr's printk backend. Note that in a normal Zephyr target interrupt handling and a custom busy wait would be provided by the SOC layer, but abusing Zephyr's layering, and for the - `inf_clock` layer to be generic, these were delegated to the board. + ``inf_clock`` layer to be generic, these were delegated to the board. The board layer provides other test specific functionality like bs_tests hooks, trace control, etc, and by means of the native simulator, provides the :c:func:`main` entry point for the Linux program, command line argument handling, and the overall time scheduling of the simulated device. - Note that the POSIX arch and `inf_clock` soc expect a set of APIs being provided by + Note that the POSIX arch and ``inf_clock`` soc expect a set of APIs being provided by the board. This includes the busy wait API, a basic tracing API, the interrupt controller and interrupt handling APIs, :c:func:`posix_exit`, and :c:func:`posix_get_hw_cycle` (see :file:`posix_board_if.h` and :file:`posix_soc_if.h`). @@ -173,7 +173,7 @@ Important limitations and unsupported features All native and bsim boards share the same set of :ref:`important limitations which` -are inherited from the POSIX arch and `inf_clock` design. +are inherited from the POSIX arch and ``inf_clock`` design. Similarly, they inherit the POSIX architecture :ref:`unsupported features set `. @@ -261,7 +261,7 @@ posix_print and nsi_print backends ================================== The bsim board provides a backend for the ``posix_print`` API which is expected by the posix -ARCH and `inf_clock` code, and for the ``nsi_print`` API expected by the native simulator. +ARCH and ``inf_clock`` code, and for the ``nsi_print`` API expected by the native simulator. These simply route this API calls into the ``bs_trace`` bsim API. Any message printed to these APIs, and by extension by default to Zephyr's ``printk``, @@ -287,12 +287,12 @@ callbacks are assigned to the respective hooks. There is a set of one time hooks at different levels of initialization of the HW and Zephyr OS, a hook to process possible command line arguments, and, a hook that can be used to sniff or capture interrupts. -`bs_tests` also provides a hook which will be called from the embedded application +``bs_tests`` also provides a hook which will be called from the embedded application :c:func:`main`, but this will only work if the main application supports it, that is, if the main app is a version for simulation which calls :c:func:`bst_main` when running in the bsim board. -Apart from these hooks, the `bs_tests` system provides facilities to build a +Apart from these hooks, the ``bs_tests`` system provides facilities to build a dedicated test "task". This will be executed in the HW models thread context, but will have access to all SW variables. This task will be driven with a special timer which can be configured to produce either periodic or one time @@ -302,15 +302,15 @@ at specific points in time. This can be combined with Babblesim's tb_defs macros to build quite complex test tasks which can wait for a given amount of time, for conditions to be fulfilled, etc. -Note when writing the tests with `bs_tests` one needs to be aware that other +Note when writing the tests with ``bs_tests`` one needs to be aware that other bs tests will probably be built with the same application, and that therefore the tests should not be registering initialization or callback functions using NATIVE_TASKS or Zephyr's PRE/POST kernel driver initialization APIs as this will execute even if the test is not selected. -Instead the equivalent `bs_tests` provided hooks should be used. +Instead the equivalent ``bs_tests`` provided hooks should be used. Note also that, for AMP targets like the :ref:`nrf5340bsim `, each embedded MCU has -its own separate `bs_tests` built with that MCU. You can select if and what test is used +its own separate ``bs_tests`` built with that MCU. You can select if and what test is used for each MCU separatedly with the command line options. Command line argument parsing diff --git a/boards/nxp/lpcxpresso54114/doc/index.rst b/boards/nxp/lpcxpresso54114/doc/index.rst index 644de94e415fa07..0402d19d239a80b 100644 --- a/boards/nxp/lpcxpresso54114/doc/index.rst +++ b/boards/nxp/lpcxpresso54114/doc/index.rst @@ -74,8 +74,8 @@ features: The default configuration for each core can be found in the defconfig files: - `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig` - `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig` +- :zephyr_file:`boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig` +- :zephyr_file:`boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig` Other hardware features are not currently supported by the port. diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst index 591770943630331..4c157c9f5f01653 100644 --- a/boards/nxp/lpcxpresso55s69/doc/index.rst +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -299,7 +299,7 @@ board. ----------------------------------------- 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware` + 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware`_ :ref:`opensda-daplink-onboard-debug-probe` ------------------------------------------ diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index 227ad4ff720573d..c6322960f248847 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -335,7 +335,7 @@ Remove resistors from R497, R498, R456 and R457. And due to pin conflict issue, the PCM interface of Bluetooth module cannot be supported. -For the debugger fails to connect with the following error, please refer to section `WiFi Module`. +For the debugger fails to connect with the following error, please refer to the next section. WiFi Module ----------- diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst index f3260f9c2734a3e..c3de9f8fd3bbc0c 100644 --- a/boards/nxp/mimxrt1170_evk/doc/index.rst +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -111,8 +111,8 @@ NXP considers the MIMXRT1170-EVK as the superset board for the i.MX RT11xx family of MCUs. This board is a focus for NXP's Full Platform Support for Zephyr, to better enable the entire RT11xx family. NXP prioritizes enabling this board with new support for Zephyr features. Note that this table -covers two boards: the RT1170 EVK (`mimxrt1170_evk//cm7/cm4`), and -RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`) +covers two boards: the RT1170 EVK (``mimxrt1170_evk//cm7/cm4``), and +RT1170 EVKB (``mimxrt1170_evk@B//cm7/cm4``) +-----------+------------+-------------------------------------+-----------------+-----------------+ | Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB | @@ -478,4 +478,4 @@ ENET1G Driver Current default of ethernet driver is to use 100M Ethernet instance ENET. To use the 1G Ethernet instance ENET1G, include the overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay` instead. +the option ``-DEXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay`` instead. diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index e195913e45c1e51..558effd60a3d1ce 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -196,7 +196,7 @@ Remove resistors: - R508 - R505 -Then, build for the board target `rd_rw612_bga//ethernet`. +Then, build for the board target ``rd_rw612_bga//ethernet``. Resources ********* diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst index 1b7423c693db95d..58e5ea3660c1cc1 100644 --- a/boards/nxp/s32z2xxdc2/doc/index.rst +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -118,7 +118,7 @@ Serial Port =========== The SoC has 12 LINFlexD instances that can be used in UART mode. The console can -be accessed by default on the USB micro-B connector `J119`. +be accessed by default on the USB micro-B connector J119. Watchdog ======== diff --git a/boards/phytec/phyboard_electra/doc/index.rst b/boards/phytec/phyboard_electra/doc/index.rst index 4fe9c5afd551f85..372f8d3cd7347f8 100644 --- a/boards/phytec/phyboard_electra/doc/index.rst +++ b/boards/phytec/phyboard_electra/doc/index.rst @@ -84,7 +84,7 @@ GPIO ---- The phyCORE-AM64x has a heartbeat LED connected to gpio6. It's configured -to build and run the `basic/blinky` sample. +to build and run the :zephyr:code-sample:`blinky` sample. SD Card ******* @@ -111,9 +111,11 @@ To test the M4F core, we build the :ref:`hello_world` sample with the following :zephyr-app: samples/hello_world :goals: build -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. +This builds the program and the binary is present in the :file:`build/zephyr` directory as +:file:`zephyr.elf`. -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am64-mcu-m4f0_0-fw`. +We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as +:file:`am64-mcu-m4f0_0-fw`. .. code-block:: console diff --git a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst index bfd3ff5579f8cee..55d4939529fe0e9 100644 --- a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst +++ b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst @@ -96,16 +96,18 @@ The Linux running on the A53 uses the remoteproc framework to manage the M4F co- Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the `hello_world` sample with the following command. +To test the M4F core, we build the :ref:`hello_world` sample with the following command. .. code-block:: console # From the root of the Zephyr repository west build -p -b phyboard_lyra/am6234/m4 samples/hello_world -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. +This builds the program and the binary is present in the :file:`build/zephyr` directory as +:file:`zephyr.elf`. -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. +We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as +:file:`am62-mcu-m4f0_0-fw`. .. code-block:: console @@ -134,7 +136,8 @@ port. Debugging ********* -The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the `debug` build target: +The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the ``debug`` build +target: .. zephyr-app-commands:: :app: diff --git a/boards/rak/rak11720/doc/index.rst b/boards/rak/rak11720/doc/index.rst index 7f4054a90d5ff2b..ff8e90a962be715 100644 --- a/boards/rak/rak11720/doc/index.rst +++ b/boards/rak/rak11720/doc/index.rst @@ -92,7 +92,7 @@ Build the Zephyr kernel and application, then flash it to the device: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/raspberrypi/rpi_5/doc/index.rst b/boards/raspberrypi/rpi_5/doc/index.rst index 46db56cff268d69..1c63e5a94ad64e0 100644 --- a/boards/raspberrypi/rpi_5/doc/index.rst +++ b/boards/raspberrypi/rpi_5/doc/index.rst @@ -69,7 +69,7 @@ In brief, * `bcm2712-rpi-5.dtb`_ 3. Insert the Micro SD card and power on the Raspberry Pi 5. -then, You will see the Raspberry Pi 5 running the `zephyr.bin`. +then, You will see the Raspberry Pi 5 running the :file:`zephyr.bin`. config.txt ---------- @@ -83,14 +83,15 @@ config.txt zephyr.bin ---------- -Build an app `samples/basic/blinky` +Build an app, for example :zephyr:code-sample:`blinky` .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky :board: rpi_5 :goals: build -Copy `zephyr.bin` from `build/zephyr` directory to the root directory of the Micro SD card. +Copy :file:`zephyr.bin` from :file:`build/zephyr` directory to the root directory of the Micro SD +card. Insert the Micro SD card and power on the Raspberry Pi 5. And then, the STAT LED will start to blink. @@ -125,14 +126,14 @@ config.txt zephyr.bin ---------- -Build an app `samples/hello_world` +Build an app, for example :ref:`hello_world`: .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: rpi_5 :goals: build -Copy `zephyr.bin` from `build/zephyr` directory to the root directory of the Micro SD card. +Copy :file:`zephyr.bin` from :file:`build/zephyr` directory to the root directory of the Micro SD card. Insert the Micro SD card into your Raspberry Pi 5. diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst index d88d1bf4f353823..b2af4693b01abea 100644 --- a/boards/raspberrypi/rpi_pico/doc/index.rst +++ b/boards/raspberrypi/rpi_pico/doc/index.rst @@ -137,11 +137,11 @@ Programmable I/O (PIO) The RP2040 SoC comes with two PIO periherals. These are two simple co-processors that are designed for I/O operations. The PIOs run a custom instruction set, generated from a custom assembly language. -PIO programs are assembled using `pioasm`, a tool provided by Raspberry Pi. +PIO programs are assembled using :command:`pioasm`, a tool provided by Raspberry Pi. Zephyr does not (currently) assemble PIO programs. Rather, they should be manually assembled and embedded in source code. An example of how this is done -can be found at `drivers/serial/uart_rpi_pico_pio.c`. +can be found at :zephyr_file:`drivers/serial/uart_rpi_pico_pio.c`. Sample: SPI via PIO ==================== @@ -187,7 +187,7 @@ Create a file in /etc/udev.rules.d with any name, and write the line below. ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess" -This example is valid for the case that the user joins to `plugdev` groups. +This example is valid for the case that the user joins to ``plugdev`` groups. The Raspberry Pi Pico has an SWD interface that can be used to program and debug the on board RP2040. This interface can be utilized by OpenOCD. @@ -208,22 +208,23 @@ Here is an example of building and flashing the :zephyr:code-sample:`blinky` app :goals: build flash :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap -Set the environment variables **OPENOCD** to `/usr/local/bin/openocd` -and **OPENOCD_DEFAULT_PATH** to `/usr/local/share/openocd/scripts`. This should work +Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd` +and **OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work with the OpenOCD that was installed with the default configuration. This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. **RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. -If **RPI_PICO_DEBUG_ADAPTER** was not assigned, `cmsis-dap` is used by default. -The other supported adapters are `raspberrypi-swd`, `jlink` and `blackmagicprobe`. -How to connect `cmsis-dap` and `raspberrypi-swd` is described in `Getting Started with Raspberry Pi Pico`_. +If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``cmsis-dap`` is used by default. +The other supported adapters are ``raspberrypi-swd``, ``jlink`` and ``blackmagicprobe``. +How to connect ``cmsis-dap`` and ``raspberrypi-swd`` is described in `Getting Started with Raspberry Pi Pico`_. Any other SWD debug adapter maybe also work with this configuration. The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from -`west flash` and `west debug` if it was previously set while running `west build`. +``west flash`` and ``west debug`` if it was previously set while running +``west build``. -**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as `"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"`. +**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. You can also flash the board with the following @@ -238,7 +239,7 @@ Using UF2 If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the Pico. @@ -270,7 +271,7 @@ Here is an example for debugging the :zephyr:code-sample:`blinky` application. :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd As with flashing, you can specify the debug adapter by specifying **RPI_PICO_DEBUG_ADAPTER** -at `west build` time. No needs to specify it at `west debug` time. +at ``west build`` time. No needs to specify it at ``west debug`` time. You can also debug with OpenOCD and gdb launching from command-line. Run the following command: diff --git a/boards/renesas/rzt2m_starterkit/doc/index.rst b/boards/renesas/rzt2m_starterkit/doc/index.rst index 72dc6615f64b6f4..eecaa1bc3c67b8f 100644 --- a/boards/renesas/rzt2m_starterkit/doc/index.rst +++ b/boards/renesas/rzt2m_starterkit/doc/index.rst @@ -67,7 +67,7 @@ By default, the board is configured for use with: * UART0 connected to the USB serial port (pins K18, K19), * UART3 connected to the PMOD Header (J25, pins H16, G20), -* LEDs defined as `led0`, `led1`, `led2` and `led3`, +* LEDs defined as ``led0``, ``led1``, ``led2`` and ``led3``, The Zephyr console uses UART0. @@ -78,7 +78,7 @@ Debugging ========= Connect to the board using the J-Link On-board USB connector. -Use `west` to start the debug server: +Use ``west`` to start the debug server: .. code-block:: console diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst index eda1476149e6055..d91729dccd6daf7 100644 --- a/boards/seeed/xiao_ble/doc/index.rst +++ b/boards/seeed/xiao_ble/doc/index.rst @@ -92,9 +92,9 @@ UF2 Flashing To enter the bootloader, connect the USB port of the XIAO BLE to your host, and double tap the reset botton to the left of the USB connector. A mass storage -device named `XIAO BLE` should appear on the host. Using the command line, or -your file manager copy the `zephyr/zephyr.uf2` file from your build to the base -of the `XIAO BLE` mass storage device. The XIAO BLE will automatically reset +device named ``XIAO BLE`` should appear on the host. Using the command line, or +your file manager copy the :file:`zephyr/zephyr.uf2` file from your build to the base +of the ``XIAO BLE`` mass storage device. The XIAO BLE will automatically reset and launch the newly flashed application. External Debugger diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst index ae2fe7a58ed8c8f..e8346632b961cc1 100644 --- a/boards/seeed/xiao_esp32c3/doc/index.rst +++ b/boards/seeed/xiao_esp32c3/doc/index.rst @@ -172,7 +172,7 @@ For the :code:`Hello, world!` application, follow the instructions below. :board: xiao_esp32c3 :goals: build flash -Since the Zephyr console is by default on the `usb_serial` device, we use +Since the Zephyr console is by default on the ``usb_serial`` device, we use the espressif monitor to view. .. code-block:: console diff --git a/boards/shields/mikroe_mcp2518fd_click/doc/index.rst b/boards/shields/mikroe_mcp2518fd_click/doc/index.rst index ad87d2a4559d682..e54bf7509c7f199 100644 --- a/boards/shields/mikroe_mcp2518fd_click/doc/index.rst +++ b/boards/shields/mikroe_mcp2518fd_click/doc/index.rst @@ -16,7 +16,7 @@ Requirements ************ The shield uses a mikroBUS interface. The target board must define -a `mikrobus_spi` and `mikrobus_header` node labels +a ``mikrobus_spi`` and ``mikrobus_header`` node labels (see :ref:`shields` for more details). The target board must also support level triggered interrupts. diff --git a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst index 203578b5a43a8ec..f7d19831e6e4afb 100644 --- a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst +++ b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst @@ -6,12 +6,13 @@ RaspberryPi Pico to UNO FlexyPin Adapter Overview ******** -Raspberry Pi Pico to Uno `FlexyPin Adapter` is a converter-PCB to Arduino UNO form-factor -from Raspberry Pi Pico that is released in Open Source Hardware. -This board design to use with `FlexyPin`. +The Raspberry Pi Pico to Uno FlexyPin Adapter is an open-source hardware converter PCB that adapts +the Raspberry Pi Pico to the Arduino UNO form factor +This board is designed to be use with FlexyPin connector pins. The FlexyPin holds Pico and contacts to castellated through-hole. -With simple soldering, it can also be used as a board to convert the RapsberryPi Pico -o the Arduino UNO form factor. + +With simple soldering, it can also be used as a board to convert the Rapsberry Pi Pico +to the Arduino UNO form factor. .. image:: img/rpi_pico_uno_flexypin.png :align: center diff --git a/boards/silabs/dev_kits/sltb010a/doc/index.rst b/boards/silabs/dev_kits/sltb010a/doc/index.rst index c7f3452ce485f9d..bbca08c762cda86 100644 --- a/boards/silabs/dev_kits/sltb010a/doc/index.rst +++ b/boards/silabs/dev_kits/sltb010a/doc/index.rst @@ -149,7 +149,7 @@ BRD4184B: :goals: flash .. note:: - `west flash` requires `SEGGER J-Link software`_ to be installed on you host + ``west flash`` requires `SEGGER J-Link software`_ to be installed on you host computer. Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst index 8bf44f5edbd8c4f..abaafbf0d2aad59 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst +++ b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst @@ -82,14 +82,14 @@ The simplest way to flash the board is by using West, which runs Simplicity Commander in unattended mode and passes all the necessary arguments to it. - If Simplicity Commander is installed in the system and the directory in - which `commander` executable is located is present in the `PATH` environment + which ``commander`` executable is located is present in the :envvar:`PATH` environment variable: .. code-block:: console west flash -- Otherwise, one should specify full path to the `commander` executable: +- Otherwise, one should specify full path to the ``commander`` executable: .. code-block:: console @@ -114,7 +114,7 @@ Build the Zephyr kernel and application: :goals: build Connect your device to your host computer using the USB port and you -should see a USB connection. Use `west`'s flash command +should see a USB connection. Use ``west``'s flash command Open a serial terminal (minicom, putty, etc.) with the following settings: diff --git a/boards/sparkfun/micromod/doc/index.rst b/boards/sparkfun/micromod/doc/index.rst index 0ba4c37bbefbf4a..294441f66d70dff 100644 --- a/boards/sparkfun/micromod/doc/index.rst +++ b/boards/sparkfun/micromod/doc/index.rst @@ -139,7 +139,7 @@ applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). The flashing tool will depend on the carrier used along with the board. -In the case of `Sparkfun asset tracking carrier`, it is possible to use +In the case of `Sparkfun asset tracking carrier`_, it is possible to use the SWD interface along with a J-Link. Here is an example for the :ref:`hello_world` application. @@ -199,6 +199,7 @@ References .. target-notes:: .. _Micromod specification website: https://www.sparkfun.com/micromod +.. _Sparkfun asset tracking carrier: https://www.sparkfun.com/products/17272 .. _Micromod nRF52840 guide: https://learn.sparkfun.com/tutorials/micromod-nrf52840-processor-hookup-guide .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html .. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/sparkfun/pro_micro_rp2040/doc/index.rst b/boards/sparkfun/pro_micro_rp2040/doc/index.rst index cc8188aa3f1ea36..f538a04b1ce3766 100644 --- a/boards/sparkfun/pro_micro_rp2040/doc/index.rst +++ b/boards/sparkfun/pro_micro_rp2040/doc/index.rst @@ -119,8 +119,8 @@ The Pro Micro board does make the SWD pins available on pads on the underside of the board. You can solder to these pins, and use a JTag debugger. You can also flash the SparkFun ProMicro RP2040 with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the Pro Micro RP2040 is powered on with -the `BOOTSEL` button pressed, it will appear on the host as a mass storage +:file:`build/zephyr/zephyr.uf2` file. If the Pro Micro RP2040 is powered on with +the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be copied to the device, which will flash the Pro Micro RP2040. diff --git a/boards/sparkfun/thing_plus/doc/index.rst b/boards/sparkfun/thing_plus/doc/index.rst index a6c7aee9742fb48..1e9994eb0ffc0a3 100644 --- a/boards/sparkfun/thing_plus/doc/index.rst +++ b/boards/sparkfun/thing_plus/doc/index.rst @@ -92,7 +92,7 @@ In most cases you'll want to use the ``ns`` target with any of the Zephyr or Nordic based examples. Some of the examples do not use secure mode, so they do not required the ``ns`` suffix. -A great example of this is the `hello_world` below. +A great example of this is the :ref:`hello_world` below. Flashing ======== diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst index f057800aed36ba5..f39be8503cebdc4 100644 --- a/boards/st/b_u585i_iot02a/doc/index.rst +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -220,7 +220,7 @@ The BOARD options are summarized below: +-------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: +using :ref:`tfm_ipc` sample: .. code-block:: bash @@ -236,7 +236,7 @@ option bit TZEN will be set). $ west flash Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/api_ns/regression.sh` once more to clean up the board from secure +run ``./build/tfm/api_ns/regression.sh`` once more to clean up the board from secure options and get back the platform back to a "normal" state and be able to run usual, non-TFM, binaries. Also note that, even then, TZEN will remain set, and you will need to use diff --git a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst index 7339c0b10bdbc6a..fa9fa9ef43ccad9 100644 --- a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst +++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst @@ -197,9 +197,9 @@ The BOARD options are summarized below: +--------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: +using :ref:`tfm_ipc` sample: - .. code-block:: bash + .. code-block:: console $ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/ @@ -213,7 +213,7 @@ option bit TZEN will be set). $ west flash Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/api_ns/regression.sh` once more to clean up the board from secure +run ``./build/tfm/api_ns/regression.sh`` once more to clean up the board from secure options and get back the platform back to a "normal" state and be able to run usual, non-TFM, binaries. Also note that, even then, TZEN will remain set, and you will need to use diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst index 5982ec34f8f280c..7fe566172dd6266 100644 --- a/boards/st/stm32l562e_dk/doc/index.rst +++ b/boards/st/stm32l562e_dk/doc/index.rst @@ -223,7 +223,7 @@ The BOARD options are summarized below: +------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: +using :ref:`tfm_ipc` sample: .. code-block:: bash @@ -239,7 +239,7 @@ option bit TZEN will be set). $ west flash Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/api_ns/regression.sh` once more to clean up the board from secure +run ``./build/tfm/api_ns/regression.sh`` once more to clean up the board from secure options and get back the platform back to a "normal" state and be able to run usual, non-TFM, binaries. Also note that, even then, TZEN will remain set, and you will need to use diff --git a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst index 254bd38fe6e6b5e..9ee025f45e95c7c 100644 --- a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst +++ b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst @@ -142,8 +142,8 @@ For compatibility information with the various versions of these binaries, please check `modules/hal/stm32/lib/stm32wb/hci/README`_ in the ``hal_stm32`` repo. -Note that since STM32WB Cube package V1.13.2, `"full stack"` binaries are not -compatible anymore for a use in Zephyr and only `"HCI Only"` versions should be +Note that since STM32WB Cube package V1.13.2, "full stack" binaries are not +compatible anymore for a use in Zephyr and only "HCI Only" versions should be used on the M0 side. Connections and IOs diff --git a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst index 4781fa0f7bc2e7e..7b8ee9f00622b67 100644 --- a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst +++ b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst @@ -248,8 +248,8 @@ the ``--runner`` (or ``-r``) option: $ west flash --runner openocd -Flashing `hci_uart` application to STM32WB5MMG ----------------------------------------------- +Flashing ``hci_uart`` application to STM32WB5MMG +------------------------------------------------ Connect the B-U585I-IOT02A to your host computer using the USB port. Put the SW4 (MCU SWD) in OFF mode and SW5 (SWD BLE) in ON mode. Then build diff --git a/boards/telink/tlsr9518adk80d/doc/index.rst b/boards/telink/tlsr9518adk80d/doc/index.rst index e80db259a77d8c4..97413403889fcb9 100644 --- a/boards/telink/tlsr9518adk80d/doc/index.rst +++ b/boards/telink/tlsr9518adk80d/doc/index.rst @@ -235,7 +235,7 @@ It is also possible to use the west flash command, but additional steps are requ Debugging ========= -This port supports UART debug and OpenOCD+GDB. The `west debug` command also supported. You may run +This port supports UART debug and OpenOCD+GDB. The ``west debug`` command also supported. You may run it in a simple way, like: .. code-block:: console diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst index f7bb4f66b91f351..98f03bf7dff106b 100644 --- a/boards/ti/sk_am62/doc/index.rst +++ b/boards/ti/sk_am62/doc/index.rst @@ -94,16 +94,18 @@ The board can using remoteproc, and uses the OpenAMP resource table to accomplis The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the `hello_world` sample with the following command. +To test the M4F core, we build the :ref:`hello_world` sample with the following command. .. code-block:: console # From the root of the Zephyr repository west build -p -b sk_am62/am6234/m4 samples/hello_world -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. +This builds the program and the binary is present in the :file:`build/zephyr` directory as +:file:`zephyr.elf`. -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. +We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as +:file:`am62-mcu-m4f0_0-fw`. .. code-block:: console @@ -122,7 +124,7 @@ The binary will run and print Hello world to the MCU_UART0 port. Debugging ********* -The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the `debug` build target: +The board is equipped with an XDS110 JTAG debugger. To debug a binary, utilize the ``debug`` build target: .. zephyr-app-commands:: :app: diff --git a/boards/wiznet/w5500_evb_pico/doc/index.rst b/boards/wiznet/w5500_evb_pico/doc/index.rst index 63d63370f765e75..4763f5e53982a1e 100644 --- a/boards/wiznet/w5500_evb_pico/doc/index.rst +++ b/boards/wiznet/w5500_evb_pico/doc/index.rst @@ -165,7 +165,7 @@ Create a file in /etc/udev.rules.d with any name, and write the line below. ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess" -This example is valid for the case that the user joins to `plugdev` groups. +This example is valid for the case that the user joins to ``plugdev`` groups. The Raspberry Pi Pico, and thus the W55500 Evaluation Board, has an SWD interface that can be used to program and debug the on board RP2040. This @@ -189,26 +189,26 @@ application. :goals: build flash :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=picoprobe -Set the environment variables **OPENOCD** to `/usr/local/bin/openocd` and -**OPENOCD_DEFAULT_PATH** to `/usr/local/share/openocd/scripts`. This should +Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd` and +**OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work with the OpenOCD that was installed with the default configuration. This configuration also works with an environment that is set up by the `pico_setup.sh`_ script. **RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging. -If **RPI_PICO_DEBUG_ADAPTER** was not assigned, `picoprobe` is used by default. -The other supported adapters are `raspberrypi-swd`, `jlink` and -`blackmagicprobe`. How to connect `picoprobe` and `raspberrypi-swd` is +If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``picoprobe`` is used by default. +The other supported adapters are ``raspberrypi-swd``, ``jlink`` and +``blackmagicprobe``. How to connect ``picoprobe`` and ``raspberrypi-swd`` is described in `Getting Started with Raspberry Pi Pico`_. Any other SWD debug adapter maybe also work with this configuration. The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from -`west flash` and `west debug` if it was previously set while running -`west build`. +``west flash`` and ``west debug`` if it was previously set while running +``west build``. **RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as -`"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"`. Thus, +``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``. Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter. @@ -224,7 +224,7 @@ Using UF2 If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with a UF2 file. By default, building an app for this board will generate a -`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the `BOOTSEL` +:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL`` button pressed, it will appear on the host as a mass storage device. The UF2 file should be drag-and-dropped to the device, which will flash the Pico. @@ -256,8 +256,8 @@ Here is an example for debugging the :zephyr:code-sample:`blinky` application. :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd As with flashing, you can specify the debug adapter by specifying -**RPI_PICO_DEBUG_ADAPTER** at `west build` time. No needs to specify it at -`west debug` time. +**RPI_PICO_DEBUG_ADAPTER** at ``west build`` time. No needs to specify it at +``west debug`` time. You can also debug with OpenOCD and gdb launching from command-line. Run the following command: diff --git a/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst b/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst index 9065f9e11cd57ba..1156f2a4e89e9a1 100644 --- a/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst +++ b/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst @@ -22,14 +22,14 @@ The overall design of the LE Audio stack is that the implementation follows the as closely as possible, both in terms of structure but also naming. Most API functions are prefixed by the specification acronym -(e.g. `bt_bap` for the Basic Audio Profile (BAP) and `bt_vcp` for the Volume Control Profile (VCP)). -The functions are then further prefixed with the specific role from each profile where applicable -(e.g. :c:func:`bt_bap_unicast_client_discover` and :c:func:`bt_vcp_vol_rend_set_vol`). +(e.g. ``bt_bap`` for the Basic Audio Profile (BAP) and ``bt_vcp`` for the Volume Control Profile +(VCP)). The functions are then further prefixed with the specific role from each profile where +applicable (e.g. :c:func:`bt_bap_unicast_client_discover` and :c:func:`bt_vcp_vol_rend_set_vol`). There are usually a function per procedure defined by the profile or service specifications, and additional helper or meta functions that do not correspond to procedures. The structure of the files generally also follow this, -where BAP related files are prefixed with `bap` and VCP related files are prefixed with `vcp`. +where BAP related files are prefixed with ``bap`` and VCP related files are prefixed with ``vcp``. If the file is specific for a profile role, the role is also embedded in the file name. Generic Audio Framework (GAF) @@ -1065,8 +1065,8 @@ but the GTBS instance will report 2 calls, making it possible for a simple Call Control Client to control all calls from a single bearer. Similarly the supported URIs for each bearer are also made into a union in GTBS, and when placing a call using the GTBS the server will pick the most suited bearer depending on the URI. -For example calls with URI `tel` would go to the regular phone application, -and calls with the URI `skype` would go to the Teams application. +For example calls with URI ``tel`` would go to the regular phone application, +and calls with the URI ``skype`` would go to the Teams application. In conclusion the GTBS implementation in Zephyr is a union of the non-generic telephone bearers. @@ -1175,8 +1175,8 @@ the data is kept in and controlled by the application. As a rule of thumb, the return types of the callbacks for each profile implementation indicate whether the data is controlled by the stack or the application. -For example all the callbacks for the VCP Volume Renderer have the return type of `void`, -but the return type of the BAP Unicast Server callbacks are `int`, +For example all the callbacks for the VCP Volume Renderer have the return type of ``void``, +but the return type of the BAP Unicast Server callbacks are ``int``, indicating that the application not only controls a lot of the Unicast Server data, but can also reject the requests. The choice of what the return type of the callbacks often depend on the specifications, @@ -1202,7 +1202,7 @@ In Zephyr we do not force the device to always use these, as a device that uses use other profiles and services that do not require such security. We guard all access to services using a custom security check implemented in :zephyr_file:`subsys/bluetooth/audio/audio.c`, where all LE Audio services must use the -internal `BT_AUDIO_CHRC` macro for proper security verification. +internal :c:macro:`BT_AUDIO_CHRC` macro for proper security verification. Access to the LTK for encrypted SIRKs in CSIS --------------------------------------------- @@ -1235,10 +1235,10 @@ The LE audio channel on Discord Zephyr has a specific Discord channel for LE Audio development, which is open to all. Find it here at https://discordapp.com/channels/720317445772017664/1207326649591271434 or simply -search for `ble-audio` from within Discord. -Since the `ble-audio` channel is open for all, +search for "ble-audio" from within Discord. +Since the ``#ble-audio`` channel is open for all, we cannot discuss any specifications that are in development in that channel. -For discussions that require a Bluetooth SIG membership we refer to the `bluetooth-sig` +For discussions that require a Bluetooth SIG membership we refer to the ``#bluetooth-sig`` Discord channel found at https://discordapp.com/channels/720317445772017664/869172014018097162. Zephyr weekly meetings diff --git a/doc/connectivity/bluetooth/bluetooth-shell.rst b/doc/connectivity/bluetooth/bluetooth-shell.rst index 94a0c2d9e70afd4..ad906e3ba8a75ce 100644 --- a/doc/connectivity/bluetooth/bluetooth-shell.rst +++ b/doc/connectivity/bluetooth/bluetooth-shell.rst @@ -218,7 +218,7 @@ Extended Advertising ==================== Let's now have a look at some extended advertising features. To enable extended advertising, use the -`ext-adv` parameter. +``ext-adv`` parameter. .. code-block:: console diff --git a/doc/connectivity/networking/api/coap_client.rst b/doc/connectivity/networking/api/coap_client.rst index 8d01d72a44d2d33..518e697b1067d2d 100644 --- a/doc/connectivity/networking/api/coap_client.rst +++ b/doc/connectivity/networking/api/coap_client.rst @@ -52,10 +52,10 @@ The callback provided in the callback will be called in following cases: - There is a response for the request - The request failed for some reason -The callback contains a flag `last_block`, which indicates if there is more data to come in the -response and means that the current response is part of a blockwise transfer. When the `last_block` -is set to true, the response is finished and the client is ready for the next request after -returning from the callback. +The callback contains a flag ``last_block``, which indicates if there is more data to come in the +response and means that the current response is part of a blockwise transfer. When the +``last_block`` is set to true, the response is finished and the client is ready for the next request +after returning from the callback. If the server responds to the request, the library provides the response to the application through the response callback registered in the request structure. diff --git a/doc/connectivity/networking/api/tls_credentials_shell.rst b/doc/connectivity/networking/api/tls_credentials_shell.rst index 76c074ae67d0eed..df2818fd039f0d2 100644 --- a/doc/connectivity/networking/api/tls_credentials_shell.rst +++ b/doc/connectivity/networking/api/tls_credentials_shell.rst @@ -206,7 +206,7 @@ After the list is printed, a final summary of the found credentials will be prin credentials found. -Where `` is the number of credentials found, and is zero if none are found. +Where ```` is the number of credentials found, and is zero if none are found. .. _tls_credentials_shell_cred_types: diff --git a/doc/connectivity/networking/api/wifi.rst b/doc/connectivity/networking/api/wifi.rst index 9ae9b8cb26cf173..7803a4560559db1 100644 --- a/doc/connectivity/networking/api/wifi.rst +++ b/doc/connectivity/networking/api/wifi.rst @@ -18,7 +18,8 @@ Only personal mode security is supported with below types: * WPA3-PSK-256 * WPA3-SAE -The Wi-Fi management API is implemented in the `wifi_mgmt` module as a part of the networking L2 stack. +The Wi-Fi management API is implemented in the ``wifi_mgmt`` module as a part of the networking L2 +stack. Currently, two types of Wi-Fi drivers are supported: * Networking or socket offloaded drivers @@ -29,7 +30,7 @@ Wi-Fi Enterprise test: X.509 Certificate header generation Wi-Fi enterprise security requires use of X.509 certificates, test certificates in PEM format are committed to the repo at :zephyr_file:`samples/net/wifi/test_certs` and the during the -build process the certificates are converted to a `C` header file that is included by the Wi-Fi shell +build process the certificates are converted to a C header file that is included by the Wi-Fi shell module. .. code-block:: bash @@ -46,16 +47,16 @@ To initiate Wi-Fi connection, the following command can be used: uart:~$ wifi connect -s -k 5 -a anon -K whatever Server certificate is also provided in the same directory for testing purposes. -Any `AAA` server can be used for testing purposes, for example, `FreeRADIUS` or `hostapd`. +Any AAA server can be used for testing purposes, for example, ``FreeRADIUS`` or ``hostapd``. .. important:: - The passphrase for the client-key.pem and the server-key.pem is `whatever`. + The passphrase for the :file:`client-key.pem`` and the :file:`server-key.pem` is ``whatever``. .. note:: The certificates are for testing purposes only and should not be used in production. - The certificates are generated using `FreeRADIUS raddb _` scripts. + They are generated using `FreeRADIUS raddb `_ scripts. API Reference ************* diff --git a/doc/connectivity/usb/device_next/usb_device.rst b/doc/connectivity/usb/device_next/usb_device.rst index f2e3556000bc85b..1213c85fb51d78c 100644 --- a/doc/connectivity/usb/device_next/usb_device.rst +++ b/doc/connectivity/usb/device_next/usb_device.rst @@ -30,7 +30,7 @@ The USB device stack has built-in USB functions. Some can be used directly in the user application through a special API, such as HID or Audio class devices, while others use a general Zephyr RTOS driver API, such as MSC and CDC class implementations. The *Identification string* identifies a class or function -instance (`n`) and is used as an argument to the :c:func:`usbd_register_class`. +instance (``n``) and is used as an argument to the :c:func:`usbd_register_class`. +-----------------------------------+-------------------------+-------------------------+ | Class or function | User API (if any) | Identification string | diff --git a/doc/contribute/index.rst b/doc/contribute/index.rst index 44106539d536a32..19f872226a5ac95 100644 --- a/doc/contribute/index.rst +++ b/doc/contribute/index.rst @@ -27,7 +27,7 @@ General Guidelines merged. :ref:`contributor-expectations` - This document is another mandatory read that describes the expected behavior of `all` + This document is another mandatory read that describes the expected behavior of *all* contributors to the project. :ref:`coding_guidelines` diff --git a/doc/develop/debug/index.rst b/doc/develop/debug/index.rst index 932d6484addfb50..e7547b3edc76742 100644 --- a/doc/develop/debug/index.rst +++ b/doc/develop/debug/index.rst @@ -291,7 +291,7 @@ Debugging I2C communication There is a possibility to log all or some of the I2C transactions done by the application. This feature is enabled by the Kconfig option :kconfig:option:`CONFIG_I2C_DUMP_MESSAGES`, but it -uses the ``LOG_DBG`` function to print the contents so the +uses the :c:macro:`LOG_DBG` function to print the contents so the :kconfig:option:`CONFIG_I2C_LOG_LEVEL_DBG` option must also be enabled. The sample output of the dump looks like this:: diff --git a/doc/develop/manifest/index.rst b/doc/develop/manifest/index.rst index a24c32de61cbb7c..bf1d4cc31d1de45 100644 --- a/doc/develop/manifest/index.rst +++ b/doc/develop/manifest/index.rst @@ -12,7 +12,7 @@ Active Projects/Modules +++++++++++++++++++++++ The projects below are enabled by default and will be downloaded when you -call `west update`. Many of the projects or modules listed below are +call :command:`west update`. Many of the projects or modules listed below are essential for building generic Zephyr application and include among others hardware support for many of the platforms available in Zephyr. @@ -30,7 +30,7 @@ Inactive and Optional Projects/Modules The projects below are optional and will not be downloaded when you -call `west update`. You can add any of the projects or modules listed below +call :command:`west update`. You can add any of the projects or modules listed below and use them to write application code and extend your workspace with the added functionality. diff --git a/doc/develop/modules.rst b/doc/develop/modules.rst index 8188e12bc00a87f..1a3107111a8522d 100644 --- a/doc/develop/modules.rst +++ b/doc/develop/modules.rst @@ -52,7 +52,7 @@ In summary: Modules are repositories that contain a :file:`zephyr/module.yml` file, so that the Zephyr build system can pull in the source code from the repository. -:ref:`West projects ` are entries in the `projects:` +:ref:`West projects ` are entries in the ``projects:`` section in the :file:`west.yml` manifest file. West projects are often also modules, but not always. There are west projects that are not included in the final firmware image (eg. tools) and thus do not @@ -545,7 +545,7 @@ The ``sysbuild-cmake: `` part specifies that use. Here is an example :file:`module.yml` file referring to -:file:`CMakeLists.txt` and :file:`Kconfig` files in the `sysbuild` directory of +:file:`CMakeLists.txt` and :file:`Kconfig` files in the ``sysbuild`` directory of the module: .. code-block:: yaml @@ -592,7 +592,7 @@ be monitored for your module. The supported formats are: - - -A real life example for `mbedTLS` module could look like this: +A real life example for ``mbedTLS`` module could look like this: .. code-block:: yaml diff --git a/doc/develop/test/pytest.rst b/doc/develop/test/pytest.rst index 3b8d1de95af212c..3f6db41fd3c468b 100644 --- a/doc/develop/test/pytest.rst +++ b/doc/develop/test/pytest.rst @@ -14,7 +14,7 @@ Pytest is a python framework that *“makes it easy to write small, readable tes support complex functional testing for applications and libraries”* (``_). Python is known for its free libraries and ease of using it for scripting. In addition, pytest utilizes the concept of plugins and fixtures, increasing its expendability and reusability. -A pytest plugin `pytest-twister-harness` was introduced to provide an integration between pytest +A pytest plugin ``pytest-twister-harness`` was introduced to provide an integration between pytest and twister, allowing Zephyr’s community to utilize pytest functionality with keeping twister as the main framework. diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst index 2b3b896986ea28f..a362c79861a89c0 100644 --- a/doc/develop/test/twister.rst +++ b/doc/develop/test/twister.rst @@ -261,11 +261,11 @@ test application and has to follow basic rules: two sections: * Ztest tests: The individual test cases in the ztest testsuite will be - concatenated by dot (`.`) to the identifier in the ``testcase.yaml`` file + concatenated by dot (``.``) to the identifier in the ``testcase.yaml`` file generating unique identifiers for every test case in the suite. * Standalone tests and samples: This type of test should at least have 3 - sections concatnated by dot (`.`) in the test scenario identifier in the + sections concatnated by dot (``.``) in the test scenario identifier in the ``testcase.yaml`` (or ``sample.yaml``) file. The last section of the name shall signify the test case itself. @@ -851,10 +851,10 @@ Command line arguments define the initial scope in the following way: * ``-l/--all``: all available platforms; * ``-G/--integration``: all platforms from an ``integration_platforms`` list in a given test configuration file. If a test has no ``integration_platforms`` - `"scope presumption"` will happen; -* No scope argument: `"scope presumption"` will happen. + *"scope presumption"* will happen; +* No scope argument: *"scope presumption"* will happen. -`"Scope presumption"`: A list of Twister's :ref:`default platforms ` +*"Scope presumption"*: A list of Twister's :ref:`default platforms ` is used as the initial list. If nothing is left after the filtration, the ``platform_allow`` list is used as the initial scope. @@ -1338,7 +1338,7 @@ locally. As of now, those options are available: CI) - Option to specify your own list of default platforms overriding what upstream defines. -- Ability to override `build_on_all` options used in some test scenarios. +- Ability to override ``build_on_all`` options used in some test scenarios. This will treat tests or sample as any other just build for default platforms you specify in the configuration file or on the command line. - Ignore some logic in twister to expand platform coverage in cases where @@ -1350,16 +1350,16 @@ Platform Configuration The following options control platform filtering in twister: -- `override_default_platforms`: override default key a platform sets in board +- ``override_default_platforms``: override default key a platform sets in board configuration and instead use the list of platforms provided in the configuration file as the list of default platforms. This option is set to False by default. -- `increased_platform_scope`: This option is set to True by default, when +- ``increased_platform_scope``: This option is set to True by default, when disabled, twister will not increase platform coverage automatically and will only build and run tests on the specified platforms. -- `default_platforms`: A list of additional default platforms to add. This list +- ``default_platforms``: A list of additional default platforms to add. This list can either be used to replace the existing default platforms or can extend it - depending on the value of `override_default_platforms`. + depending on the value of ``override_default_platforms``. And example platforms configuration: diff --git a/doc/develop/test/ztest.rst b/doc/develop/test/ztest.rst index 5def69164f2e123..a14ebad2d42dbf9 100644 --- a/doc/develop/test/ztest.rst +++ b/doc/develop/test/ztest.rst @@ -600,7 +600,7 @@ By default the tests are sorted and ran in alphanumerical order. Test cases may be dependent on this sequence. Enable :kconfig:option:`CONFIG_ZTEST_SHUFFLE` to randomize the order. The output from the test will display the seed for failed tests. For native simulator builds you can provide the seed as an argument to -twister with `--seed` +twister with ``--seed``. Static configuration of ZTEST_SHUFFLE contains: diff --git a/doc/develop/tools/vscode.rst b/doc/develop/tools/vscode.rst index f82d7c7c8bc145a..b3f0781b1c8a8c2 100644 --- a/doc/develop/tools/vscode.rst +++ b/doc/develop/tools/vscode.rst @@ -17,7 +17,7 @@ Get VS Code `Download VS Code`_ and install it. -Install the required extensions through the `Extensions` marketplace in the left panel. +Install the required extensions through the :guilabel:`Extensions` marketplace in the left panel. Search for the `C/C++ Extension Pack`_ and install it. Initialize a new workspace diff --git a/doc/develop/west/sign.rst b/doc/develop/west/sign.rst index ef98631be1cb364..355682c032dffda 100644 --- a/doc/develop/west/sign.rst +++ b/doc/develop/west/sign.rst @@ -116,7 +116,7 @@ for all images, for example: west build -b -DSIGNING_SCRIPT= The zephyr property method is achieved by adjusting the ``SIGNING_SCRIPT`` property -on the `zephyr_property_target`, ideally from by a module by using: +on the ``zephyr_property_target``, ideally from by a module by using: .. code-block:: cmake diff --git a/doc/glossary.rst b/doc/glossary.rst index 7c643a9495e8fee..95507c4e9241565 100644 --- a/doc/glossary.rst +++ b/doc/glossary.rst @@ -60,7 +60,7 @@ Glossary of Terms See :ref:`board_terminology` for additional details. board qualifiers - The set of additional tokens, separated by a forward slash (`/`) that + The set of additional tokens, separated by a forward slash (``/``) that follow the :term:`board name` (and optionally :term:`board revision`) to form the :term:`board target`. The currently accepted qualifiers are :term:`SoC`, :term:`CPU cluster` and :term:`variant`. diff --git a/doc/hardware/arch/risc-v.rst b/doc/hardware/arch/risc-v.rst index cd5db3aa6a6a29b..1484781f6586b88 100644 --- a/doc/hardware/arch/risc-v.rst +++ b/doc/hardware/arch/risc-v.rst @@ -23,7 +23,7 @@ ISA extensions ************** It's possible to set in Zephyr which ISA extensions (RV32/64I(E)MAFD(G)QC) -are available on a given platform, by setting the appropriate `RISCV_ISA_*` +are available on a given platform, by setting the appropriate ``CONFIG_RISCV_ISA_*`` kconfig. Look at :file:`arch/riscv/Kconfig.isa` for more information. Note that Zephyr SDK toolchain support may not be defined for all @@ -33,5 +33,5 @@ SMP support *********** SMP is supported on RISC-V, but currently only on Qemu platforms. In -order to test the SMP support, one can use `qemu_riscv32_smp` or -`qemu_riscv64_smp` boards. +order to test the SMP support, one can use ``qemu_riscv32_smp`` or +``qemu_riscv64_smp`` boards. diff --git a/doc/hardware/emulator/bus_emulators.rst b/doc/hardware/emulator/bus_emulators.rst index e46ba985946f008..381f0a1ad58d332 100644 --- a/doc/hardware/emulator/bus_emulators.rst +++ b/doc/hardware/emulator/bus_emulators.rst @@ -73,7 +73,7 @@ an emulator instance using one of the :c:func:`EMUL_DT_DEFINE()` or :c:func:`EMUL_DT_INST_DEFINE()` APIs. Emulators for peripheral devices reuse the same devicetree node as the real -device driver. This means that your emulator defines `DT_DRV_COMPAT` using the +device driver. This means that your emulator defines ``DT_DRV_COMPAT`` using the same ``compat`` value from the real driver. .. code-block:: C diff --git a/doc/hardware/peripherals/uart.rst b/doc/hardware/peripherals/uart.rst index 177a54dbbfef756..644068eb7f89ccf 100644 --- a/doc/hardware/peripherals/uart.rst +++ b/doc/hardware/peripherals/uart.rst @@ -14,9 +14,9 @@ on the method, different API functions are used according to below sections: 3. :ref:`uart_async_api` using :ref:`dma_api` Polling is the most basic method to access the UART peripheral. The reading -function, `uart_poll_in`, is a non-blocking function and returns a character -or `-1` when no valid data is available. The writing function, -`uart_poll_out`, is a blocking function and the thread waits until the given +function, :c:func:`uart_poll_in`, is a non-blocking function and returns a character +or ``-1`` when no valid data is available. The writing function, +:c:func:`uart_poll_out`, is a blocking function and the thread waits until the given character is sent. With the Interrupt-driven API, possibly slow communication can happen in the diff --git a/doc/kernel/object_cores/index.rst b/doc/kernel/object_cores/index.rst index 3e8a72d68a5c757..ae28d33082c99f2 100644 --- a/doc/kernel/object_cores/index.rst +++ b/doc/kernel/object_cores/index.rst @@ -13,7 +13,7 @@ perform operations on registered objects. Object Core Concepts ******************** -Each instance of an object embeds an object core field named `obj_core`. +Each instance of an object embeds an object core field named ``obj_core``. Objects of the same type are linked together via their respective object cores to form a singly linked list. Each object core also links to the their respective object type. Each object type contains a singly linked list diff --git a/doc/kernel/services/interrupts.rst b/doc/kernel/services/interrupts.rst index 3a0cfec22ab704a..044e9ddea1fef0d 100644 --- a/doc/kernel/services/interrupts.rst +++ b/doc/kernel/services/interrupts.rst @@ -604,8 +604,8 @@ If this configuration is supported by the used architecture and toolchaing the :kconfig:option:`ISR_TABLES_LOCAL_DECLARATION_SUPPORTED` is set. See details of this option for the information about currently supported configurations. -Any invocation of :c:macro:`IRQ_CONNECT` or `IRQ_DIRECT_CONNECT` will declare an instance of struct -_isr_list_sname which is placde in a special .intList section: +Any invocation of :c:macro:`IRQ_CONNECT` or :c:macro:`IRQ_DIRECT_CONNECT` will declare an instance +of ``struct _isr_list_sname`` which is placed in a special .intList section: .. code-block:: c @@ -619,7 +619,7 @@ _isr_list_sname which is placde in a special .intList section: }; Note that the section name is placed in flexible array member. -It means that the size of the initialized structure will warry depending on the +It means that the size of the initialized structure will vary depending on the structure name length. The whole entry is used by the script during the build of the application and has all the information needed for proper interrupt placement. @@ -720,7 +720,7 @@ aggregator. In this case it may be desirable to override these defaults and use number of bits per level. Regardless of how many bits used for each level, the sum of the total bits used between all levels must sum to be less than or equal to 32-bits, fitting into a single 32-bit integer. To modify the bit total per level, override the -default 8 in `Kconfig.multilevel` by setting :kconfig:option:`CONFIG_1ST_LEVEL_INTERRUPT_BITS` +default 8 in :file:`Kconfig.multilevel` by setting :kconfig:option:`CONFIG_1ST_LEVEL_INTERRUPT_BITS` for the first level, :kconfig:option:`CONFIG_2ND_LEVEL_INTERRUPT_BITS` for the second level and :kconfig:option:`CONFIG_3RD_LEVEL_INTERRUPT_BITS` for the third level. These masks control the length of the bit masks and shift to apply when generating interrupt values, when checking the diff --git a/doc/project/release_process.rst b/doc/project/release_process.rst index 50534e14c05b93b..82fd5e303490e62 100644 --- a/doc/project/release_process.rst +++ b/doc/project/release_process.rst @@ -127,7 +127,7 @@ feature freeze milestone. An issue labeled as a blocker practically blocks a release from happening. All blocker bugs shall be resolved before a release is created. -A fix for a bug that is granted `blocker` status can be merged to 'main' and included in +A fix for a bug that is granted ``blocker`` status can be merged to 'main' and included in the release all the way until the final release date. Bugs of moderate severity and higher that have impact on all users are typically diff --git a/doc/releases/index.rst b/doc/releases/index.rst index 0ec12aace5398b3..0f4c7f8ccdd5193 100644 --- a/doc/releases/index.rst +++ b/doc/releases/index.rst @@ -73,7 +73,7 @@ Release Notes Release notes contain a list of changes that have been made to the different areas of the project during the development cycle of the release. Changes that require the user to modify their own application to support the new -release may be mentioned in the release notes, but the details regarding `what` +release may be mentioned in the release notes, but the details regarding *what* needs to be changed are to be detailed in the release's migration guide. .. toctree:: diff --git a/doc/releases/migration-guide-4.0.rst b/doc/releases/migration-guide-4.0.rst index ac3e30269b18710..f7bf9213cc3f726 100644 --- a/doc/releases/migration-guide-4.0.rst +++ b/doc/releases/migration-guide-4.0.rst @@ -30,14 +30,14 @@ Boards to define default flash and ram partitioning based on TF-M. * STM32WBA: The command used for fetching blobs required to build ble applications is now - `west blobs fetch hal_stm32` instead of `west blobs fetch stm32`. + ``west blobs fetch hal_stm32`` instead of ``west blobs fetch stm32``. STM32 ===== -* On all official STM32 boards, `west flash` selects STM32CubeProgrammer as the default west runner. +* On all official STM32 boards, ``west flash`` selects STM32CubeProgrammer as the default west runner. If you want to enforce the selection of another runner like OpenOCD or pyOCD for flashing, you should - specify it using the west `--runner` or `-r` option. (:github:`75284`) + specify it using the west ``--runner`` or ``-r`` option. (:github:`75284`) Modules ******* @@ -69,10 +69,10 @@ zcbor Migration guide at https://github.com/NordicSemiconductor/zcbor/blob/0.9.0/MIGRATION_GUIDE.md Migration guide copied here: - * `zcbor_simple_*()` functions have been removed to avoid confusion about their use. + * ``zcbor_simple_*()`` functions have been removed to avoid confusion about their use. They are still in the C file because they are used by other functions. Instead, use the specific functions for the currently supported simple values, i.e. - `zcbor_bool_*()`, `zcbor_nil_*()`, and `zcbor_undefined_*()`. + ``zcbor_bool_*()``, ``zcbor_nil_*()``, and ``zcbor_undefined_*()``. If a removed variant is strictly needed, add your own forward declaration in your code. * Code generation naming: diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index abff147cdcd2b40..841e4eaadb41938 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -68,8 +68,8 @@ Architectures has an additional field ``csf`` that points to the callee-saved-registers upon an fatal error, which can be accessed in :c:func:`k_sys_fatal_error_handler` by ``esf->csf``. - * For SoCs that select `RISCV_SOC_HAS_ISR_STACKING`, the `SOC_ISR_STACKING_ESF_DECLARE` has to - include the `csf` member, otherwise the build would fail. + * For SoCs that select ``RISCV_SOC_HAS_ISR_STACKING``, the ``SOC_ISR_STACKING_ESF_DECLARE`` has to + include the ``csf`` member, otherwise the build would fail. * Xtensa diff --git a/doc/security/standards/etsi-303645.rst b/doc/security/standards/etsi-303645.rst index 6acb51ee7eaa360..7870a492884c511 100644 --- a/doc/security/standards/etsi-303645.rst +++ b/doc/security/standards/etsi-303645.rst @@ -4,7 +4,7 @@ ETSI 303-645 ############ -`ETSI EN 303 645`, also known as "Cyber Security for Consumer Internet +**ETSI EN 303 645**, also known as "Cyber Security for Consumer Internet of Things: Baseline Requirements," is a standard developed by the European Telecommunications Standards Institute (ETSI). diff --git a/doc/services/device_mgmt/ec_host_cmd.rst b/doc/services/device_mgmt/ec_host_cmd.rst index 2be0e4c244d4362..8419e767c5816b5 100644 --- a/doc/services/device_mgmt/ec_host_cmd.rst +++ b/doc/services/device_mgmt/ec_host_cmd.rst @@ -76,7 +76,7 @@ SoCs, modify the compatible string as shown. ... }; -The chip that runs Zephyr is a SPI slave and the `cs-gpios` property is used to point our CS pin. +The chip that runs Zephyr is a SPI slave and the ``cs-gpios`` property is used to point our CS pin. For the SPI, it is required to set the backend chosen node ``zephyr,host-cmd-spi-backend``. The supported backend and peripheral drivers: @@ -120,10 +120,10 @@ Logging The host command has an embedded logging system of the ongoing communication. The are a few logging levels: -* `LOG_INF` is used to log a command id of a new command and not success responses. Repeats of the +* :c:macro:`LOG_INF` is used to log a command id of a new command and not success responses. Repeats of the same command are not logged -* `LOG_DBG` logs every command, even repeats -* `LOG_DBG` + :kconfig:option:`CONFIG_EC_HOST_CMD_LOG_DBG_BUFFERS` logs every command and responses +* :c:macro:`LOG_DBG` logs every command, even repeats +* :c:macro:`LOG_DBG` + :kconfig:option:`CONFIG_EC_HOST_CMD_LOG_DBG_BUFFERS` logs every command and responses with the data buffers API Reference diff --git a/doc/services/device_mgmt/smp_groups/smp_group_0.rst b/doc/services/device_mgmt/smp_groups/smp_group_0.rst index eb3b90b3a1d7fe6..b33a90a9241fb5f 100644 --- a/doc/services/device_mgmt/smp_groups/smp_group_0.rst +++ b/doc/services/device_mgmt/smp_groups/smp_group_0.rst @@ -546,7 +546,7 @@ the :kconfig:option:`CONFIG_MCUMGR_GRP_OS_RESET_HOOK` is enabled and an application registers a callback, the callback will be called when this command is issued and can be used to perform any necessary tidy operations prior to the module rebooting, or to reject the reset request outright altogether with an -error response. For details on this functionality, see `ref:`mcumgr_callbacks`. +error response. For details on this functionality, see :ref:`mcumgr_callbacks`. System reset request ==================== diff --git a/doc/services/device_mgmt/smp_transport.rst b/doc/services/device_mgmt/smp_transport.rst index af3eba4dd84d513..d01300475769bc2 100644 --- a/doc/services/device_mgmt/smp_transport.rst +++ b/doc/services/device_mgmt/smp_transport.rst @@ -14,8 +14,8 @@ BLE (Bluetooth Low Energy) MCUmgr Clients need to use following BLE Characteristics, when implementing SMP client: -- **Service UUID**: `8D53DC1D-1DB7-4CD3-868B-8A527460AA84` -- **Characteristic UUID**: `DA2E7828-FBCE-4E01-AE9E-261174997C48` +- **Service UUID**: ``8D53DC1D-1DB7-4CD3-868B-8A527460AA84`` +- **Characteristic UUID**: ``DA2E7828-FBCE-4E01-AE9E-261174997C48`` All SMP communication utilizes a single GATT characteristic. An SMP request is sent via a GATT Write Without Response command. An SMP response is sent in the form diff --git a/doc/services/input/gpio-kbd.rst b/doc/services/input/gpio-kbd.rst index 162e7cb974003d7..f93d16a5efdbf62 100644 --- a/doc/services/input/gpio-kbd.rst +++ b/doc/services/input/gpio-kbd.rst @@ -171,7 +171,7 @@ Actual key mask configuration ***************************** If the key matrix is not complete, a map of the keys that are actually -populated can be specified using the `actual-key-mask` property. This allows +populated can be specified using the ``actual-key-mask`` property. This allows the matrix state to be filtered to remove keys that are not present before ghosting detection, potentially allowing key combinations that would otherwise be blocked by it. diff --git a/doc/services/llext/build.rst b/doc/services/llext/build.rst index 78522fc8162c336..eae96259d245dcc 100644 --- a/doc/services/llext/build.rst +++ b/doc/services/llext/build.rst @@ -112,18 +112,18 @@ The different build steps are: ``PRE_BUILD`` Before the extension code is linked, if the architecture uses dynamic - libraries. This step can access `lib_target` and its own properties. + libraries. This step can access ``lib_target`` and its own properties. ``POST_BUILD`` After the extension code is built, but before packaging it in an ``.llext`` - file. This step is expected to create a `pkg_input` file by reading the - contents of `lib_output`. + file. This step is expected to create a :file:`pkg_input` file by reading the + contents of :file:`lib_output`. ``POST_PKG`` After the extension output file has been created. The command can operate - on the final llext file `pkg_output`. + on the final llext file :file:`pkg_output`. Anything else after ``COMMAND`` will be passed to ``add_custom_command()`` as-is (including multiple commands and other options). diff --git a/doc/services/llext/config.rst b/doc/services/llext/config.rst index 3772c26a4454b9e..5fec87908bdc956 100644 --- a/doc/services/llext/config.rst +++ b/doc/services/llext/config.rst @@ -104,7 +104,7 @@ significant as the number of exported symbols increases. Perform an extra processing step on the Zephyr binary and on all extensions being built, converting every string in the symbol tables to - a pointer-sized hash called `Symbol Link Identifier` (SLID), which is + a pointer-sized hash called Symbol Link Identifier (SLID), which is stored in the binary. This speeds up the symbol lookup process by allowing usage of diff --git a/doc/services/logging/index.rst b/doc/services/logging/index.rst index f9717c075a5386c..5aa868362b80f4b 100644 --- a/doc/services/logging/index.rst +++ b/doc/services/logging/index.rst @@ -500,7 +500,7 @@ backends. In some cases, logs need to be redirected at the macro level. For these cases, :kconfig:option:`CONFIG_LOG_CUSTOM_HEADER` can be used to inject an application provided -header named `zephyr_custom_log.h` at the end of :zephyr_file:`include/zephyr/logging/log.h`. +header named :file:`zephyr_custom_log.h` at the end of :zephyr_file:`include/zephyr/logging/log.h`. Frontend using ARM Coresight STM (System Trace Macrocell) --------------------------------------------------------- diff --git a/doc/services/mem_mgmt/index.rst b/doc/services/mem_mgmt/index.rst index 3f63edf39a54ba1..86d36b3961ce3a4 100644 --- a/doc/services/mem_mgmt/index.rst +++ b/doc/services/mem_mgmt/index.rst @@ -66,8 +66,8 @@ and act on regions and attributes (see next section for more details). A test for the ``mem-attr`` library and its usage is provided in ``tests/subsys/mem_mgmt/mem_attr/``. -Migration guide from `zephyr,memory-region-mpu` -*********************************************** +Migration guide from ``zephyr,memory-region-mpu`` +************************************************* When the ``zephyr,memory-attr`` property was introduced, the ``zephyr,memory-region-mpu`` property was removed and deprecated. diff --git a/doc/services/pm/device_runtime.rst b/doc/services/pm/device_runtime.rst index a1ffb0a670ecc13..c6173ef66f110c7 100644 --- a/doc/services/pm/device_runtime.rst +++ b/doc/services/pm/device_runtime.rst @@ -32,7 +32,7 @@ in response to :c:func:`pm_device_runtime_get` and :c:func:`pm_device_runtime_pu calls on the child device. For the previous to automatically control the power domain state, device runtime PM must be enabled -on the power domain device (either through the `zephyr,pm-device-runtime-auto` devicetree property +on the power domain device (either through the ``zephyr,pm-device-runtime-auto`` devicetree property or :c:func:`pm_device_runtime_enable`). .. graphviz:: diff --git a/doc/services/portability/posix/conformance/index.rst b/doc/services/portability/posix/conformance/index.rst index a2b391f143eacf8..acba97e6d85f8fc 100644 --- a/doc/services/portability/posix/conformance/index.rst +++ b/doc/services/portability/posix/conformance/index.rst @@ -3,7 +3,9 @@ POSIX Conformance ################# -As per `IEEE 1003.1-2017`, this section details Zephyr's POSIX conformance. +As per `IEEE 1003.1-2017`_, this section details Zephyr's POSIX conformance. + +.. _IEEE 1003.1-2017: https://standards.ieee.org/ieee/1003.1/7101/ .. _posix_system_interfaces: diff --git a/doc/services/storage/flash_map/flash_map.rst b/doc/services/storage/flash_map/flash_map.rst index 801e75bd6bcb387..6a90cc628f27502 100644 --- a/doc/services/storage/flash_map/flash_map.rst +++ b/doc/services/storage/flash_map/flash_map.rst @@ -32,7 +32,7 @@ Most ```` API functions require a :c:struct:`flash_a characterizing the flash area they will be working on. There are two possible methods to obtain such a pointer: - * obtain it using `flash_area_open`; + * obtain it using :c:func:`flash_area_open`; * defining a :c:struct:`flash_area` type object, which requires providing a valid :c:struct:`device` object pointer with offset and size of the area diff --git a/doc/services/tracing/index.rst b/doc/services/tracing/index.rst index 17552781c323483..2519df266a0a6cb 100644 --- a/doc/services/tracing/index.rst +++ b/doc/services/tracing/index.rst @@ -365,7 +365,7 @@ To enable tracing support with `SEGGER SystemView`_ add the configuration option it to *y*. For example, this can be added to the :zephyr:code-sample:`synchronization` sample to visualize fast switching between threads. SystemView can also be used for post-mortem tracing, which can be enabled with -`CONFIG_SEGGER_SYSVIEW_POST_MORTEM_MODE`. In this mode, a debugger can +:kconfig:option:`CONFIG_SEGGER_SYSVIEW_POST_MORTEM_MODE`. In this mode, a debugger can be attached after the system has crashed using ``west attach`` after which the latest data from the internal RAM buffer can be loaded into SystemView:: diff --git a/doc/services/zbus/index.rst b/doc/services/zbus/index.rst index 1b685bb2bbf091b..401fd47c70128e4 100644 --- a/doc/services/zbus/index.rst +++ b/doc/services/zbus/index.rst @@ -380,7 +380,8 @@ Limitations Based on the fact that developers can use zbus to solve many different problems, some challenges arise. ZBus will not solve every problem, so it is necessary to analyze the situation to be sure zbus is applicable. For instance, based on the zbus benchmark, it would not be well suited to a -high-speed stream of bytes between threads. The `Pipe` kernel object solves this kind of need. +high-speed stream of bytes between threads. The :ref:`Pipe ` kernel object solves this +kind of need. Delivery guarantees ------------------- @@ -524,12 +525,12 @@ sequence of the static observers. notified. -Channels can have a `validator function` that enables a channel to accept only valid messages. +Channels can have a *validator function* that enables a channel to accept only valid messages. Publish attempts invalidated by hard channels will return immediately with an error code. This allows original creators of a channel to exert some authority over other developers/publishers who may want to piggy-back on their channels. The following code defines and initializes a :dfn:`hard channel` and its dependencies. Only valid messages can be published to a :dfn:`hard channel`. It is -possible because a `validator function` was passed to the channel's definition. In this example, +possible because a *validator function* was passed to the channel's definition. In this example, only messages with ``move`` equal to 0, -1, and 1 are valid. Publish function will discard all other values to ``move``. diff --git a/samples/bluetooth/bap_broadcast_sink/README.rst b/samples/bluetooth/bap_broadcast_sink/README.rst index 0ec8fb70542d659..efbb69e3810bc70 100644 --- a/samples/bluetooth/bap_broadcast_sink/README.rst +++ b/samples/bluetooth/bap_broadcast_sink/README.rst @@ -16,9 +16,9 @@ This sample can be found under Check the :ref:`bluetooth samples section ` for general information. -Use `CONFIG_TARGET_BROADCAST_NAME` Kconfig to specify the name (CONFIG_BT_DEVICE_NAME) -of a broadcast source to listen to. With default value (empty string), sink -device will listen to all available broadcast sources. +Use :kconfig:option:`CONFIG_TARGET_BROADCAST_NAME` Kconfig to specify the name +(:kconfig:option:`CONFIG_BT_DEVICE_NAME`) of a broadcast source to listen to. With default value +(empty string), sink device will listen to all available broadcast sources. Requirements ************ @@ -30,7 +30,7 @@ Building and Running ******************** When building targeting an nrf52 series board with the Zephyr Bluetooth Controller, -use `-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf` to enable the required ISO +use ``-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf`` to enable the required ISO feature support. Building for an nrf5340dk @@ -67,7 +67,7 @@ Similarly to how you would for real HW, you can do: :goals: build :west-args: --sysbuild -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf52_bsim diff --git a/samples/bluetooth/bap_broadcast_source/README.rst b/samples/bluetooth/bap_broadcast_source/README.rst index 4afa96da77eb4ee..1baf971623b2323 100644 --- a/samples/bluetooth/bap_broadcast_source/README.rst +++ b/samples/bluetooth/bap_broadcast_source/README.rst @@ -29,7 +29,7 @@ Building and Running ******************** When building targeting an nrf52 series board with the Zephyr Bluetooth Controller, -use `-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf` to enable the required ISO +use ``-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf`` to enable the required ISO feature support. Building for an nrf5340dk @@ -66,7 +66,7 @@ Similarly to how you would for real HW, you can do: :goals: build :west-args: --sysbuild -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf52_bsim diff --git a/samples/bluetooth/bap_unicast_client/README.rst b/samples/bluetooth/bap_unicast_client/README.rst index 7ff7a387afd9249..b99826f5fa0be03 100644 --- a/samples/bluetooth/bap_unicast_client/README.rst +++ b/samples/bluetooth/bap_unicast_client/README.rst @@ -25,7 +25,7 @@ Building and Running ******************** When building targeting an nrf52 series board with the Zephyr Bluetooth Controller, -use `-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf` to enable the required ISO +use ``-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf`` to enable the required ISO feature support. Building for an nrf52840dk @@ -71,7 +71,7 @@ Similarly to how you would for real HW, you can do: :goals: build :gen-args: -DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf5340bsim diff --git a/samples/bluetooth/bap_unicast_server/README.rst b/samples/bluetooth/bap_unicast_server/README.rst index 8ef31b7373633c7..b24c6385443eb03 100644 --- a/samples/bluetooth/bap_unicast_server/README.rst +++ b/samples/bluetooth/bap_unicast_server/README.rst @@ -25,7 +25,7 @@ Building and Running ******************** When building targeting an nrf52 series board with the Zephyr Bluetooth Controller, -use `-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf` to enable the required ISO +use ``-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf`` to enable the required ISO feature support. Building for an nrf52840dk @@ -71,7 +71,7 @@ Similarly to how you would for real HW, you can do: :goals: build :gen-args: -DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf5340bsim diff --git a/samples/bluetooth/broadcaster_multiple/README.rst b/samples/bluetooth/broadcaster_multiple/README.rst index ab24c541270a929..5170cf9dbff7fd3 100644 --- a/samples/bluetooth/broadcaster_multiple/README.rst +++ b/samples/bluetooth/broadcaster_multiple/README.rst @@ -12,11 +12,11 @@ uses multiple advertising sets functionality. This sample advertises two non-connectable non-scannable advertising sets with two different SID. Number of advertising sets can be increased by updating the -`CONFIG_BT_EXT_ADV_MAX_ADV_SET` value in the project configuration file. +:kconfig:option:`CONFIG_BT_EXT_ADV_MAX_ADV_SET` value in the project configuration file. When building this sample combined with a Bluetooth LE Controller, the advertising data length can be increased from the default 31 bytes by updating -the Controller's `CONFIG_BT_CTLR_ADV_DATA_LEN_MAX` value. The size of the +the Controller's :kconfig:option:`CONFIG_BT_CTLR_ADV_DATA_LEN_MAX` value. The size of the manufacturer data is calculated to maximize the use of supported AD data length. Requirements diff --git a/samples/bluetooth/cap_acceptor/README.rst b/samples/bluetooth/cap_acceptor/README.rst index b964ae544ce94c4..0a9854616f10d97 100644 --- a/samples/bluetooth/cap_acceptor/README.rst +++ b/samples/bluetooth/cap_acceptor/README.rst @@ -61,7 +61,7 @@ Similarly to how you would for real HW, you can do: :goals: build :west-args: --sysbuild -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf52_bsim diff --git a/samples/bluetooth/cap_initiator/README.rst b/samples/bluetooth/cap_initiator/README.rst index 71e01a07713b878..b3c84ff9dec55ff 100644 --- a/samples/bluetooth/cap_initiator/README.rst +++ b/samples/bluetooth/cap_initiator/README.rst @@ -62,7 +62,7 @@ Similarly to how you would for real HW, you can do: :goals: build :west-args: --sysbuild -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf52_bsim diff --git a/samples/bluetooth/encrypted_advertising/README.rst b/samples/bluetooth/encrypted_advertising/README.rst index 8079acb672b424b..b62a479fccac959 100644 --- a/samples/bluetooth/encrypted_advertising/README.rst +++ b/samples/bluetooth/encrypted_advertising/README.rst @@ -15,7 +15,7 @@ This sample demonstrates the use of the encrypted advertising feature, such as: - the decryption of those advertising payloads, - and the update of the Randomizer field whenever the RPA is changed. -To use the `bt_ead_encrypt` and `bt_ead_decrypt` functions, you must enable +To use the :c:func:`bt_ead_encrypt` and :c:func:`bt_ead_decrypt` functions, you must enable the Kconfig symbol :kconfig:option:`CONFIG_BT_EAD`. While this sample uses extended advertising, it is **not** mandatory when using diff --git a/samples/bluetooth/extended_adv/README.rst b/samples/bluetooth/extended_adv/README.rst index a88244642eb003d..b7901fd8e6b094a 100644 --- a/samples/bluetooth/extended_adv/README.rst +++ b/samples/bluetooth/extended_adv/README.rst @@ -21,7 +21,7 @@ while the scanner cools-down for 5 seconds to restart its process. This sample handles all actions in a separate thread, to promote good design practices. Even though it is not strictly required, scheduling from another context is strongly recommended (e.g. using a work item), as re-starting an advertiser or -scanner from within the `recycled` callback exposes the application to deadlocking. +scanner from within the ``recycled`` callback exposes the application to deadlocking. Requirements ************ diff --git a/samples/bluetooth/hci_uart/README.rst b/samples/bluetooth/hci_uart/README.rst index e671927095a9b67..d07ddd4421e41df 100644 --- a/samples/bluetooth/hci_uart/README.rst +++ b/samples/bluetooth/hci_uart/README.rst @@ -157,7 +157,7 @@ Using the controller with the Zephyr host This describes how to hook up a board running this sample to a board running an application that uses the Zephyr host. -On the controller side, the `zephyr,bt-c2h-uart` DTS property (in the `chosen` +On the controller side, the ``zephyr,bt-c2h-uart`` DTS property (in the ``chosen`` block) is used to select which uart device to use. For example if we want to keep the console logs, we can keep console on uart0 and the HCI on uart1 like so: @@ -180,7 +180,7 @@ driver instead of the built-in controller: CONFIG_BT_HCI=y CONFIG_BT_CTLR=n -Similarly, the `zephyr,bt-hci` DTS property selects which HCI instance to use. +Similarly, the ``zephyr,bt-hci`` DTS property selects which HCI instance to use. The UART needs to have as its child node a HCI UART node: .. code-block:: dts diff --git a/samples/bluetooth/hci_uart_3wire/README.rst b/samples/bluetooth/hci_uart_3wire/README.rst index f4a809be2a13cbf..effd001c7600d4b 100644 --- a/samples/bluetooth/hci_uart_3wire/README.rst +++ b/samples/bluetooth/hci_uart_3wire/README.rst @@ -157,7 +157,7 @@ Using the controller with the Zephyr host This describes how to hook up a board running this sample to a board running an application that uses the Zephyr host. -On the controller side, the `zephyr,bt-c2h-uart` DTS property (in the `chosen` +On the controller side, the ``zephyr,bt-c2h-uart`` DTS property (in the ``chosen`` block) is used to select which uart device to use. For example if we want to keep the console logs, we can keep console on uart0 and the HCI on uart1 like so: @@ -180,7 +180,7 @@ driver instead of the built-in controller: CONFIG_BT_HCI=y CONFIG_BT_CTLR=n -Similarly, the `zephyr,bt-hci` DTS property selects which HCI instance to use. +Similarly, the ``zephyr,bt-hci`` DTS property selects which HCI instance to use. The UART needs to have as its child node a HCI UART node: .. code-block:: dts diff --git a/samples/bluetooth/hci_uart_async/README.rst b/samples/bluetooth/hci_uart_async/README.rst index 6dca7b85ecc50e5..0bf85fdb7653a51 100644 --- a/samples/bluetooth/hci_uart_async/README.rst +++ b/samples/bluetooth/hci_uart_async/README.rst @@ -125,7 +125,7 @@ Using the controller with the Zephyr host This describes how to hook up a board running this sample to a board running an application that uses the Zephyr host. -On the controller side, the `zephyr,bt-c2h-uart` DTS property (in the `chosen` +On the controller side, the ``zephyr,bt-c2h-uart`` DTS property (in the ``chosen`` block) is used to select which uart device to use. For example if we want to keep the console logs, we can keep console on uart0 and the HCI on uart1 like so: @@ -148,7 +148,7 @@ driver instead of the built-in controller: CONFIG_BT_HCI=y CONFIG_BT_CTLR=n -Similarly, the `zephyr,bt-hci` DTS property selects which HCI instance to use. +Similarly, the ``zephyr,bt-hci`` DTS property selects which HCI instance to use. The UART needs to have as its child node a HCI UART node: .. code-block:: dts diff --git a/samples/bluetooth/iso_broadcast/README.rst b/samples/bluetooth/iso_broadcast/README.rst index c560e0e5fab3e9b..a27f302247f36b1 100644 --- a/samples/bluetooth/iso_broadcast/README.rst +++ b/samples/bluetooth/iso_broadcast/README.rst @@ -22,7 +22,7 @@ Building and Running ******************** This sample can be found under :zephyr_file:`samples/bluetooth/iso_broadcast` in -the Zephyr tree. Use `-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf` to enable +the Zephyr tree. Use ``-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf`` to enable required ISO feature support in Zephyr Bluetooth Controller on supported boards. Use the sample found under :zephyr_file:`samples/bluetooth/iso_receive` in the diff --git a/samples/bluetooth/iso_receive/README.rst b/samples/bluetooth/iso_receive/README.rst index b93db57b92b1518..85201981c7f7056 100644 --- a/samples/bluetooth/iso_receive/README.rst +++ b/samples/bluetooth/iso_receive/README.rst @@ -22,7 +22,7 @@ Building and Running ******************** This sample can be found under :zephyr_file:`samples/bluetooth/iso_receive` in -the Zephyr tree. Use `-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf` to enable +the Zephyr tree. Use ``-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf`` to enable required ISO feature support in Zephyr Bluetooth Controller on supported boards. Use the sample found under :zephyr_file:`samples/bluetooth/iso_broadcast` on diff --git a/samples/bluetooth/observer/README.rst b/samples/bluetooth/observer/README.rst index 8f807b915b4820b..42001e3624225d9 100644 --- a/samples/bluetooth/observer/README.rst +++ b/samples/bluetooth/observer/README.rst @@ -13,7 +13,7 @@ If any found, prints the address of the device, the RSSI value, the Advertising type, and the Advertising data length to the console. If the used Bluetooth Low Energy Controller supports Extended Scanning, you may -enable `CONFIG_BT_EXT_ADV` in the project configuration file. Refer to the +enable :kconfig:option:`CONFIG_BT_EXT_ADV` in the project configuration file. Refer to the project configuration file for further details. Requirements diff --git a/samples/bluetooth/pbp_public_broadcast_sink/README.rst b/samples/bluetooth/pbp_public_broadcast_sink/README.rst index 8414eba7e33494a..72ec4fc3c8fb2ad 100644 --- a/samples/bluetooth/pbp_public_broadcast_sink/README.rst +++ b/samples/bluetooth/pbp_public_broadcast_sink/README.rst @@ -27,7 +27,7 @@ Building and Running ******************** When building targeting an nrf52 series board with the Zephyr Bluetooth Controller, -use `-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf` to enable the required ISO +use ``-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf`` to enable the required ISO feature support. Building for an nrf5340dk @@ -64,7 +64,7 @@ Similarly to how you would for real HW, you can do: :goals: build :west-args: --sysbuild -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf52_bsim diff --git a/samples/bluetooth/pbp_public_broadcast_source/README.rst b/samples/bluetooth/pbp_public_broadcast_source/README.rst index 5e5f855137c9386..c12c2b762f40127 100644 --- a/samples/bluetooth/pbp_public_broadcast_source/README.rst +++ b/samples/bluetooth/pbp_public_broadcast_source/README.rst @@ -27,7 +27,7 @@ Building and Running ******************** When building targeting an nrf52 series board with the Zephyr Bluetooth Controller, -use `-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf` to enable the required ISO +use ``-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf`` to enable the required ISO feature support. Building for an nrf5340dk @@ -64,7 +64,7 @@ Similarly to how you would for real HW, you can do: :goals: build :west-args: --sysbuild -Note this will produce a Linux executable in `./build/zephyr/zephyr.exe`. +Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`. For more information, check :ref:`this board documentation `. Building for a simulated nrf52_bsim diff --git a/samples/bluetooth/peripheral_hids/README.rst b/samples/bluetooth/peripheral_hids/README.rst index 00c579957a44376..72be337fc883162 100644 --- a/samples/bluetooth/peripheral_hids/README.rst +++ b/samples/bluetooth/peripheral_hids/README.rst @@ -15,7 +15,7 @@ In the default configuration the sample uses passkey authentication (displays a code on the peripheral and requires that to be entered on the host during pairing) and requires an authenticated link to access the GATT characteristics. To disable authentication and just use encrypted channels instead, build the -sample with `CONFIG_SAMPLE_BT_USE_AUTHENTICATION=n`. +sample with ``CONFIG_SAMPLE_BT_USE_AUTHENTICATION=n``. Requirements ************ diff --git a/samples/boards/espressif/flash_memory_mapped/README.rst b/samples/boards/espressif/flash_memory_mapped/README.rst index 11b53851def1056..5605c970948e673 100644 --- a/samples/boards/espressif/flash_memory_mapped/README.rst +++ b/samples/boards/espressif/flash_memory_mapped/README.rst @@ -13,7 +13,7 @@ contents of flash memory by writing to a mapped memory region. Mapping happens in 64 KB pages. Memory mapping hardware can map flash into the data address space and the instruction address space. See the technical reference manual for more details and -limitations about memory mapping hardware. For more information, check `_ESP32 Flash Memory-Mapping`. +limitations about memory mapping hardware. For more information, check `ESP32 Flash Memory-Mapping`_. Supported SoCs ************** diff --git a/samples/boards/espressif/spiram_test/README.rst b/samples/boards/espressif/spiram_test/README.rst index a4bf818978c074a..e91e2b24ed8906c 100644 --- a/samples/boards/espressif/spiram_test/README.rst +++ b/samples/boards/espressif/spiram_test/README.rst @@ -7,7 +7,7 @@ Overview ******** This sample shows how to allocate memory from SPIRAM by using -:c:func:`shared_multi_heap_aligned_alloc` with `SMH_REG_ATTR_EXTERNAL` attribute. Checks if the +:c:func:`shared_multi_heap_aligned_alloc` with ``SMH_REG_ATTR_EXTERNAL`` attribute. Checks if the memory was correctly allocated then frees it by calling :c:func:`shared_multi_heap_free`. It also allocates memory from internal memory and checks if the address range is correct. @@ -31,7 +31,7 @@ Make sure you have your board connected over USB port. west flash If using another supported Espressif board, replace the argument in the above -command with a proper board name (e.g., `esp32s2_saola`). +command with a proper board name (e.g., ``esp32s2_saola``). Sample Output ============= diff --git a/samples/boards/espressif/xt_wdt/README.rst b/samples/boards/espressif/xt_wdt/README.rst index 0e4ab9d1ebaa641..782188dd523ceec 100644 --- a/samples/boards/espressif/xt_wdt/README.rst +++ b/samples/boards/espressif/xt_wdt/README.rst @@ -36,7 +36,7 @@ to pins XTAL_32K_P and XTAL_32K_N. west flash If using another supported Espressif board, replace the argument in the above -command with a proper board name (e.g., `esp32s2_saola`). +command with a proper board name (e.g., ``esp32s2_saola``). Sample Output ============= diff --git a/samples/boards/nxp/s32/netc/README.rst b/samples/boards/nxp/s32/netc/README.rst index 35652cb479f0c12..ea2ee66ef1baf0d 100644 --- a/samples/boards/nxp/s32/netc/README.rst +++ b/samples/boards/nxp/s32/netc/README.rst @@ -88,8 +88,8 @@ Setting up Host To be able to reach the board from the host, it's needed to configure the host network interface IP's and default routes. This guide assumes the host IPv4 and -IPv6 addresses are `192.0.2.3` and `2001:db8::3`, respectively. For example, -using a network interface named `enp1s0` in a GNU/Linux host or `Ethernet` in +IPv6 addresses are ``192.0.2.3`` and ``2001:db8::3``, respectively. For example, +using a network interface named ``enp1s0`` in a GNU/Linux host or ``Ethernet`` in a Windows host, this can be done with the following commands: .. tabs:: @@ -121,4 +121,4 @@ the following commands from the Zephyr shell: net ping -I 192.0.2.3 net ping -I 2001:db8::3 -Where `` is the interface number starting from 1. +Where ```` is the interface number starting from 1. diff --git a/samples/boards/st/uart/single_wire/README.rst b/samples/boards/st/uart/single_wire/README.rst index f9f41198d567cbc..09c01c817251feb 100644 --- a/samples/boards/st/uart/single_wire/README.rst +++ b/samples/boards/st/uart/single_wire/README.rst @@ -12,7 +12,7 @@ functionality of STM32. Without adaptions this example runs on STM32F3 discovery board. You need to establish a physical connection between pins PA2 (USART2_TX) and PC10 (UART4_TX). -Add a `single_wire_uart_loopback` fixture to your board in the hardware map to allow +Add a ``single_wire_uart_loopback`` fixture to your board in the hardware map to allow twister to verify this sample's output automatically. Building and Running diff --git a/samples/drivers/auxdisplay/README.rst b/samples/drivers/auxdisplay/README.rst index 67bfb0e56777bec..813e91ca43170a6 100644 --- a/samples/drivers/auxdisplay/README.rst +++ b/samples/drivers/auxdisplay/README.rst @@ -14,7 +14,7 @@ Building and Running ******************** Note that this sample requires a board with an auxiliary display setup. A -sample overlay is provided for the `nucleo_f746zg` board fly-wired to a Hitachi +sample overlay is provided for the ``nucleo_f746zg`` board fly-wired to a Hitachi HD44780-compatible 20 character by 4 line display. See the overlay file :zephyr_file:`samples/drivers/auxdisplay/boards/nucleo_f746zg.overlay` for wiring configuration. @@ -26,4 +26,4 @@ wiring configuration. :goals: build flash :compact: -If successful, the display will show `Hello World from `. +If successful, the display will show "Hello World from ". diff --git a/samples/drivers/dac/README.rst b/samples/drivers/dac/README.rst index a99834943890890..c58d7f3de27edaf 100644 --- a/samples/drivers/dac/README.rst +++ b/samples/drivers/dac/README.rst @@ -201,8 +201,7 @@ The sample can be built and executed for the :goals: build flash :compact: -also can run for the -:ref: `longan_nano_lite` as follows: +also can run for the Longan Nano Lite as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/dac diff --git a/samples/drivers/fpga/fpga_controller/README.rst b/samples/drivers/fpga/fpga_controller/README.rst index d971c138541a9af..371cc23a372c6d7 100644 --- a/samples/drivers/fpga/fpga_controller/README.rst +++ b/samples/drivers/fpga/fpga_controller/README.rst @@ -82,8 +82,8 @@ To upload the bitstream again you need to reset the FPGA: FPGA: resetting FPGA You can also use your own bitstream. -To load a bitstream into device memory, use `devmem load` command. -It is important to use the -e option when sending a bitstream via `xxd`: +To load a bitstream into device memory, use ``devmem load`` command. +It is important to use the -e option when sending a bitstream via ``xxd``: .. code-block:: console @@ -92,14 +92,14 @@ It is important to use the -e option when sending a bitstream via `xxd`: Press ctrl-x + ctrl-q to stop Now, the loader is waiting for data. -You can either type it directly from the console or send it from the host PC (replace `ttyX` with the appropriate one for your shell console): +You can either type it directly from the console or send it from the host PC (replace ``ttyX`` with the appropriate one for your shell console): .. code-block:: console xxd -p data > /dev/ttyX (It is important to use plain-style hex dump) -Once the data is transferred, use `ctrl-x + ctrl-q` to quit loader. +Once the data is transferred, use :kbd:`Ctrl-X Ctrl-Q` to quit loader. It will print the sum of the read bytes and return to the shell: .. code-block:: console diff --git a/samples/drivers/led/is31fl3733/README.rst b/samples/drivers/led/is31fl3733/README.rst index 8f0f30e61cf7033..eefa04b184f3dc5 100644 --- a/samples/drivers/led/is31fl3733/README.rst +++ b/samples/drivers/led/is31fl3733/README.rst @@ -29,7 +29,7 @@ Building and Running ******************** This sample can be run on any board with an IS31FL3733 LED driver connected via -I2C, and a node with the `issi,is31fl3733` compatible present in its devicetree. +I2C, and a node with the :dtcompatible:`issi,is31fl3733` compatible present in its devicetree. This sample provides a DTS overlay for the :ref:`frdm_k22f` board (:file:`boards/frdm_k22f.overlay`). It assumes that the IS31FL3733 LED diff --git a/samples/drivers/mspi/mspi_async/README.rst b/samples/drivers/mspi/mspi_async/README.rst index 08a5bdd92a83c5a..a3c52013cc53d8f 100644 --- a/samples/drivers/mspi/mspi_async/README.rst +++ b/samples/drivers/mspi/mspi_async/README.rst @@ -18,7 +18,7 @@ Building and Running The application will build only for a target that has a :ref:`devicetree ` ``dev0`` alias that refers to an entry with the following bindings as a compatible: -* :dtcompatible:`ambiq,mspi-device`, `mspi-aps6404l` +* :dtcompatible:`ambiq,mspi-device`, :dtcompatible:`mspi-aps6404l` .. zephyr-app-commands:: :zephyr-app: samples/drivers/mspi/mspi_async diff --git a/samples/drivers/mspi/mspi_flash/README.rst b/samples/drivers/mspi/mspi_flash/README.rst index 06875e5bd665751..991143992b6fac7 100644 --- a/samples/drivers/mspi/mspi_flash/README.rst +++ b/samples/drivers/mspi/mspi_flash/README.rst @@ -18,7 +18,7 @@ Building and Running The application will build only for a target that has a :ref:`devicetree ` ``flash0`` alias that refers to an entry with the following bindings as a compatible: -* :dtcompatible:`ambiq,mspi-device`, `mspi-atxp032` +* :dtcompatible:`ambiq,mspi-device`, :dtcompatible:`mspi-atxp032` .. zephyr-app-commands:: :zephyr-app: samples/drivers/mspi/mspi_flash diff --git a/samples/fuel_gauge/max17048/README.rst b/samples/fuel_gauge/max17048/README.rst index bd26aa3152393a2..f2fd26182209845 100644 --- a/samples/fuel_gauge/max17048/README.rst +++ b/samples/fuel_gauge/max17048/README.rst @@ -6,7 +6,7 @@ MAX17048 Li-Ion battery fuel gauge Overview ******** -This sample shows how to use the Zephyr :ref:`fuel_gauge_api` API driver for the `MAX17048` fuel gauge. +This sample shows how to use the Zephyr :ref:`fuel_gauge_api` API driver for the MAX17048 fuel gauge. .. _MAX17048: https://www.maximintegrated.com/en/products/power/battery-management/MAX17048.html diff --git a/samples/modules/tflite-micro/hello_world/README.rst b/samples/modules/tflite-micro/hello_world/README.rst index f88e12f13238fdd..10192c337c8fb53 100644 --- a/samples/modules/tflite-micro/hello_world/README.rst +++ b/samples/modules/tflite-micro/hello_world/README.rst @@ -61,7 +61,7 @@ or as a that can be emulated on a host machine. Assuming that the Corstone-300 FVP has been downloaded, installed and added to -the `PATH` variable, then building and testing can be done with following +the :envvar:`PATH` variable, then building and testing can be done with following commands. ``` diff --git a/samples/philosophers/README.rst b/samples/philosophers/README.rst index 2392af05165ff38..d0701832cbeb4ac 100644 --- a/samples/philosophers/README.rst +++ b/samples/philosophers/README.rst @@ -19,7 +19,7 @@ is waiting for the second fork to be available. Each Philosopher will randomly alternate between the ``EATING`` and ``THINKING`` states. -It is possible to run the demo in `coop-only` or `preempt-only` mode. To achieve this, set these +It is possible to run the demo in ``coop-only`` or ``preempt-only`` mode. To achieve this, set these values for ``CONFIG_NUM_COOP_PRIORITIES`` and ``CONFIG_NUM_PREEMPT_PRIORITIES`` in :file:`prj.conf`: preempt-only diff --git a/samples/subsys/dap/README.rst b/samples/subsys/dap/README.rst index 7d3d117358bb46b..1f34f02c523eab0 100644 --- a/samples/subsys/dap/README.rst +++ b/samples/subsys/dap/README.rst @@ -14,8 +14,8 @@ Requirements This sample supports multiple hardware configurations: -The simplest configuration would be to connect `SWDIO` to `dio`, `SWDCLK` to `clk` -and optionally `nRESET` to `reset`. The optional `noe` pin is used to enable the port, +The simplest configuration would be to connect ``SWDIO`` to ``dio``, ``SWDCLK`` to ``clk`` +and optionally ``nRESET`` to ``reset``. The optional ``noe`` pin is used to enable the port, e.g. if the SWD connections are multiplexed. Building and Running diff --git a/samples/subsys/fs/format/README.rst b/samples/subsys/fs/format/README.rst index 4840ddb53418b3f..59029d2dbfae5a0 100644 --- a/samples/subsys/fs/format/README.rst +++ b/samples/subsys/fs/format/README.rst @@ -21,7 +21,8 @@ To run this sample, build it for the desired board and scenario and flash it. The Flash scenario is supported on the nrf52dk/nrf52832 board. The RAM disk scenario is supported on the mimxrt1064_evk board. -To build the RAM disk sample, the configuration `prj_ram.conf` needs to be used by setting `CONF_FILE=prj_ram.conf`. +To build the RAM disk sample, the configuration :file:`prj_ram.conf` needs to be used by setting +``CONF_FILE=prj_ram.conf``. The Flash sample for the nrf 52DK board can be built as follow: diff --git a/samples/subsys/fs/littlefs/README.rst b/samples/subsys/fs/littlefs/README.rst index 69be12cfefeca7b..342614b59146382 100644 --- a/samples/subsys/fs/littlefs/README.rst +++ b/samples/subsys/fs/littlefs/README.rst @@ -91,19 +91,19 @@ To build the test: At the moment, only two types of block devices are acceptable in this sample: SDMMC and MMC. -It is possible that both the `zephyr,sdmmc-disk` and `zephyr,mmc-disk` block devices will be +It is possible that both the ``zephyr,sdmmc-disk`` and ``zephyr,mmc-disk`` block devices will be present and enabled in the final board dts and configuration files simultaneously, the mount -point name for the `littlefs` file system block device will be determined based on the +point name for the ``littlefs`` file system block device will be determined based on the following logic: -* if the ``CONFIG_SDMMC_VOLUME_NAME`` configuration is defined, it will be used +* if the :kconfig:option:`CONFIG_SDMMC_VOLUME_NAME` configuration is defined, it will be used as the mount point name; -* if the ``CONFIG_SDMMC_VOLUME_NAME`` configuration is not defined, but the - ``CONFIG_MMC_VOLUME_NAME`` configuration is defined, ``CONFIG_MMC_VOLUME_NAME`` will - be used as the mount point name; -* if neither ``CONFIG_SDMMC_VOLUME_NAME`` nor ``CONFIG_MMC_VOLUME_NAME`` configurations - are defined, the mount point name will not be determined, and an appropriate error will - apear during the sample build. +* if the :kconfig:option:`CONFIG_SDMMC_VOLUME_NAME` configuration is not defined, but the + :kconfig:option:`CONFIG_MMC_VOLUME_NAME` configuration is defined, + :kconfig:option:`CONFIG_MMC_VOLUME_NAME` will be used as the mount point name; +* if neither :kconfig:option:`CONFIG_SDMMC_VOLUME_NAME` nor :kconfig:option:`CONFIG_MMC_VOLUME_NAME` + configurations are defined, the mount point name will not be determined, and an appropriate error + will appear during the sample build. NRF52840 Development Kit ======================== diff --git a/samples/subsys/llext/shell_loader/README.rst b/samples/subsys/llext/shell_loader/README.rst index ec6d8427bbd1eff..681a9487cedab5e 100644 --- a/samples/subsys/llext/shell_loader/README.rst +++ b/samples/subsys/llext/shell_loader/README.rst @@ -136,9 +136,9 @@ The resulting hex string can be used to load the extension. uart:~$ llext load_hex hello_world 7f454c4601010100000000000000000001002800010000000000000000000000680200000000000534000000000028000b000a0080b500af084b1800084b00f013f82a22074b11001800054b00f00cf8c046bd4680bc01bc0047c0460400000000000000140000001847c0462a00000068656c6c6f20776f726c640a0000000041206e756d62657220697320256c750a00004743433a20285a65706879722053444b20302e31362e31292031322e322e30004129000000616561626900011f000000053454000602080109011204140115011703180119011a011e06000000000000000000000000000000000100000000000000000000000400f1ff000000000000000000000000030001000000000000000000000000000300030000000000000000000000000003000400000000000000000000000000030005000f00000000000000000000000000050012000000000000000400000001000500190000000000000000000000000001000f0000002800000000000000000001001900000034000000000000000000010000000000000000000000000003000600000000000000000000000000030007001c000000010000003400000012000100280000000000000000000000100000000068656c6c6f5f776f726c642e63002464006e756d6265720024740068656c6c6f5f776f726c64007072696e746b000028000000020500002c000000020e00003000000002050000002e73796d746162002e737472746162002e7368737472746162002e72656c2e74657874002e64617461002e627373002e726f64617461002e636f6d6d656e74002e41524d2e6174747269627574657300000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f0000000100000006000000000000003400000038000000000000000000000004000000000000001b000000090000004000000000000000fc0100001800000008000000010000000400000008000000250000000100000003000000000000006c00000000000000000000000000000001000000000000002b0000000800000003000000000000006c0000000000000000000000000000000100000000000000300000000100000002000000000000006c00000025000000000000000000000004000000000000003800000001000000300000000000000091000000210000000000000000000000010000000100000041000000030000700000000000000000b20000002a0000000000000000000000010000000000000001000000020000000000000000000000dc000000f0000000090000000d000000040000001000000009000000030000000000000000000000cc0100002f0000000000000000000000010000000000000011000000030000000000000000000000140200005100000000000000000000000100000000000000 -This extension can then be seen in the list of loaded extensions (`list`), its symbols printed -(`list_symbols`), and the hello_world function which the extension exports can be called and -run (`call_fn`). +This extension can then be seen in the list of loaded extensions (``list``), its symbols printed +(``list_symbols``), and the hello_world function which the extension exports can be called and +run (``call_fn``). .. code-block:: console diff --git a/samples/subsys/usb/shell/README.rst b/samples/subsys/usb/shell/README.rst index 9f2ddb8898d6eda..5e5437b56dc35ca 100644 --- a/samples/subsys/usb/shell/README.rst +++ b/samples/subsys/usb/shell/README.rst @@ -36,7 +36,7 @@ currently it is only MAX3421E. The example can be built as follows: It is theoretically possible to build USB support using virtual USB controllers for all platforms, eventually the devicetree overlay has to be adjusted slightly if -the platform has already defined or not `zephyr_uhc0` or `zephyr_udc0` nodelabels. +the platform has already defined or not ``zephyr_uhc0`` or ``zephyr_udc0`` nodelabels. .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/shell diff --git a/samples/sysbuild/with_mcuboot/README.rst b/samples/sysbuild/with_mcuboot/README.rst index 7428406a62ea833..6ae3b81e6ec0107 100644 --- a/samples/sysbuild/with_mcuboot/README.rst +++ b/samples/sysbuild/with_mcuboot/README.rst @@ -19,7 +19,7 @@ sysbuild. This is achieved with a sysbuild specific Kconfig configuration, :file:`sysbuild.conf`. -The `SB_CONFIG_BOOTLOADER_MCUBOOT=y` setting in the sysbuild Kconfig file +The ``SB_CONFIG_BOOTLOADER_MCUBOOT=y`` setting in the sysbuild Kconfig file enables the bootloader when building with sysbuild. The :file:`sysbuild/mcuboot.conf` file will be used as an extra fragment that diff --git a/scripts/pylib/pytest-twister-harness/README.rst b/scripts/pylib/pytest-twister-harness/README.rst index 2c7baf4e89245e4..99e0045ee08773b 100644 --- a/scripts/pylib/pytest-twister-harness/README.rst +++ b/scripts/pylib/pytest-twister-harness/README.rst @@ -7,8 +7,8 @@ Installation If you plan to use this plugin with Twister, then you don't need to install it separately by pip. When Twister uses this plugin for pytest tests, it updates -`PYTHONPATH` variable, and then extends pytest command by -`-p twister_harness.plugin` argument. +:envvar:`PYTHONPATH` variable, and then extends pytest command by +``-p twister_harness.plugin`` argument. Usage diff --git a/snippets/xen_dom0/README.rst b/snippets/xen_dom0/README.rst index a871d9f4f5151f1..b9a83452dcb616e 100644 --- a/snippets/xen_dom0/README.rst +++ b/snippets/xen_dom0/README.rst @@ -29,12 +29,14 @@ For example: QEMU example with Xen *********************** -Overlay for qemu_cortex_a53 board, that is present in `board/` directory of this snippet is QEMU -Xen control domain example. To run such setup, you need to: +Overlay for qemu_cortex_a53 board, that is present in :zephyr_file:`snippets/xen_dom0/boards/` +directory of this snippet is QEMU Xen control domain example. + +To run such setup, you need to: * fetch and build Xen (e.g. RELEASE-4.17.0) for arm64 platform -* take and compile sample device tree from `example/` directory -* build your Zephyr sample/application with `xen_dom0` snippet and start it as Xen control domain +* take and compile sample device tree from :file:`example/` directory +* build your Zephyr sample/application with ``xen_dom0`` snippet and start it as Xen control domain For starting you can use QEMU from Zephyr SDK by following command: @@ -47,5 +49,7 @@ For starting you can use QEMU from Zephyr SDK by following command: -dtb /xen.dtb -kernel /xen This will start you a Xen hypervisor with your application as Xen control domain. To make it usable, -you can add `zephyr-xenlib` by Xen-troops library to your project. It'll provide basic domain +you can add `zephyr-xenlib`_ by Xen-troops library to your project. It'll provide basic domain management functionalities - domain creation and configuration. + +.. _zephyr-xenlib: https://github.com/xen-troops/zephyr-xenlib diff --git a/tests/boards/espressif_esp32/rtc_clk/README.rst b/tests/boards/espressif_esp32/rtc_clk/README.rst index f629ae1ae2ada22..5e48922de0eb212 100644 --- a/tests/boards/espressif_esp32/rtc_clk/README.rst +++ b/tests/boards/espressif_esp32/rtc_clk/README.rst @@ -34,7 +34,7 @@ To run the test with twister, use the following command: west twister -p --device-testing --device-serial=/dev/ttyUSB0 -vv --flash-before -T tests/boards/espressif_esp32/rtc_clk -If the external 32K crystal is connect to pins 32K_XP and 32K_XN, the test can be run with `external_xtal` fixture enabled: +If the external 32K crystal is connect to pins 32K_XP and 32K_XN, the test can be run with ``external_xtal`` fixture enabled: .. code-block:: console diff --git a/tests/ztest/fail/README.rst b/tests/ztest/fail/README.rst index ab5788ba821af93..a87cccf4a0f3326 100644 --- a/tests/ztest/fail/README.rst +++ b/tests/ztest/fail/README.rst @@ -8,7 +8,7 @@ Overview In order to test the actual framework's failure cases, this test suite has to do something unique. There's a subdirectory to this test called 'core'. This project builds a sample as a -:ref:`native_sim ` or `:ref:unit_testing ` +:ref:`native_sim ` or :ref:`unit_testing ` binary which is expected to fail by calling one of the following: - ``ztest_test_fail()`` during either the ``after`` or ``teardown`` phase of the test suite - ``ztest_test_skip()`` during either the ``after`` or ``teardown`` phase of the test suite From 6cf5ac58793695b7c7375866f279804d3c7f3ff1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 11 Sep 2024 10:50:50 +0200 Subject: [PATCH 006/269] doc: guidelines: drop mention of "any" links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 204860857edbcfd4a57928acae8a64ee0e43f00a (PR #41061) dropped support for "any" as the default role, so this should be dropped from the documentation guidelines as well. Signed-off-by: Benjamin Cabé --- doc/contribute/documentation/guidelines.rst | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/doc/contribute/documentation/guidelines.rst b/doc/contribute/documentation/guidelines.rst index 052f038302cab0b..12e0b3f6d446cd5 100644 --- a/doc/contribute/documentation/guidelines.rst +++ b/doc/contribute/documentation/guidelines.rst @@ -349,22 +349,6 @@ you can reference it with:: Read the `Zephyr Wikipedia Page`_ for more information about the project. - -\`any\` links -************* - -Within the Zephyr project, we've defined the default role to be "any", -meaning if you just write a phrase in back-ticks, e.g., -```doc_guidelines```, Sphinx will search through all domains looking for -something called doc_guidelines to link to. In this case it will find -the label at the top of this document, and link to `doc_guidelines`. -This can be useful for linking to doxygen-generated links for function -names and such, but will cause a warning such as:: - - WARNING: 'any' reference target not found: doc_giudelines - -if you misspelled ```doc_guidelines``` as ```doc_giudelines```. - Non-ASCII Characters ******************** From 88983f71d820ffe78964acd82447cc75a24fb728 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Thu, 12 Sep 2024 11:17:57 +0200 Subject: [PATCH 007/269] doc: releases: fix kconfig role typo in mbedtls section MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit trivial typo fix where single backticks should be used instead of double for the sphinx role kconfig:option Signed-off-by: Benjamin Cabé --- doc/releases/migration-guide-4.0.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/releases/migration-guide-4.0.rst b/doc/releases/migration-guide-4.0.rst index f7bf9213cc3f726..1437b4044de657c 100644 --- a/doc/releases/migration-guide-4.0.rst +++ b/doc/releases/migration-guide-4.0.rst @@ -48,8 +48,8 @@ Mbed TLS * The Kconfig options ``CONFIG_MBEDTLS_TLS_VERSION_1_0`` and ``CONFIG_MBEDTLS_TLS_VERSION_1_1`` have been removed because Mbed TLS doesn't support TLS 1.0 and 1.1 anymore since v3.0. (:github:`76833`) * The following Kconfig symbols were renamed (:github:`76408`): - * ``CONFIG_MBEDTLS_ENTROPY_ENABLED`` is now :kconfig:option:``CONFIG_MBEDTLS_ENTROPY_C``, - * ``CONFIG_MBEDTLS_ZEPHYR_ENTROPY`` is now :kconfig:option:``CONFIG_MBEDTLS_ENTROPY_POLL_ZEPHYR``. + * ``CONFIG_MBEDTLS_ENTROPY_ENABLED`` is now :kconfig:option:`CONFIG_MBEDTLS_ENTROPY_C`, + * ``CONFIG_MBEDTLS_ZEPHYR_ENTROPY`` is now :kconfig:option:`CONFIG_MBEDTLS_ENTROPY_POLL_ZEPHYR`. * The Kconfig option ``CONFIG_MBEDTLS_SSL_EXPORT_KEYS`` was removed because the corresponding build symbol was removed in Mbed TLS 3.1.0 and is now assumed to From fd4f3ce246c9ce1ddbd04b20054ebca3b9bbdc6f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Tue, 10 Sep 2024 18:00:00 +0200 Subject: [PATCH 008/269] scripts: compliance: add sphinx-lint linter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ReStructuredText can sometimes be tricky to get right, especially for folks that might be more familiar with Markdown. This adds a Sphinx/RST linter to the compliance check script to help catch common issues that can easily go unnoticed and cause rendering issues. Signed-off-by: Benjamin Cabé --- .github/workflows/compliance.yml | 2 +- .gitignore | 1 + scripts/ci/check_compliance.py | 43 +++++++++++++++++++++++++++++ scripts/requirements-compliance.txt | 1 + 4 files changed, 46 insertions(+), 1 deletion(-) diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 09168abed0279e3..39815d8baa36b7d 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -38,7 +38,7 @@ jobs: run: | pip3 install setuptools pip3 install wheel - pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint clang-format unidiff + pip3 install python-magic lxml junitparser gitlint pylint pykwalify yamllint clang-format unidiff sphinx-lint pip3 install west - name: west setup diff --git a/.gitignore b/.gitignore index f590a8a38bb6330..266b95a424a85f0 100644 --- a/.gitignore +++ b/.gitignore @@ -91,4 +91,5 @@ MaintainersFormat.txt ModulesMaintainers.txt Nits.txt Pylint.txt +SphinxLint.txt YAMLLint.txt diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 54964d4449a713d..58a2e6da6bb996f 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -1495,6 +1495,49 @@ def run(self): p.line, col=p.column, desc=p.desc) +class SphinxLint(ComplianceTest): + """ + SphinxLint + """ + + name = "SphinxLint" + doc = "Check Sphinx/reStructuredText files with sphinx-lint." + path_hint = "" + + # Checkers added/removed to sphinx-lint's default set + DISABLE_CHECKERS = ["horizontal-tab", "missing-space-before-default-role"] + ENABLE_CHECKERS = ["default-role"] + + def run(self): + for file in get_files(): + if not file.endswith(".rst"): + continue + + try: + # sphinx-lint does not expose a public API so interaction is done via CLI + subprocess.run( + f"sphinx-lint -d {','.join(self.DISABLE_CHECKERS)} -e {','.join(self.ENABLE_CHECKERS)} {file}", + check=True, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + shell=True, + cwd=GIT_TOP, + ) + + except subprocess.CalledProcessError as ex: + for line in ex.output.decode("utf-8").splitlines(): + match = re.match(r"^(.*):(\d+): (.*)$", line) + + if match: + self.fmtd_failure( + "error", + "SphinxLint", + match.group(1), + int(match.group(2)), + desc=match.group(3), + ) + + class KeepSorted(ComplianceTest): """ Check for blocks of code or config that should be kept sorted. diff --git a/scripts/requirements-compliance.txt b/scripts/requirements-compliance.txt index 0d5fe218e68514f..a4396986934471e 100644 --- a/scripts/requirements-compliance.txt +++ b/scripts/requirements-compliance.txt @@ -9,3 +9,4 @@ junitparser>=2 pylint>=3 unidiff yamllint +sphinx-lint From c53e8e7086909d3071b897f5ddcf47915b7debd5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 13 Sep 2024 19:25:57 +0200 Subject: [PATCH 009/269] boards: doc: reference tfm_ipc sample using zephyr:code-sample: role MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit tfm_ipc sample is now using the zephyr:code-sample directive so it should be referenced with the respective role, not :ref: anymore. Signed-off-by: Benjamin Cabé --- boards/st/b_u585i_iot02a/doc/index.rst | 2 +- boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst | 2 +- boards/st/stm32l562e_dk/doc/index.rst | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst index f39be8503cebdc4..f09b6f3dc2e977d 100644 --- a/boards/st/b_u585i_iot02a/doc/index.rst +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -220,7 +220,7 @@ The BOARD options are summarized below: +-------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using :ref:`tfm_ipc` sample: +using :zephyr:code-sample:`tfm_ipc` sample: .. code-block:: bash diff --git a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst index fa9fa9ef43ccad9..79a91fe52013267 100644 --- a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst +++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst @@ -197,7 +197,7 @@ The BOARD options are summarized below: +--------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using :ref:`tfm_ipc` sample: +using :zephyr:code-sample:`tfm_ipc` sample: .. code-block:: console diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst index 7fe566172dd6266..922c03cbebdbea3 100644 --- a/boards/st/stm32l562e_dk/doc/index.rst +++ b/boards/st/stm32l562e_dk/doc/index.rst @@ -223,7 +223,7 @@ The BOARD options are summarized below: +------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, -using :ref:`tfm_ipc` sample: +using :zephyr:code-sample:`tfm_ipc` sample: .. code-block:: bash From f4717acd996843a12959b9f529b2780daede0168 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 11 Sep 2024 18:02:47 +0200 Subject: [PATCH 010/269] samples: arch: use zephyr:code-sample directive MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds missing code-sample directive to all the arch samples in preparation for upcoming changes to the Zephyr documentation that will be leveraging the provided description and metadata. Signed-off-by: Benjamin Cabé --- samples/arch/mpu/mpu_test/README.rst | 6 +++--- samples/arch/smp/pi/README.rst | 6 +++--- samples/arch/smp/pktqueue/README.rst | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/samples/arch/mpu/mpu_test/README.rst b/samples/arch/mpu/mpu_test/README.rst index 750bdda41bccbfe..8c0be7ad1f6fa66 100644 --- a/samples/arch/mpu/mpu_test/README.rst +++ b/samples/arch/mpu/mpu_test/README.rst @@ -1,7 +1,7 @@ -.. _mpu_test: +.. zephyr:code-sample:: mpu + :name: Memory Protection Unit (MPU) -Memory Protection Unit (MPU) Sample -################################### + Use memory protection to prevent common security issues. Overview ******** diff --git a/samples/arch/smp/pi/README.rst b/samples/arch/smp/pi/README.rst index ffdd5540ecc0305..2db473da88f4648 100644 --- a/samples/arch/smp/pi/README.rst +++ b/samples/arch/smp/pi/README.rst @@ -1,7 +1,7 @@ -.. _smp_pi: +.. zephyr:code-sample:: smp_pi + :name: SMP Pi -SMP Pi -########### + Calculate the first 240 digits of Pi on multiple execution units. Overview ******** diff --git a/samples/arch/smp/pktqueue/README.rst b/samples/arch/smp/pktqueue/README.rst index dd2d12213826549..beddc40623084f4 100644 --- a/samples/arch/smp/pktqueue/README.rst +++ b/samples/arch/smp/pktqueue/README.rst @@ -1,7 +1,7 @@ -.. _smp_pktqueue: +.. zephyr:code-sample:: smp_pktqueue + :name: SMP pktqueue -SMP pktqueue -############ + Use SMP to process multiple packet headers in parallel. Overview ******** From 86af9c4b0766842aa97b5b9bead12c71ca5d69ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 11 Sep 2024 18:06:23 +0200 Subject: [PATCH 011/269] samples: arch: fix toctree hierarchy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix glob pattern so that samples' hierarchy is not lost. Signed-off-by: Benjamin Cabé --- samples/arch/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/samples/arch/index.rst b/samples/arch/index.rst index 916f8cdf0636a91..a43bda20d807086 100644 --- a/samples/arch/index.rst +++ b/samples/arch/index.rst @@ -4,7 +4,7 @@ Architecture Dependent Samples ############################## .. toctree:: - :maxdepth: 1 + :maxdepth: 2 :glob: - **/* + */* From 437bfa5b1a3b917d693a19fa95814ba69c97e564 Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Wed, 11 Sep 2024 12:52:17 +0200 Subject: [PATCH 012/269] Bluetooth: Controller: Infinite loop assertion on node_rx release Add assertion check to catch infinite loop due to incorrect node_rx release. If same node_rx is released twice then it can lead to infinite looping when releaseing link or node_rx buffers. Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/ll_sw/ull.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/subsys/bluetooth/controller/ll_sw/ull.c b/subsys/bluetooth/controller/ll_sw/ull.c index 7cadc34d48a0144..1e5f3bff7c05325 100644 --- a/subsys/bluetooth/controller/ll_sw/ull.c +++ b/subsys/bluetooth/controller/ll_sw/ull.c @@ -1053,6 +1053,7 @@ void ll_rx_dequeue(void) { struct node_rx_pdu *rx_curr; struct pdu_adv *adv; + uint8_t loop = PDU_RX_POOL_SIZE / PDU_RX_NODE_POOL_ELEMENT_SIZE; adv = (struct pdu_adv *)rx->pdu; if (adv->type != PDU_ADV_TYPE_EXT_IND) { @@ -1063,6 +1064,9 @@ void ll_rx_dequeue(void) while (rx_curr) { memq_link_t *link_free; + LL_ASSERT(loop); + loop--; + link_free = rx_curr->hdr.link; rx_curr = rx_curr->rx_ftr.extra; From 9fa18600eea54115d69d919906de78f835c1ecc7 Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Wed, 11 Sep 2024 12:56:27 +0200 Subject: [PATCH 013/269] Bluetooth: Controller: Fix hang due to loop in node_rx list Fix Controller hang due to infinite looping caused by duplicate node_rx enqueued in auxiliary context. When LLL scheduling is not applied due to invalid aux offset then ULL scheduling too would skip setting up the reception after similarly checking the validity of aux offset required to schedule the reception of auxiliary PDU. This check in ULL was after the received node_rx being enqueued into the auxiliary context causing a loop in the list of node_rx. Dequeue of a list with a loop of node_rx caused an infinite loop execution in the Controller. Regression introduced in commit 3590bd648f8f ("Bluetooth: Controller: Fix missing invalid aux offset check"). Signed-off-by: Vinayak Kariappa Chettimada --- .../ll_sw/nordic/lll/lll_scan_aux.c | 4 +-- .../bluetooth/controller/ll_sw/ull_scan_aux.c | 33 ++++++++++--------- 2 files changed, 20 insertions(+), 17 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c index eb97ab789fd57c2..3c4c591d228455f 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c @@ -124,8 +124,8 @@ uint8_t lll_scan_aux_setup(struct pdu_adv *pdu, uint8_t pdu_phy, struct pdu_cte_info *cte_info; struct node_rx_pdu *node_rx; uint32_t window_widening_us; - uint32_t window_size_us; struct node_rx_ftr *ftr; + uint16_t window_size_us; uint32_t aux_offset_us; uint32_t overhead_us; uint8_t *pri_dptr; @@ -186,7 +186,7 @@ uint8_t lll_scan_aux_setup(struct pdu_adv *pdu, uint8_t pdu_phy, /* Skip reception if invalid aux offset */ pdu_us = PDU_AC_US(pdu->len, pdu_phy, pdu_phy_flags_rx); - if (aux_offset_us < pdu_us) { + if (unlikely((aux_offset_us + window_size_us) < (pdu_us + EVENT_MAFS_US))) { return 0U; } diff --git a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c index 0e4bbf0f2cd689e..864a8240d35658f 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c @@ -116,6 +116,7 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) struct pdu_adv_adi *adi; struct node_rx_ftr *ftr; uint32_t ready_delay_us; + uint16_t window_size_us; uint32_t aux_offset_us; uint32_t ticker_status; struct lll_scan *lll; @@ -511,6 +512,22 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) goto ull_scan_aux_rx_flush; } + /* Determine the window size */ + if (aux_ptr->offs_units) { + window_size_us = OFFS_UNIT_300_US; + } else { + window_size_us = OFFS_UNIT_30_US; + } + + /* Calculate received aux offset we need to have ULL schedule a reception */ + aux_offset_us = (uint32_t)PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) * window_size_us; + + /* Skip reception if invalid aux offset */ + pdu_us = PDU_AC_US(pdu->len, phy, ftr->phy_flags); + if (unlikely((aux_offset_us + window_size_us) < (pdu_us + EVENT_MAFS_US))) { + goto ull_scan_aux_rx_flush; + } + if (!aux) { aux = aux_acquire(); if (!aux) { @@ -697,21 +714,6 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) aux->rx_head = rx; } - /* Determine the window size */ - if (aux_ptr->offs_units) { - lll_aux->window_size_us = OFFS_UNIT_300_US; - } else { - lll_aux->window_size_us = OFFS_UNIT_30_US; - } - - aux_offset_us = (uint32_t)PDU_ADV_AUX_PTR_OFFSET_GET(aux_ptr) * lll_aux->window_size_us; - - /* Skip reception if invalid aux offset */ - pdu_us = PDU_AC_US(pdu->len, phy, ftr->phy_flags); - if (aux_offset_us < pdu_us) { - goto ull_scan_aux_rx_flush; - } - /* CA field contains the clock accuracy of the advertiser; * 0 - 51 ppm to 500 ppm * 1 - 0 ppm to 50 ppm @@ -722,6 +724,7 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) window_widening_us = SCA_DRIFT_500_PPM_US(aux_offset_us); } + lll_aux->window_size_us = window_size_us; lll_aux->window_size_us += ((EVENT_TICKER_RES_MARGIN_US + EVENT_JITTER_US + window_widening_us) << 1); From 176d8ff760cf53717c9438f33111443722ed36de Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Thu, 12 Sep 2024 16:11:49 +0200 Subject: [PATCH 014/269] Bluetooth: Controller: Define a macro to validate aux offset value Define a macro to validate aux offset value as it is checked both in LLL and ULL execution contexts. Signed-off-by: Vinayak Kariappa Chettimada --- subsys/bluetooth/controller/ll_sw/lll_scan_aux.h | 3 +++ subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c | 2 +- subsys/bluetooth/controller/ll_sw/ull_scan_aux.c | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/lll_scan_aux.h b/subsys/bluetooth/controller/ll_sw/lll_scan_aux.h index 6430abbd24c1f55..7d2446c227e071a 100644 --- a/subsys/bluetooth/controller/ll_sw/lll_scan_aux.h +++ b/subsys/bluetooth/controller/ll_sw/lll_scan_aux.h @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#define AUX_OFFSET_IS_VALID(_offset_us, _win_size_us, _pdu_us) \ + (((_offset_us) + (_win_size_us)) >= ((_pdu_us) + (EVENT_MAFS_US))) + int lll_scan_aux_init(void); int lll_scan_aux_reset(void); void lll_scan_aux_prepare(void *param); diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c index 3c4c591d228455f..657d6ddfbb5fb64 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c @@ -186,7 +186,7 @@ uint8_t lll_scan_aux_setup(struct pdu_adv *pdu, uint8_t pdu_phy, /* Skip reception if invalid aux offset */ pdu_us = PDU_AC_US(pdu->len, pdu_phy, pdu_phy_flags_rx); - if (unlikely((aux_offset_us + window_size_us) < (pdu_us + EVENT_MAFS_US))) { + if (unlikely(!AUX_OFFSET_IS_VALID(aux_offset_us, window_size_us, pdu_us))) { return 0U; } diff --git a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c index 864a8240d35658f..4b6090175245242 100644 --- a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c @@ -524,7 +524,7 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx) /* Skip reception if invalid aux offset */ pdu_us = PDU_AC_US(pdu->len, phy, ftr->phy_flags); - if (unlikely((aux_offset_us + window_size_us) < (pdu_us + EVENT_MAFS_US))) { + if (unlikely(!AUX_OFFSET_IS_VALID(aux_offset_us, window_size_us, pdu_us))) { goto ull_scan_aux_rx_flush; } From 50b07f9480a49f2b489ade9dae98b91fc3f2a643 Mon Sep 17 00:00:00 2001 From: Vinayak Kariappa Chettimada Date: Thu, 12 Sep 2024 16:34:10 +0200 Subject: [PATCH 015/269] Bluetooth: Controller: Add missing branch prediction in lll_scan_aux Add missing branch prediction likely/unlikely hint. Signed-off-by: Vinayak Kariappa Chettimada --- .../ll_sw/nordic/lll/lll_scan_aux.c | 25 +++++++++---------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c index 657d6ddfbb5fb64..2424ab8a653a138 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c +++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan_aux.c @@ -136,7 +136,7 @@ uint8_t lll_scan_aux_setup(struct pdu_adv *pdu, uint8_t pdu_phy, /* Get reference to extended header */ pri_com_hdr = (void *)&pdu->adv_ext_ind; - if (!pdu->len || !pri_com_hdr->ext_hdr_len) { + if (unlikely(!pdu->len || !pri_com_hdr->ext_hdr_len)) { return 0U; } @@ -385,7 +385,7 @@ bool lll_scan_aux_addr_match_get(const struct lll_scan *lll, const struct pdu_adv_ext_hdr *ext_hdr; ext_hdr = &pdu->adv_ext_ind.ext_hdr; - if (!ext_hdr->adv_addr) { + if (unlikely(!ext_hdr->adv_addr)) { return false; } @@ -786,7 +786,7 @@ static void isr_rx(struct lll_scan *lll, struct lll_scan_aux *lll_aux, lll_isr_rx_status_reset(); /* No Rx */ - if (!trx_done || !crc_ok) { + if (unlikely(!trx_done || !crc_ok)) { /* TODO: Combine the early exit with above if-then-else block */ err = -EINVAL; @@ -802,7 +802,7 @@ static void isr_rx(struct lll_scan *lll, struct lll_scan_aux *lll_aux, } pdu = (void *)node_rx->pdu; - if ((pdu->type != PDU_ADV_TYPE_EXT_IND) || !pdu->len) { + if (unlikely((pdu->type != PDU_ADV_TYPE_EXT_IND) || !pdu->len)) { err = -EINVAL; goto isr_rx_do_close; @@ -1509,7 +1509,7 @@ static void isr_rx_connect_rsp(void *param) } /* No Rx or invalid PDU received */ - if (!trx_done) { + if (unlikely(!trx_done)) { struct node_rx_ftr *ftr; /* Try again with connection initiation */ @@ -1525,6 +1525,7 @@ static void isr_rx_connect_rsp(void *param) rx = ftr->extra; rx->hdr.type = NODE_RX_TYPE_RELEASE; + goto isr_rx_connect_rsp_do_close; } @@ -1600,20 +1601,18 @@ static bool isr_rx_connect_rsp_check(struct lll_scan *lll, struct pdu_adv *pdu_tx, struct pdu_adv *pdu_rx, uint8_t rl_idx) { - if (pdu_rx->type != PDU_ADV_TYPE_AUX_CONNECT_RSP) { + if (unlikely(pdu_rx->type != PDU_ADV_TYPE_AUX_CONNECT_RSP)) { return false; } - if (pdu_rx->len != offsetof(struct pdu_adv_com_ext_adv, - ext_hdr_adv_data) + - offsetof(struct pdu_adv_ext_hdr, data) + ADVA_SIZE + - TARGETA_SIZE) { + if (unlikely(pdu_rx->len != (offsetof(struct pdu_adv_com_ext_adv, ext_hdr_adv_data) + + offsetof(struct pdu_adv_ext_hdr, data) + ADVA_SIZE + + TARGETA_SIZE))) { return false; } - if (pdu_rx->adv_ext_ind.adv_mode || - !pdu_rx->adv_ext_ind.ext_hdr.adv_addr || - !pdu_rx->adv_ext_ind.ext_hdr.tgt_addr) { + if (unlikely(pdu_rx->adv_ext_ind.adv_mode || !pdu_rx->adv_ext_ind.ext_hdr.adv_addr || + !pdu_rx->adv_ext_ind.ext_hdr.tgt_addr)) { return false; } From 6bd0dcf9209fc4064ac7db95fecbc94e1d6557a6 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 12 Jul 2024 14:56:43 -0700 Subject: [PATCH 016/269] xtensa: mpu: make sure write to MPU regions is atomic This adds a spinlock to make sure writing to hardware MPU regions is atomic, and cannot be interrupted until all regions are written to hardware. Signed-off-by: Daniel Leung --- arch/xtensa/core/mpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/xtensa/core/mpu.c b/arch/xtensa/core/mpu.c index edca3ec2bd040d7..20ee31727648364 100644 --- a/arch/xtensa/core/mpu.c +++ b/arch/xtensa/core/mpu.c @@ -33,6 +33,9 @@ extern char _heap_start[]; /** MPU foreground map for kernel mode. */ static struct xtensa_mpu_map xtensa_mpu_map_fg_kernel; +/** Make sure write to the MPU region is atomic. */ +static struct k_spinlock xtensa_mpu_lock; + /* * Additional information about the MPU maps: foreground and background * maps. @@ -629,6 +632,9 @@ void xtensa_mpu_map_write(struct xtensa_mpu_map *map) #endif { int entry; + k_spinlock_key_t key; + + key = k_spin_lock(&xtensa_mpu_lock); #ifdef CONFIG_USERSPACE struct xtensa_mpu_map *map = thread->arch.mpu_map; @@ -652,6 +658,8 @@ void xtensa_mpu_map_write(struct xtensa_mpu_map *map) __asm__ volatile("wptlb %0, %1\n\t" : : "a"(map->entries[entry].at), "a"(map->entries[entry].as)); } + + k_spin_unlock(&xtensa_mpu_lock, key); } /** From da5f7e18162485dac8df0cedda2f0390b03dda57 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 12 Jul 2024 14:50:03 -0700 Subject: [PATCH 017/269] xtensa: mpu: update hardware if manipulating current domain If adding/removing to the domain of the current running thread, we need to update the hardware MPU regions or else the addition or removal would not be reflected to current running thread. Signed-off-by: Daniel Leung --- arch/xtensa/core/mpu.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/xtensa/core/mpu.c b/arch/xtensa/core/mpu.c index 20ee31727648364..09385323dc72950 100644 --- a/arch/xtensa/core/mpu.c +++ b/arch/xtensa/core/mpu.c @@ -773,6 +773,7 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain, { int ret; uint32_t perm; + struct k_thread *cur_thread; struct xtensa_mpu_map *map = &domain->arch.mpu_map; struct k_mem_partition *partition = &domain->partitions[partition_id]; uintptr_t end_addr = partition->start + partition->size; @@ -841,6 +842,15 @@ int arch_mem_domain_partition_remove(struct k_mem_domain *domain, CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, NULL); + /* + * Need to update hardware MPU regions if we are removing + * partition from the domain of the current running thread. + */ + cur_thread = _current_cpu->current; + if (cur_thread->mem_domain_info.mem_domain == domain) { + xtensa_mpu_map_write(cur_thread); + } + out: return ret; } @@ -849,6 +859,7 @@ int arch_mem_domain_partition_add(struct k_mem_domain *domain, uint32_t partition_id) { int ret; + struct k_thread *cur_thread; struct xtensa_mpu_map *map = &domain->arch.mpu_map; struct k_mem_partition *partition = &domain->partitions[partition_id]; uintptr_t end_addr = partition->start + partition->size; @@ -863,6 +874,20 @@ int arch_mem_domain_partition_add(struct k_mem_domain *domain, CONFIG_XTENSA_MPU_DEFAULT_MEM_TYPE, NULL); + /* + * Need to update hardware MPU regions if we are removing + * partition from the domain of the current running thread. + * + * Note that this function can be called with dummy thread + * at boot so we need to avoid writing MPU regions to + * hardware. + */ + cur_thread = _current_cpu->current; + if (((cur_thread->base.thread_state & _THREAD_DUMMY) != _THREAD_DUMMY) && + (cur_thread->mem_domain_info.mem_domain == domain)) { + xtensa_mpu_map_write(cur_thread); + } + out: return ret; } From 83bdc7f1d9286c19180ce42306f58751359249f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 7 Aug 2024 12:38:14 +0200 Subject: [PATCH 018/269] doc: doxygen: add kconfig_dep alias MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This new alias provides a handy shortcut for listing the Kconfig options that are required for a given symbol to be available. Fixes #76578 Signed-off-by: Benjamin Cabé --- doc/zephyr.doxyfile.in | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/zephyr.doxyfile.in b/doc/zephyr.doxyfile.in index fa59b29dee60eca..05b541c517d9d90 100644 --- a/doc/zephyr.doxyfile.in +++ b/doc/zephyr.doxyfile.in @@ -285,6 +285,9 @@ ALIASES = "rst=\verbatim embed:rst:leading-asterisk" \ "req{1}=\ref ZEPH_\1 \"ZEPH-\1\"" \ "satisfy{1}=\xrefitem satisfy \"Satisfies requirement\" \"Requirement Implementation\" \1" \ "verify{1}=\xrefitem verify \"Verifies requirement\" \"Requirement Verification\" \1" \ + "kconfig_dep{1}=\attention Available only when the following Kconfig option is enabled: \kconfig{\1}." \ + "kconfig_dep{2}=\attention Available only when the following Kconfig options are enabled: \kconfig{\1}, \kconfig{\2}." \ + "kconfig_dep{3}=\attention Available only when the following Kconfig options are enabled: \kconfig{\1}, \kconfig{\2}, \kconfig{\3}." \ "funcprops=\par \"Function properties (list may not be complete)\"" \ "reschedule=\htmlonly reschedule \endhtmlonly \xmlonly embed:rst:inline :ref:`api_term_reschedule` \endxmlonly" \ "sleep=\htmlonly sleep \endhtmlonly \xmlonly embed:rst:inline :ref:`api_term_sleep` \endxmlonly" \ From 8b066bcfe7846a6a3e9a7790b68d32374b22480e Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Thu, 8 Aug 2024 16:36:04 +0900 Subject: [PATCH 019/269] dts: bindings: clock: renesas_ra: Change `_` to `-` in property name `-` is preferred over `_` in devicetree property names. Since, change `clk_src`, `clk_div`, and `clk_out_div` to `clk-src`, `clk-div`, and `clk-out-div`. Signed-off-by: TOKITA Hiroshi --- boards/renesas/ek_ra6m4/ek_ra6m4.dts | 4 ++-- boards/renesas/ek_ra8d1/ek_ra8d1.dts | 4 ++-- boards/renesas/ek_ra8m1/ek_ra8m1.dts | 4 ++-- boards/renesas/mck_ra8t1/mck_ra8t1.dts | 4 ++-- dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi | 8 ++++---- dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi | 12 +++++------ dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi | 12 +++++------ dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi | 12 +++++------ dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi | 14 ++++++------- dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi | 12 +++++------ dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi | 12 +++++------ dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi | 18 ++++++++--------- dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi | 18 ++++++++--------- dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi | 18 ++++++++--------- dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi | 16 +++++++-------- dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi | 16 +++++++-------- dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi | 20 +++++++++---------- dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi | 20 +++++++++---------- dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi | 20 +++++++++---------- dts/bindings/clock/renesas,ra-cgc-busclk.yaml | 2 +- dts/bindings/clock/renesas,ra-cgc-pclk.yaml | 4 ++-- 21 files changed, 125 insertions(+), 125 deletions(-) diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts index 5fcb92a2b93a0cb..f0f447eede7b543 100644 --- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts +++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts @@ -75,7 +75,7 @@ }; &pclka { - clk_src = ; - clk_div = ; + clk-src = ; + clk-div = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts index 879e319ac2ea2d6..698e90e631cd0eb 100644 --- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts +++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts @@ -69,8 +69,8 @@ }; &sciclk { - clk_src = ; - clk_div = ; + clk-src = ; + clk-div = ; status = "okay"; }; diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts index 730e6b3ced2368c..de64b9ecf252b59 100644 --- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts +++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts @@ -92,8 +92,8 @@ }; &sciclk { - clk_src = ; - clk_div = ; + clk-src = ; + clk-div = ; status = "okay"; }; diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts index e51821df8eaaa4d..f7046d491490111 100644 --- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts +++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts @@ -73,8 +73,8 @@ }; &sciclk { - clk_src = ; - clk_div = ; + clk-src = ; + clk-div = ; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index 7f9d1e34c27ebd5..57d2c9201a1ccfa 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -69,28 +69,28 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index 8225091dcdd63ef..ce2185e097cdfe5 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -101,42 +101,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index e914f446ae217b2..d3e763b6e9ad1bc 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -161,42 +161,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index 47781959d66c90c..524ac6322410652 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -169,42 +169,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 6a80685af6ea273..2be6da132529ba4 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -95,42 +95,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; @@ -143,7 +143,7 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index 5a729e425d86975..b92f8a3ead60271 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -161,42 +161,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 51970e2d3db6acf..6af6db001f4df6e 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -91,42 +91,42 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index 015982357eb63ed..f8bbb0e154de029 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -85,45 +85,45 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <0>; #clock-cells = <0>; }; @@ -133,14 +133,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index 560d25e52c39eba..5843d6c7ce899c4 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -116,45 +116,45 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <1>; #clock-cells = <0>; }; @@ -164,14 +164,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index d4148891b52f939..cf3d8e97bce7118 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -156,45 +156,45 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <1>; #clock-cells = <0>; }; @@ -204,14 +204,14 @@ uclk: uclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 1b1b87373773b76..3c5c308fb81623d 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -197,45 +197,45 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <0>; #clock-cells = <0>; }; @@ -245,7 +245,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index 77a46261884dc11..2b1fe78cbd21c04 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -257,45 +257,45 @@ iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <0>; #clock-cells = <0>; }; @@ -305,7 +305,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index 36071180425f390..89beb25bc7bf35f 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -90,59 +90,59 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <1>; #clock-cells = <0>; }; @@ -152,7 +152,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 6007448b8d77721..164928c4cd4b6a9 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -90,59 +90,59 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <1>; #clock-cells = <0>; }; @@ -152,7 +152,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index 8ccbcf29e6f7ca1..51a07401b23d8c9 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -90,59 +90,59 @@ cpuclk: cpuclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; iclk: iclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclka: pclka { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkb: pclkb { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkc: pclkc { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclkd: pclkd { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; pclke: pclke { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; bclk: bclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; bclkout: bclkout { compatible = "renesas,ra-cgc-busclk"; - clk_out_div = <2>; + clk-out-div = <2>; sdclk = <1>; #clock-cells = <0>; }; @@ -152,7 +152,7 @@ fclk: fclk { compatible = "renesas,ra-cgc-pclk"; - clk_div = ; + clk-div = ; #clock-cells = <2>; status = "okay"; }; diff --git a/dts/bindings/clock/renesas,ra-cgc-busclk.yaml b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml index 949a739f2d43ab1..c5c9e0bbfaa299a 100644 --- a/dts/bindings/clock/renesas,ra-cgc-busclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-busclk.yaml @@ -8,7 +8,7 @@ compatible: "renesas,ra-cgc-busclk" include: [clock-controller.yaml, base.yaml] properties: - clk_out_div: + clk-out-div: type: int enum: - 0 diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml index cc001c1717593de..5ea4d708894fead 100644 --- a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml +++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml @@ -8,10 +8,10 @@ compatible: "renesas,ra-cgc-pclk" include: [clock-controller.yaml, base.yaml] properties: - clk_src: + clk-src: type: int - clk_div: + clk-div: type: int required: true description: Prescale divider to calculate the subclock frequency from the From 475ff826d6c206840eadc6b5e3bbba4f77c4a769 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Mon, 9 Sep 2024 13:40:24 +0800 Subject: [PATCH 020/269] drivers: intc: plic: fix IRQ on every hart regardless of mapping Allow IRQs to work on every hart regardless of the mapping of the contexts. Add a test to validate the hart-context mapping. Signed-off-by: Yong Cong Sin Signed-off-by: Yong Cong Sin --- drivers/interrupt_controller/intc_plic.c | 39 ++++++++++--------- .../interrupt_controller/intc_plic/Kconfig | 3 ++ .../intc_plic/alt_mapping.overlay | 29 ++++++++++++++ .../interrupt_controller/intc_plic/src/main.c | 27 +++++++++++++ .../intc_plic/testcase.yaml | 19 ++++++--- 5 files changed, 93 insertions(+), 24 deletions(-) create mode 100644 tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay diff --git a/drivers/interrupt_controller/intc_plic.c b/drivers/interrupt_controller/intc_plic.c index c67041f45e7566a..7a235083cb245ae 100644 --- a/drivers/interrupt_controller/intc_plic.c +++ b/drivers/interrupt_controller/intc_plic.c @@ -64,9 +64,11 @@ #ifdef CONFIG_TEST_INTC_PLIC #define INTC_PLIC_STATIC +#define INTC_PLIC_STATIC_INLINE #else -#define INTC_PLIC_STATIC static inline -#endif +#define INTC_PLIC_STATIC static +#define INTC_PLIC_STATIC_INLINE static inline +#endif /* CONFIG_TEST_INTC_PLIC */ typedef void (*riscv_plic_irq_config_func_t)(void); struct plic_config { @@ -78,6 +80,7 @@ struct plic_config { uint32_t num_irqs; riscv_plic_irq_config_func_t irq_config_func; struct _isr_table_entry *isr_table; + const uint32_t *const hart_context; }; struct plic_stats { @@ -92,12 +95,12 @@ struct plic_data { static uint32_t save_irq; static const struct device *save_dev; -INTC_PLIC_STATIC uint32_t local_irq_to_reg_index(uint32_t local_irq) +INTC_PLIC_STATIC_INLINE uint32_t local_irq_to_reg_index(uint32_t local_irq) { return local_irq >> LOG2(PLIC_REG_SIZE); } -INTC_PLIC_STATIC uint32_t local_irq_to_reg_offset(uint32_t local_irq) +INTC_PLIC_STATIC_INLINE uint32_t local_irq_to_reg_offset(uint32_t local_irq) { return local_irq_to_reg_index(local_irq) * sizeof(uint32_t); } @@ -109,9 +112,11 @@ static inline uint32_t get_plic_enabled_size(const struct device *dev) return local_irq_to_reg_index(config->num_irqs) + 1; } -static inline uint32_t get_first_context(uint32_t hartid) +static ALWAYS_INLINE uint32_t get_hart_context(const struct device *dev, uint32_t hartid) { - return hartid == 0 ? 0 : (hartid * 2) - 1; + const struct plic_config *config = dev->config; + + return config->hart_context[hartid]; } static inline mem_addr_t get_context_en_addr(const struct device *dev, uint32_t cpu_num) @@ -120,17 +125,13 @@ static inline mem_addr_t get_context_en_addr(const struct device *dev, uint32_t uint32_t hartid; /* * We want to return the irq_en address for the context of given hart. - * If hartid is 0, we return the devices irq_en property, job done. If it is - * greater than zero, we assume that there are two context's associated with - * each hart: M mode enable, followed by S mode enable. We return the M mode - * enable address. */ #if CONFIG_SMP hartid = _kernel.cpus[cpu_num].arch.hartid; #else hartid = arch_proc_id(); #endif - return config->irq_en + get_first_context(hartid) * CONTEXT_ENABLE_SIZE; + return config->irq_en + get_hart_context(dev, hartid) * CONTEXT_ENABLE_SIZE; } static inline mem_addr_t get_claim_complete_addr(const struct device *dev) @@ -139,14 +140,9 @@ static inline mem_addr_t get_claim_complete_addr(const struct device *dev) /* * We want to return the claim complete addr for the hart's context. - * We are making a few assumptions here: - * 1. for hart 0, return the first context claim complete. - * 2. for any other hart, we assume they have two privileged mode contexts - * which are contiguous, where the m mode context is first. - * We return the m mode context. */ - return config->reg + get_first_context(arch_proc_id()) * CONTEXT_SIZE + + return config->reg + get_hart_context(dev, arch_proc_id()) * CONTEXT_SIZE + CONTEXT_CLAIM; } @@ -162,7 +158,7 @@ static inline mem_addr_t get_threshold_priority_addr(const struct device *dev, u hartid = arch_proc_id(); #endif - return config->reg + (get_first_context(hartid) * CONTEXT_SIZE); + return config->reg + (get_hart_context(dev, hartid) * CONTEXT_SIZE); } /** @@ -571,8 +567,14 @@ SHELL_CMD_ARG_REGISTER(plic, &plic_cmds, "PLIC shell commands", irq_enable(DT_INST_IRQN(n)); \ } +#define HART_CONTEXTS(i, n) IF_ENABLED(IS_EQ(DT_INST_IRQN_BY_IDX(n, i), DT_INST_IRQN(n)), (i,)) +#define PLIC_HART_CONTEXT_DECLARE(n) \ + INTC_PLIC_STATIC const uint32_t plic_hart_contexts_##n[DT_CHILD_NUM(DT_PATH(cpus))] = { \ + LISTIFY(DT_INST_NUM_IRQS(n), HART_CONTEXTS, (), n)} + #define PLIC_INTC_CONFIG_INIT(n) \ PLIC_INTC_IRQ_FUNC_DECLARE(n); \ + PLIC_HART_CONTEXT_DECLARE(n); \ static const struct plic_config plic_config_##n = { \ .prio = PLIC_BASE_ADDR(n), \ .irq_en = PLIC_BASE_ADDR(n) + CONTEXT_ENABLE_BASE, \ @@ -583,6 +585,7 @@ SHELL_CMD_ARG_REGISTER(plic, &plic_cmds, "PLIC shell commands", .num_irqs = DT_INST_PROP(n, riscv_ndev), \ .irq_config_func = plic_irq_config_func_##n, \ .isr_table = &_sw_isr_table[INTC_INST_ISR_TBL_OFFSET(n)], \ + .hart_context = plic_hart_contexts_##n, \ }; \ PLIC_INTC_IRQ_FUNC_DEFINE(n) diff --git a/tests/drivers/interrupt_controller/intc_plic/Kconfig b/tests/drivers/interrupt_controller/intc_plic/Kconfig index 53ccc57348211ac..476593aa3602a92 100644 --- a/tests/drivers/interrupt_controller/intc_plic/Kconfig +++ b/tests/drivers/interrupt_controller/intc_plic/Kconfig @@ -7,4 +7,7 @@ config TEST_INTC_PLIC help Declare some intc_plic.c functions in the global scope for verification. +config TEST_INTC_PLIC_ALT_MAPPING + bool "Test alternate hartid - context mapping" + source "Kconfig" diff --git a/tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay b/tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay new file mode 100644 index 000000000000000..a25223d03d147f5 --- /dev/null +++ b/tests/drivers/interrupt_controller/intc_plic/alt_mapping.overlay @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/{ + soc { + plic: interrupt-controller@c000000 { + riscv,max-priority = <7>; + riscv,ndev = < 1024 >; + reg = <0x0c000000 0x04000000>; + interrupts-extended = < + &hlic0 0x0b + &hlic1 0x0b &hlic1 0x09 + &hlic2 0x0b &hlic2 0x09 + &hlic3 0x0b &hlic3 0x09 + &hlic4 0x0b &hlic4 0x09 + &hlic5 0x0b &hlic5 0x09 + &hlic6 0x0b &hlic6 0x09 + &hlic7 0x0b &hlic7 0x09 + >; + interrupt-controller; + compatible = "sifive,plic-1.0.0"; + #address-cells = < 0x00 >; + #interrupt-cells = < 0x02 >; + }; + }; +}; diff --git a/tests/drivers/interrupt_controller/intc_plic/src/main.c b/tests/drivers/interrupt_controller/intc_plic/src/main.c index 631e0e8915a3735..de22642e787b808 100644 --- a/tests/drivers/interrupt_controller/intc_plic/src/main.c +++ b/tests/drivers/interrupt_controller/intc_plic/src/main.c @@ -29,3 +29,30 @@ ZTEST(intc_plic, test_local_irq_to_reg_offset) zassert_equal(4, local_irq_to_reg_offset(0x3f)); zassert_equal(8, local_irq_to_reg_offset(0x40)); } + +ZTEST(intc_plic, test_hart_context_mapping) +{ + extern const uint32_t plic_hart_contexts_0[]; + + if (!IS_ENABLED(CONFIG_TEST_INTC_PLIC_ALT_MAPPING)) { + /* Based on the default qemu_riscv64 devicetree */ + zassert_equal(plic_hart_contexts_0[0], 0); + zassert_equal(plic_hart_contexts_0[1], 2); + zassert_equal(plic_hart_contexts_0[2], 4); + zassert_equal(plic_hart_contexts_0[3], 6); + zassert_equal(plic_hart_contexts_0[4], 8); + zassert_equal(plic_hart_contexts_0[5], 10); + zassert_equal(plic_hart_contexts_0[6], 12); + zassert_equal(plic_hart_contexts_0[7], 14); + } else { + /* Based on the definition in the `alt_mapping.overlay` */ + zassert_equal(plic_hart_contexts_0[0], 0); + zassert_equal(plic_hart_contexts_0[1], 1); + zassert_equal(plic_hart_contexts_0[2], 3); + zassert_equal(plic_hart_contexts_0[3], 5); + zassert_equal(plic_hart_contexts_0[4], 7); + zassert_equal(plic_hart_contexts_0[5], 9); + zassert_equal(plic_hart_contexts_0[6], 11); + zassert_equal(plic_hart_contexts_0[7], 13); + } +} diff --git a/tests/drivers/interrupt_controller/intc_plic/testcase.yaml b/tests/drivers/interrupt_controller/intc_plic/testcase.yaml index 11c1f74fa39a32b..a798cd76f8fa709 100644 --- a/tests/drivers/interrupt_controller/intc_plic/testcase.yaml +++ b/tests/drivers/interrupt_controller/intc_plic/testcase.yaml @@ -1,7 +1,14 @@ +common: + platform_allow: qemu_riscv64 + tags: + - drivers + - interrupt + - plic + tests: - drivers.interrupt_controller.intc_plic: - tags: - - drivers - - interrupt - - plic - platform_allow: qemu_riscv64 + drivers.interrupt_controller.intc_plic: {} + drivers.interrupt_controller.intc_plic.alt_mapping: + extra_args: + DTC_OVERLAY_FILE="./alt_mapping.overlay" + extra_configs: + - CONFIG_TEST_INTC_PLIC_ALT_MAPPING=y From 7dff1c13742116e078108bace1a4419d4a18ed03 Mon Sep 17 00:00:00 2001 From: Sean Madigan Date: Tue, 10 Sep 2024 11:02:58 +0100 Subject: [PATCH 021/269] bluetooth: kconfig: Add channel sounding kconfigs Add new controller and host kconfigs for Bluetooth 6.0 Channel Sounding. Signed-off-by: Sean Madigan --- subsys/bluetooth/Kconfig | 7 +++++++ subsys/bluetooth/controller/Kconfig | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/subsys/bluetooth/Kconfig b/subsys/bluetooth/Kconfig index fad998375bd808b..e8c7d9676d74b6d 100644 --- a/subsys/bluetooth/Kconfig +++ b/subsys/bluetooth/Kconfig @@ -189,6 +189,13 @@ config BT_SUBRATING Enable support for LE Connection Subrating feature that is defined in the Bluetooth Core specification, Version 5.4 | Vol 6, Part B, Section 4.6.35. +config BT_CHANNEL_SOUNDING + bool "Channel Sounding support" + select EXPERIMENTAL + depends on !BT_CTLR || BT_CTLR_CHANNEL_SOUNDING_SUPPORT + help + Enable support for Bluetooth 6.0 Channel Sounding feature. + endif # BT_CONN rsource "Kconfig.iso" diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig index 9069e402ba8bb87..25f480788e14ef0 100644 --- a/subsys/bluetooth/controller/Kconfig +++ b/subsys/bluetooth/controller/Kconfig @@ -118,6 +118,9 @@ config BT_CTLR_LE_PATH_LOSS_MONITORING_SUPPORT config BT_CTLR_SUBRATING_SUPPORT bool +config BT_CTLR_CHANNEL_SOUNDING_SUPPORT + bool + config BT_CTLR bool "Bluetooth Controller" help @@ -1069,6 +1072,15 @@ config BT_CTLR_SUBRATING Enable support for Bluetooth v5.3 LE Connection Subrating in the Controller. +config BT_CTLR_CHANNEL_SOUNDING + bool "Channel Sounding support" + depends on BT_CTLR_CHANNEL_SOUNDING_SUPPORT + select BT_CTLR_SET_HOST_FEATURE + default y if BT_CHANNEL_SOUNDING + help + Enable support for Bluetooth 6.0 Channel Sounding in the + Controller. + rsource "Kconfig.df" rsource "Kconfig.ll_sw_split" rsource "Kconfig.dtm" From aedb330c709b8cef6876843b70e397d5b3436c4f Mon Sep 17 00:00:00 2001 From: Sean Madigan Date: Fri, 13 Sep 2024 08:09:37 +0100 Subject: [PATCH 022/269] bluetooth: host: Add support for CS set default settings Added support for a new API for setting default channel sounding settings, this is mainly a wrapper around the HCI command. For this add a new module for channel sounding, where new channel sounding APIs will go. Signed-off-by: Sean Madigan --- include/zephyr/bluetooth/cs.h | 86 ++++++++++++++++++++++++++++ include/zephyr/bluetooth/hci_types.h | 22 +++++++ subsys/bluetooth/host/CMakeLists.txt | 5 ++ subsys/bluetooth/host/cs.c | 44 ++++++++++++++ 4 files changed, 157 insertions(+) create mode 100644 include/zephyr/bluetooth/cs.h create mode 100644 subsys/bluetooth/host/cs.c diff --git a/include/zephyr/bluetooth/cs.h b/include/zephyr/bluetooth/cs.h new file mode 100644 index 000000000000000..903f32eccb03919 --- /dev/null +++ b/include/zephyr/bluetooth/cs.h @@ -0,0 +1,86 @@ +/** @file + * @brief Bluetooth Channel Sounding handling + */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_CS_H_ +#define ZEPHYR_INCLUDE_BLUETOOTH_CS_H_ + +/** + * @brief Channel Sounding (CS) + * @defgroup bt_cs Channel Sounding (CS) + * @ingroup bluetooth + * @{ + */ + +#include +#include + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum bt_cs_sync_antenna_selection_opt { + /** Use antenna identifier 1 for CS_SYNC packets. */ + BT_CS_ANTENNA_SELECTION_OPT_ONE = BT_HCI_OP_LE_CS_ANTENNA_SEL_ONE, + /** Use antenna identifier 2 for CS_SYNC packets. */ + BT_CS_ANTENNA_SELECTION_OPT_TWO = BT_HCI_OP_LE_CS_ANTENNA_SEL_TWO, + /** Use antenna identifier 3 for CS_SYNC packets. */ + BT_CS_ANTENNA_SELECTION_OPT_THREE = BT_HCI_OP_LE_CS_ANTENNA_SEL_THREE, + /** Use antenna identifier 4 for CS_SYNC packets. */ + BT_CS_ANTENNA_SELECTION_OPT_FOUR = BT_HCI_OP_LE_CS_ANTENNA_SEL_FOUR, + /** Use antennas in repetitive order from 1 to 4 for CS_SYNC packets. */ + BT_CS_ANTENNA_SELECTION_OPT_REPETITIVE = BT_HCI_OP_LE_CS_ANTENNA_SEL_REP, + /** No recommendation for local controller antenna selection. */ + BT_CS_ANTENNA_SELECTION_OPT_NO_RECOMMENDATION = BT_HCI_OP_LE_CS_ANTENNA_SEL_NONE, +}; + +/** Default CS settings in the local Controller */ +struct bt_cs_set_default_settings_param { + /** Enable CS initiator role. */ + bool enable_initiator_role; + /** Enable CS reflector role. */ + bool enable_reflector_role; + /** Antenna identifier to be used for CS_SYNC packets by the local controller. + */ + enum bt_cs_sync_antenna_selection_opt cs_sync_antenna_selection; + /** Maximum output power (Effective Isotropic Radiated Power) to be used + * for all CS transmissions. + * + * Value range is @ref BT_HCI_OP_LE_CS_MIN_MAX_TX_POWER to + * @ref BT_HCI_OP_LE_CS_MAX_MAX_TX_POWER. + */ + int8_t max_tx_power; +}; + +/** @brief Set Channel Sounding default settings. + * + * This command is used to set default Channel Sounding settings for this + * connection. + * + * @note To use this API @kconfig{CONFIG_BT_CHANNEL_SOUNDING} must be set. + * + * @param conn Connection Object. + * @param params Channel sounding default settings parameters. + * + * @return Zero on success or (negative) error code on failure. + */ +int bt_cs_set_default_settings(struct bt_conn *conn, + const struct bt_cs_set_default_settings_param *params); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_CS_H_ */ diff --git a/include/zephyr/bluetooth/hci_types.h b/include/zephyr/bluetooth/hci_types.h index 83bd3a55d4c059b..afdb03f0ce9bfa2 100644 --- a/include/zephyr/bluetooth/hci_types.h +++ b/include/zephyr/bluetooth/hci_types.h @@ -2395,6 +2395,28 @@ struct bt_hci_cp_le_tx_test_v4_tx_power { int8_t tx_power; } __packed; +#define BT_HCI_OP_LE_CS_SET_DEFAULT_SETTINGS BT_OP(BT_OGF_LE, 0x008D) /* 0x208D */ + +#define BT_HCI_OP_LE_CS_INITIATOR_ROLE_MASK BIT(0) +#define BT_HCI_OP_LE_CS_REFLECTOR_ROLE_MASK BIT(1) + +#define BT_HCI_OP_LE_CS_MIN_MAX_TX_POWER -127 +#define BT_HCI_OP_LE_CS_MAX_MAX_TX_POWER 20 + +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_ONE 0x01 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_TWO 0x02 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_THREE 0x03 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_FOUR 0x04 +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_REP 0xFE +#define BT_HCI_OP_LE_CS_ANTENNA_SEL_NONE 0xFF + +struct bt_hci_cp_le_cs_set_default_settings { + uint16_t handle; + uint8_t role_enable; + uint8_t cs_sync_antenna_selection; + int8_t max_tx_power; +} __packed; + /* Event definitions */ #define BT_HCI_EVT_UNKNOWN 0x00 diff --git a/subsys/bluetooth/host/CMakeLists.txt b/subsys/bluetooth/host/CMakeLists.txt index 1b1b6a58543698a..860e9cc7d746096 100644 --- a/subsys/bluetooth/host/CMakeLists.txt +++ b/subsys/bluetooth/host/CMakeLists.txt @@ -68,6 +68,11 @@ if(CONFIG_BT_HCI_HOST) conn.c ) + zephyr_library_sources_ifdef( + CONFIG_BT_CHANNEL_SOUNDING + cs.c + ) + if(CONFIG_BT_DF) zephyr_library_sources( direction.c diff --git a/subsys/bluetooth/host/cs.c b/subsys/bluetooth/host/cs.c new file mode 100644 index 000000000000000..4ec67fd42cea38a --- /dev/null +++ b/subsys/bluetooth/host/cs.c @@ -0,0 +1,44 @@ +/* cs.c - Bluetooth Channel Sounding handling */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include "conn_internal.h" + +#if defined(CONFIG_BT_CHANNEL_SOUNDING) +int bt_cs_set_default_settings(struct bt_conn *conn, + const struct bt_cs_set_default_settings_param *params) +{ + struct bt_hci_cp_le_cs_set_default_settings *cp; + struct net_buf *buf; + + buf = bt_hci_cmd_create(BT_HCI_OP_LE_CS_SET_DEFAULT_SETTINGS, sizeof(*cp)); + if (!buf) { + return -ENOBUFS; + } + + cp = net_buf_add(buf, sizeof(*cp)); + cp->handle = sys_cpu_to_le16(conn->handle); + cp->max_tx_power = params->max_tx_power; + cp->cs_sync_antenna_selection = params->cs_sync_antenna_selection; + cp->role_enable = 0; + + if (params->enable_initiator_role) { + cp->role_enable |= BT_HCI_OP_LE_CS_INITIATOR_ROLE_MASK; + } + + if (params->enable_reflector_role) { + cp->role_enable |= BT_HCI_OP_LE_CS_REFLECTOR_ROLE_MASK; + } + + return bt_hci_cmd_send_sync(BT_HCI_OP_LE_CS_SET_DEFAULT_SETTINGS, buf, NULL); +} +#endif /* CONFIG_BT_CHANNEL_SOUNDING */ From aa67cb238a1bca98ae516525817122e8216b22f0 Mon Sep 17 00:00:00 2001 From: Sean Madigan Date: Tue, 10 Sep 2024 11:02:29 +0100 Subject: [PATCH 023/269] bluetooth: shell: Add CS to BT shell with set default settings command Use a new file and command for this where all CS commands can live. Added support for bt_cs_set_default_settings command. Added test case where shell is built with CS to ensure code is built in CI. Signed-off-by: Sean Madigan --- subsys/bluetooth/shell/CMakeLists.txt | 4 + subsys/bluetooth/shell/cs.c | 123 ++++++++++++++++++++++++++ tests/bluetooth/shell/testcase.yaml | 7 ++ 3 files changed, 134 insertions(+) create mode 100644 subsys/bluetooth/shell/cs.c diff --git a/subsys/bluetooth/shell/CMakeLists.txt b/subsys/bluetooth/shell/CMakeLists.txt index 58d3ba5b2d951ed..f6cc40e6d4a0634 100644 --- a/subsys/bluetooth/shell/CMakeLists.txt +++ b/subsys/bluetooth/shell/CMakeLists.txt @@ -29,6 +29,10 @@ zephyr_library_sources_ifdef( CONFIG_BT_ISO iso.c ) +zephyr_library_sources_ifdef( + CONFIG_BT_CHANNEL_SOUNDING + cs.c + ) zephyr_library_sources_ifdef( CONFIG_BT_IAS ias.c diff --git a/subsys/bluetooth/shell/cs.c b/subsys/bluetooth/shell/cs.c new file mode 100644 index 000000000000000..00a16cb4adb8852 --- /dev/null +++ b/subsys/bluetooth/shell/cs.c @@ -0,0 +1,123 @@ +/** @file + * @brief Bluetooth Channel Sounding (CS) shell + * + */ + +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "bt.h" + +static int check_cs_sync_antenna_selection_input(uint16_t input) +{ + if (input != BT_CS_ANTENNA_SELECTION_OPT_ONE && input != BT_CS_ANTENNA_SELECTION_OPT_TWO && + input != BT_CS_ANTENNA_SELECTION_OPT_THREE && + input != BT_CS_ANTENNA_SELECTION_OPT_FOUR && + input != BT_CS_ANTENNA_SELECTION_OPT_REPETITIVE && + input != BT_CS_ANTENNA_SELECTION_OPT_NO_RECOMMENDATION) { + return -EINVAL; + } + + return 0; +} + +static int cmd_set_default_settings(const struct shell *sh, size_t argc, char *argv[]) +{ + int err = 0; + struct bt_cs_set_default_settings_param params; + uint16_t antenna_input; + int16_t tx_power_input; + + if (default_conn == NULL) { + shell_error(sh, "Conn handle error, at least one connection is required."); + return -ENOEXEC; + } + + params.enable_initiator_role = shell_strtobool(argv[1], 10, &err); + if (err) { + shell_help(sh); + shell_error(sh, "Could not parse input 1, Enable initiator role"); + return SHELL_CMD_HELP_PRINTED; + } + + params.enable_reflector_role = shell_strtobool(argv[2], 10, &err); + if (err) { + shell_help(sh); + shell_error(sh, "Could not parse input 2, Enable reflector role"); + return SHELL_CMD_HELP_PRINTED; + } + + antenna_input = shell_strtoul(argv[3], 16, &err); + if (err) { + shell_help(sh); + shell_error(sh, "Could not parse input 3, CS_SYNC antenna selection"); + return SHELL_CMD_HELP_PRINTED; + } + + err = check_cs_sync_antenna_selection_input(antenna_input); + if (err) { + shell_help(sh); + shell_error(sh, "CS_SYNC antenna selection input invalid"); + return SHELL_CMD_HELP_PRINTED; + } + + tx_power_input = shell_strtol(argv[4], 10, &err); + if (err) { + shell_help(sh); + shell_error(sh, "Could not parse input 4, Max TX power"); + return SHELL_CMD_HELP_PRINTED; + } + + params.cs_sync_antenna_selection = antenna_input; + params.max_tx_power = tx_power_input; + + err = bt_cs_set_default_settings(default_conn, ¶ms); + if (err) { + shell_error(sh, "bt_cs_set_default_settings returned error %d", err); + return -ENOEXEC; + } + + return 0; +} + +SHELL_STATIC_SUBCMD_SET_CREATE( + cs_cmds, + SHELL_CMD_ARG( + set_default_settings, NULL, + " " + " ", + cmd_set_default_settings, 5, 0), + SHELL_SUBCMD_SET_END); + +static int cmd_cs(const struct shell *sh, size_t argc, char **argv) +{ + if (argc == 1) { + shell_help(sh); + + return SHELL_CMD_HELP_PRINTED; + } + + shell_error(sh, "%s unknown parameter: %s", argv[0], argv[1]); + + return -EINVAL; +} + +SHELL_CMD_ARG_REGISTER(cs, &cs_cmds, "Bluetooth CS shell commands", cmd_cs, 1, 1); diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml index 269d9319b7cbff0..129792ee63f0479 100644 --- a/tests/bluetooth/shell/testcase.yaml +++ b/tests/bluetooth/shell/testcase.yaml @@ -43,6 +43,13 @@ tests: platform_allow: - native_sim build_only: true + bluetooth.shell.channel_sounding: + extra_configs: + - CONFIG_BT_CHANNEL_SOUNDING=y + - CONFIG_BT_CTLR=n + platform_allow: + - native_sim + build_only: true bluetooth.shell.cdc_acm: extra_args: - OVERLAY_CONFIG=cdc_acm.conf From 1dde70637d2a3a28fd4ae5ca9ec4a0bc9d4b0261 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 11 Sep 2024 14:06:26 +0200 Subject: [PATCH 024/269] Intel: ACE: move hpsram_mask to a data section On platforms with enforced memory access modes, .text is read-only. Move hpsram_mask to a cached data section to fix PTL. Signed-off-by: Guennadi Liakhovetski --- soc/intel/intel_adsp/ace/power_down.S | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/soc/intel/intel_adsp/ace/power_down.S b/soc/intel/intel_adsp/ace/power_down.S index 234c8570bddabe4..42ea10899efaea0 100644 --- a/soc/intel/intel_adsp/ace/power_down.S +++ b/soc/intel/intel_adsp/ace/power_down.S @@ -4,20 +4,24 @@ #include "asm_memory_management.h" + .section .cached.hpsram_mask, "w" + .align 64 +hpsram_mask: + .rept MAX_MEMORY_SEGMENTS + .word 0 + .endr + + .global hpsram_mask + .section .text, "ax" .align 64 power_down_literals: .literal_position ipc_flag: .word 0x80000000 // IPC_DIPCTDR_BUSY -hpsram_mask: - .rept MAX_MEMORY_SEGMENTS - .word 0 - .endr sram_dis_loop_cnt: .word 4096 - .global hpsram_mask .global power_down .type power_down, @function From 7f63faa4f5a9b94bed615c59c4583336b95e0480 Mon Sep 17 00:00:00 2001 From: Hake Huang Date: Wed, 11 Sep 2024 21:19:06 +0800 Subject: [PATCH 025/269] twister: hwmap: add script parameter support for pre/post/post_flash script, add timeout as param Signed-off-by: Hake Huang --- scripts/pylib/twister/twisterlib/handlers.py | 16 +++++++++++++--- scripts/pylib/twister/twisterlib/hardwaremap.py | 4 ++++ scripts/schemas/twister/hwmap-schema.yaml | 13 +++++++++++++ scripts/tests/twister/test_hardwaremap.py | 14 ++++++++++++-- 4 files changed, 42 insertions(+), 5 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 26472a795f0f425..90b834cd4025654 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -689,9 +689,13 @@ def handle(self, harness): pre_script = hardware.pre_script post_flash_script = hardware.post_flash_script post_script = hardware.post_script + script_param = hardware.script_param if pre_script: - self.run_custom_script(pre_script, 30) + timeout = 30 + if script_param: + timeout = script_param.get("pre_script_timeout", timeout) + self.run_custom_script(pre_script, timeout) flash_timeout = hardware.flash_timeout if hardware.flash_with_test: @@ -756,7 +760,10 @@ def handle(self, harness): flash_error = True if post_flash_script: - self.run_custom_script(post_flash_script, 30) + timeout = 30 + if script_param: + timeout = script_param.get("post_flash_timeout", timeout) + self.run_custom_script(post_flash_script, timeout) # Connect to device after flashing it if hardware.flash_before: @@ -795,7 +802,10 @@ def handle(self, harness): self._final_handle_actions(harness, handler_time) if post_script: - self.run_custom_script(post_script, 30) + timeout = 30 + if script_param: + timeout = script_param.get("post_script_timeout", timeout) + self.run_custom_script(post_script, timeout) self.make_dut_available(hardware) diff --git a/scripts/pylib/twister/twisterlib/hardwaremap.py b/scripts/pylib/twister/twisterlib/hardwaremap.py index 979366d93cece9d..616538002809d9e 100644 --- a/scripts/pylib/twister/twisterlib/hardwaremap.py +++ b/scripts/pylib/twister/twisterlib/hardwaremap.py @@ -47,6 +47,7 @@ def __init__(self, pre_script=None, post_script=None, post_flash_script=None, + script_param=None, runner=None, flash_timeout=60, flash_with_test=False, @@ -70,6 +71,7 @@ def __init__(self, self.post_flash_script = post_flash_script self.post_script = post_script self.pre_script = pre_script + self.script_param = script_param self.probe_id = None self.notes = None self.lock = Lock() @@ -248,6 +250,7 @@ def load(self, map_file): duts = scl.yaml_load_verify(map_file, hwm_schema) for dut in duts: pre_script = dut.get('pre_script') + script_param = dut.get('script_param') post_script = dut.get('post_script') post_flash_script = dut.get('post_flash_script') flash_timeout = dut.get('flash_timeout') or self.options.device_flash_timeout @@ -282,6 +285,7 @@ def load(self, map_file): flash_before=flash_before, post_script=post_script, post_flash_script=post_flash_script, + script_param=script_param, flash_timeout=flash_timeout, flash_with_test=flash_with_test) new_dut.fixtures = fixtures diff --git a/scripts/schemas/twister/hwmap-schema.yaml b/scripts/schemas/twister/hwmap-schema.yaml index 1865462fc46d76b..f45bd8f79c79337 100644 --- a/scripts/schemas/twister/hwmap-schema.yaml +++ b/scripts/schemas/twister/hwmap-schema.yaml @@ -64,3 +64,16 @@ sequence: "flash_before": type: bool required: false + "script_param": + type: map + required: false + mapping: + "pre_script_timeout": + type: int + required: false + "post_script_timeout": + type: int + required: false + "post_flash_timeout": + type: int + required: false diff --git a/scripts/tests/twister/test_hardwaremap.py b/scripts/tests/twister/test_hardwaremap.py index 8bb0c27ffa8273f..501791f73223b6f 100644 --- a/scripts/tests/twister/test_hardwaremap.py +++ b/scripts/tests/twister/test_hardwaremap.py @@ -59,7 +59,12 @@ def mocked_hm(): 'post_flash_script': 'dummy post flash script', 'runner': 'dummy runner', 'flash_timeout': 30, - 'flash_with_test': True + 'flash_with_test': True, + 'script_param': { + 'pre_script_timeout' : 30, + 'post_flash_timeout' : 30, + 'post_script_timeout' : 30, + } }, { 'lock': mock.ANY, @@ -76,7 +81,12 @@ def mocked_hm(): 'post_flash_script': 'dummy post flash script', 'runner': 'dummy runner', 'flash_timeout': 30, - 'flash_with_test': True + 'flash_with_test': True, + 'script_param': { + 'pre_script_timeout' : 30, + 'post_flash_timeout' : 30, + 'post_script_timeout' : 30, + } }, '' ), From f1374b7fa69173e3e32205f8f0f11a515aba0c36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Sat, 14 Sep 2024 09:25:47 +0200 Subject: [PATCH 026/269] doc: misc Sphinx/ReST lint fixes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fixed some ReST/Sphinx lint issues missed in earlier cleanups prior to introducing Sphinx-linter in compliance check Signed-off-by: Benjamin Cabé --- boards/acrn/acrn/doc/index.rst | 4 ++-- boards/espressif/esp_wrover_kit/doc/index.rst | 4 ++-- boards/snps/iotdk/doc/index.rst | 2 +- boards/ti/msp_exp432p401r_launchxl/doc/index.rst | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/boards/acrn/acrn/doc/index.rst b/boards/acrn/acrn/doc/index.rst index 9251284106d7a68..5cf24a37232f450 100644 --- a/boards/acrn/acrn/doc/index.rst +++ b/boards/acrn/acrn/doc/index.rst @@ -5,8 +5,8 @@ Zephyr's is capable of running as a guest under the x86 ACRN hypervisor (see https://projectacrn.org/). The process for getting this to work is somewhat involved, however. -ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so- -called "pre-launched" mode. This means Zephyr will access the ACRN +ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so-called +"pre-launched" mode. This means Zephyr will access the ACRN hypervisor directly without involving the SOS VM. This is the most practical user scenario in the real world because Zephyr's real-time and safety capability can be assured without influence from other diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst index 7f9cfcaa393c95a..67991e02019a207 100644 --- a/boards/espressif/esp_wrover_kit/doc/index.rst +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -272,8 +272,8 @@ Legend: Since GPIO32 and GPIO33 are connected to the oscillator by default, they are not connected to the JP1 I/O connector to maintain signal integrity. This allocation may be changed from the - oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re- - soldering them to positions R12 / R24. + oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re-soldering + them to positions R12 / R24. SPI Flash / JP2 *************** diff --git a/boards/snps/iotdk/doc/index.rst b/boards/snps/iotdk/doc/index.rst index e3d99ce242359df..8057e851b6645cb 100644 --- a/boards/snps/iotdk/doc/index.rst +++ b/boards/snps/iotdk/doc/index.rst @@ -191,7 +191,7 @@ References .. _embARC website: https://www.embarc.org -.. _Designware ARC IoT Development Kit website: `_ +.. _Designware ARC IoT Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit .. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules diff --git a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst index e24d8140a253b79..78662d6b7ba9bb4 100644 --- a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst +++ b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst @@ -32,8 +32,8 @@ Supported Features ================== * The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the - default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low- - power modes to be used. + default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low-power + modes to be used. * The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK. The MSP-EXP432P401R LaunchXL development board configuration supports the following hardware features: From 9a16b938689e7ec374422ba08da18499575e31ef Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Wed, 11 Sep 2024 22:26:10 +0200 Subject: [PATCH 027/269] samples: hello_world: use zephyr:code-sample directive MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds missing code-sample directive to the Hello World sample in preparation for upcoming changes to the Zephyr documentation that will be leveraging the provided description and metadata. Signed-off-by: Benjamin Cabé --- boards/96boards/aerocore2/doc/index.rst | 2 +- boards/96boards/argonkey/doc/index.rst | 2 +- boards/96boards/carbon/doc/stm32f401xe.rst | 2 +- boards/96boards/neonkey/doc/index.rst | 2 +- boards/96boards/nitrogen/doc/index.rst | 4 ++-- boards/96boards/stm32_sensor_mez/doc/index.rst | 6 +++--- boards/96boards/wistrio/doc/96b_wistrio.rst | 2 +- boards/adafruit/feather_m0_basic_proto/doc/index.rst | 2 +- boards/adafruit/feather_m0_lora/doc/index.rst | 2 +- boards/adafruit/grand_central_m4_express/doc/index.rst | 2 +- boards/adafruit/itsybitsy_m4_express/doc/index.rst | 2 +- boards/adafruit/nrf52_adafruit_feather/doc/index.rst | 4 ++-- boards/adafruit/trinket_m0/doc/index.rst | 2 +- boards/adi/eval_adin1110ebz/doc/index.rst | 4 ++-- boards/adi/eval_adin2111ebz/doc/index.rst | 4 ++-- boards/adi/max32690fthr/doc/index.rst | 4 ++-- boards/adi/sdp_k1/doc/index.rst | 2 +- boards/alientek/pandora_stm32l475/doc/index.rst | 4 ++-- boards/altr/max10/doc/index.rst | 2 +- boards/ambiq/apollo3_evb/doc/index.rst | 2 +- boards/ambiq/apollo3p_evb/doc/index.rst | 2 +- boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst | 2 +- boards/ambiq/apollo4p_evb/doc/index.rst | 2 +- boards/andestech/adp_xc7k_ae350/doc/index.rst | 2 +- boards/arduino/due/doc/index.rst | 2 +- boards/arduino/giga_r1/doc/index.rst | 2 +- boards/arduino/mkrzero/doc/index.rst | 2 +- boards/arduino/nano_33_iot/doc/index.rst | 2 +- boards/arduino/nicla_sense_me/doc/index.rst | 4 ++-- boards/arduino/nicla_vision/doc/index.rst | 2 +- boards/arduino/portenta_h7/doc/index.rst | 2 +- boards/arduino/zero/doc/index.rst | 2 +- boards/arm/mps2/doc/mps2_an385.rst | 2 +- boards/arm/mps2/doc/mps2_an521.rst | 2 +- boards/arm/mps3/doc/index.rst | 2 +- boards/arm/v2m_beetle/doc/index.rst | 2 +- boards/arm/v2m_musca_b1/doc/index.rst | 2 +- boards/arm/v2m_musca_s1/doc/index.rst | 4 ++-- boards/atmel/sam/sam4e_xpro/doc/index.rst | 6 +++--- boards/atmel/sam/sam4l_ek/doc/index.rst | 4 ++-- boards/atmel/sam/sam4s_xplained/doc/index.rst | 6 +++--- boards/atmel/sam/sam_e70_xplained/doc/index.rst | 4 ++-- boards/atmel/sam/sam_v71_xult/doc/index.rst | 4 ++-- boards/atmel/sam0/samd20_xpro/doc/index.rst | 2 +- boards/atmel/sam0/samr21_xpro/doc/index.rst | 2 +- boards/bbc/microbit/doc/index.rst | 2 +- boards/bbc/microbit_v2/doc/index.rst | 2 +- boards/blues/swan_r5/doc/index.rst | 2 +- boards/bytesatwork/bytesensi_l/doc/index.rst | 2 +- boards/circuitdojo/feather/doc/index.rst | 2 +- boards/contextualelectronics/abc/doc/index.rst | 2 +- boards/cypress/cy8ckit_062_ble/doc/index.rst | 4 ++-- boards/digilent/arty_a7/doc/index.rst | 4 ++-- boards/digilent/zybo/doc/index.rst | 6 +++--- boards/dragino/lsn50/doc/index.rst | 4 ++-- boards/dragino/nbsn95/doc/index.rst | 4 ++-- boards/electronut/nrf52840_blip/doc/index.rst | 2 +- boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst | 2 +- boards/espressif/esp32_devkitc_wroom/doc/index.rst | 6 +++--- boards/espressif/esp32_devkitc_wrover/doc/index.rst | 6 +++--- boards/espressif/esp32_ethernet_kit/doc/index.rst | 6 +++--- boards/espressif/esp32c3_devkitc/doc/index.rst | 6 +++--- boards/espressif/esp32c3_devkitm/doc/index.rst | 6 +++--- boards/espressif/esp32c3_rust/doc/index.rst | 6 +++--- boards/espressif/esp32c6_devkitc/doc/index.rst | 6 +++--- boards/espressif/esp32s2_devkitc/doc/index.rst | 6 +++--- boards/espressif/esp32s2_saola/doc/index.rst | 6 +++--- boards/espressif/esp32s3_devkitc/doc/index.rst | 6 +++--- boards/espressif/esp32s3_devkitm/doc/index.rst | 6 +++--- boards/espressif/esp8684_devkitm/doc/index.rst | 6 +++--- boards/espressif/esp_wrover_kit/doc/index.rst | 6 +++--- boards/ezurio/bl5340_dvk/doc/index.rst | 2 +- boards/ezurio/bl652_dvk/doc/bl652_dvk.rst | 2 +- boards/ezurio/bl653_dvk/doc/bl653_dvk.rst | 2 +- boards/ezurio/bl654_dvk/doc/bl654_dvk.rst | 2 +- .../ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst | 2 +- boards/ezurio/bt510/doc/bt510.rst | 2 +- boards/ezurio/bt610/doc/bt610.rst | 2 +- boards/ezurio/mg100/doc/index.rst | 2 +- boards/ezurio/pinnacle_100_dvk/doc/index.rst | 2 +- boards/ezurio/rm1xx_dvk/doc/index.rst | 2 +- boards/fanke/fk7b0m1_vbt6/doc/index.rst | 2 +- boards/franzininho/esp32s2_franzininho/doc/index.rst | 2 +- boards/gd/gd32a503v_eval/doc/index.rst | 4 ++-- boards/gd/gd32e103v_eval/doc/index.rst | 4 ++-- boards/gd/gd32e507v_start/doc/index.rst | 2 +- boards/gd/gd32e507z_eval/doc/index.rst | 2 +- boards/gd/gd32f350r_eval/doc/index.rst | 2 +- boards/gd/gd32f403z_eval/doc/index.rst | 4 ++-- boards/gd/gd32f407v_start/doc/index.rst | 2 +- boards/gd/gd32f450i_eval/doc/index.rst | 2 +- boards/gd/gd32f450v_start/doc/index.rst | 2 +- boards/gd/gd32f450z_eval/doc/index.rst | 2 +- boards/gd/gd32f470i_eval/doc/index.rst | 2 +- boards/gd/gd32l233r_eval/doc/index.rst | 2 +- boards/gd/gd32vf103c_starter/doc/index.rst | 2 +- boards/gd/gd32vf103v_eval/doc/index.rst | 2 +- boards/hardkernel/odroid_go/doc/index.rst | 6 +++--- boards/heltec/heltec_wifi_lora32_v2/doc/index.rst | 6 +++--- boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst | 6 +++--- boards/infineon/xmc45_relax_kit/doc/index.rst | 4 ++-- boards/infineon/xmc47_relax_kit/doc/index.rst | 4 ++-- boards/innblue/innblue21/doc/index.rst | 2 +- boards/innblue/innblue22/doc/index.rst | 2 +- boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst | 2 +- boards/ite/it82xx2_evb/doc/index.rst | 2 +- boards/ite/it8xxx2_evb/doc/index.rst | 2 +- boards/khadas/edgev/doc/index.rst | 2 +- boards/kincony/kincony_kc868_a32/doc/index.rst | 2 +- boards/lilygo/ttgo_lora32/doc/index.rst | 2 +- boards/lilygo/ttgo_t8c3/doc/index.rst | 2 +- boards/lowrisc/opentitan_earlgrey/doc/index.rst | 2 +- boards/luatos/esp32c3_luatos_core/doc/index.rst | 6 +++--- boards/luatos/esp32s3_luatos_core/doc/index.rst | 6 +++--- boards/m5stack/m5stack_atom_lite/doc/index.rst | 2 +- boards/m5stack/m5stack_atoms3/doc/index.rst | 2 +- boards/m5stack/m5stack_atoms3_lite/doc/index.rst | 2 +- boards/m5stack/m5stack_core2/doc/index.rst | 2 +- boards/m5stack/m5stack_stamps3/doc/index.rst | 2 +- boards/m5stack/m5stickc_plus/doc/index.rst | 2 +- boards/m5stack/stamp_c3/doc/index.rst | 6 +++--- boards/madmachine/mm_feather/doc/index.rst | 4 ++-- boards/madmachine/mm_swiftio/doc/index.rst | 2 +- boards/microchip/mec1501modular_assy6885/doc/index.rst | 2 +- boards/microchip/mec15xxevb_assy6853/doc/index.rst | 2 +- boards/microchip/mec172xevb_assy6906/doc/index.rst | 2 +- .../doc/mec172xmodular_assy6930.rst | 2 +- boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst | 4 ++-- .../mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst | 4 ++-- boards/mxchip/az3166_iotdevkit/doc/index.rst | 2 +- boards/nordic/nrf21540dk/doc/index.rst | 2 +- boards/nordic/nrf51dk/doc/index.rst | 2 +- boards/nordic/nrf51dongle/doc/index.rst | 2 +- boards/nordic/nrf52833dk/doc/index.rst | 2 +- boards/nordic/nrf52840dk/doc/index.rst | 2 +- boards/nordic/nrf52dk/doc/index.rst | 2 +- boards/nordic/nrf5340dk/doc/index.rst | 2 +- boards/nordic/nrf54h20dk/doc/index.rst | 2 +- boards/nordic/nrf54l15dk/doc/index.rst | 2 +- boards/nordic/nrf54l15pdk/doc/index.rst | 2 +- boards/nordic/nrf54l20pdk/doc/index.rst | 2 +- boards/nordic/nrf7002dk/doc/index.rst | 2 +- boards/nordic/nrf9131ek/doc/index.rst | 2 +- boards/nordic/nrf9151dk/doc/index.rst | 2 +- boards/nordic/nrf9160dk/doc/index.rst | 4 ++-- boards/nordic/nrf9161dk/doc/index.rst | 2 +- boards/nordic/nrf9280pdk/doc/index.rst | 2 +- boards/nuvoton/npcm400_evb/doc/index.rst | 2 +- boards/nuvoton/numaker_m2l31ki/doc/index.rst | 4 ++-- boards/nuvoton/numaker_pfm_m467/doc/index.rst | 4 ++-- boards/nuvoton/numaker_pfm_m487/doc/index.rst | 4 ++-- boards/nxp/frdm_k22f/doc/index.rst | 4 ++-- boards/nxp/frdm_k64f/doc/index.rst | 4 ++-- boards/nxp/frdm_k82f/doc/index.rst | 4 ++-- boards/nxp/frdm_ke15z/doc/index.rst | 4 ++-- boards/nxp/frdm_ke17z/doc/index.rst | 4 ++-- boards/nxp/frdm_ke17z512/doc/index.rst | 4 ++-- boards/nxp/frdm_kl25z/doc/index.rst | 4 ++-- boards/nxp/frdm_kw41z/doc/index.rst | 4 ++-- boards/nxp/frdm_mcxa156/doc/index.rst | 4 ++-- boards/nxp/frdm_mcxc242/doc/index.rst | 4 ++-- boards/nxp/frdm_mcxn236/doc/index.rst | 4 ++-- boards/nxp/frdm_mcxn947/doc/index.rst | 6 +++--- boards/nxp/frdm_rw612/doc/index.rst | 4 ++-- boards/nxp/hexiwear/doc/index.rst | 8 ++++---- boards/nxp/imx8mm_evk/doc/index.rst | 2 +- boards/nxp/imx8mp_evk/doc/index.rst | 2 +- boards/nxp/imx8mq_evk/doc/index.rst | 2 +- boards/nxp/imx95_evk/doc/index.rst | 2 +- boards/nxp/lpcxpresso51u68/doc/index.rst | 4 ++-- boards/nxp/lpcxpresso54114/doc/index.rst | 4 ++-- boards/nxp/lpcxpresso55s06/doc/index.rst | 4 ++-- boards/nxp/lpcxpresso55s16/doc/index.rst | 4 ++-- boards/nxp/lpcxpresso55s28/doc/index.rst | 4 ++-- boards/nxp/lpcxpresso55s36/doc/index.rst | 4 ++-- boards/nxp/lpcxpresso55s69/doc/index.rst | 4 ++-- boards/nxp/mimxrt1010_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1015_evk/doc/index.rst | 2 +- boards/nxp/mimxrt1020_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1024_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1040_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1050_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1060_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1062_fmurt6/doc/index.rst | 4 ++-- boards/nxp/mimxrt1064_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1160_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1170_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt1180_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt595_evk/doc/index.rst | 4 ++-- boards/nxp/mimxrt685_evk/doc/index.rst | 4 ++-- boards/nxp/rd_rw612_bga/doc/index.rst | 4 ++-- boards/nxp/rddrone_fmuk66/doc/index.rst | 4 ++-- boards/nxp/s32z2xxdc2/doc/index.rst | 4 ++-- boards/nxp/twr_ke18f/doc/index.rst | 4 ++-- boards/nxp/twr_kv58f220m/doc/index.rst | 4 ++-- boards/nxp/usb_kw24d512/doc/index.rst | 4 ++-- boards/nxp/vmu_rt1170/doc/index.rst | 4 ++-- boards/olimex/olimex_esp32_evb/doc/index.rst | 6 +++--- boards/olimex/stm32_e407/doc/index.rst | 4 ++-- boards/olimex/stm32_h103/doc/index.rst | 2 +- boards/olimex/stm32_h405/doc/index.rst | 4 ++-- boards/olimex/stm32_h407/doc/index.rst | 4 ++-- boards/olimex/stm32_p405/doc/index.rst | 4 ++-- boards/openisa/rv32m1_vega/doc/index.rst | 2 +- boards/others/black_f407ve/doc/index.rst | 2 +- boards/others/black_f407zg_pro/doc/index.rst | 2 +- boards/others/icev_wireless/doc/index.rst | 4 ++-- boards/others/neorv32/doc/index.rst | 4 ++-- boards/others/stm32_min_dev/doc/index.rst | 2 +- boards/particle/argon/doc/index.rst | 2 +- boards/particle/boron/doc/index.rst | 2 +- boards/particle/nrf51_blenano/doc/index.rst | 4 ++-- boards/particle/nrf52_blenano2/doc/index.rst | 4 ++-- boards/particle/xenon/doc/index.rst | 2 +- boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst | 2 +- boards/phytec/phyboard_electra/doc/index.rst | 2 +- .../phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst | 2 +- .../phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst | 2 +- boards/phytec/reel_board/doc/index.rst | 4 ++-- boards/qorvo/decawave_dwm1001_dev/doc/index.rst | 2 +- boards/rak/rak11720/doc/index.rst | 2 +- boards/rak/rak4631/doc/index.rst | 4 ++-- boards/rak/rak5010/doc/index.rst | 4 ++-- boards/raspberrypi/rpi_5/doc/index.rst | 2 +- boards/raytac/mdbt50q_db_33/doc/index.rst | 2 +- boards/raytac/mdbt50q_db_40/doc/index.rst | 2 +- boards/raytac/mdbt53_db_40/doc/index.rst | 2 +- boards/raytac/mdbt53v_db_40/doc/index.rst | 2 +- boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst | 2 +- boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst | 2 +- boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst | 2 +- boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst | 2 +- boards/sc/scobc_module1/doc/index.rst | 4 ++-- boards/seco/stm32f3_seco_d23/doc/index.rst | 2 +- boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst | 2 +- boards/seeed/lora_e5_mini/doc/index.rst | 2 +- boards/seeed/seeeduino_xiao/doc/index.rst | 2 +- boards/seeed/xiao_ble/doc/index.rst | 2 +- boards/seeed/xiao_esp32c3/doc/index.rst | 4 ++-- boards/seeed/xiao_esp32s3/doc/index.rst | 6 +++--- boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst | 2 +- boards/silabs/dev_kits/sltb004a/doc/index.rst | 2 +- boards/silabs/dev_kits/sltb009a/doc/index.rst | 2 +- boards/silabs/dev_kits/sltb010a/doc/index.rst | 2 +- boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst | 2 +- boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst | 2 +- boards/silabs/radio_boards/slwrb4104a/doc/index.rst | 2 +- boards/silabs/radio_boards/slwrb4161a/doc/index.rst | 2 +- boards/silabs/radio_boards/slwrb4170a/doc/index.rst | 2 +- boards/silabs/radio_boards/slwrb4180a/doc/index.rst | 2 +- boards/silabs/radio_boards/slwrb4250b/doc/index.rst | 2 +- boards/silabs/radio_boards/slwrb4255a/doc/index.rst | 2 +- boards/silabs/radio_boards/slwrb4321a/doc/index.rst | 2 +- boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst | 2 +- boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst | 2 +- boards/silabs/starter_kits/slstk3400a/doc/index.rst | 2 +- boards/silabs/starter_kits/slstk3401a/doc/index.rst | 2 +- boards/silabs/starter_kits/slstk3402a/doc/index.rst | 2 +- boards/silabs/starter_kits/slstk3701a/doc/index.rst | 2 +- boards/snps/em_starterkit/doc/index.rst | 4 ++-- boards/snps/emsdp/doc/index.rst | 4 ++-- boards/snps/hsdk/doc/index.rst | 4 ++-- boards/snps/hsdk4xd/doc/index.rst | 4 ++-- boards/snps/iotdk/doc/index.rst | 4 ++-- boards/sparkfun/micromod/doc/index.rst | 2 +- boards/sparkfun/thing_plus/doc/index.rst | 4 ++-- boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst | 2 +- boards/st/b_g474e_dpow1/doc/index.rst | 2 +- boards/st/b_l072z_lrwan1/doc/index.rst | 4 ++-- boards/st/b_l4s5i_iot01a/doc/index.rst | 4 ++-- boards/st/b_u585i_iot02a/doc/index.rst | 2 +- boards/st/disco_l475_iot1/doc/index.rst | 4 ++-- boards/st/nucleo_f070rb/doc/index.rst | 2 +- boards/st/nucleo_f091rc/doc/index.rst | 2 +- boards/st/nucleo_f401re/doc/index.rst | 4 ++-- boards/st/nucleo_f410rb/doc/index.rst | 4 ++-- boards/st/nucleo_f411re/doc/index.rst | 4 ++-- boards/st/nucleo_f446re/doc/index.rst | 4 ++-- boards/st/nucleo_f446ze/doc/index.rst | 4 ++-- boards/st/nucleo_f722ze/doc/index.rst | 2 +- boards/st/nucleo_f746zg/doc/index.rst | 4 ++-- boards/st/nucleo_f756zg/doc/index.rst | 4 ++-- boards/st/nucleo_f767zi/doc/index.rst | 4 ++-- boards/st/nucleo_g031k8/doc/index.rst | 2 +- boards/st/nucleo_g070rb/doc/index.rst | 2 +- boards/st/nucleo_g071rb/doc/index.rst | 2 +- boards/st/nucleo_g0b1re/doc/index.rst | 2 +- boards/st/nucleo_g431rb/doc/index.rst | 4 ++-- boards/st/nucleo_g474re/doc/index.rst | 4 ++-- boards/st/nucleo_h503rb/doc/index.rst | 2 +- boards/st/nucleo_h533re/doc/index.rst | 2 +- boards/st/nucleo_h563zi/doc/index.rst | 2 +- boards/st/nucleo_h723zg/doc/index.rst | 4 ++-- boards/st/nucleo_h743zi/doc/index.rst | 4 ++-- boards/st/nucleo_h745zi_q/doc/index.rst | 4 ++-- boards/st/nucleo_h753zi/doc/index.rst | 4 ++-- boards/st/nucleo_h755zi_q/doc/index.rst | 4 ++-- boards/st/nucleo_h7a3zi_q/doc/index.rst | 4 ++-- boards/st/nucleo_l011k4/doc/index.rst | 2 +- boards/st/nucleo_l031k6/doc/index.rst | 2 +- boards/st/nucleo_l053r8/doc/index.rst | 2 +- boards/st/nucleo_l073rz/doc/index.rst | 2 +- boards/st/nucleo_l152re/doc/index.rst | 2 +- boards/st/nucleo_l412rb_p/doc/index.rst | 4 ++-- boards/st/nucleo_l432kc/doc/index.rst | 4 ++-- boards/st/nucleo_l433rc_p/doc/index.rst | 4 ++-- boards/st/nucleo_l452re/doc/index.rst | 4 ++-- boards/st/nucleo_l476rg/doc/index.rst | 4 ++-- boards/st/nucleo_l496zg/doc/index.rst | 4 ++-- boards/st/nucleo_l4a6zg/doc/index.rst | 4 ++-- boards/st/nucleo_l4r5zi/doc/index.rst | 2 +- boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst | 4 ++-- boards/st/nucleo_u031r8/doc/index.rst | 2 +- boards/st/nucleo_u083rc/doc/index.rst | 2 +- boards/st/nucleo_u575zi_q/doc/index.rst | 2 +- boards/st/nucleo_u5a5zj_q/doc/index.rst | 2 +- boards/st/nucleo_wb05kz/doc/index.rst | 4 ++-- boards/st/nucleo_wb09ke/doc/index.rst | 4 ++-- boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst | 2 +- boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst | 2 +- boards/st/st25dv_mb1283_disco/docs/index.rst | 4 ++-- boards/st/steval_fcu001v1/doc/index.rst | 4 ++-- boards/st/stm3210c_eval/doc/index.rst | 2 +- boards/st/stm32c0116_dk/doc/index.rst | 2 +- boards/st/stm32f072b_disco/doc/index.rst | 4 ++-- boards/st/stm32f3_disco/doc/index.rst | 4 ++-- boards/st/stm32f412g_disco/doc/index.rst | 4 ++-- boards/st/stm32f429i_disc1/doc/index.rst | 4 ++-- boards/st/stm32f469i_disco/doc/index.rst | 4 ++-- boards/st/stm32f4_disco/doc/index.rst | 2 +- boards/st/stm32f723e_disco/doc/index.rst | 4 ++-- boards/st/stm32f746g_disco/doc/index.rst | 4 ++-- boards/st/stm32f7508_dk/doc/index.rst | 4 ++-- boards/st/stm32f769i_disco/doc/index.rst | 4 ++-- boards/st/stm32g0316_disco/doc/index.rst | 2 +- boards/st/stm32g071b_disco/doc/index.rst | 2 +- boards/st/stm32g081b_eval/doc/index.rst | 2 +- boards/st/stm32h573i_dk/doc/index.rst | 4 ++-- boards/st/stm32h735g_disco/doc/index.rst | 2 +- boards/st/stm32h745i_disco/doc/index.rst | 4 ++-- boards/st/stm32h747i_disco/doc/index.rst | 4 ++-- boards/st/stm32h750b_dk/doc/index.rst | 4 ++-- boards/st/stm32h7b3i_dk/doc/index.rst | 4 ++-- boards/st/stm32h7s78_dk/doc/index.rst | 4 ++-- boards/st/stm32l476g_disco/doc/index.rst | 4 ++-- boards/st/stm32l496g_disco/doc/index.rst | 4 ++-- boards/st/stm32l4r9i_disco/doc/index.rst | 4 ++-- boards/st/stm32l562e_dk/doc/index.rst | 4 ++-- boards/st/stm32u083c_dk/doc/index.rst | 2 +- boards/st/stm32u5a9j_dk/doc/index.rst | 2 +- boards/tdk/robokit1/doc/index.rst | 4 ++-- boards/ti/cc1352p1_launchxl/doc/index.rst | 4 ++-- boards/ti/cc1352p7_launchpad/doc/index.rst | 4 ++-- boards/ti/cc1352r1_launchxl/doc/index.rst | 4 ++-- boards/ti/cc1352r_sensortag/doc/index.rst | 4 ++-- boards/ti/cc26x2r1_launchxl/doc/index.rst | 4 ++-- boards/ti/msp_exp432p401r_launchxl/doc/index.rst | 2 +- boards/ti/sk_am62/doc/index.rst | 2 +- boards/toradex/verdin_imx8mp/doc/index.rst | 2 +- boards/u-blox/ubx_bmd300eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd330eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd340eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd345eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd360eval/doc/index.rst | 2 +- boards/u-blox/ubx_bmd380eval/doc/index.rst | 2 +- boards/u-blox/ubx_evkannab1/doc/index.rst | 2 +- boards/u-blox/ubx_evkninab1/doc/index.rst | 2 +- boards/u-blox/ubx_evkninab3/doc/index.rst | 2 +- boards/u-blox/ubx_evkninab4/doc/index.rst | 2 +- boards/vcc-gnd/yd_esp32/doc/index.rst | 6 +++--- boards/vcc-gnd/yd_stm32h750vb/doc/index.rst | 2 +- boards/vngiotlab/nrf51_vbluno51/doc/index.rst | 2 +- boards/vngiotlab/nrf52_vbluno52/doc/index.rst | 4 ++-- boards/waveshare/nrf51_ble400/doc/index.rst | 2 +- boards/waveshare/open103z/doc/index.rst | 4 ++-- boards/we/ophelia1ev/doc/index.rst | 2 +- boards/we/proteus2ev/doc/index.rst | 2 +- boards/we/proteus3ev/doc/index.rst | 2 +- boards/weact/mini_stm32h743/doc/index.rst | 2 +- boards/wemos/esp32s2_lolin_mini/doc/index.rst | 2 +- boards/witte/linum/doc/index.rst | 4 ++-- doc/build/dts/howtos.rst | 4 ++-- doc/build/dts/troubleshooting.rst | 4 ++-- doc/build/sysbuild/index.rst | 2 +- doc/develop/application/index.rst | 2 +- doc/develop/beyond-GSG.rst | 2 +- doc/develop/getting_started/index.rst | 2 +- doc/develop/west/build-flash-debug.rst | 6 +++--- doc/develop/west/sign.rst | 2 +- doc/hardware/peripherals/can/shell.rst | 2 +- doc/hardware/peripherals/eeprom/shell.rst | 2 +- samples/hello_world/README.rst | 5 ++++- samples/subsys/usb/dfu/README.rst | 2 +- 393 files changed, 600 insertions(+), 597 deletions(-) diff --git a/boards/96boards/aerocore2/doc/index.rst b/boards/96boards/aerocore2/doc/index.rst index ca12b694950ebae..489433e09f3b39a 100644 --- a/boards/96boards/aerocore2/doc/index.rst +++ b/boards/96boards/aerocore2/doc/index.rst @@ -311,7 +311,7 @@ You should see following confirmation on your Linux host: usb 1-2.1: SerialNumber: 3574364C3034 Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/argonkey/doc/index.rst b/boards/96boards/argonkey/doc/index.rst index 810ab2e578133ef..f5cc913f3909e1a 100644 --- a/boards/96boards/argonkey/doc/index.rst +++ b/boards/96boards/argonkey/doc/index.rst @@ -145,7 +145,7 @@ Programming and Debugging Building ======== -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/carbon/doc/stm32f401xe.rst b/boards/96boards/carbon/doc/stm32f401xe.rst index 8f0d38c8dc9ddb8..c493c0a7fd62ce9 100644 --- a/boards/96boards/carbon/doc/stm32f401xe.rst +++ b/boards/96boards/carbon/doc/stm32f401xe.rst @@ -299,7 +299,7 @@ You should see following confirmation on your Linux host: usb 1-2.1: SerialNumber: 3574364C3034 Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/neonkey/doc/index.rst b/boards/96boards/neonkey/doc/index.rst index 96308784941cc5c..df9fb1619c11583 100644 --- a/boards/96boards/neonkey/doc/index.rst +++ b/boards/96boards/neonkey/doc/index.rst @@ -135,7 +135,7 @@ Programming and Debugging Building ======== -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/nitrogen/doc/index.rst b/boards/96boards/nitrogen/doc/index.rst index 952f11237bfeb57..df3d0236ca5965f 100644 --- a/boards/96boards/nitrogen/doc/index.rst +++ b/boards/96boards/nitrogen/doc/index.rst @@ -273,7 +273,7 @@ and install a more recent version of pyOCD. Flashing an Application to 96Boards Nitrogen ============================================ -Here is an example for the :ref:`hello_world` application. This +Here is an example for the :zephyr:code-sample:`hello_world` application. This requires installing the :ref:`pyocd-debug-host-tools`. .. zephyr-app-commands:: @@ -302,7 +302,7 @@ Debugging with GDB ================== You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. This also requires pyOCD. +:zephyr:code-sample:`hello_world` application. This also requires pyOCD. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/stm32_sensor_mez/doc/index.rst b/boards/96boards/stm32_sensor_mez/doc/index.rst index 350d4720a8018a3..1539a8148a184ed 100644 --- a/boards/96boards/stm32_sensor_mez/doc/index.rst +++ b/boards/96boards/stm32_sensor_mez/doc/index.rst @@ -181,7 +181,7 @@ Programming and Debugging Building ======== -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -198,7 +198,7 @@ included in the Zephyr SDK. Flashing an application to 96Boards STM32 Sensor Mezzanine ---------------------------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine board. @@ -224,7 +224,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/96boards/wistrio/doc/96b_wistrio.rst b/boards/96boards/wistrio/doc/96b_wistrio.rst index 14f93e6bae116b9..8db31fcf6cbfbde 100644 --- a/boards/96boards/wistrio/doc/96b_wistrio.rst +++ b/boards/96boards/wistrio/doc/96b_wistrio.rst @@ -148,7 +148,7 @@ More detailed information on activating the ROM bootloader can be found in Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing via UART, and I2C protocols. -Here is an example for building and flashing the :ref:`hello_world` application using `stm32flash`_ command line utility: +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application using `stm32flash`_ command line utility: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/feather_m0_basic_proto/doc/index.rst b/boards/adafruit/feather_m0_basic_proto/doc/index.rst index a9dc7f0c2297dac..04206783b1543a9 100644 --- a/boards/adafruit/feather_m0_basic_proto/doc/index.rst +++ b/boards/adafruit/feather_m0_basic_proto/doc/index.rst @@ -110,7 +110,7 @@ the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/feather_m0_lora/doc/index.rst b/boards/adafruit/feather_m0_lora/doc/index.rst index 3303c6e480c77fe..b75f73d6fdc8566 100644 --- a/boards/adafruit/feather_m0_lora/doc/index.rst +++ b/boards/adafruit/feather_m0_lora/doc/index.rst @@ -119,7 +119,7 @@ the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/grand_central_m4_express/doc/index.rst b/boards/adafruit/grand_central_m4_express/doc/index.rst index ec8ab08afdfff55..e9cf733843a5dd0 100644 --- a/boards/adafruit/grand_central_m4_express/doc/index.rst +++ b/boards/adafruit/grand_central_m4_express/doc/index.rst @@ -111,7 +111,7 @@ The bootloader can be entered by quickly tapping the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/itsybitsy_m4_express/doc/index.rst b/boards/adafruit/itsybitsy_m4_express/doc/index.rst index a25df0bf2fa6b2c..ce3efb89b1f342f 100644 --- a/boards/adafruit/itsybitsy_m4_express/doc/index.rst +++ b/boards/adafruit/itsybitsy_m4_express/doc/index.rst @@ -122,7 +122,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst index 0e7680e70b86f39..1fff89aaeab8a9c 100644 --- a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst +++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst @@ -118,10 +118,10 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adafruit/trinket_m0/doc/index.rst b/boards/adafruit/trinket_m0/doc/index.rst index 4e23822b242c437..e02b829d7a03727 100644 --- a/boards/adafruit/trinket_m0/doc/index.rst +++ b/boards/adafruit/trinket_m0/doc/index.rst @@ -114,7 +114,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adi/eval_adin1110ebz/doc/index.rst b/boards/adi/eval_adin1110ebz/doc/index.rst index 92b70f0c1c06a1e..f39a04b73620dd5 100644 --- a/boards/adi/eval_adin1110ebz/doc/index.rst +++ b/boards/adi/eval_adin1110ebz/doc/index.rst @@ -145,7 +145,7 @@ program to connect with your ADI board. For example: $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN1110EBZ_AVAS_XXXXXX-if00-port0 where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. +Then, build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -161,7 +161,7 @@ You should see the following message on the console: Debugging ========= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/adi/eval_adin2111ebz/doc/index.rst b/boards/adi/eval_adin2111ebz/doc/index.rst index c88e6d520edc6e7..ea0ce92be2a6b8a 100644 --- a/boards/adi/eval_adin2111ebz/doc/index.rst +++ b/boards/adi/eval_adin2111ebz/doc/index.rst @@ -146,7 +146,7 @@ program to connect with your ADI board. For example: $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN2111EBZ_XXXXXX-12-if00-port0 where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. +Then, build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -162,7 +162,7 @@ You should see the following message on the console: Debugging ========= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/adi/max32690fthr/doc/index.rst b/boards/adi/max32690fthr/doc/index.rst index 714adb82dc4a741..edb480f38983505 100644 --- a/boards/adi/max32690fthr/doc/index.rst +++ b/boards/adi/max32690fthr/doc/index.rst @@ -98,7 +98,7 @@ Logic levels are fixed to VDDIO (1.8V). Once the debug probe is connected to your host computer, then you can run the ``west flash`` command to write a firmware image into flash. Here is an example -for the :ref:`hello_world` application. +for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -118,7 +118,7 @@ Debugging Once the debug probe is connected to your host computer, then you can run the ``west debug`` command to write a firmware image into flash and start a debug -session. Here is an example for the :ref:`hello_world` application. +session. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst index 1f6f918e0a6cff1..0b23797da6bb505 100644 --- a/boards/adi/sdp_k1/doc/index.rst +++ b/boards/adi/sdp_k1/doc/index.rst @@ -151,7 +151,7 @@ Run a serial host program to connect with your board: $ minicom -D /dev/serial/by-id/usb-ARM_DAPLink_CMSIS-DAP_<...> -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst index cee292e1e56acbf..082c814914af92b 100644 --- a/boards/alientek/pandora_stm32l475/doc/index.rst +++ b/boards/alientek/pandora_stm32l475/doc/index.rst @@ -182,7 +182,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -199,7 +199,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst index 6a35d05b009f1ad..0ff861b4f83bcbf 100644 --- a/boards/altr/max10/doc/index.rst +++ b/boards/altr/max10/doc/index.rst @@ -147,7 +147,7 @@ Flashing Kernel into UFM ------------------------ The usual ``flash`` target will work with the ``altera_max10`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/ambiq/apollo3_evb/doc/index.rst b/boards/ambiq/apollo3_evb/doc/index.rst index 1982236becf7546..570e1d54d456475 100644 --- a/boards/ambiq/apollo3_evb/doc/index.rst +++ b/boards/ambiq/apollo3_evb/doc/index.rst @@ -60,7 +60,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: diff --git a/boards/ambiq/apollo3p_evb/doc/index.rst b/boards/ambiq/apollo3p_evb/doc/index.rst index 58b354288d2580e..c06f3b1e168fa63 100644 --- a/boards/ambiq/apollo3p_evb/doc/index.rst +++ b/boards/ambiq/apollo3p_evb/doc/index.rst @@ -60,7 +60,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst index 33a68ce8875937e..3a1876297d2ef3f 100644 --- a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -68,7 +68,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst index 662b6c41515a514..fef698b0a1b2bb0 100644 --- a/boards/ambiq/apollo4p_evb/doc/index.rst +++ b/boards/ambiq/apollo4p_evb/doc/index.rst @@ -63,7 +63,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: diff --git a/boards/andestech/adp_xc7k_ae350/doc/index.rst b/boards/andestech/adp_xc7k_ae350/doc/index.rst index ee7dc40d35599bb..3e290dd2f284be5 100644 --- a/boards/andestech/adp_xc7k_ae350/doc/index.rst +++ b/boards/andestech/adp_xc7k_ae350/doc/index.rst @@ -226,7 +226,7 @@ Building ======== You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/due/doc/index.rst b/boards/arduino/due/doc/index.rst index 5d9840275345754..dfc6e0078011f92 100644 --- a/boards/arduino/due/doc/index.rst +++ b/boards/arduino/due/doc/index.rst @@ -175,7 +175,7 @@ Applications for the ``arduino_due`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. After +Here is an example for the :zephyr:code-sample:`hello_world` application. After building the application, press the Reset button before running the flash command, so the board will boot into the SAM-BA bootloader and be prepared to receive the new program. diff --git a/boards/arduino/giga_r1/doc/index.rst b/boards/arduino/giga_r1/doc/index.rst index 0e95653edfaee1b..696844a71fabb17 100644 --- a/boards/arduino/giga_r1/doc/index.rst +++ b/boards/arduino/giga_r1/doc/index.rst @@ -130,7 +130,7 @@ First, connect the Arduino GIGA R1 board to your host computer using the USB port to prepare it for flashing. Double click the ``RST`` button to put the board into the Arduino Bootloader mode. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/mkrzero/doc/index.rst b/boards/arduino/mkrzero/doc/index.rst index b6fe37ddd16410e..2ea120d93135f17 100644 --- a/boards/arduino/mkrzero/doc/index.rst +++ b/boards/arduino/mkrzero/doc/index.rst @@ -130,7 +130,7 @@ bootloader can be entered by quickly tapping the reset button twice. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/nano_33_iot/doc/index.rst b/boards/arduino/nano_33_iot/doc/index.rst index 5b87fb52c182abc..e6a51198b92361c 100644 --- a/boards/arduino/nano_33_iot/doc/index.rst +++ b/boards/arduino/nano_33_iot/doc/index.rst @@ -118,7 +118,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/nicla_sense_me/doc/index.rst b/boards/arduino/nicla_sense_me/doc/index.rst index 6a6eb3a0d1b54a4..1bf984f23f4fb4b 100644 --- a/boards/arduino/nicla_sense_me/doc/index.rst +++ b/boards/arduino/nicla_sense_me/doc/index.rst @@ -95,7 +95,7 @@ Flashing First, connect the Arduino Nicla Sense ME board to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -118,7 +118,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/nicla_vision/doc/index.rst b/boards/arduino/nicla_vision/doc/index.rst index 3dacfc597637381..fac12f25fac61d9 100644 --- a/boards/arduino/nicla_vision/doc/index.rst +++ b/boards/arduino/nicla_vision/doc/index.rst @@ -137,7 +137,7 @@ First, connect the Arduino Nicla Vision board to your host computer using the US port to prepare it for flashing. Double click the ``RST`` button to put the board into the Arduino Bootloader mode. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst index 241c0c4b25bb052..3ed69927f4fbdbc 100644 --- a/boards/arduino/portenta_h7/doc/index.rst +++ b/boards/arduino/portenta_h7/doc/index.rst @@ -114,7 +114,7 @@ First, connect the Arduino Portenta H7 board to your host computer using the USB port to prepare it for flashing. Double tap the button to put the board into the Arduino Bootloader mode. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arduino/zero/doc/index.rst b/boards/arduino/zero/doc/index.rst index 46eb837040c507a..3ec0a0fd82a271e 100644 --- a/boards/arduino/zero/doc/index.rst +++ b/boards/arduino/zero/doc/index.rst @@ -118,7 +118,7 @@ OpenOCD. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/mps2/doc/mps2_an385.rst b/boards/arm/mps2/doc/mps2_an385.rst index ffd8942dbfddf6c..79f01dc9c53e074 100644 --- a/boards/arm/mps2/doc/mps2_an385.rst +++ b/boards/arm/mps2/doc/mps2_an385.rst @@ -253,7 +253,7 @@ V2M MPS2 provides: Flashing an application to V2M MPS2 ----------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/mps2/doc/mps2_an521.rst b/boards/arm/mps2/doc/mps2_an521.rst index 7149902b0db238d..33a4f4d7ca6ef03 100644 --- a/boards/arm/mps2/doc/mps2_an521.rst +++ b/boards/arm/mps2/doc/mps2_an521.rst @@ -489,7 +489,7 @@ MPS2+ AN521 provides: - A Serial Port which is J10 on MPS2+ board Build applications as described above. -Here is an example for the :ref:`hello_world` application built as +Here is an example for the :zephyr:code-sample:`hello_world` application built as a secure-only application for CPU0. .. zephyr-app-commands:: diff --git a/boards/arm/mps3/doc/index.rst b/boards/arm/mps3/doc/index.rst index 530999206d4ffce..e618b9a714c5e3c 100644 --- a/boards/arm/mps3/doc/index.rst +++ b/boards/arm/mps3/doc/index.rst @@ -142,7 +142,7 @@ Building an application ----------------------- You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/v2m_beetle/doc/index.rst b/boards/arm/v2m_beetle/doc/index.rst index 7673e510ebfae6c..49df438d3f908cf 100644 --- a/boards/arm/v2m_beetle/doc/index.rst +++ b/boards/arm/v2m_beetle/doc/index.rst @@ -229,7 +229,7 @@ Flashing an application to V2M Beetle ------------------------------------- You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/v2m_musca_b1/doc/index.rst b/boards/arm/v2m_musca_b1/doc/index.rst index 0a7d41ac883c1df..cb9aa61a0fdbab9 100644 --- a/boards/arm/v2m_musca_b1/doc/index.rst +++ b/boards/arm/v2m_musca_b1/doc/index.rst @@ -308,7 +308,7 @@ Building a secure only application You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/arm/v2m_musca_s1/doc/index.rst b/boards/arm/v2m_musca_s1/doc/index.rst index 7072ef7e2191322..86806891295eb74 100644 --- a/boards/arm/v2m_musca_s1/doc/index.rst +++ b/boards/arm/v2m_musca_s1/doc/index.rst @@ -301,7 +301,7 @@ Building a secure only application ---------------------------------- You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -318,7 +318,7 @@ Open a serial terminal (minicom, putty, etc.) with the following settings: Uploading an application to V2M Musca-S1 ---------------------------------------- -To upload the :ref:`hello_world` application to the board, no extra steps are +To upload the :zephyr:code-sample:`hello_world` application to the board, no extra steps are required. You can directly upload ``build/zephyr/zephyr.hex``, which is generated by Zephyr's build system. diff --git a/boards/atmel/sam/sam4e_xpro/doc/index.rst b/boards/atmel/sam/sam4e_xpro/doc/index.rst index 18d0836c6d6ff04..b01e60cd56d4800 100644 --- a/boards/atmel/sam/sam4e_xpro/doc/index.rst +++ b/boards/atmel/sam/sam4e_xpro/doc/index.rst @@ -122,7 +122,7 @@ Using OpenOCD ------------- #. Connect the SAM4E Xplained Pro board to your host computer using the USB - debug port. Then build and flash the :ref:`hello_world` application. + debug port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -138,7 +138,7 @@ Using SAM-BA bootloader #. Open the ``ERASE`` jumper. #. Connect the SAM4E Xplained Pro board to your host computer using the SoC - USB port. Then build and flash the :ref:`hello_world` application. + USB port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -175,7 +175,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam4l_ek/doc/index.rst b/boards/atmel/sam/sam4l_ek/doc/index.rst index a28b0728836ea65..f3e4e27d37683dd 100644 --- a/boards/atmel/sam/sam4l_ek/doc/index.rst +++ b/boards/atmel/sam/sam4l_ek/doc/index.rst @@ -140,7 +140,7 @@ Flashing - Stop bits: 1 #. Connect the SAM4L-EK board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. + Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -153,7 +153,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam4s_xplained/doc/index.rst b/boards/atmel/sam/sam4s_xplained/doc/index.rst index 9c1b999eca91fec..a5276bd67161afa 100644 --- a/boards/atmel/sam/sam4s_xplained/doc/index.rst +++ b/boards/atmel/sam/sam4s_xplained/doc/index.rst @@ -111,7 +111,7 @@ Using JLink accessible from your path. #. Connect the SAM4S Xplained board to your host computer using the USB debug - port. Then build and flash the :ref:`hello_world` application. + port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -128,7 +128,7 @@ Using SAM-BA bootloader #. Open the ``J25`` jumper. #. Connect the SAM4S Xplained board to your host computer using the SoC USB - port. Then build and flash the :ref:`hello_world` application. + port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -167,7 +167,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam_e70_xplained/doc/index.rst b/boards/atmel/sam/sam_e70_xplained/doc/index.rst index bab33f538c461cc..67b90d42c59cfcf 100644 --- a/boards/atmel/sam/sam_e70_xplained/doc/index.rst +++ b/boards/atmel/sam/sam_e70_xplained/doc/index.rst @@ -141,7 +141,7 @@ Flashing - Stop bits: 1 #. Connect the SAM E70 Xplained board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` + USB debug port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -171,7 +171,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam/sam_v71_xult/doc/index.rst b/boards/atmel/sam/sam_v71_xult/doc/index.rst index e0b5fce6c04d32f..7ce56d58a7090ec 100644 --- a/boards/atmel/sam/sam_v71_xult/doc/index.rst +++ b/boards/atmel/sam/sam_v71_xult/doc/index.rst @@ -144,7 +144,7 @@ Flashing - Stop bits: 1 #. Connect the SAM V71 Xplained Ultra board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` + USB debug port. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -174,7 +174,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam0/samd20_xpro/doc/index.rst b/boards/atmel/sam0/samd20_xpro/doc/index.rst index b0dbff2822941ea..7b788cbbf73a478 100644 --- a/boards/atmel/sam0/samd20_xpro/doc/index.rst +++ b/boards/atmel/sam0/samd20_xpro/doc/index.rst @@ -110,7 +110,7 @@ OpenOCD. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/atmel/sam0/samr21_xpro/doc/index.rst b/boards/atmel/sam0/samr21_xpro/doc/index.rst index abb5cd9a21e58bc..91a47615b9afa64 100644 --- a/boards/atmel/sam0/samr21_xpro/doc/index.rst +++ b/boards/atmel/sam0/samr21_xpro/doc/index.rst @@ -174,7 +174,7 @@ OpenOCD. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/bbc/microbit/doc/index.rst b/boards/bbc/microbit/doc/index.rst index aa36d3d662bfc06..c4d11f7a6717cdc 100644 --- a/boards/bbc/microbit/doc/index.rst +++ b/boards/bbc/microbit/doc/index.rst @@ -77,7 +77,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/bbc/microbit_v2/doc/index.rst b/boards/bbc/microbit_v2/doc/index.rst index 7c94a3e5a4e414b..d906f13660b3058 100644 --- a/boards/bbc/microbit_v2/doc/index.rst +++ b/boards/bbc/microbit_v2/doc/index.rst @@ -71,7 +71,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst index a5d9dd6243618a1..6ee06251f30ef8a 100644 --- a/boards/blues/swan_r5/doc/index.rst +++ b/boards/blues/swan_r5/doc/index.rst @@ -198,7 +198,7 @@ Programming and Debugging Connect Swan to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Swan: diff --git a/boards/bytesatwork/bytesensi_l/doc/index.rst b/boards/bytesatwork/bytesensi_l/doc/index.rst index e50402fc0f1b26e..9d16e74d21bf601 100644 --- a/boards/bytesatwork/bytesensi_l/doc/index.rst +++ b/boards/bytesatwork/bytesensi_l/doc/index.rst @@ -134,7 +134,7 @@ Flashing The byteSENSI-L board can be flashed with the SEGGER JLink programmer. You can build and flash applications in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/circuitdojo/feather/doc/index.rst b/boards/circuitdojo/feather/doc/index.rst index 998cfbcfdac774a..032b06d29d85fe5 100644 --- a/boards/circuitdojo/feather/doc/index.rst +++ b/boards/circuitdojo/feather/doc/index.rst @@ -111,7 +111,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/contextualelectronics/abc/doc/index.rst b/boards/contextualelectronics/abc/doc/index.rst index 15f9e52bca8bb1d..dd8aa8acfb033f6 100644 --- a/boards/contextualelectronics/abc/doc/index.rst +++ b/boards/contextualelectronics/abc/doc/index.rst @@ -93,7 +93,7 @@ Flashing Flashing Zephyr onto the ``contextualelectronics_abc`` board requires an external programmer. The programmer is attached to the SWD header. -Build the Zephyr kernel and the :ref:`hello_world` sample application. +Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst index 155f94f7b032fa1..46940f0691a662f 100644 --- a/boards/cypress/cy8ckit_062_ble/doc/index.rst +++ b/boards/cypress/cy8ckit_062_ble/doc/index.rst @@ -154,7 +154,7 @@ and J12 that can be used with Segger J-Link [default]. A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and Cy_WDT_Disable(). -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,7 +248,7 @@ connections may not allow the correct use of shields. The default board revision (0.0.0) allows use of default connections. The use of Arduino headers are only possible after rework the board and using the revision 1.0.0. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application for +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application for board revision 1.0.0: .. zephyr-app-commands:: diff --git a/boards/digilent/arty_a7/doc/index.rst b/boards/digilent/arty_a7/doc/index.rst index 4284320d6de4522..c6cad8d9453f77b 100644 --- a/boards/digilent/arty_a7/doc/index.rst +++ b/boards/digilent/arty_a7/doc/index.rst @@ -159,7 +159,7 @@ etc.): Flashing ======== -Here is an example for building and flashing the :ref:`hello_world` application +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application for the Cortex-M1 reference design: .. zephyr-app-commands:: @@ -191,7 +191,7 @@ dump :file:`zephyr.mem` file suitable for initialising the block RAM using Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/digilent/zybo/doc/index.rst b/boards/digilent/zybo/doc/index.rst index f8e3857227df049..7b5bf386f03a79d 100644 --- a/boards/digilent/zybo/doc/index.rst +++ b/boards/digilent/zybo/doc/index.rst @@ -77,7 +77,7 @@ Clone and build Das U-Boot for the Digilent Zybo: Flashing ======== -Here is an example for running the :ref:`hello_world` application via JTAG. +Here is an example for running the :zephyr:code-sample:`hello_world` application via JTAG. Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot @@ -97,7 +97,7 @@ You should see the following message in the terminal: *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** Hello World! zybo -Another option is to load and run the :ref:`hello_world` application via U-Boot. Copy +Another option is to load and run the :zephyr:code-sample:`hello_world` application via U-Boot. Copy ``u-boot/spl/boot.bin``, ``u-boot/u-boot.img``, and ``zephyr/zephyr.bin`` to a FAT32 formatted microSD card, insert the card in the ``SD MICRO`` slot on the Zybo board, ensure the board is configured for ``SD`` boot, and turn on the board. @@ -116,7 +116,7 @@ Once U-boot is done initializing, load an run the Zephyr application: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst index b3d14f928856f8e..4a29c56af1d571a 100644 --- a/boards/dragino/lsn50/doc/index.rst +++ b/boards/dragino/lsn50/doc/index.rst @@ -149,7 +149,7 @@ Dragino LSN50 board requires an external debugger. Flashing an application to Dragino LSN50 ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then run a serial host program to connect with your board. For example: @@ -175,7 +175,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst index 09a8b91f6ceef13..27e32b7d06f5cb7 100644 --- a/boards/dragino/nbsn95/doc/index.rst +++ b/boards/dragino/nbsn95/doc/index.rst @@ -148,7 +148,7 @@ Dragino NBSN95 board requires an external debugger. Flashing an application to Dragino NBSN95 ----------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the Dragino NBSN95 to a STLinkV2 to your host computer using the USB port, then run a serial host program to connect with your board. For example: @@ -174,7 +174,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/electronut/nrf52840_blip/doc/index.rst b/boards/electronut/nrf52840_blip/doc/index.rst index 9f78cee51ec6e8d..67a736bcd063996 100644 --- a/boards/electronut/nrf52840_blip/doc/index.rst +++ b/boards/electronut/nrf52840_blip/doc/index.rst @@ -141,7 +141,7 @@ Flashing Applications are flashed and run as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst index 7890cd108e4179d..814ef881360915f 100644 --- a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst +++ b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst @@ -151,7 +151,7 @@ debugger (see _Bumpy). Applications are flashed and run as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst index f38470e09b2063d..68955f9c17c0867 100644 --- a/boards/espressif/esp32_devkitc_wroom/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wroom/doc/index.rst @@ -213,7 +213,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -264,14 +264,14 @@ to the external programmer (e.g. a Flyswatter2): Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32_devkitc_wroom/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst index 24a2207ab1aa48d..81c75c598ca3f16 100644 --- a/boards/espressif/esp32_devkitc_wrover/doc/index.rst +++ b/boards/espressif/esp32_devkitc_wrover/doc/index.rst @@ -213,7 +213,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -264,14 +264,14 @@ to the external programmer (e.g. a Flyswatter2): Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32_devkitc_wrover/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst index a23d94daebbbc66..4437e479bdf37e1 100644 --- a/boards/espressif/esp32_ethernet_kit/doc/index.rst +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -530,7 +530,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32_ethernet_kit`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -563,7 +563,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -571,7 +571,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32c3_devkitc/doc/index.rst b/boards/espressif/esp32c3_devkitc/doc/index.rst index f000b959f1fc0ed..97ce7f181b5fc65 100644 --- a/boards/espressif/esp32c3_devkitc/doc/index.rst +++ b/boards/espressif/esp32c3_devkitc/doc/index.rst @@ -195,7 +195,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32c3_devkitc`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -228,7 +228,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -236,7 +236,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst index 0100950ce9c4aba..aed67104255afe0 100644 --- a/boards/espressif/esp32c3_devkitm/doc/index.rst +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -195,7 +195,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32c3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -228,7 +228,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -236,7 +236,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32c3_rust/doc/index.rst b/boards/espressif/esp32c3_rust/doc/index.rst index fc049ef6ea585bf..7b80d30ee5fd63d 100644 --- a/boards/espressif/esp32c3_rust/doc/index.rst +++ b/boards/espressif/esp32c3_rust/doc/index.rst @@ -240,7 +240,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32c3_rust`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -273,7 +273,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -281,7 +281,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32c6_devkitc/doc/index.rst b/boards/espressif/esp32c6_devkitc/doc/index.rst index 9383ed6ba3630a4..7b856912a9a1cbb 100644 --- a/boards/espressif/esp32c6_devkitc/doc/index.rst +++ b/boards/espressif/esp32c6_devkitc/doc/index.rst @@ -229,7 +229,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32c6_devkitc`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -262,7 +262,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -270,7 +270,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst index 4d7d400fe04b9ba..9e1bb15fd10de37 100644 --- a/boards/espressif/esp32s2_devkitc/doc/index.rst +++ b/boards/espressif/esp32s2_devkitc/doc/index.rst @@ -192,7 +192,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s2_devkitc`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -235,14 +235,14 @@ The following table shows the pin mapping between ESP32-S2 board and JTAG interf Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s2_devkitc :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst index 05db30be9a7978d..dba54f93cae0d2a 100644 --- a/boards/espressif/esp32s2_saola/doc/index.rst +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -192,7 +192,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s2_saola`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -235,14 +235,14 @@ The following table shows the pin mapping between ESP32-S2 board and JTAG interf Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s2_saola :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst index f026ba34c4b5aa3..984a714d0f7fe8d 100644 --- a/boards/espressif/esp32s3_devkitc/doc/index.rst +++ b/boards/espressif/esp32s3_devkitc/doc/index.rst @@ -231,7 +231,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s3_devkitc`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -262,14 +262,14 @@ ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additiona Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_devkitc/esp32s3/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst index 4cc05c4bfb824cb..b1e79766ed9d635 100644 --- a/boards/espressif/esp32s3_devkitm/doc/index.rst +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -231,7 +231,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -262,14 +262,14 @@ ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additiona Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_devkitm/esp32s3/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst index e3d2b93d1df80d4..5dd05ab7ceca694 100644 --- a/boards/espressif/esp8684_devkitm/doc/index.rst +++ b/boards/espressif/esp8684_devkitm/doc/index.rst @@ -187,7 +187,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp8684_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -220,7 +220,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -228,7 +228,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst index 67991e02019a207..0bef9a9ce4dfa5f 100644 --- a/boards/espressif/esp_wrover_kit/doc/index.rst +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -598,7 +598,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp_wrover_kit`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -634,7 +634,7 @@ headers are on the right side of the board as viewed from the power switch, next to similar headers for SPI and UART. See `ESP-WROVER-32 V3 Getting Started Guide`_ for details. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -642,7 +642,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ezurio/bl5340_dvk/doc/index.rst b/boards/ezurio/bl5340_dvk/doc/index.rst index 7ec697507c59792..62a7de87f934ed7 100644 --- a/boards/ezurio/bl5340_dvk/doc/index.rst +++ b/boards/ezurio/bl5340_dvk/doc/index.rst @@ -379,7 +379,7 @@ applications as usual (:ref:`build_an_application` and Further information on how to install the nRF Command Line Tools can be found in :ref:`nordic_segger_flashing`. -Here is an example for the :ref:`hello_world` application running on the +Here is an example for the :zephyr:code-sample:`hello_world` application running on the BL5340's application core. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst index c7ed935392c58a8..aaae4b9071b34e1 100644 --- a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst +++ b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst @@ -214,7 +214,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst index 4011984a8184746..48c252b5ff9e13f 100644 --- a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst +++ b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst @@ -120,7 +120,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst index 2affaca8f5bec79..d262a9a5146abf7 100644 --- a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst @@ -131,7 +131,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst index bfea48d0f362e8a..32036e38ada8d01 100644 --- a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst +++ b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst @@ -145,7 +145,7 @@ as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). If using a Ezurio USB-SWD Programmer Board, see the `pyOCD website`_ to find details about the software and how to install it. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output - note that an external UART is required to be connected to the BL654 sensor board's UART, if diff --git a/boards/ezurio/bt510/doc/bt510.rst b/boards/ezurio/bt510/doc/bt510.rst index ec0890c74803f18..bcdaf272265369b 100644 --- a/boards/ezurio/bt510/doc/bt510.rst +++ b/boards/ezurio/bt510/doc/bt510.rst @@ -187,7 +187,7 @@ Then build and flash applications as usual (see :ref:`build_an_application` and $ ninja flash -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/bt610/doc/bt610.rst b/boards/ezurio/bt610/doc/bt610.rst index 6c72804eb8ee45a..528186ec88062b0 100644 --- a/boards/ezurio/bt610/doc/bt610.rst +++ b/boards/ezurio/bt610/doc/bt610.rst @@ -545,7 +545,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/mg100/doc/index.rst b/boards/ezurio/mg100/doc/index.rst index 29274d98a04b2c1..86b92c52abf14ed 100644 --- a/boards/ezurio/mg100/doc/index.rst +++ b/boards/ezurio/mg100/doc/index.rst @@ -174,7 +174,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/pinnacle_100_dvk/doc/index.rst b/boards/ezurio/pinnacle_100_dvk/doc/index.rst index de8735f3a60d2b8..7b63ada033bd816 100644 --- a/boards/ezurio/pinnacle_100_dvk/doc/index.rst +++ b/boards/ezurio/pinnacle_100_dvk/doc/index.rst @@ -144,7 +144,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/ezurio/rm1xx_dvk/doc/index.rst b/boards/ezurio/rm1xx_dvk/doc/index.rst index f530c9b791fd589..bd57e8f400d0720 100644 --- a/boards/ezurio/rm1xx_dvk/doc/index.rst +++ b/boards/ezurio/rm1xx_dvk/doc/index.rst @@ -143,7 +143,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/fanke/fk7b0m1_vbt6/doc/index.rst b/boards/fanke/fk7b0m1_vbt6/doc/index.rst index dfabfd54e88229c..19b346585befa0d 100644 --- a/boards/fanke/fk7b0m1_vbt6/doc/index.rst +++ b/boards/fanke/fk7b0m1_vbt6/doc/index.rst @@ -145,7 +145,7 @@ To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using t interface. Next, connect the ST-Link to your host computer via a USB port. Once this setup is complete, you can proceed to build and flash your application to the board -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst index b2d1a8f64336aa9..efa47c90719ff88 100644 --- a/boards/franzininho/esp32s2_franzininho/doc/index.rst +++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst @@ -148,7 +148,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32s2_franzininho`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/gd/gd32a503v_eval/doc/index.rst b/boards/gd/gd32a503v_eval/doc/index.rst index b926a265bb45e14..bd9170b16c43b9f 100644 --- a/boards/gd/gd32a503v_eval/doc/index.rst +++ b/boards/gd/gd32a503v_eval/doc/index.rst @@ -119,7 +119,7 @@ The GD32A503V-EVAL includes an onboard programmer/debugger (GD-Link) which allow flash programming and debug over USB. There are also program and debug headers J2 and J100 that can be used with any ARM compatible tools. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -168,7 +168,7 @@ The GD32A503 MCU have a ROM bootloader which allow flash programming. User should install `GD32 ISP Console`_ software at some Linux path. The recommended is :code:`$HOME/.local/bin`. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32e103v_eval/doc/index.rst b/boards/gd/gd32e103v_eval/doc/index.rst index 3d9058793fe08c4..f53d0b173d318d5 100644 --- a/boards/gd/gd32e103v_eval/doc/index.rst +++ b/boards/gd/gd32e103v_eval/doc/index.rst @@ -111,7 +111,7 @@ The GD32E103V-EVAL includes an onboard programmer/debugger (GD-Link) which allow flash programming and debug over USB. There are also program and debug headers J1 and J100 that can be used with any ARM compatible tools. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -160,7 +160,7 @@ The GD32E103 MCU have a ROM bootloader which allow flash programming. User should install `GD32 ISP Console`_ software at some Linux path. The recommended is :code:`$HOME/.local/bin`. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32e507v_start/doc/index.rst b/boards/gd/gd32e507v_start/doc/index.rst index 097c5a5c976e6e9..902b4a207667299 100644 --- a/boards/gd/gd32e507v_start/doc/index.rst +++ b/boards/gd/gd32e507v_start/doc/index.rst @@ -94,7 +94,7 @@ provided you install the necessary CMSIS-Pack: J-Link can also be used to program the board using the SWD interface exposed in the JP1 header. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32e507z_eval/doc/index.rst b/boards/gd/gd32e507z_eval/doc/index.rst index c3484d8beec8439..edaac6344109410 100644 --- a/boards/gd/gd32e507z_eval/doc/index.rst +++ b/boards/gd/gd32e507z_eval/doc/index.rst @@ -102,7 +102,7 @@ provided you install the necessary CMSIS-Pack: J-Link can also be used to program the board using the JTAG interface exposed in the JP2 header. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f350r_eval/doc/index.rst b/boards/gd/gd32f350r_eval/doc/index.rst index 8a2317da68e6782..d5dc24f46c9567f 100644 --- a/boards/gd/gd32f350r_eval/doc/index.rst +++ b/boards/gd/gd32f350r_eval/doc/index.rst @@ -87,7 +87,7 @@ The GD32F350R-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a SWD header (J3) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f403z_eval/doc/index.rst b/boards/gd/gd32f403z_eval/doc/index.rst index 4ea432c31d1dd5b..c5c97fd727c552d 100644 --- a/boards/gd/gd32f403z_eval/doc/index.rst +++ b/boards/gd/gd32f403z_eval/doc/index.rst @@ -114,7 +114,7 @@ The GD32F403Z-EVAL includes an onboard programmer/debugger (GD-Link) which allow flash programming and debug over USB. There are also program and debug headers J1 and J100 that can be used with any ARM compatible tools. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -163,7 +163,7 @@ The GD32F403 MCU have a ROM bootloader which allow flash programming. User should install `GD32 ISP Console`_ software at some Linux path. The recommended is :code:`$HOME/.local/bin`. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f407v_start/doc/index.rst b/boards/gd/gd32f407v_start/doc/index.rst index cd67921e59e3890..a59243db49887db 100644 --- a/boards/gd/gd32f407v_start/doc/index.rst +++ b/boards/gd/gd32f407v_start/doc/index.rst @@ -96,7 +96,7 @@ if not installed yet. Also, J-Link can be used to program the board via the SWD interface (PA13/SWDIO and PA14/SWCLK in the JP6 header). -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f450i_eval/doc/index.rst b/boards/gd/gd32f450i_eval/doc/index.rst index 59e9d258975cbdd..e01c3957652be6a 100644 --- a/boards/gd/gd32f450i_eval/doc/index.rst +++ b/boards/gd/gd32f450i_eval/doc/index.rst @@ -112,7 +112,7 @@ The GD32F450I-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (J1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f450v_start/doc/index.rst b/boards/gd/gd32f450v_start/doc/index.rst index e45f05a58a65c4e..0b1a781758b594c 100644 --- a/boards/gd/gd32f450v_start/doc/index.rst +++ b/boards/gd/gd32f450v_start/doc/index.rst @@ -89,7 +89,7 @@ The GD32F450V-START includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a SWD header (JP100) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f450z_eval/doc/index.rst b/boards/gd/gd32f450z_eval/doc/index.rst index 0e31f262db3c6e9..cdc4f8f42a73c4f 100644 --- a/boards/gd/gd32f450z_eval/doc/index.rst +++ b/boards/gd/gd32f450z_eval/doc/index.rst @@ -107,7 +107,7 @@ The GD32F450Z-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (J1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32f470i_eval/doc/index.rst b/boards/gd/gd32f470i_eval/doc/index.rst index 627dc1fa9e924db..75e33eaed2a2800 100644 --- a/boards/gd/gd32f470i_eval/doc/index.rst +++ b/boards/gd/gd32f470i_eval/doc/index.rst @@ -111,7 +111,7 @@ The GD32F470I-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (J1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32l233r_eval/doc/index.rst b/boards/gd/gd32l233r_eval/doc/index.rst index 8b5a08514e31a83..884978fd021070f 100644 --- a/boards/gd/gd32l233r_eval/doc/index.rst +++ b/boards/gd/gd32l233r_eval/doc/index.rst @@ -88,7 +88,7 @@ The GD32L233R-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a SWD header which can be used with tools like Segger J-Link(latest version required). -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32vf103c_starter/doc/index.rst b/boards/gd/gd32vf103c_starter/doc/index.rst index aee1ea612e775dc..29a428c6c980951 100644 --- a/boards/gd/gd32vf103c_starter/doc/index.rst +++ b/boards/gd/gd32vf103c_starter/doc/index.rst @@ -83,7 +83,7 @@ The GD32VF103C-STARTER includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (JP1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/gd/gd32vf103v_eval/doc/index.rst b/boards/gd/gd32vf103v_eval/doc/index.rst index 42af6d765d6d6e4..5aa8e8327bd23fd 100644 --- a/boards/gd/gd32vf103v_eval/doc/index.rst +++ b/boards/gd/gd32vf103v_eval/doc/index.rst @@ -93,7 +93,7 @@ The GD32VF103V-EVAL includes an onboard programmer/debugger (GD-Link) which allows flash programming and debugging over USB. There is also a JTAG header (JP1) which can be used with tools like Segger J-Link. -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/hardkernel/odroid_go/doc/index.rst b/boards/hardkernel/odroid_go/doc/index.rst index 86eb0afae269133..62f38d4799df94b 100644 --- a/boards/hardkernel/odroid_go/doc/index.rst +++ b/boards/hardkernel/odroid_go/doc/index.rst @@ -192,7 +192,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``odroid_go`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -225,7 +225,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -233,7 +233,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst index b1c0713070377f1..ee595e0a847b03e 100644 --- a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst +++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst @@ -136,7 +136,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``heltec_wifi_lora32_v2`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -169,7 +169,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -177,7 +177,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst index c2b141ae15988e1..352d158fbacb8c3 100644 --- a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst +++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst @@ -250,7 +250,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``heltec_wireless_stick_lite_v3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -283,7 +283,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -291,7 +291,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/infineon/xmc45_relax_kit/doc/index.rst b/boards/infineon/xmc45_relax_kit/doc/index.rst index 89c9bcf04e3224e..621fc1cc83e056a 100644 --- a/boards/infineon/xmc45_relax_kit/doc/index.rst +++ b/boards/infineon/xmc45_relax_kit/doc/index.rst @@ -74,7 +74,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -84,7 +84,7 @@ Here is an example for the :ref:`hello_world` application. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/infineon/xmc47_relax_kit/doc/index.rst b/boards/infineon/xmc47_relax_kit/doc/index.rst index 35457f387dfe1ce..57eb28efaedb133 100644 --- a/boards/infineon/xmc47_relax_kit/doc/index.rst +++ b/boards/infineon/xmc47_relax_kit/doc/index.rst @@ -77,7 +77,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -87,7 +87,7 @@ Here is an example for the :ref:`hello_world` application. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/innblue/innblue21/doc/index.rst b/boards/innblue/innblue21/doc/index.rst index 333db42bfd9255a..0990c395c62eff9 100644 --- a/boards/innblue/innblue21/doc/index.rst +++ b/boards/innblue/innblue21/doc/index.rst @@ -119,7 +119,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/innblue/innblue22/doc/index.rst b/boards/innblue/innblue22/doc/index.rst index 862c42cdd22c44f..3485ad4de7713d0 100644 --- a/boards/innblue/innblue22/doc/index.rst +++ b/boards/innblue/innblue22/doc/index.rst @@ -119,7 +119,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst index 752284a63b9c797..6183491690c52f9 100644 --- a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst +++ b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst @@ -163,7 +163,7 @@ Flashing Kernel into the board ------------------------------ The usual ``flash`` target will work with the ``cyclonev_socdk`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. ``Important!!!`` : Before flashing the board a ``preloader`` is required, diff --git a/boards/ite/it82xx2_evb/doc/index.rst b/boards/ite/it82xx2_evb/doc/index.rst index 0080c4f3e139888..d31b989f225c081 100644 --- a/boards/ite/it82xx2_evb/doc/index.rst +++ b/boards/ite/it82xx2_evb/doc/index.rst @@ -151,7 +151,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do +#. Build :zephyr:code-sample:`hello_world` application as you would normally do (see :`Zephyr Getting Started Guide`_):. .. zephyr-app-commands:: diff --git a/boards/ite/it8xxx2_evb/doc/index.rst b/boards/ite/it8xxx2_evb/doc/index.rst index 5fab9cc412c56bf..0e215fddf7efa8d 100644 --- a/boards/ite/it8xxx2_evb/doc/index.rst +++ b/boards/ite/it8xxx2_evb/doc/index.rst @@ -133,7 +133,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do +#. Build :zephyr:code-sample:`hello_world` application as you would normally do (see :`Zephyr Getting Started Guide`_):. .. zephyr-app-commands:: diff --git a/boards/khadas/edgev/doc/index.rst b/boards/khadas/edgev/doc/index.rst index 2c73d109b09caeb..c6c3e44826a6acd 100644 --- a/boards/khadas/edgev/doc/index.rst +++ b/boards/khadas/edgev/doc/index.rst @@ -41,7 +41,7 @@ Programming and Debugging ************************* Use the following configuration to run basic Zephyr applications and -kernel tests on Khadas Edge-V board. For example, with the :ref:`hello_world`: +kernel tests on Khadas Edge-V board. For example, with the :zephyr:code-sample:`hello_world`: 1. Non-SMP mode diff --git a/boards/kincony/kincony_kc868_a32/doc/index.rst b/boards/kincony/kincony_kc868_a32/doc/index.rst index a6117bec55e9f16..ccc8676f512a4d6 100644 --- a/boards/kincony/kincony_kc868_a32/doc/index.rst +++ b/boards/kincony/kincony_kc868_a32/doc/index.rst @@ -58,7 +58,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``kincony_kc868_a32`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/lilygo/ttgo_lora32/doc/index.rst b/boards/lilygo/ttgo_lora32/doc/index.rst index 6814a66543fe689..c7a04423e905ecb 100644 --- a/boards/lilygo/ttgo_lora32/doc/index.rst +++ b/boards/lilygo/ttgo_lora32/doc/index.rst @@ -179,7 +179,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``ttgo_lora32`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/lilygo/ttgo_t8c3/doc/index.rst b/boards/lilygo/ttgo_t8c3/doc/index.rst index e4ad3978cef8f65..2b11dd90a0a71b4 100644 --- a/boards/lilygo/ttgo_t8c3/doc/index.rst +++ b/boards/lilygo/ttgo_t8c3/doc/index.rst @@ -177,7 +177,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``ttgo_t8c3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/lowrisc/opentitan_earlgrey/doc/index.rst b/boards/lowrisc/opentitan_earlgrey/doc/index.rst index f3edf95e44ed8ff..b91c0700def27d3 100644 --- a/boards/lowrisc/opentitan_earlgrey/doc/index.rst +++ b/boards/lowrisc/opentitan_earlgrey/doc/index.rst @@ -57,7 +57,7 @@ Setup`_ guide . Building and Flashing ===================== -Here is an example for building the :ref:`hello_world` application. The +Here is an example for building the :zephyr:code-sample:`hello_world` application. The following steps were tested on OpenTitan master branch @ 6a3c2e98. .. zephyr-app-commands:: diff --git a/boards/luatos/esp32c3_luatos_core/doc/index.rst b/boards/luatos/esp32c3_luatos_core/doc/index.rst index 03a9ccc9d3b9fd6..2e0d5ed56b25a3e 100644 --- a/boards/luatos/esp32c3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32c3_luatos_core/doc/index.rst @@ -203,7 +203,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``esp32c3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -236,7 +236,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -244,7 +244,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/luatos/esp32s3_luatos_core/doc/index.rst b/boards/luatos/esp32s3_luatos_core/doc/index.rst index 9a5bec48362f449..7aa4310206947c1 100644 --- a/boards/luatos/esp32s3_luatos_core/doc/index.rst +++ b/boards/luatos/esp32s3_luatos_core/doc/index.rst @@ -237,7 +237,7 @@ If CH343 chip is disabled, You need use the following command to build: :goals: build The usual ``flash`` target will work with the ``esp32s3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -268,14 +268,14 @@ ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additiona Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: esp32s3_luatos_core/esp32s3/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/m5stack/m5stack_atom_lite/doc/index.rst b/boards/m5stack/m5stack_atom_lite/doc/index.rst index 2e8c1fade477af8..6a47c4a7f324ffc 100644 --- a/boards/m5stack/m5stack_atom_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atom_lite/doc/index.rst @@ -96,7 +96,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_atom_lite`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_atoms3/doc/index.rst b/boards/m5stack/m5stack_atoms3/doc/index.rst index c053f73c101773d..69bff1ee0cfbe3f 100644 --- a/boards/m5stack/m5stack_atoms3/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3/doc/index.rst @@ -98,7 +98,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_atoms3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst index 204d8e5bbec506e..ffbe8f1cb05d68b 100644 --- a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst +++ b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst @@ -96,7 +96,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_atoms3_lite`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst index c7a907a3e3433c0..02ba5fa72492454 100644 --- a/boards/m5stack/m5stack_core2/doc/index.rst +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -183,7 +183,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_core2`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stack_stamps3/doc/index.rst b/boards/m5stack/m5stack_stamps3/doc/index.rst index 59e1d5145aab54d..36881121e8a3906 100644 --- a/boards/m5stack/m5stack_stamps3/doc/index.rst +++ b/boards/m5stack/m5stack_stamps3/doc/index.rst @@ -153,7 +153,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stack_stamps3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/m5stickc_plus/doc/index.rst b/boards/m5stack/m5stickc_plus/doc/index.rst index e59da05f93b5eb9..4fe431fea849ca7 100644 --- a/boards/m5stack/m5stickc_plus/doc/index.rst +++ b/boards/m5stack/m5stickc_plus/doc/index.rst @@ -181,7 +181,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``m5stickc_plus`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/m5stack/stamp_c3/doc/index.rst b/boards/m5stack/stamp_c3/doc/index.rst index 721c62eacc7442c..40869ee01664a96 100644 --- a/boards/m5stack/stamp_c3/doc/index.rst +++ b/boards/m5stack/stamp_c3/doc/index.rst @@ -150,7 +150,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``stamp_c3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -183,7 +183,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -191,7 +191,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/madmachine/mm_feather/doc/index.rst b/boards/madmachine/mm_feather/doc/index.rst index 5b53ddfc586ac8c..0a556bc42b0899f 100644 --- a/boards/madmachine/mm_feather/doc/index.rst +++ b/boards/madmachine/mm_feather/doc/index.rst @@ -195,7 +195,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect a DAPLink debugger from your PC to corresponding SWD pins of SwiftIO Feather. @@ -215,7 +215,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/madmachine/mm_swiftio/doc/index.rst b/boards/madmachine/mm_swiftio/doc/index.rst index d9361404d57d829..5fb0837e1ead1d2 100644 --- a/boards/madmachine/mm_swiftio/doc/index.rst +++ b/boards/madmachine/mm_swiftio/doc/index.rst @@ -206,7 +206,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect a USB cable from your PC to "Serial" port of SwiftIO. On Ubuntu, DAPLink debug probes appear on the host diff --git a/boards/microchip/mec1501modular_assy6885/doc/index.rst b/boards/microchip/mec1501modular_assy6885/doc/index.rst index a74f48163fb6d54..a70c20ee96198b1 100644 --- a/boards/microchip/mec1501modular_assy6885/doc/index.rst +++ b/boards/microchip/mec1501modular_assy6885/doc/index.rst @@ -260,7 +260,7 @@ Setup Building ========== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. Once you have ``zephyr.bin``, use the `MEC152x SPI Image Gen`_ microchip tool to create the final binary. You need the output from this tool to flash diff --git a/boards/microchip/mec15xxevb_assy6853/doc/index.rst b/boards/microchip/mec15xxevb_assy6853/doc/index.rst index e3b29e99212a5fb..4eafd2e758c777a 100644 --- a/boards/microchip/mec15xxevb_assy6853/doc/index.rst +++ b/boards/microchip/mec15xxevb_assy6853/doc/index.rst @@ -352,7 +352,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. The file :file:`spi_image.bin` will be created if the build system can find the image generation tool. This binary image can be used diff --git a/boards/microchip/mec172xevb_assy6906/doc/index.rst b/boards/microchip/mec172xevb_assy6906/doc/index.rst index a2100e5a2d6b007..4765d787d948e44 100644 --- a/boards/microchip/mec172xevb_assy6906/doc/index.rst +++ b/boards/microchip/mec172xevb_assy6906/doc/index.rst @@ -360,7 +360,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. The file :file:`spi_image.bin` will be created if the build system can find the image generation tool. This binary image can be used diff --git a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst index a3a854873426b0a..a85226e87d02642 100644 --- a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst +++ b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst @@ -241,7 +241,7 @@ Wiring Building ======== -#. Build :ref:`hello_world` application as you would normally do. +#. Build :zephyr:code-sample:`hello_world` application as you would normally do. #. The file :file:`spi_image.bin` will be created if the build system can find the image generation tool. This binary image can be used diff --git a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst index 99cb9ce0c61aa58..a1ef4aa09ecbc97 100644 --- a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst +++ b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst @@ -91,7 +91,7 @@ Unlocking with openocd makes it possible to flash. -f /usr/share/openocd/scripts/target/stm32f4x.cfg -c init\ -c "reset halt" -c "stm32f4x unlock 0" -c "reset run" -c shutdown -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -109,7 +109,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst index 7198f2da36e8e3a..6194953b1daa8b0 100644 --- a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst +++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst @@ -118,7 +118,7 @@ Unlocking with openocd makes it possible to flash. -f /usr/share/openocd/scripts/target/stm32f4x.cfg -c init\ -c "reset halt" -c "stm32f4x unlock 0" -c "reset run" -c shutdown -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -135,7 +135,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/mxchip/az3166_iotdevkit/doc/index.rst b/boards/mxchip/az3166_iotdevkit/doc/index.rst index 2e44339bec20b39..694d53517a6b5ac 100644 --- a/boards/mxchip/az3166_iotdevkit/doc/index.rst +++ b/boards/mxchip/az3166_iotdevkit/doc/index.rst @@ -76,7 +76,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf21540dk/doc/index.rst b/boards/nordic/nrf21540dk/doc/index.rst index 8ea583edb1a09f0..7ed102b2b611441 100644 --- a/boards/nordic/nrf21540dk/doc/index.rst +++ b/boards/nordic/nrf21540dk/doc/index.rst @@ -135,7 +135,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf51dk/doc/index.rst b/boards/nordic/nrf51dk/doc/index.rst index c905dc0f4764b13..f5a2acbbcde5136 100644 --- a/boards/nordic/nrf51dk/doc/index.rst +++ b/boards/nordic/nrf51dk/doc/index.rst @@ -110,7 +110,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf51dongle/doc/index.rst b/boards/nordic/nrf51dongle/doc/index.rst index d8183371654a836..63f288e23fcc828 100644 --- a/boards/nordic/nrf51dongle/doc/index.rst +++ b/boards/nordic/nrf51dongle/doc/index.rst @@ -105,7 +105,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf52833dk/doc/index.rst b/boards/nordic/nrf52833dk/doc/index.rst index 027f471586fed23..ed057bbc93cbf37 100644 --- a/boards/nordic/nrf52833dk/doc/index.rst +++ b/boards/nordic/nrf52833dk/doc/index.rst @@ -119,7 +119,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf52840dk/doc/index.rst b/boards/nordic/nrf52840dk/doc/index.rst index faa7f07d5c931ca..7c948d7cffd828d 100644 --- a/boards/nordic/nrf52840dk/doc/index.rst +++ b/boards/nordic/nrf52840dk/doc/index.rst @@ -124,7 +124,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf52dk/doc/index.rst b/boards/nordic/nrf52dk/doc/index.rst index 4ebcac44e6c2530..61349e8d31c2ba5 100644 --- a/boards/nordic/nrf52dk/doc/index.rst +++ b/boards/nordic/nrf52dk/doc/index.rst @@ -357,7 +357,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf5340dk/doc/index.rst b/boards/nordic/nrf5340dk/doc/index.rst index e933f43bdb4b5f1..9aa3f79180b1d85 100644 --- a/boards/nordic/nrf5340dk/doc/index.rst +++ b/boards/nordic/nrf5340dk/doc/index.rst @@ -278,7 +278,7 @@ applications as usual (:ref:`build_an_application` and information on how to install the nRF Command Line Tools can be found in :ref:`nordic_segger_flashing`. -Here is an example for the :ref:`hello_world` application running on the +Here is an example for the :zephyr:code-sample:`hello_world` application running on the nRF5340 application core. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf54h20dk/doc/index.rst b/boards/nordic/nrf54h20dk/doc/index.rst index 6aa59b7c735f961..41306357fe4a4c6 100644 --- a/boards/nordic/nrf54h20dk/doc/index.rst +++ b/boards/nordic/nrf54h20dk/doc/index.rst @@ -129,7 +129,7 @@ cores only, using :ref:`nordic_segger`. Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. To build and program the sample to the nRF54H20 DK, complete the following steps: diff --git a/boards/nordic/nrf54l15dk/doc/index.rst b/boards/nordic/nrf54l15dk/doc/index.rst index d411032ff2c69a9..7d450912661b8e1 100644 --- a/boards/nordic/nrf54l15dk/doc/index.rst +++ b/boards/nordic/nrf54l15dk/doc/index.rst @@ -103,7 +103,7 @@ Enter the following command to compile ``hello_world`` for the FLPR core:: Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. .. warning:: diff --git a/boards/nordic/nrf54l15pdk/doc/index.rst b/boards/nordic/nrf54l15pdk/doc/index.rst index ccc6230dd7dff6c..dc6e69b65e5aea2 100644 --- a/boards/nordic/nrf54l15pdk/doc/index.rst +++ b/boards/nordic/nrf54l15pdk/doc/index.rst @@ -97,7 +97,7 @@ building and running. Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. .. warning:: diff --git a/boards/nordic/nrf54l20pdk/doc/index.rst b/boards/nordic/nrf54l20pdk/doc/index.rst index 2297df5dd41ffb9..aaed616eccef1f9 100644 --- a/boards/nordic/nrf54l20pdk/doc/index.rst +++ b/boards/nordic/nrf54l20pdk/doc/index.rst @@ -68,7 +68,7 @@ building and running. Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. Follow the instructions in the :ref:`nordic_segger` page to install diff --git a/boards/nordic/nrf7002dk/doc/index.rst b/boards/nordic/nrf7002dk/doc/index.rst index 5b25a7aa28fbe26..3e3153c376f609c 100644 --- a/boards/nordic/nrf7002dk/doc/index.rst +++ b/boards/nordic/nrf7002dk/doc/index.rst @@ -278,7 +278,7 @@ applications as usual (:ref:`build_an_application` and information on how to install the nRF Command Line Tools can be found in :ref:`nordic_segger_flashing`. -Here is an example for the :ref:`hello_world` application running on the +Here is an example for the :zephyr:code-sample:`hello_world` application running on the nRF5340 application core. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9131ek/doc/index.rst b/boards/nordic/nrf9131ek/doc/index.rst index accd403a2868356..236f6b396fc2a46 100644 --- a/boards/nordic/nrf9131ek/doc/index.rst +++ b/boards/nordic/nrf9131ek/doc/index.rst @@ -180,7 +180,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9151dk/doc/index.rst b/boards/nordic/nrf9151dk/doc/index.rst index 4017347c4f84b70..2365de529f7eb0d 100644 --- a/boards/nordic/nrf9151dk/doc/index.rst +++ b/boards/nordic/nrf9151dk/doc/index.rst @@ -150,7 +150,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9160dk/doc/index.rst b/boards/nordic/nrf9160dk/doc/index.rst index 70fd2c2fc46ec03..a91cf76547b1fa6 100644 --- a/boards/nordic/nrf9160dk/doc/index.rst +++ b/boards/nordic/nrf9160dk/doc/index.rst @@ -214,7 +214,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -346,7 +346,7 @@ applications as usual (see :ref:`build_an_application` and Remember to set the PROG/DEBUG switch on the DK to nRF52. -See the following example for the :ref:`hello_world` application. +See the following example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9161dk/doc/index.rst b/boards/nordic/nrf9161dk/doc/index.rst index 251c8467a214c2a..bb9d4eebbe4f6e6 100644 --- a/boards/nordic/nrf9161dk/doc/index.rst +++ b/boards/nordic/nrf9161dk/doc/index.rst @@ -153,7 +153,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/nordic/nrf9280pdk/doc/index.rst b/boards/nordic/nrf9280pdk/doc/index.rst index 052d2e5218c7581..394229217f7a53f 100644 --- a/boards/nordic/nrf9280pdk/doc/index.rst +++ b/boards/nordic/nrf9280pdk/doc/index.rst @@ -71,7 +71,7 @@ and :ref:`application_run` for more details on building and running. Flashing ======== -As an example, this section shows how to build and flash the :ref:`hello_world` +As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` application. Follow the instructions in the :ref:`nordic_segger` page to install diff --git a/boards/nuvoton/npcm400_evb/doc/index.rst b/boards/nuvoton/npcm400_evb/doc/index.rst index 930ac3dfe3a8c52..d5d9ee550c25751 100644 --- a/boards/nuvoton/npcm400_evb/doc/index.rst +++ b/boards/nuvoton/npcm400_evb/doc/index.rst @@ -86,7 +86,7 @@ If the correct headers are installed, this board supports J-TAG. To flash with J-TAG, install the drivers for your programmer, for example: SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nuvoton/numaker_m2l31ki/doc/index.rst b/boards/nuvoton/numaker_m2l31ki/doc/index.rst index 3e2c8b9550b8741..8c2e8b8bf77fe49 100644 --- a/boards/nuvoton/numaker_m2l31ki/doc/index.rst +++ b/boards/nuvoton/numaker_m2l31ki/doc/index.rst @@ -58,7 +58,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb, To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. @@ -77,7 +77,7 @@ run a serial host program to connect with your board. For example: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nuvoton/numaker_pfm_m467/doc/index.rst b/boards/nuvoton/numaker_pfm_m467/doc/index.rst index 483ab34b6234012..6620acce55947eb 100644 --- a/boards/nuvoton/numaker_pfm_m467/doc/index.rst +++ b/boards/nuvoton/numaker_pfm_m467/doc/index.rst @@ -62,7 +62,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb, To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. @@ -81,7 +81,7 @@ run a serial host program to connect with your board. For example: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nuvoton/numaker_pfm_m487/doc/index.rst b/boards/nuvoton/numaker_pfm_m487/doc/index.rst index 323be5f5923f6fd..180ae3c5665a1f0 100644 --- a/boards/nuvoton/numaker_pfm_m487/doc/index.rst +++ b/boards/nuvoton/numaker_pfm_m487/doc/index.rst @@ -61,7 +61,7 @@ Building and Flashing Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. On board debugger Nu-link-Me can emulate UART0 as a virtual COM port over usb, To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. @@ -80,7 +80,7 @@ run a serial host program to connect with your board. For example: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_k22f/doc/index.rst b/boards/nxp/frdm_k22f/doc/index.rst index b92fa508cd0223e..2e5ea18aab8567d 100644 --- a/boards/nxp/frdm_k22f/doc/index.rst +++ b/boards/nxp/frdm_k22f/doc/index.rst @@ -237,7 +237,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -255,7 +255,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_k64f/doc/index.rst b/boards/nxp/frdm_k64f/doc/index.rst index 1c240ef400ff362..17af8d4cf2950a8 100644 --- a/boards/nxp/frdm_k64f/doc/index.rst +++ b/boards/nxp/frdm_k64f/doc/index.rst @@ -309,7 +309,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -327,7 +327,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_k82f/doc/index.rst b/boards/nxp/frdm_k82f/doc/index.rst index f306dc6dada7754..9903e1b449320a2 100644 --- a/boards/nxp/frdm_k82f/doc/index.rst +++ b/boards/nxp/frdm_k82f/doc/index.rst @@ -194,7 +194,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -212,7 +212,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_ke15z/doc/index.rst b/boards/nxp/frdm_ke15z/doc/index.rst index fd1dec9bc67f6d7..772de4f86786077 100644 --- a/boards/nxp/frdm_ke15z/doc/index.rst +++ b/boards/nxp/frdm_ke15z/doc/index.rst @@ -129,7 +129,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -147,7 +147,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_ke17z/doc/index.rst b/boards/nxp/frdm_ke17z/doc/index.rst index 7fb9f29d84ec563..1f15fc99fb93a39 100644 --- a/boards/nxp/frdm_ke17z/doc/index.rst +++ b/boards/nxp/frdm_ke17z/doc/index.rst @@ -156,7 +156,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -174,7 +174,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_ke17z512/doc/index.rst b/boards/nxp/frdm_ke17z512/doc/index.rst index 3e5be805da6e7d6..ab4948307da672c 100644 --- a/boards/nxp/frdm_ke17z512/doc/index.rst +++ b/boards/nxp/frdm_ke17z512/doc/index.rst @@ -152,7 +152,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -170,7 +170,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_kl25z/doc/index.rst b/boards/nxp/frdm_kl25z/doc/index.rst index 6695974c29ebbf4..215c476df03d696 100644 --- a/boards/nxp/frdm_kl25z/doc/index.rst +++ b/boards/nxp/frdm_kl25z/doc/index.rst @@ -189,7 +189,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -207,7 +207,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_kw41z/doc/index.rst b/boards/nxp/frdm_kw41z/doc/index.rst index 4457b6d9b16b7b7..b1643939f8efba5 100644 --- a/boards/nxp/frdm_kw41z/doc/index.rst +++ b/boards/nxp/frdm_kw41z/doc/index.rst @@ -201,7 +201,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -219,7 +219,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_mcxa156/doc/index.rst b/boards/nxp/frdm_mcxa156/doc/index.rst index 96255473c2f1b50..df622a40ddfdaa0 100644 --- a/boards/nxp/frdm_mcxa156/doc/index.rst +++ b/boards/nxp/frdm_mcxa156/doc/index.rst @@ -149,7 +149,7 @@ Connect a USB cable from your PC to J21, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -167,7 +167,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_mcxc242/doc/index.rst b/boards/nxp/frdm_mcxc242/doc/index.rst index 4d5b0f89aaac72c..ecde1643da91367 100644 --- a/boards/nxp/frdm_mcxc242/doc/index.rst +++ b/boards/nxp/frdm_mcxc242/doc/index.rst @@ -171,7 +171,7 @@ Connect a USB cable from your PC to J9, and use the serial terminal of your choi Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -189,7 +189,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_mcxn236/doc/index.rst b/boards/nxp/frdm_mcxn236/doc/index.rst index 0793d68e2466d18..3ee20c5c1e817a1 100644 --- a/boards/nxp/frdm_mcxn236/doc/index.rst +++ b/boards/nxp/frdm_mcxn236/doc/index.rst @@ -156,7 +156,7 @@ Connect a USB cable from your PC to J10, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -174,7 +174,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst index 5febc07a861bf70..1559dcea969ba07 100644 --- a/boards/nxp/frdm_mcxn947/doc/index.rst +++ b/boards/nxp/frdm_mcxn947/doc/index.rst @@ -190,7 +190,7 @@ Connect a USB cable from your PC to J17, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -208,7 +208,7 @@ see the following message in the terminal: Flashing to QSPI ================ -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :app: zephyr/samples/hello_world @@ -245,7 +245,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/frdm_rw612/doc/index.rst b/boards/nxp/frdm_rw612/doc/index.rst index f6aec20817682b4..0044b09cb9c0429 100644 --- a/boards/nxp/frdm_rw612/doc/index.rst +++ b/boards/nxp/frdm_rw612/doc/index.rst @@ -102,7 +102,7 @@ Connect a USB cable from your PC to J10, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -121,7 +121,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: diff --git a/boards/nxp/hexiwear/doc/index.rst b/boards/nxp/hexiwear/doc/index.rst index bc4d58a70d43378..6f47bddf00d33bd 100644 --- a/boards/nxp/hexiwear/doc/index.rst +++ b/boards/nxp/hexiwear/doc/index.rst @@ -227,7 +227,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -245,7 +245,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -460,7 +460,7 @@ Once you have started a debug session, run telnet: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -486,7 +486,7 @@ terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst index e782798c1594936..d834726d0c1420e 100644 --- a/boards/nxp/imx8mm_evk/doc/index.rst +++ b/boards/nxp/imx8mm_evk/doc/index.rst @@ -222,7 +222,7 @@ MIMX8MM EVK board can be debugged by connecting an external JLink JTAG debugger to the J902 debug connector and to the PC. Then the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst index 839288cf67007d2..69a9b463b747249 100644 --- a/boards/nxp/imx8mp_evk/doc/index.rst +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -297,7 +297,7 @@ MIMX8MP EVK board can be debugged by connecting an external JLink JTAG debugger to the J24 debug connector and to the PC. Then the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/imx8mq_evk/doc/index.rst b/boards/nxp/imx8mq_evk/doc/index.rst index 40bd5ac5c5042a8..8f21c6e9328cd2d 100644 --- a/boards/nxp/imx8mq_evk/doc/index.rst +++ b/boards/nxp/imx8mq_evk/doc/index.rst @@ -190,7 +190,7 @@ MIMX8MQ EVK board can be debugged by connecting an external JLink JTAG debugger to the J401 debug connector and to the PC. Then the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/imx95_evk/doc/index.rst b/boards/nxp/imx95_evk/doc/index.rst index e4664a282b7113a..3b7a69ceece2684 100644 --- a/boards/nxp/imx95_evk/doc/index.rst +++ b/boards/nxp/imx95_evk/doc/index.rst @@ -229,7 +229,7 @@ MCUXpresso SDK for IMX95LPD5EVK-19.pdf`` in i.MX95 `MCUX SDK release`_. See ``4.2 Run an example application``, just rename ``zephyr.bin`` to ``m7_image.bin`` to make flash.bin and program to SD/eMMC. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso51u68/doc/index.rst b/boards/nxp/lpcxpresso51u68/doc/index.rst index c1fff7e4d7b1d94..491aa2beab14877 100644 --- a/boards/nxp/lpcxpresso51u68/doc/index.rst +++ b/boards/nxp/lpcxpresso51u68/doc/index.rst @@ -133,7 +133,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -148,7 +148,7 @@ Here is an example for the :ref:`hello_world` application. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso54114/doc/index.rst b/boards/nxp/lpcxpresso54114/doc/index.rst index 0402d19d239a80b..df2e2aabf0d6823 100644 --- a/boards/nxp/lpcxpresso54114/doc/index.rst +++ b/boards/nxp/lpcxpresso54114/doc/index.rst @@ -166,7 +166,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -184,7 +184,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s06/doc/index.rst b/boards/nxp/lpcxpresso55s06/doc/index.rst index 01f7f6b539bf229..10a1b6728ca585d 100644 --- a/boards/nxp/lpcxpresso55s06/doc/index.rst +++ b/boards/nxp/lpcxpresso55s06/doc/index.rst @@ -156,7 +156,7 @@ settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -174,7 +174,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s16/doc/index.rst b/boards/nxp/lpcxpresso55s16/doc/index.rst index f0d0c52bb0022a8..8089e3de0ef7a56 100644 --- a/boards/nxp/lpcxpresso55s16/doc/index.rst +++ b/boards/nxp/lpcxpresso55s16/doc/index.rst @@ -191,7 +191,7 @@ settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -209,7 +209,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s28/doc/index.rst b/boards/nxp/lpcxpresso55s28/doc/index.rst index 1e97071456fe970..df40571a18b4556 100644 --- a/boards/nxp/lpcxpresso55s28/doc/index.rst +++ b/boards/nxp/lpcxpresso55s28/doc/index.rst @@ -164,7 +164,7 @@ choice (minicom, putty, etc.) with the following settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -182,7 +182,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s36/doc/index.rst b/boards/nxp/lpcxpresso55s36/doc/index.rst index bff3ef5d36a178e..32c7993c3a3e52d 100644 --- a/boards/nxp/lpcxpresso55s36/doc/index.rst +++ b/boards/nxp/lpcxpresso55s36/doc/index.rst @@ -195,7 +195,7 @@ settings: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -213,7 +213,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst index 4c157c9f5f01653..85336fa285550a5 100644 --- a/boards/nxp/lpcxpresso55s69/doc/index.rst +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -322,7 +322,7 @@ Connect a USB cable from your PC to P6, and use the serial terminal of your choi Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -365,7 +365,7 @@ an example of building for both cores with sysbuild, see Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: diff --git a/boards/nxp/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst index c0d9670d06c7661..6422927371ec531 100644 --- a/boards/nxp/mimxrt1010_evk/doc/index.rst +++ b/boards/nxp/mimxrt1010_evk/doc/index.rst @@ -201,7 +201,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1015_evk/doc/index.rst b/boards/nxp/mimxrt1015_evk/doc/index.rst index fb81c2d841073c2..7e22bd4c5541f45 100644 --- a/boards/nxp/mimxrt1015_evk/doc/index.rst +++ b/boards/nxp/mimxrt1015_evk/doc/index.rst @@ -203,7 +203,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1020_evk/doc/index.rst b/boards/nxp/mimxrt1020_evk/doc/index.rst index 5e3f240c70df029..0057dcd58ab2f1f 100644 --- a/boards/nxp/mimxrt1020_evk/doc/index.rst +++ b/boards/nxp/mimxrt1020_evk/doc/index.rst @@ -261,7 +261,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -279,7 +279,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1024_evk/doc/index.rst b/boards/nxp/mimxrt1024_evk/doc/index.rst index 991c9c1ce6ea0b3..e451a0274327a84 100644 --- a/boards/nxp/mimxrt1024_evk/doc/index.rst +++ b/boards/nxp/mimxrt1024_evk/doc/index.rst @@ -243,7 +243,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -261,7 +261,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst index c6322960f248847..fffd3873fa549f8 100644 --- a/boards/nxp/mimxrt1040_evk/doc/index.rst +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -252,7 +252,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -270,7 +270,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst index 8e283c0e0bf4918..19deec55f09ab05 100644 --- a/boards/nxp/mimxrt1050_evk/doc/index.rst +++ b/boards/nxp/mimxrt1050_evk/doc/index.rst @@ -367,7 +367,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -385,7 +385,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst index b7df78d597f770d..e17f57ee77f4c7d 100644 --- a/boards/nxp/mimxrt1060_evk/doc/index.rst +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -378,7 +378,7 @@ SWO frequency of 7500KHz. Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -396,7 +396,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst index edcd5bc5f11a2a4..e587a8c50872133 100644 --- a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst +++ b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst @@ -303,7 +303,7 @@ SWO frequency of 7500KHz. Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -321,7 +321,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst index fdd21841ca7db9c..4f6fab6f0f646e2 100644 --- a/boards/nxp/mimxrt1064_evk/doc/index.rst +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -373,7 +373,7 @@ SWO frequency of 7500KHz. Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -391,7 +391,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst index 8cc8b7408de3834..5b8a110d1b01e56 100644 --- a/boards/nxp/mimxrt1160_evk/doc/index.rst +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -314,7 +314,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Before power on the board, make sure SW1 is set to 0001b @@ -335,7 +335,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst index c3de9f8fd3bbc0c..7500442bd1b6efc 100644 --- a/boards/nxp/mimxrt1170_evk/doc/index.rst +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -410,7 +410,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Before powering the board, make sure SW1 is set to 0001b @@ -431,7 +431,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt1180_evk/doc/index.rst b/boards/nxp/mimxrt1180_evk/doc/index.rst index 80926edc46484a3..71066d77f3f3de4 100644 --- a/boards/nxp/mimxrt1180_evk/doc/index.rst +++ b/boards/nxp/mimxrt1180_evk/doc/index.rst @@ -211,7 +211,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application on cm33 core. +Here is an example for the :zephyr:code-sample:`hello_world` application on cm33 core. Before power on the board, make sure SW5 is set to 0100b @@ -232,7 +232,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/mimxrt595_evk/doc/index.rst b/boards/nxp/mimxrt595_evk/doc/index.rst index 5be8e0da21c8dd7..5465a912e8be0af 100644 --- a/boards/nxp/mimxrt595_evk/doc/index.rst +++ b/boards/nxp/mimxrt595_evk/doc/index.rst @@ -244,7 +244,7 @@ Connect a USB cable from your PC to J40, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -263,7 +263,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst index 4e8f9d79f516bdc..4f53d6435b5b4d4 100644 --- a/boards/nxp/mimxrt685_evk/doc/index.rst +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -285,7 +285,7 @@ Connect a USB cable from your PC to J16, and use the serial terminal of your cho Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`linkserver-debug-host-tools` as default. .. zephyr-app-commands:: @@ -304,7 +304,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`linkserver-debug-host-tools` as default. .. zephyr-app-commands:: diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst index 558effd60a3d1ce..e0215ececad5a76 100644 --- a/boards/nxp/rd_rw612_bga/doc/index.rst +++ b/boards/nxp/rd_rw612_bga/doc/index.rst @@ -111,7 +111,7 @@ Connect a USB cable from your PC to J7, and use the serial terminal of your choi Flashing ======== -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: @@ -130,7 +130,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. This example uses the +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the :ref:`jlink-debug-host-tools` as default. .. zephyr-app-commands:: diff --git a/boards/nxp/rddrone_fmuk66/doc/index.rst b/boards/nxp/rddrone_fmuk66/doc/index.rst index 69d862455ac6249..e938c685ba73d9e 100644 --- a/boards/nxp/rddrone_fmuk66/doc/index.rst +++ b/boards/nxp/rddrone_fmuk66/doc/index.rst @@ -144,7 +144,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -162,7 +162,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst index 58e5ea3660c1cc1..d864059de00bbfc 100644 --- a/boards/nxp/s32z2xxdc2/doc/index.rst +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -200,7 +200,7 @@ under Linux, ``/dev/ttyUSB0``. Debugging ========= -You can build and debug the :ref:`hello_world` sample for the board +You can build and debug the :zephyr:code-sample:`hello_world` sample for the board ``s32z2xxdc2/s32z270/rtu0`` with: .. zephyr-app-commands:: @@ -296,7 +296,7 @@ Where: - ```` is the zero-based core index relative to the RTU on which to run the Zephyr application (0, 1, 2 or 3) -For example, to build the :ref:`hello_world` sample for the board +For example, to build the :zephyr:code-sample:`hello_world` sample for the board ``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration: .. zephyr-app-commands:: diff --git a/boards/nxp/twr_ke18f/doc/index.rst b/boards/nxp/twr_ke18f/doc/index.rst index a72227beb67663f..4d91e6e33524eac 100644 --- a/boards/nxp/twr_ke18f/doc/index.rst +++ b/boards/nxp/twr_ke18f/doc/index.rst @@ -193,7 +193,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -211,7 +211,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/twr_kv58f220m/doc/index.rst b/boards/nxp/twr_kv58f220m/doc/index.rst index 98cc3a880afe759..f9adc60064a24a4 100644 --- a/boards/nxp/twr_kv58f220m/doc/index.rst +++ b/boards/nxp/twr_kv58f220m/doc/index.rst @@ -148,7 +148,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -166,7 +166,7 @@ see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/usb_kw24d512/doc/index.rst b/boards/nxp/usb_kw24d512/doc/index.rst index b617edcf6d6f8df..37bbb88726d42a2 100644 --- a/boards/nxp/usb_kw24d512/doc/index.rst +++ b/boards/nxp/usb_kw24d512/doc/index.rst @@ -170,7 +170,7 @@ Once you have started a debug session, run telnet: Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -196,7 +196,7 @@ terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/nxp/vmu_rt1170/doc/index.rst b/boards/nxp/vmu_rt1170/doc/index.rst index fa0327c0a9fcebf..4ad7bad0c177975 100644 --- a/boards/nxp/vmu_rt1170/doc/index.rst +++ b/boards/nxp/vmu_rt1170/doc/index.rst @@ -507,7 +507,7 @@ etc.): Flashing ======== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -524,7 +524,7 @@ You should see the following message in the terminal: Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/olimex_esp32_evb/doc/index.rst b/boards/olimex/olimex_esp32_evb/doc/index.rst index f904861af22244c..5af913a12732d92 100644 --- a/boards/olimex/olimex_esp32_evb/doc/index.rst +++ b/boards/olimex/olimex_esp32_evb/doc/index.rst @@ -205,7 +205,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``olimex_esp32_evb`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -238,7 +238,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -246,7 +246,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_e407/doc/index.rst b/boards/olimex/stm32_e407/doc/index.rst index 6abdc3b564cc18f..6af85cf75e07a9f 100644 --- a/boards/olimex/stm32_e407/doc/index.rst +++ b/boards/olimex/stm32_e407/doc/index.rst @@ -336,7 +336,7 @@ Flashing an application to the Olimex-STM32-E407 Connect the ST-Link USB dongle to your host computer and to the JTAG port of the OLIMEX-STM32-E407 board. Then build and flash an application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -360,7 +360,7 @@ Debugging ========= Provided that you have a JTAG probe, you can debug an application in the usual -way. Here is an example for the :ref:`hello_world` application. +way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_h103/doc/index.rst b/boards/olimex/stm32_h103/doc/index.rst index 3abfb3b8885ba2a..291b34bfc34c428 100644 --- a/boards/olimex/stm32_h103/doc/index.rst +++ b/boards/olimex/stm32_h103/doc/index.rst @@ -219,7 +219,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_h405/doc/index.rst b/boards/olimex/stm32_h405/doc/index.rst index ab051345b9c0319..ff3c8b2bf463829 100644 --- a/boards/olimex/stm32_h405/doc/index.rst +++ b/boards/olimex/stm32_h405/doc/index.rst @@ -171,7 +171,7 @@ In the following examples a ST-Link V2 USB dongle is used. Flashing an application to the Olimex-STM32-H405 ================================================ -The sample application :ref:`hello_world` is being used in this tutorial. +The sample application :zephyr:code-sample:`hello_world` is being used in this tutorial. Connect the ST-Link USB dongle to your host computer and to the JTAG port of the OLIMEX-STM32-H405 board. @@ -201,7 +201,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_h407/doc/index.rst b/boards/olimex/stm32_h407/doc/index.rst index 3555ed52a350327..114543e27cfaa23 100644 --- a/boards/olimex/stm32_h407/doc/index.rst +++ b/boards/olimex/stm32_h407/doc/index.rst @@ -332,7 +332,7 @@ Flashing an application to the Olimex-STM32-H407 Connect the ARM-USB-OCD-H debugger to your host computer and to the JTAG port of the OLIMEX-STM32-H407 board. Then build and flash an application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -357,7 +357,7 @@ Debugging ========= Provided that you have a JTAG probe, you can debug an application in the usual -way. Here is an example for the :ref:`hello_world` application. +way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/olimex/stm32_p405/doc/index.rst b/boards/olimex/stm32_p405/doc/index.rst index e68bcb589ca4d59..c754213c954d09b 100644 --- a/boards/olimex/stm32_p405/doc/index.rst +++ b/boards/olimex/stm32_p405/doc/index.rst @@ -216,7 +216,7 @@ In the following examples a ST-Link V2 USB dongle is used. Flashing an application to the Olimex-STM32-P405 ================================================ -The sample application :ref:`hello_world` is being used in this tutorial. +The sample application :zephyr:code-sample:`hello_world` is being used in this tutorial. Connect the ST-Link USB dongle to your host computer and to the JTAG port of the OLIMEX-STM32-P405 board. @@ -245,7 +245,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/openisa/rv32m1_vega/doc/index.rst b/boards/openisa/rv32m1_vega/doc/index.rst index 339b8dc5e0ccd4d..92d9e9997523f96 100644 --- a/boards/openisa/rv32m1_vega/doc/index.rst +++ b/boards/openisa/rv32m1_vega/doc/index.rst @@ -577,7 +577,7 @@ toolchain and OpenOCD:: The above only sets these variables for your current shell session. You need to make sure this happens every time you use this board. -Now let's compile the :ref:`hello_world` application. (You can try +Now let's compile the :zephyr:code-sample:`hello_world` application. (You can try others as well; see :ref:`samples-and-demos` for more.) .. We can't use zephyr-app-commands to provide build instructions diff --git a/boards/others/black_f407ve/doc/index.rst b/boards/others/black_f407ve/doc/index.rst index a338e7ccf4b6a47..cffdd4d41be4d57 100644 --- a/boards/others/black_f407ve/doc/index.rst +++ b/boards/others/black_f407ve/doc/index.rst @@ -222,7 +222,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/black_f407zg_pro/doc/index.rst b/boards/others/black_f407zg_pro/doc/index.rst index 1ca764cdf1d786a..4857e8bb8da57c2 100644 --- a/boards/others/black_f407zg_pro/doc/index.rst +++ b/boards/others/black_f407zg_pro/doc/index.rst @@ -204,7 +204,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/icev_wireless/doc/index.rst b/boards/others/icev_wireless/doc/index.rst index 32598b6e53f35a1..5b56cd94c3d2d6d 100644 --- a/boards/others/icev_wireless/doc/index.rst +++ b/boards/others/icev_wireless/doc/index.rst @@ -224,7 +224,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -233,7 +233,7 @@ Here is an example for building the :ref:`hello_world` application. :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst index 6626c24d0d02bbe..a2dedba0a76f72c 100644 --- a/boards/others/neorv32/doc/index.rst +++ b/boards/others/neorv32/doc/index.rst @@ -121,7 +121,7 @@ etc.): Flashing via JTAG ================= -Here is an example for building and flashing the :ref:`hello_world` application +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application for the NEORV32 via JTAG. Flashing via JTAG requires a NEORV32 SoC implementation with the On-Chip Debugger (OCD) and bootloader enabled. @@ -185,7 +185,7 @@ built-in bootloader as described in the NEORV32 user guide. Debugging via JTAG ================== -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/others/stm32_min_dev/doc/index.rst b/boards/others/stm32_min_dev/doc/index.rst index 61caf674f95921e..e27ea5c59f5afd5 100644 --- a/boards/others/stm32_min_dev/doc/index.rst +++ b/boards/others/stm32_min_dev/doc/index.rst @@ -172,7 +172,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/argon/doc/index.rst b/boards/particle/argon/doc/index.rst index 2bbb15a546f8c35..0cfedf946db838a 100644 --- a/boards/particle/argon/doc/index.rst +++ b/boards/particle/argon/doc/index.rst @@ -145,7 +145,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/boron/doc/index.rst b/boards/particle/boron/doc/index.rst index d5b7ce1f5d0fe74..da87b144a0ddf38 100644 --- a/boards/particle/boron/doc/index.rst +++ b/boards/particle/boron/doc/index.rst @@ -141,7 +141,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/nrf51_blenano/doc/index.rst b/boards/particle/nrf51_blenano/doc/index.rst index 4caae408e212c43..1d6d2ea4a2a93dd 100644 --- a/boards/particle/nrf51_blenano/doc/index.rst +++ b/boards/particle/nrf51_blenano/doc/index.rst @@ -79,7 +79,7 @@ DAPLink board, then attach that to your computer via USB. properly solder headers and assemble the DAPLink and BLE Nano boards. Now build and flash applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -91,7 +91,7 @@ Debugging After mounting the BLE Nano on its DAPLink board as described above, you can debug an application in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/nrf52_blenano2/doc/index.rst b/boards/particle/nrf52_blenano2/doc/index.rst index 6c32b4f3d776d46..b2d0824bfc116b5 100644 --- a/boards/particle/nrf52_blenano2/doc/index.rst +++ b/boards/particle/nrf52_blenano2/doc/index.rst @@ -77,7 +77,7 @@ DAPLink board, then attach that to your computer via USB. connector. Now build and flash applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -89,7 +89,7 @@ Debugging After mounting the BLE Nano 2 on its DAPLink board as described above, you can debug an application in the usual way. Here is an example for -the :ref:`hello_world` application. +the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/particle/xenon/doc/index.rst b/boards/particle/xenon/doc/index.rst index cf18340943a7094..d28b8aac1c086d0 100644 --- a/boards/particle/xenon/doc/index.rst +++ b/boards/particle/xenon/doc/index.rst @@ -146,7 +146,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst index b9643a359e306ab..6314b716513cc58 100644 --- a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst +++ b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst @@ -215,7 +215,7 @@ the M7 core has to be switched on: u-boot=> bootaux 0x7e0000 -Here is an example for the :ref:`hello_world` application: +Here is an example for the :zephyr:code-sample:`hello_world` application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/phytec/phyboard_electra/doc/index.rst b/boards/phytec/phyboard_electra/doc/index.rst index 372f8d3cd7347f8..9af3400555d4e18 100644 --- a/boards/phytec/phyboard_electra/doc/index.rst +++ b/boards/phytec/phyboard_electra/doc/index.rst @@ -104,7 +104,7 @@ The Linux running on the A53 uses the remoteproc framework to manage the M4F co- Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the :ref:`hello_world` sample with the following command. +To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command. .. zephyr-app-commands:: :board: phyboard_electra/am6442/m4 diff --git a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst index 410debfd9b7d0d7..9b6d2f42a3d2acb 100644 --- a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst +++ b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst @@ -80,7 +80,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: phyboard_lyra/am6234/a53 diff --git a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst index 55d4939529fe0e9..d0f61264890f289 100644 --- a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst +++ b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst @@ -96,7 +96,7 @@ The Linux running on the A53 uses the remoteproc framework to manage the M4F co- Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the :ref:`hello_world` sample with the following command. +To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command. .. code-block:: console diff --git a/boards/phytec/reel_board/doc/index.rst b/boards/phytec/reel_board/doc/index.rst index 79001a009e55018..d468a6c559af61d 100644 --- a/boards/phytec/reel_board/doc/index.rst +++ b/boards/phytec/reel_board/doc/index.rst @@ -497,7 +497,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -528,7 +528,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst index 4699de8c3816ba7..93966edb73990ae 100644 --- a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst +++ b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst @@ -31,7 +31,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/rak/rak11720/doc/index.rst b/boards/rak/rak11720/doc/index.rst index ff8e90a962be715..238ba6d830378d6 100644 --- a/boards/rak/rak11720/doc/index.rst +++ b/boards/rak/rak11720/doc/index.rst @@ -83,7 +83,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: .. zephyr-app-commands:: diff --git a/boards/rak/rak4631/doc/index.rst b/boards/rak/rak4631/doc/index.rst index ffa39ca82659117..14c6c912976874a 100644 --- a/boards/rak/rak4631/doc/index.rst +++ b/boards/rak/rak4631/doc/index.rst @@ -121,7 +121,7 @@ Flashing - Stop bits: 1 #. Connect the RAK4631 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. + Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -134,7 +134,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/rak/rak5010/doc/index.rst b/boards/rak/rak5010/doc/index.rst index fac00cf72dfa02d..851d89248428790 100644 --- a/boards/rak/rak5010/doc/index.rst +++ b/boards/rak/rak5010/doc/index.rst @@ -126,7 +126,7 @@ Flashing - Stop bits: 1 #. Connect the RAK5010 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. + Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -139,7 +139,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/raspberrypi/rpi_5/doc/index.rst b/boards/raspberrypi/rpi_5/doc/index.rst index 1c63e5a94ad64e0..fd0ad27df0a4459 100644 --- a/boards/raspberrypi/rpi_5/doc/index.rst +++ b/boards/raspberrypi/rpi_5/doc/index.rst @@ -126,7 +126,7 @@ config.txt zephyr.bin ---------- -Build an app, for example :ref:`hello_world`: +Build an app, for example :zephyr:code-sample:`hello_world`: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst index b078dd2984e0e38..8089b7b5e489b10 100644 --- a/boards/raytac/mdbt50q_db_33/doc/index.rst +++ b/boards/raytac/mdbt50q_db_33/doc/index.rst @@ -147,7 +147,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_33/nrf52833 J10 connector. Then run your favorite terminal program to listen for output. diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst index f9d79818f6a8e2d..269b42bb9d583d5 100644 --- a/boards/raytac/mdbt50q_db_40/doc/index.rst +++ b/boards/raytac/mdbt50q_db_40/doc/index.rst @@ -149,7 +149,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_40/nrf52840 J10 connector. Then run your favorite terminal program to listen for output. diff --git a/boards/raytac/mdbt53_db_40/doc/index.rst b/boards/raytac/mdbt53_db_40/doc/index.rst index a57fc5225dc5f80..9ddb5b77c5d6e5c 100644 --- a/boards/raytac/mdbt53_db_40/doc/index.rst +++ b/boards/raytac/mdbt53_db_40/doc/index.rst @@ -225,7 +225,7 @@ applications as usual (see :ref:`build_an_application` and If you are flashing with :ref:`west `, run this command for more details on the related ``--recover`` option: -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt53_db_40_nrf5340 J10 connector. Then run your favorite terminal program to listen for output. diff --git a/boards/raytac/mdbt53v_db_40/doc/index.rst b/boards/raytac/mdbt53v_db_40/doc/index.rst index ca38f03a78108c4..27a2aeee34591c4 100644 --- a/boards/raytac/mdbt53v_db_40/doc/index.rst +++ b/boards/raytac/mdbt53v_db_40/doc/index.rst @@ -218,7 +218,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Use a USB to TTL converter to connect the computer and raytac_mdbt53v_db_40_nrf5340 J13 connector pin 8(RX), 9(TX) and GND. Then run your favorite terminal program to listen for output. diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst index 5fcd4fa090910ff..f77c16196fa1cf2 100644 --- a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst @@ -224,7 +224,7 @@ Debugging First of all, open your serial terminal. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst index e95049a42c43032..3e7b57729444f89 100644 --- a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst +++ b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst @@ -147,7 +147,7 @@ Debugging First of all, open your serial terminal. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst index 2f45cf1521ee6e3..b66975af164b9e9 100644 --- a/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider_a55.rst @@ -63,7 +63,7 @@ One of the ways to load Zephyr is shown below. tftp 0x48000000 booti 0x48000000 -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst index d7fec18e0366cc9..9c7be4d8f99b71b 100644 --- a/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider_r52.rst @@ -161,7 +161,7 @@ Debugging First of all, open your serial terminal. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/sc/scobc_module1/doc/index.rst b/boards/sc/scobc_module1/doc/index.rst index fd6f82e0b8e0c3b..260a062692f975c 100644 --- a/boards/sc/scobc_module1/doc/index.rst +++ b/boards/sc/scobc_module1/doc/index.rst @@ -73,7 +73,7 @@ Flashing Here is an example for building and flashing the \`hello\_world\` application for the board: -Here is an example for building and flashing the :ref:`hello_world` application +Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application for the default design: .. zephyr-app-commands:: @@ -94,7 +94,7 @@ above steps. It was merely written to internal RAM in the FPGA. Debugging ========= -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seco/stm32f3_seco_d23/doc/index.rst b/boards/seco/stm32f3_seco_d23/doc/index.rst index 17be6bcd6f80938..bc2626767f0598e 100644 --- a/boards/seco/stm32f3_seco_d23/doc/index.rst +++ b/boards/seco/stm32f3_seco_d23/doc/index.rst @@ -208,7 +208,7 @@ The pinout is (1-8): Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst index 8d96f1e53471637..ca2342107348088 100644 --- a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst +++ b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst @@ -242,7 +242,7 @@ Flashing an application to LoRa-E5 Dev board Connect the LoRa-E5 to your host computer using the external debug probe. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your board: Per default the console on ``usart1`` is available on the USB Type C connector diff --git a/boards/seeed/lora_e5_mini/doc/index.rst b/boards/seeed/lora_e5_mini/doc/index.rst index 7f36a92e7d6f155..78227fcb62bfed0 100644 --- a/boards/seeed/lora_e5_mini/doc/index.rst +++ b/boards/seeed/lora_e5_mini/doc/index.rst @@ -178,7 +178,7 @@ Flashing an application to LoRa-E5 mini Connect the LoRa-E5 to your host computer using the external debug probe. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your board: Per default the console on ``usart1`` is available on the USB Type C connector diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst index aa11b812c386c66..8f3614918f6fe9a 100644 --- a/boards/seeed/seeeduino_xiao/doc/index.rst +++ b/boards/seeed/seeeduino_xiao/doc/index.rst @@ -120,7 +120,7 @@ will be entered automatically when you run :code:`west flash`. Flashing ======== -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: +#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample application: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst index d91729dccd6daf7..c33d786e024158d 100644 --- a/boards/seeed/xiao_ble/doc/index.rst +++ b/boards/seeed/xiao_ble/doc/index.rst @@ -117,7 +117,7 @@ BlackMagic Probe). Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst index e8346632b961cc1..48ce9ddae0d6381 100644 --- a/boards/seeed/xiao_esp32c3/doc/index.rst +++ b/boards/seeed/xiao_esp32c3/doc/index.rst @@ -198,7 +198,7 @@ The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite t ``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` parameter when building. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -206,7 +206,7 @@ Here is an example for building the :ref:`hello_world` application. :goals: build flash :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/seeed/xiao_esp32s3/doc/index.rst b/boards/seeed/xiao_esp32s3/doc/index.rst index 7f830f65340934b..4c029bd5d645e7c 100644 --- a/boards/seeed/xiao_esp32s3/doc/index.rst +++ b/boards/seeed/xiao_esp32s3/doc/index.rst @@ -189,7 +189,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``xiao_esp32s3`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -220,14 +220,14 @@ ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additiona Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: xiao_esp32s3/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst index 14d176bd3560a75..67284c4b7822ca9 100644 --- a/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst +++ b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst @@ -98,7 +98,7 @@ Programming and Debugging Flashing ======== -The sample application :ref:`hello_world` is used for this example. Build the Zephyr kernel and +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/dev_kits/sltb004a/doc/index.rst b/boards/silabs/dev_kits/sltb004a/doc/index.rst index 8ee2b64604d06a0..e11145365fbaee8 100644 --- a/boards/silabs/dev_kits/sltb004a/doc/index.rst +++ b/boards/silabs/dev_kits/sltb004a/doc/index.rst @@ -165,7 +165,7 @@ board. The adaptor provides: Flashing an application to SLTB004A ----------------------------------- -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/dev_kits/sltb009a/doc/index.rst b/boards/silabs/dev_kits/sltb009a/doc/index.rst index 2ec7a83f3257447..9366a7d26499130 100644 --- a/boards/silabs/dev_kits/sltb009a/doc/index.rst +++ b/boards/silabs/dev_kits/sltb009a/doc/index.rst @@ -126,7 +126,7 @@ Flashing an application to SLTB009A Connect the SLTB009A to your host computer using the USB port. -Here is an example to build and flash the :ref:`hello_world` application. +Here is an example to build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/dev_kits/sltb010a/doc/index.rst b/boards/silabs/dev_kits/sltb010a/doc/index.rst index bbca08c762cda86..a335924359f471c 100644 --- a/boards/silabs/dev_kits/sltb010a/doc/index.rst +++ b/boards/silabs/dev_kits/sltb010a/doc/index.rst @@ -131,7 +131,7 @@ Flashing an application ----------------------- Connect your device to your host computer using the USB port. -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application, then flash it to the device: BRD4184A: diff --git a/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst index c5ec0f6a683a817..069b1d8923f12cb 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst +++ b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst @@ -124,7 +124,7 @@ Programming and Debugging Flashing ======== -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst index abaafbf0d2aad59..273b78e60ba5cb2 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst +++ b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst @@ -105,7 +105,7 @@ Commander in unattended mode and passes all the necessary arguments to it. Programming and Debugging ========================= -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/radio_boards/slwrb4104a/doc/index.rst b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst index 6522489e79ac6c5..3496421743c043b 100644 --- a/boards/silabs/radio_boards/slwrb4104a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst @@ -128,7 +128,7 @@ Flashing Connect the BRD4001A board with a mounted BRD4104A radio module to your host computer using the USB port. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/radio_boards/slwrb4161a/doc/index.rst b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst index 1f09e7d551c77ca..927e27c20ae1eef 100644 --- a/boards/silabs/radio_boards/slwrb4161a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst @@ -122,7 +122,7 @@ Flashing Connect the BRD4001A board with a mounted BRD4161A radio module to your host computer using the USB port. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/radio_boards/slwrb4170a/doc/index.rst b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst index b6a29d13ad1380f..ccc2b7248ea6a6c 100644 --- a/boards/silabs/radio_boards/slwrb4170a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst @@ -122,7 +122,7 @@ Flashing Connect the BRD4001A board with a mounted BRD4170A radio module to your host computer using the USB port. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/radio_boards/slwrb4180a/doc/index.rst b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst index 01864a54b1b3acf..057e8ec9b00447a 100644 --- a/boards/silabs/radio_boards/slwrb4180a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst @@ -119,7 +119,7 @@ Flashing Connect the BRD4001A board with a mounted BRD4180A radio module to your host computer using the USB port. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/radio_boards/slwrb4250b/doc/index.rst b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst index 59a38cf26f8be5d..7a865b5b5738ba9 100644 --- a/boards/silabs/radio_boards/slwrb4250b/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst @@ -126,7 +126,7 @@ Flashing Connect the BRD4001A board with a mounted BRD4250B radio module to your host computer using the USB port. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/radio_boards/slwrb4255a/doc/index.rst b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst index d7e303c13262c1f..43dd6e65aadf393 100644 --- a/boards/silabs/radio_boards/slwrb4255a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst @@ -122,7 +122,7 @@ Flashing Connect the BRD4001A board with a mounted BRD4255A radio module to your host computer using the USB port. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/radio_boards/slwrb4321a/doc/index.rst b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst index 1170205e1b8324f..50ec07b7f7989a0 100644 --- a/boards/silabs/radio_boards/slwrb4321a/doc/index.rst +++ b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst @@ -137,7 +137,7 @@ Flashing an application to SLWSTK6121A Connect the SLWSTK6121A to your host computer using the USB port. -Here is an example to build and flash the :ref:`hello_world` application. +Here is an example to build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst index 5100a4bf045cb03..82da55861ce5ba0 100644 --- a/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst +++ b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst @@ -120,7 +120,7 @@ Flashing Connect the BRD4002A board with a mounted BRD4187C radio module to your host computer using the USB port. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst index 139d89379b07e4f..0c04b7b21de0000 100644 --- a/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst +++ b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst @@ -125,7 +125,7 @@ board. The adaptor provides: Flashing an application to EFM32-STK3800 ---------------------------------------- -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/starter_kits/slstk3400a/doc/index.rst b/boards/silabs/starter_kits/slstk3400a/doc/index.rst index a48cc3f65faa767..7f3f919643bc26a 100644 --- a/boards/silabs/starter_kits/slstk3400a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3400a/doc/index.rst @@ -125,7 +125,7 @@ board. The adaptor provides: Flashing an application to EFM32-SLSTK3400A ------------------------------------------- -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/starter_kits/slstk3401a/doc/index.rst b/boards/silabs/starter_kits/slstk3401a/doc/index.rst index 2de4948e2175e4b..d1e41ade626af90 100644 --- a/boards/silabs/starter_kits/slstk3401a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3401a/doc/index.rst @@ -136,7 +136,7 @@ board. The adaptor provides: Flashing an application to SLSTK3401A ------------------------------------- -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/starter_kits/slstk3402a/doc/index.rst b/boards/silabs/starter_kits/slstk3402a/doc/index.rst index 8d6193e85cdc7d3..4e5293ee08f1c16 100644 --- a/boards/silabs/starter_kits/slstk3402a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3402a/doc/index.rst @@ -159,7 +159,7 @@ board. The adaptor provides: Flashing an application to SLSTK3402A ------------------------------------- -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/silabs/starter_kits/slstk3701a/doc/index.rst b/boards/silabs/starter_kits/slstk3701a/doc/index.rst index d270bf346c240d7..6209984049eea6d 100644 --- a/boards/silabs/starter_kits/slstk3701a/doc/index.rst +++ b/boards/silabs/starter_kits/slstk3701a/doc/index.rst @@ -148,7 +148,7 @@ board. The adaptor provides: Flashing an application to SLSTK3701A ------------------------------------- -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/snps/em_starterkit/doc/index.rst b/boards/snps/em_starterkit/doc/index.rst index 4390ab2e4c6348d..e569031e37805a7 100644 --- a/boards/snps/em_starterkit/doc/index.rst +++ b/boards/snps/em_starterkit/doc/index.rst @@ -173,7 +173,7 @@ Building Sample Applications ============================== You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. +the one called :zephyr:code-sample:`hello_world`. It is found in :zephyr_file:`samples/hello_world`. Configuring @@ -201,7 +201,7 @@ Building You can build application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: em_starterkit diff --git a/boards/snps/emsdp/doc/index.rst b/boards/snps/emsdp/doc/index.rst index fa4606d98f89e1b..bad8a48e4bbb279 100644 --- a/boards/snps/emsdp/doc/index.rst +++ b/boards/snps/emsdp/doc/index.rst @@ -161,7 +161,7 @@ Building Sample Applications ============================== You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. +the one called :zephyr:code-sample:`hello_world`. It is found in :zephyr_file:`samples/hello_world`. Configuring @@ -184,7 +184,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world` for the em4. +:zephyr:code-sample:`hello_world` for the em4. .. zephyr-app-commands:: :board: emsdp/emsdp_em4 diff --git a/boards/snps/hsdk/doc/index.rst b/boards/snps/hsdk/doc/index.rst index 5d5fb1aa521c1c1..a7165a27658ce41 100644 --- a/boards/snps/hsdk/doc/index.rst +++ b/boards/snps/hsdk/doc/index.rst @@ -388,7 +388,7 @@ Building Sample Applications ============================== You can try many of the :ref:`sample applications and demos -`. We'll use :ref:`hello_world`, found in +`. We'll use :zephyr:code-sample:`hello_world`, found in :zephyr_file:`samples/hello_world` as an example. Configuring @@ -410,7 +410,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: hsdk diff --git a/boards/snps/hsdk4xd/doc/index.rst b/boards/snps/hsdk4xd/doc/index.rst index b373f22cee319e3..a5cfd534c00400b 100644 --- a/boards/snps/hsdk4xd/doc/index.rst +++ b/boards/snps/hsdk4xd/doc/index.rst @@ -385,7 +385,7 @@ Building Sample Applications ============================== You can try many of the :ref:`sample applications and demos -`. We'll use :ref:`hello_world`, found in +`. We'll use :zephyr:code-sample:`hello_world`, found in :zephyr_file:`samples/hello_world` as an example. Configuring @@ -407,7 +407,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: hsdk4xd diff --git a/boards/snps/iotdk/doc/index.rst b/boards/snps/iotdk/doc/index.rst index 8057e851b6645cb..5482bed17d938cb 100644 --- a/boards/snps/iotdk/doc/index.rst +++ b/boards/snps/iotdk/doc/index.rst @@ -68,7 +68,7 @@ Building Sample Applications ============================== You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. +the one called :zephyr:code-sample:`hello_world`. It is found in :zephyr_file:`samples/hello_world`. Configuring @@ -90,7 +90,7 @@ Building You can build an application in the usual way. Refer to :ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :board: iotdk diff --git a/boards/sparkfun/micromod/doc/index.rst b/boards/sparkfun/micromod/doc/index.rst index 294441f66d70dff..507ef52e4268891 100644 --- a/boards/sparkfun/micromod/doc/index.rst +++ b/boards/sparkfun/micromod/doc/index.rst @@ -142,7 +142,7 @@ The flashing tool will depend on the carrier used along with the board. In the case of `Sparkfun asset tracking carrier`_, it is possible to use the SWD interface along with a J-Link. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/sparkfun/thing_plus/doc/index.rst b/boards/sparkfun/thing_plus/doc/index.rst index 1e9994eb0ffc0a3..802c77ffb1a822a 100644 --- a/boards/sparkfun/thing_plus/doc/index.rst +++ b/boards/sparkfun/thing_plus/doc/index.rst @@ -92,7 +92,7 @@ In most cases you'll want to use the ``ns`` target with any of the Zephyr or Nordic based examples. Some of the examples do not use secure mode, so they do not required the ``ns`` suffix. -A great example of this is the :ref:`hello_world` below. +A great example of this is the :zephyr:code-sample:`hello_world` below. Flashing ======== @@ -103,7 +103,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst b/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst index f9ffd1f62020624..cdaed771bd8baf4 100644 --- a/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst +++ b/boards/sparkfun/thing_plus_matter_mgm240p/doc/index.rst @@ -105,7 +105,7 @@ Programming and Debugging Flashing ======== -The sample application :ref:`hello_world` is used for this example. +The sample application :zephyr:code-sample:`hello_world` is used for this example. Build the Zephyr kernel and application: .. zephyr-app-commands:: diff --git a/boards/st/b_g474e_dpow1/doc/index.rst b/boards/st/b_g474e_dpow1/doc/index.rst index 39f7bf045aa21d3..7e1f584b5221d2e 100644 --- a/boards/st/b_g474e_dpow1/doc/index.rst +++ b/boards/st/b_g474e_dpow1/doc/index.rst @@ -137,7 +137,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/b_l072z_lrwan1/doc/index.rst b/boards/st/b_l072z_lrwan1/doc/index.rst index 87a98d67910c96c..527461c24a44b11 100644 --- a/boards/st/b_l072z_lrwan1/doc/index.rst +++ b/boards/st/b_l072z_lrwan1/doc/index.rst @@ -214,7 +214,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to B-L072Z-LRWAN1 Discovery board --------------------------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the B-L072Z-LRWAN1 Discovery board to a STLinkV2 to your host computer using the USB port, then run a serial host program to connect with your board. For example: @@ -240,7 +240,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/b_l4s5i_iot01a/doc/index.rst b/boards/st/b_l4s5i_iot01a/doc/index.rst index b66df638cd5570c..fb1620c672d6cf9 100644 --- a/boards/st/b_l4s5i_iot01a/doc/index.rst +++ b/boards/st/b_l4s5i_iot01a/doc/index.rst @@ -205,7 +205,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -222,7 +222,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst index f09b6f3dc2e977d..2400f75e3d172a9 100644 --- a/boards/st/b_u585i_iot02a/doc/index.rst +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -317,7 +317,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/disco_l475_iot1/doc/index.rst b/boards/st/disco_l475_iot1/doc/index.rst index a5ba3b59978823e..197881078a31b5a 100644 --- a/boards/st/disco_l475_iot1/doc/index.rst +++ b/boards/st/disco_l475_iot1/doc/index.rst @@ -216,7 +216,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Disco L475 IoT ----------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Connect the Disco L475 IoT to your host computer using the USB port, then run a serial host program to connect with your Nucleo board. For example: @@ -242,7 +242,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f070rb/doc/index.rst b/boards/st/nucleo_f070rb/doc/index.rst index b017b2186993e19..acecfb20979375e 100644 --- a/boards/st/nucleo_f070rb/doc/index.rst +++ b/boards/st/nucleo_f070rb/doc/index.rst @@ -169,7 +169,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f091rc/doc/index.rst b/boards/st/nucleo_f091rc/doc/index.rst index 38cb5e6c38b6574..2cce144c1fbccda 100644 --- a/boards/st/nucleo_f091rc/doc/index.rst +++ b/boards/st/nucleo_f091rc/doc/index.rst @@ -186,7 +186,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f401re/doc/index.rst b/boards/st/nucleo_f401re/doc/index.rst index ceb25368d571a5c..123992ac18b70e7 100644 --- a/boards/st/nucleo_f401re/doc/index.rst +++ b/boards/st/nucleo_f401re/doc/index.rst @@ -179,7 +179,7 @@ then run a serial host program to connect with your Nucleo board: $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -197,7 +197,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f410rb/doc/index.rst b/boards/st/nucleo_f410rb/doc/index.rst index f260608dafbf5e7..af87b501923aa72 100644 --- a/boards/st/nucleo_f410rb/doc/index.rst +++ b/boards/st/nucleo_f410rb/doc/index.rst @@ -176,7 +176,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo F410RB ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -201,7 +201,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f411re/doc/index.rst b/boards/st/nucleo_f411re/doc/index.rst index fb6cf4ecba954cd..e4c10085d9bca21 100644 --- a/boards/st/nucleo_f411re/doc/index.rst +++ b/boards/st/nucleo_f411re/doc/index.rst @@ -164,7 +164,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo F411RE ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -189,7 +189,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f446re/doc/index.rst b/boards/st/nucleo_f446re/doc/index.rst index 49748acbde0185d..e111880ef32315d 100644 --- a/boards/st/nucleo_f446re/doc/index.rst +++ b/boards/st/nucleo_f446re/doc/index.rst @@ -187,7 +187,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo F446RE ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -212,7 +212,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f446ze/doc/index.rst b/boards/st/nucleo_f446ze/doc/index.rst index 676da09ebb74c4b..0029f016ccf7104 100644 --- a/boards/st/nucleo_f446ze/doc/index.rst +++ b/boards/st/nucleo_f446ze/doc/index.rst @@ -212,7 +212,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo F446ZE ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -237,7 +237,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f722ze/doc/index.rst b/boards/st/nucleo_f722ze/doc/index.rst index 37d3237d2604468..fde339622a82747 100644 --- a/boards/st/nucleo_f722ze/doc/index.rst +++ b/boards/st/nucleo_f722ze/doc/index.rst @@ -201,7 +201,7 @@ the ``--runner`` (or ``-r``) option: $ west flash --runner openocd $ west flash --runner jlink -Build the :ref:`hello_world` application and flash it using the on-board +Build the :zephyr:code-sample:`hello_world` application and flash it using the on-board ST-LINK interface: .. zephyr-app-commands:: diff --git a/boards/st/nucleo_f746zg/doc/index.rst b/boards/st/nucleo_f746zg/doc/index.rst index c4d4a0f9fc1d25d..59566cf34c7f0a7 100644 --- a/boards/st/nucleo_f746zg/doc/index.rst +++ b/boards/st/nucleo_f746zg/doc/index.rst @@ -202,7 +202,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo F746ZG ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -227,7 +227,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f756zg/doc/index.rst b/boards/st/nucleo_f756zg/doc/index.rst index 371464038d39299..6d512dcca375954 100644 --- a/boards/st/nucleo_f756zg/doc/index.rst +++ b/boards/st/nucleo_f756zg/doc/index.rst @@ -183,7 +183,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo F756ZG ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -208,7 +208,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_f767zi/doc/index.rst b/boards/st/nucleo_f767zi/doc/index.rst index 87c08558518e3d3..e0b500501519409 100644 --- a/boards/st/nucleo_f767zi/doc/index.rst +++ b/boards/st/nucleo_f767zi/doc/index.rst @@ -203,7 +203,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo F767ZI ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -228,7 +228,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_g031k8/doc/index.rst b/boards/st/nucleo_g031k8/doc/index.rst index 29ecc49cdff939c..c3776071ee24849 100644 --- a/boards/st/nucleo_g031k8/doc/index.rst +++ b/boards/st/nucleo_g031k8/doc/index.rst @@ -146,7 +146,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_g070rb/doc/index.rst b/boards/st/nucleo_g070rb/doc/index.rst index 055b11b5c1026f7..87b8cef25af3893 100644 --- a/boards/st/nucleo_g070rb/doc/index.rst +++ b/boards/st/nucleo_g070rb/doc/index.rst @@ -180,7 +180,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_g071rb/doc/index.rst b/boards/st/nucleo_g071rb/doc/index.rst index 0dc30a94049b4ae..2202157b6cd69dd 100644 --- a/boards/st/nucleo_g071rb/doc/index.rst +++ b/boards/st/nucleo_g071rb/doc/index.rst @@ -186,7 +186,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_g0b1re/doc/index.rst b/boards/st/nucleo_g0b1re/doc/index.rst index ba5f8600558e82c..3a32623a82ea13e 100644 --- a/boards/st/nucleo_g0b1re/doc/index.rst +++ b/boards/st/nucleo_g0b1re/doc/index.rst @@ -192,7 +192,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_g431rb/doc/index.rst b/boards/st/nucleo_g431rb/doc/index.rst index 9d87f2f41d25468..62805c011cde802 100644 --- a/boards/st/nucleo_g431rb/doc/index.rst +++ b/boards/st/nucleo_g431rb/doc/index.rst @@ -222,7 +222,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -240,7 +240,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_g474re/doc/index.rst b/boards/st/nucleo_g474re/doc/index.rst index e4dc198a9d4c123..8ef04ed8fa19e2d 100644 --- a/boards/st/nucleo_g474re/doc/index.rst +++ b/boards/st/nucleo_g474re/doc/index.rst @@ -229,7 +229,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -247,7 +247,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_h503rb/doc/index.rst b/boards/st/nucleo_h503rb/doc/index.rst index e8ab73b8cb5b4a3..ed7133cb5b177fb 100644 --- a/boards/st/nucleo_h503rb/doc/index.rst +++ b/boards/st/nucleo_h503rb/doc/index.rst @@ -242,7 +242,7 @@ Flashing an application to Nucleo-H503RB Connect the Nucleo-H503RB to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_h533re/doc/index.rst b/boards/st/nucleo_h533re/doc/index.rst index eec0ad90721ca37..428f79b83c266d4 100644 --- a/boards/st/nucleo_h533re/doc/index.rst +++ b/boards/st/nucleo_h533re/doc/index.rst @@ -293,7 +293,7 @@ Flashing an application to Nucleo H533RE Connect the Nucleo H533RE to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst index f448483fb54c629..8bbb099147e0724 100644 --- a/boards/st/nucleo_h563zi/doc/index.rst +++ b/boards/st/nucleo_h563zi/doc/index.rst @@ -307,7 +307,7 @@ Flashing an application to Nucleo H563ZI Connect the Nucleo H563ZI to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_h723zg/doc/index.rst b/boards/st/nucleo_h723zg/doc/index.rst index 1e364d882631b10..5e97327386d6c01 100644 --- a/boards/st/nucleo_h723zg/doc/index.rst +++ b/boards/st/nucleo_h723zg/doc/index.rst @@ -197,7 +197,7 @@ Flashing an application to Nucleo H723ZG First, connect the NUCLEO-H723ZG to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your NUCLEO-H723ZG board. @@ -235,7 +235,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_h743zi/doc/index.rst b/boards/st/nucleo_h743zi/doc/index.rst index 403f356b862c684..2a790927bfc1b21 100644 --- a/boards/st/nucleo_h743zi/doc/index.rst +++ b/boards/st/nucleo_h743zi/doc/index.rst @@ -208,7 +208,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo H743ZI ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -233,7 +233,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst index 35e9dd2fbb1b040..c0e5d3db722164f 100644 --- a/boards/st/nucleo_h745zi_q/doc/index.rst +++ b/boards/st/nucleo_h745zi_q/doc/index.rst @@ -220,7 +220,7 @@ Flashing an application to STM32H745ZI M7 Core First, connect the NUCLEO-H745ZI-Q to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your NUCLEO-H745ZI-Q board. @@ -270,7 +270,7 @@ Debugging ========= You can debug an application on Cortex M7 side in the usual way. Here is an example -for the :ref:`hello_world` application. +for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_h753zi/doc/index.rst b/boards/st/nucleo_h753zi/doc/index.rst index d03b6c1b5e781a8..e9af66a323260c9 100644 --- a/boards/st/nucleo_h753zi/doc/index.rst +++ b/boards/st/nucleo_h753zi/doc/index.rst @@ -192,7 +192,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo H753ZI ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -217,7 +217,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_h755zi_q/doc/index.rst b/boards/st/nucleo_h755zi_q/doc/index.rst index d511cb1d7db9be9..3d509cc90ba352c 100644 --- a/boards/st/nucleo_h755zi_q/doc/index.rst +++ b/boards/st/nucleo_h755zi_q/doc/index.rst @@ -209,7 +209,7 @@ Flashing an application to STM32H755ZI M7 Core First, connect the NUCLEO-H755ZI-Q to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your NUCLEO-H755ZI-Q board. @@ -259,7 +259,7 @@ Debugging ========= You can debug an application on the Cortex M7 core in the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_h7a3zi_q/doc/index.rst b/boards/st/nucleo_h7a3zi_q/doc/index.rst index 1683e04d87a6ce1..0de0ef109eb8258 100644 --- a/boards/st/nucleo_h7a3zi_q/doc/index.rst +++ b/boards/st/nucleo_h7a3zi_q/doc/index.rst @@ -171,7 +171,7 @@ the ``--runner`` (or ``-r``) option: Flashing an application to Nucleo H7A3ZI-Q ------------------------------------------ -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -196,7 +196,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l011k4/doc/index.rst b/boards/st/nucleo_l011k4/doc/index.rst index 7e13a9040a7bbb3..b1d9396f7ed7693 100644 --- a/boards/st/nucleo_l011k4/doc/index.rst +++ b/boards/st/nucleo_l011k4/doc/index.rst @@ -154,7 +154,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l031k6/doc/index.rst b/boards/st/nucleo_l031k6/doc/index.rst index 2b1a32321280f52..0845a046fc04ca5 100644 --- a/boards/st/nucleo_l031k6/doc/index.rst +++ b/boards/st/nucleo_l031k6/doc/index.rst @@ -147,7 +147,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l053r8/doc/index.rst b/boards/st/nucleo_l053r8/doc/index.rst index 101d4c80d64cd3d..4fd63f57f4384f5 100644 --- a/boards/st/nucleo_l053r8/doc/index.rst +++ b/boards/st/nucleo_l053r8/doc/index.rst @@ -163,7 +163,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l073rz/doc/index.rst b/boards/st/nucleo_l073rz/doc/index.rst index 70c49d66b719e67..6ea4076a98a2684 100644 --- a/boards/st/nucleo_l073rz/doc/index.rst +++ b/boards/st/nucleo_l073rz/doc/index.rst @@ -179,7 +179,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l152re/doc/index.rst b/boards/st/nucleo_l152re/doc/index.rst index 29a7cab6ac61b7b..c4d18190a23aee1 100644 --- a/boards/st/nucleo_l152re/doc/index.rst +++ b/boards/st/nucleo_l152re/doc/index.rst @@ -172,7 +172,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l412rb_p/doc/index.rst b/boards/st/nucleo_l412rb_p/doc/index.rst index 97d998d84542246..11a12390782354a 100644 --- a/boards/st/nucleo_l412rb_p/doc/index.rst +++ b/boards/st/nucleo_l412rb_p/doc/index.rst @@ -239,7 +239,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -257,7 +257,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l432kc/doc/index.rst b/boards/st/nucleo_l432kc/doc/index.rst index b54031aaa627be9..f312380a07c3253 100644 --- a/boards/st/nucleo_l432kc/doc/index.rst +++ b/boards/st/nucleo_l432kc/doc/index.rst @@ -199,7 +199,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -217,7 +217,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l433rc_p/doc/index.rst b/boards/st/nucleo_l433rc_p/doc/index.rst index 9269652973b3dd7..75b3a8fe20ebcf0 100644 --- a/boards/st/nucleo_l433rc_p/doc/index.rst +++ b/boards/st/nucleo_l433rc_p/doc/index.rst @@ -204,7 +204,7 @@ then run a serial host program to connect with your Nucleo board. $ picocom /dev/ttyACM0 -b 115200 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -222,7 +222,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l452re/doc/index.rst b/boards/st/nucleo_l452re/doc/index.rst index 26ff761d06caf09..9587b9e6c02eea1 100644 --- a/boards/st/nucleo_l452re/doc/index.rst +++ b/boards/st/nucleo_l452re/doc/index.rst @@ -223,7 +223,7 @@ then run a serial host program to connect with your Nucleo board. $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,7 +248,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l476rg/doc/index.rst b/boards/st/nucleo_l476rg/doc/index.rst index 2e1557e22efacbe..ac566003430cf8d 100644 --- a/boards/st/nucleo_l476rg/doc/index.rst +++ b/boards/st/nucleo_l476rg/doc/index.rst @@ -206,7 +206,7 @@ Flashing an application to Nucleo L476RG Connect the Nucleo L476RG to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -231,7 +231,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l496zg/doc/index.rst b/boards/st/nucleo_l496zg/doc/index.rst index cc95df28dd7f73b..4abdc105c6a6db6 100644 --- a/boards/st/nucleo_l496zg/doc/index.rst +++ b/boards/st/nucleo_l496zg/doc/index.rst @@ -209,7 +209,7 @@ Flashing an application to Nucleo L496ZG Connect the Nucleo L496ZG to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -234,7 +234,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l4a6zg/doc/index.rst b/boards/st/nucleo_l4a6zg/doc/index.rst index 428ece2b645a48e..267d5f619b803e7 100644 --- a/boards/st/nucleo_l4a6zg/doc/index.rst +++ b/boards/st/nucleo_l4a6zg/doc/index.rst @@ -206,7 +206,7 @@ Flashing an application to Nucleo L4A6ZG Connect the Nucleo L4A6ZG to your host computer using the ST-LINK USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -231,7 +231,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_l4r5zi/doc/index.rst b/boards/st/nucleo_l4r5zi/doc/index.rst index 7de08708650ca57..1a1302aa3e2d2b7 100644 --- a/boards/st/nucleo_l4r5zi/doc/index.rst +++ b/boards/st/nucleo_l4r5zi/doc/index.rst @@ -243,7 +243,7 @@ Flashing an application to Nucleo L4R4ZI Connect the Nucleo L4R5ZI to your host computer using the USB port. Then build and flash an application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst index 79a91fe52013267..0d5aa6e0fd87385 100644 --- a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst +++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst @@ -315,7 +315,7 @@ Flashing an application to Nucleo L552ZE Q Connect the Nucleo L552ZE Q to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -340,7 +340,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_u031r8/doc/index.rst b/boards/st/nucleo_u031r8/doc/index.rst index 869149fc0670156..9df168c0fad291b 100644 --- a/boards/st/nucleo_u031r8/doc/index.rst +++ b/boards/st/nucleo_u031r8/doc/index.rst @@ -211,7 +211,7 @@ Flashing an application to Nucleo U031R8 Connect the Nucleo U031R8 to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_u083rc/doc/index.rst b/boards/st/nucleo_u083rc/doc/index.rst index 467894ab724b0f6..dd6e3db0e837520 100644 --- a/boards/st/nucleo_u083rc/doc/index.rst +++ b/boards/st/nucleo_u083rc/doc/index.rst @@ -227,7 +227,7 @@ Flashing an application to Nucleo U083RC Connect the Nucleo U083RC to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_u575zi_q/doc/index.rst b/boards/st/nucleo_u575zi_q/doc/index.rst index 1852246f0699047..080bd074c4f0221 100644 --- a/boards/st/nucleo_u575zi_q/doc/index.rst +++ b/boards/st/nucleo_u575zi_q/doc/index.rst @@ -273,7 +273,7 @@ Flashing an application to Nucleo U575ZI Q Connect the Nucleo U575ZI Q to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst index 47b36fce8addef3..d3f90a178d40b50 100644 --- a/boards/st/nucleo_u5a5zj_q/doc/index.rst +++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst @@ -305,7 +305,7 @@ Flashing an application to Nucleo U5A5ZJ Q Connect the Nucleo U5A5ZJ Q to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_wb05kz/doc/index.rst b/boards/st/nucleo_wb05kz/doc/index.rst index b7434039c7277a2..7d242549ffe4e44 100644 --- a/boards/st/nucleo_wb05kz/doc/index.rst +++ b/boards/st/nucleo_wb05kz/doc/index.rst @@ -110,7 +110,7 @@ then run a serial host program to connect with your Nucleo board: $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -128,7 +128,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_wb09ke/doc/index.rst b/boards/st/nucleo_wb09ke/doc/index.rst index af6a5f7d0277a9d..9e4ce9eb7286bee 100644 --- a/boards/st/nucleo_wb09ke/doc/index.rst +++ b/boards/st/nucleo_wb09ke/doc/index.rst @@ -110,7 +110,7 @@ then run a serial host program to connect with your Nucleo board: $ minicom -D /dev/ttyACM0 Now build and flash an application. Here is an example for -:ref:`hello_world`. +:zephyr:code-sample:`hello_world`. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -128,7 +128,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst index 3a97a2bfc90efd8..fb1b76e76ca337a 100644 --- a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst +++ b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst @@ -274,7 +274,7 @@ Flashing an application to Nucleo WB55RG Connect the Nucleo WB55RG to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst index ca0276ebb0072d5..98ce41d587723a3 100644 --- a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst +++ b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst @@ -282,7 +282,7 @@ Flashing an application to Nucleo WL55JC Connect the Nucleo WL55JC to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/st25dv_mb1283_disco/docs/index.rst b/boards/st/st25dv_mb1283_disco/docs/index.rst index 03acec44fc56a70..1fef60ebf63a900 100644 --- a/boards/st/st25dv_mb1283_disco/docs/index.rst +++ b/boards/st/st25dv_mb1283_disco/docs/index.rst @@ -101,7 +101,7 @@ Flashing an application to ST25DV Discovery First, connect the ST25DV Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -124,7 +124,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/steval_fcu001v1/doc/index.rst b/boards/st/steval_fcu001v1/doc/index.rst index a76f99c6e01cd7f..f10c0300957e2b4 100644 --- a/boards/st/steval_fcu001v1/doc/index.rst +++ b/boards/st/steval_fcu001v1/doc/index.rst @@ -123,7 +123,7 @@ program to connect with your steval_fcu001v1 via the FT232 board: $ minicom -D /dev/ttyUSB0 -Now build and flash an application. Here is an example for :ref:`hello_world` +Now build and flash an application. Here is an example for :zephyr:code-sample:`hello_world` .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -140,7 +140,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm3210c_eval/doc/index.rst b/boards/st/stm3210c_eval/doc/index.rst index 383a0e2f5fbde89..117e378b659f7fa 100644 --- a/boards/st/stm3210c_eval/doc/index.rst +++ b/boards/st/stm3210c_eval/doc/index.rst @@ -145,7 +145,7 @@ example, on Linux: $ minicom -D /dev/ttyACM0 You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32c0116_dk/doc/index.rst b/boards/st/stm32c0116_dk/doc/index.rst index 98276b3494611af..52e3c24ef208bbc 100644 --- a/boards/st/stm32c0116_dk/doc/index.rst +++ b/boards/st/stm32c0116_dk/doc/index.rst @@ -131,7 +131,7 @@ Flashing an application to STM32C0116-DK First, connect the STM32C0116 Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f072b_disco/doc/index.rst b/boards/st/stm32f072b_disco/doc/index.rst index 6ce491e362102f2..6f97341d2b37a18 100644 --- a/boards/st/stm32f072b_disco/doc/index.rst +++ b/boards/st/stm32f072b_disco/doc/index.rst @@ -170,7 +170,7 @@ Flashing an application to STM32F072B-DISCO First, connect the STM32F072B-DISCO Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -198,7 +198,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f3_disco/doc/index.rst b/boards/st/stm32f3_disco/doc/index.rst index 4ad79931ba93712..e557eb013c7df35 100644 --- a/boards/st/stm32f3_disco/doc/index.rst +++ b/boards/st/stm32f3_disco/doc/index.rst @@ -228,7 +228,7 @@ Flashing an application to STM32F3DISCOVERY First, connect the STM32F3DISCOVERY Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -266,7 +266,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f412g_disco/doc/index.rst b/boards/st/stm32f412g_disco/doc/index.rst index 28a5499d878178e..ae84de7cea784e7 100644 --- a/boards/st/stm32f412g_disco/doc/index.rst +++ b/boards/st/stm32f412g_disco/doc/index.rst @@ -172,7 +172,7 @@ board: $ minicom -D /dev/ttyACM0 Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -190,7 +190,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f429i_disc1/doc/index.rst b/boards/st/stm32f429i_disc1/doc/index.rst index c61cfcaa739855e..28a79e9ac2acb61 100644 --- a/boards/st/stm32f429i_disc1/doc/index.rst +++ b/boards/st/stm32f429i_disc1/doc/index.rst @@ -182,7 +182,7 @@ Alternatively, you can use `STM32CubeProgrammer`_ (after installing it) using th First, connect the STM32F429I-DISC1 Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -206,7 +206,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f469i_disco/doc/index.rst b/boards/st/stm32f469i_disco/doc/index.rst index 85ebec3778fbee6..549ffd4c67ec6a8 100644 --- a/boards/st/stm32f469i_disco/doc/index.rst +++ b/boards/st/stm32f469i_disco/doc/index.rst @@ -162,7 +162,7 @@ Flashing an application to STM32F469I-DISCO First, connect the STM32F469I-DISCO Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -186,7 +186,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f4_disco/doc/index.rst b/boards/st/stm32f4_disco/doc/index.rst index 128b84f31685040..e590250741abcca 100644 --- a/boards/st/stm32f4_disco/doc/index.rst +++ b/boards/st/stm32f4_disco/doc/index.rst @@ -199,7 +199,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f723e_disco/doc/index.rst b/boards/st/stm32f723e_disco/doc/index.rst index df2015192197cc9..755e87d4a12843f 100644 --- a/boards/st/stm32f723e_disco/doc/index.rst +++ b/boards/st/stm32f723e_disco/doc/index.rst @@ -158,7 +158,7 @@ Flashing an application to STM32F723E-DISCO First, connect the STM32F723E Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -181,7 +181,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f746g_disco/doc/index.rst b/boards/st/stm32f746g_disco/doc/index.rst index 7900c49436a94a7..7bd37aa26523b5f 100644 --- a/boards/st/stm32f746g_disco/doc/index.rst +++ b/boards/st/stm32f746g_disco/doc/index.rst @@ -209,7 +209,7 @@ Flashing an application to STM32F746G First, connect the STM32F746G Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -232,7 +232,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f7508_dk/doc/index.rst b/boards/st/stm32f7508_dk/doc/index.rst index 0ebde3c4fdc8c83..7a3c1c96c2200bf 100644 --- a/boards/st/stm32f7508_dk/doc/index.rst +++ b/boards/st/stm32f7508_dk/doc/index.rst @@ -204,7 +204,7 @@ Flashing an application to STM32F7508-DK First, connect the STM32F746G Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -227,7 +227,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32f769i_disco/doc/index.rst b/boards/st/stm32f769i_disco/doc/index.rst index 60edc99273fce08..210eb840ff07e70 100644 --- a/boards/st/stm32f769i_disco/doc/index.rst +++ b/boards/st/stm32f769i_disco/doc/index.rst @@ -191,7 +191,7 @@ Flashing an application to STM32F769I First, connect the STM32F769I Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -214,7 +214,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32g0316_disco/doc/index.rst b/boards/st/stm32g0316_disco/doc/index.rst index 401613763331d63..de6c2d91e554505 100644 --- a/boards/st/stm32g0316_disco/doc/index.rst +++ b/boards/st/stm32g0316_disco/doc/index.rst @@ -116,7 +116,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32g071b_disco/doc/index.rst b/boards/st/stm32g071b_disco/doc/index.rst index 9b1b3c230418ac8..e64a06d12135d79 100644 --- a/boards/st/stm32g071b_disco/doc/index.rst +++ b/boards/st/stm32g071b_disco/doc/index.rst @@ -147,7 +147,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32g081b_eval/doc/index.rst b/boards/st/stm32g081b_eval/doc/index.rst index 1bae82739c68b07..1f737c8daa109e8 100644 --- a/boards/st/stm32g081b_eval/doc/index.rst +++ b/boards/st/stm32g081b_eval/doc/index.rst @@ -185,7 +185,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst index 5fad2280266bfc6..86190a77deda7fb 100644 --- a/boards/st/stm32h573i_dk/doc/index.rst +++ b/boards/st/stm32h573i_dk/doc/index.rst @@ -298,7 +298,7 @@ Flashing an application to STM32H573I-DK Discovery Connect the STM32H573I-DK Discovery to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -331,7 +331,7 @@ requires to enable "pack" support with the following pyOCD command: $ pyocd pack --install stm32h5 Once installed, you can debug an application in the usual way. Here is an -example for the :ref:`hello_world` application. +example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h735g_disco/doc/index.rst b/boards/st/stm32h735g_disco/doc/index.rst index ae14832ea21684f..3ec250bb4e849f7 100644 --- a/boards/st/stm32h735g_disco/doc/index.rst +++ b/boards/st/stm32h735g_disco/doc/index.rst @@ -140,7 +140,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h745i_disco/doc/index.rst b/boards/st/stm32h745i_disco/doc/index.rst index 2c5fc70dd3465c4..c5b0ef79276cc3d 100644 --- a/boards/st/stm32h745i_disco/doc/index.rst +++ b/boards/st/stm32h745i_disco/doc/index.rst @@ -195,7 +195,7 @@ Flashing an application to STM32H745XI M7 Core First, connect the STM32H745I-DISCO to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your STM32H745I-DISCO board. @@ -245,7 +245,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h747i_disco/doc/index.rst b/boards/st/stm32h747i_disco/doc/index.rst index 3af51370885cac9..4f7a345ccc4d800 100644 --- a/boards/st/stm32h747i_disco/doc/index.rst +++ b/boards/st/stm32h747i_disco/doc/index.rst @@ -260,7 +260,7 @@ Flashing an application to STM32H747I M7 Core First, connect the STM32H747I Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -297,7 +297,7 @@ Debugging ========= You can debug an application on Cortex M7 side in the usual way. Here is an example -for the :ref:`hello_world` application. +for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h750b_dk/doc/index.rst b/boards/st/stm32h750b_dk/doc/index.rst index e450488ed4d39ee..3e2cd3d009eb7f5 100644 --- a/boards/st/stm32h750b_dk/doc/index.rst +++ b/boards/st/stm32h750b_dk/doc/index.rst @@ -110,7 +110,7 @@ USB port, then run a serial host program to connect with the board. For example: $ minicom -b 115200 -D /dev/ttyACM0 You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -128,7 +128,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h7b3i_dk/doc/index.rst b/boards/st/stm32h7b3i_dk/doc/index.rst index ff6f833fa8c1eda..954f4342d56ecbe 100644 --- a/boards/st/stm32h7b3i_dk/doc/index.rst +++ b/boards/st/stm32h7b3i_dk/doc/index.rst @@ -225,7 +225,7 @@ Flashing an application to STM32H7B3I First, connect the STM32H7B3I Discovery kit to your host computer using the USB port to prepare it for flashing. Then build and flash your application. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -248,7 +248,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32h7s78_dk/doc/index.rst b/boards/st/stm32h7s78_dk/doc/index.rst index 62c059cf0ec54c2..2352fde0fc9c925 100644 --- a/boards/st/stm32h7s78_dk/doc/index.rst +++ b/boards/st/stm32h7s78_dk/doc/index.rst @@ -257,7 +257,7 @@ Flashing an application to STM32H7S78-DK Discovery Connect the STM32H7S78-DK Discovery to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -282,7 +282,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32l476g_disco/doc/index.rst b/boards/st/stm32l476g_disco/doc/index.rst index 91695acae20969d..94a6e9ce24f1425 100644 --- a/boards/st/stm32l476g_disco/doc/index.rst +++ b/boards/st/stm32l476g_disco/doc/index.rst @@ -190,7 +190,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -207,7 +207,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32l496g_disco/doc/index.rst b/boards/st/stm32l496g_disco/doc/index.rst index 22e575e4b11d75d..15461fb1a71bb9b 100644 --- a/boards/st/stm32l496g_disco/doc/index.rst +++ b/boards/st/stm32l496g_disco/doc/index.rst @@ -230,7 +230,7 @@ board. For example: $ minicom -D /dev/ttyACM0 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -247,7 +247,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32l4r9i_disco/doc/index.rst b/boards/st/stm32l4r9i_disco/doc/index.rst index 5d71a40633a44db..6fadc331d45ba98 100644 --- a/boards/st/stm32l4r9i_disco/doc/index.rst +++ b/boards/st/stm32l4r9i_disco/doc/index.rst @@ -122,7 +122,7 @@ USB port, then run a serial host program to connect with the board. For example: $ minicom -b 115200 -D /dev/ttyACM0 You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -140,7 +140,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst index 922c03cbebdbea3..55fd91a34fa7896 100644 --- a/boards/st/stm32l562e_dk/doc/index.rst +++ b/boards/st/stm32l562e_dk/doc/index.rst @@ -316,7 +316,7 @@ Flashing an application to STM32L562E-DK Discovery Connect the STM32L562E-DK Discovery to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: @@ -341,7 +341,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/st/stm32u083c_dk/doc/index.rst b/boards/st/stm32u083c_dk/doc/index.rst index ed6717a63ad8828..d2f098b6b60b80e 100644 --- a/boards/st/stm32u083c_dk/doc/index.rst +++ b/boards/st/stm32u083c_dk/doc/index.rst @@ -240,7 +240,7 @@ Flashing an application to STM32U083C_DK Connect the STM32U083C_DK to your host computer using the USB port. Then build and flash an application. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board: diff --git a/boards/st/stm32u5a9j_dk/doc/index.rst b/boards/st/stm32u5a9j_dk/doc/index.rst index 7e3d638fa3ead56..571ee80f334b116 100644 --- a/boards/st/stm32u5a9j_dk/doc/index.rst +++ b/boards/st/stm32u5a9j_dk/doc/index.rst @@ -154,7 +154,7 @@ board. For example: $ minicom -D /dev/ttyACM0 -b 115200 Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/tdk/robokit1/doc/index.rst b/boards/tdk/robokit1/doc/index.rst index ef65431b7e5a962..abc90a0a611b624 100644 --- a/boards/tdk/robokit1/doc/index.rst +++ b/boards/tdk/robokit1/doc/index.rst @@ -153,7 +153,7 @@ Flashing #. Connect the TDK RoboKit1 board to your host computer using the USB debug port (USB1), USB2 for a serial console, and remaining micro USB for - power. Then build and flash the :ref:`hello_world` application. + power. Then build and flash the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -166,7 +166,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc1352p1_launchxl/doc/index.rst b/boards/ti/cc1352p1_launchxl/doc/index.rst index a5f88cc19ffd6cc..b751b357307b3e9 100644 --- a/boards/ti/cc1352p1_launchxl/doc/index.rst +++ b/boards/ti/cc1352p1_launchxl/doc/index.rst @@ -168,7 +168,7 @@ Applications for the ``CC1352P LaunchPad`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -190,7 +190,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc1352p7_launchpad/doc/index.rst b/boards/ti/cc1352p7_launchpad/doc/index.rst index 8deae6e3104893d..2b7fbc12a2c6c37 100644 --- a/boards/ti/cc1352p7_launchpad/doc/index.rst +++ b/boards/ti/cc1352p7_launchpad/doc/index.rst @@ -168,7 +168,7 @@ Applications for the ``CC1352P7 LaunchPad`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -190,7 +190,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc1352r1_launchxl/doc/index.rst b/boards/ti/cc1352r1_launchxl/doc/index.rst index 0002b1e1c6f7995..2e7ed0ae2ff37d5 100644 --- a/boards/ti/cc1352r1_launchxl/doc/index.rst +++ b/boards/ti/cc1352r1_launchxl/doc/index.rst @@ -167,7 +167,7 @@ Applications for the ``CC1352R LaunchPad`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -189,7 +189,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc1352r_sensortag/doc/index.rst b/boards/ti/cc1352r_sensortag/doc/index.rst index c270e85fd57c310..4120f4934df83a0 100644 --- a/boards/ti/cc1352r_sensortag/doc/index.rst +++ b/boards/ti/cc1352r_sensortag/doc/index.rst @@ -188,7 +188,7 @@ Applications for the ``CC1352R SensorTag`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -214,7 +214,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/cc26x2r1_launchxl/doc/index.rst b/boards/ti/cc26x2r1_launchxl/doc/index.rst index 8177df13ae3aa3a..1f6a02d92ddf1c4 100644 --- a/boards/ti/cc26x2r1_launchxl/doc/index.rst +++ b/boards/ti/cc26x2r1_launchxl/doc/index.rst @@ -173,7 +173,7 @@ Applications for the ``CC26x2R LaunchPad`` board configuration can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. @@ -195,7 +195,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst index 78662d6b7ba9bb4..e59942416f98960 100644 --- a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst +++ b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst @@ -100,7 +100,7 @@ Flashing Follow the :ref:`getting_started` instructions for Zephyr application development. -For example, to build and flash the :ref:`hello_world` application for the +For example, to build and flash the :zephyr:code-sample:`hello_world` application for the MSP-EXP432P401R LaunchXL: .. zephyr-app-commands:: diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst index 98f03bf7dff106b..60252c236ebded8 100644 --- a/boards/ti/sk_am62/doc/index.rst +++ b/boards/ti/sk_am62/doc/index.rst @@ -94,7 +94,7 @@ The board can using remoteproc, and uses the OpenAMP resource table to accomplis The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. -To test the M4F core, we build the :ref:`hello_world` sample with the following command. +To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command. .. code-block:: console diff --git a/boards/toradex/verdin_imx8mp/doc/index.rst b/boards/toradex/verdin_imx8mp/doc/index.rst index de7751ff0e6843c..e59101fa212e857 100644 --- a/boards/toradex/verdin_imx8mp/doc/index.rst +++ b/boards/toradex/verdin_imx8mp/doc/index.rst @@ -251,7 +251,7 @@ Toradex Verdin iMX8M Plus SoM can be debugged by connecting an external JLink JT X56 debug connector and to the PC, or simply connecting a USB-C to X66 on the Verdin Development Board. Then, the application can be debugged using the usual way. -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/u-blox/ubx_bmd300eval/doc/index.rst b/boards/u-blox/ubx_bmd300eval/doc/index.rst index d1aea13208f32cb..d7043adf19e0e90 100644 --- a/boards/u-blox/ubx_bmd300eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd300eval/doc/index.rst @@ -348,7 +348,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd330eval/doc/index.rst b/boards/u-blox/ubx_bmd330eval/doc/index.rst index 3f065cfc6d2d1ba..63c1755edfd758c 100644 --- a/boards/u-blox/ubx_bmd330eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd330eval/doc/index.rst @@ -339,7 +339,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd340eval/doc/index.rst b/boards/u-blox/ubx_bmd340eval/doc/index.rst index 4e1fed4e8a1382c..8129bf36d4d9467 100644 --- a/boards/u-blox/ubx_bmd340eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd340eval/doc/index.rst @@ -408,7 +408,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd345eval/doc/index.rst b/boards/u-blox/ubx_bmd345eval/doc/index.rst index 0bcb1d201daa6ba..907370fb8a06a0b 100644 --- a/boards/u-blox/ubx_bmd345eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd345eval/doc/index.rst @@ -421,7 +421,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd360eval/doc/index.rst b/boards/u-blox/ubx_bmd360eval/doc/index.rst index 556620a17645cf0..f0fbf264f012fb3 100644 --- a/boards/u-blox/ubx_bmd360eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd360eval/doc/index.rst @@ -337,7 +337,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_bmd380eval/doc/index.rst b/boards/u-blox/ubx_bmd380eval/doc/index.rst index 1547cfc301ed9e7..e903b1ec125eebd 100644 --- a/boards/u-blox/ubx_bmd380eval/doc/index.rst +++ b/boards/u-blox/ubx_bmd380eval/doc/index.rst @@ -407,7 +407,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_evkannab1/doc/index.rst b/boards/u-blox/ubx_evkannab1/doc/index.rst index f464ab5265bf972..79606e292ae5e06 100644 --- a/boards/u-blox/ubx_evkannab1/doc/index.rst +++ b/boards/u-blox/ubx_evkannab1/doc/index.rst @@ -116,7 +116,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Open a terminal program to the USB Serial Port installed when connecting the board and listen for output. diff --git a/boards/u-blox/ubx_evkninab1/doc/index.rst b/boards/u-blox/ubx_evkninab1/doc/index.rst index 9073c223585dcaf..33dcecb2f00b3b4 100644 --- a/boards/u-blox/ubx_evkninab1/doc/index.rst +++ b/boards/u-blox/ubx_evkninab1/doc/index.rst @@ -124,7 +124,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Open a terminal program to the USB Serial Port installed when connecting the board and listen for output. diff --git a/boards/u-blox/ubx_evkninab3/doc/index.rst b/boards/u-blox/ubx_evkninab3/doc/index.rst index fb8b0159b34e1ab..d19f49ca704240b 100644 --- a/boards/u-blox/ubx_evkninab3/doc/index.rst +++ b/boards/u-blox/ubx_evkninab3/doc/index.rst @@ -223,7 +223,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/u-blox/ubx_evkninab4/doc/index.rst b/boards/u-blox/ubx_evkninab4/doc/index.rst index 5ad6289b590d906..ebb3ee05918d6b3 100644 --- a/boards/u-blox/ubx_evkninab4/doc/index.rst +++ b/boards/u-blox/ubx_evkninab4/doc/index.rst @@ -119,7 +119,7 @@ Flashing Build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details) -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Open a terminal program to the USB Serial Port installed when connecting the board and listen for output. diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst index d847f45505d62a6..20201b3a347f68d 100644 --- a/boards/vcc-gnd/yd_esp32/doc/index.rst +++ b/boards/vcc-gnd/yd_esp32/doc/index.rst @@ -213,7 +213,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and :goals: build The usual ``flash`` target will work with the ``yd_esp32`` board -configuration. Here is an example for the :ref:`hello_world` +configuration. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: @@ -278,14 +278,14 @@ to the external programmer (e.g. a Flyswatter2): Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32`_. -Here is an example for building the :ref:`hello_world` application. +Here is an example for building the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: yd_esp32/esp32/procpu :goals: build flash -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst index 5a5775cae1fe309..2b5e1794bd2553c 100644 --- a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst +++ b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst @@ -105,7 +105,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst index 92d74c00c99e2b5..b56bcdd093ddc1e 100644 --- a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst +++ b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst @@ -135,7 +135,7 @@ Testing the VBLUno51 with Zephyr: buttons, LEDs, UART, BLE Here are some sample applications that you can use to test different components on the VBLUno51 board: - * :ref:`hello_world` + * :zephyr:code-sample:`hello_world` * :zephyr:code-sample:`blinky` * :zephyr:code-sample:`button` * :zephyr:code-sample:`bluetooth_beacon` diff --git a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst index f534ae372057ee8..68a7c1b97c64055 100644 --- a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst +++ b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst @@ -87,7 +87,7 @@ See the :ref:`getting_started` for general information on setting up your development environment. You can build and flash applications in the usual way. Here is an -example for the :ref:`hello_world` application. +example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -100,7 +100,7 @@ Testing the VBLUno52 with Zephyr: buttons, LEDs, UART, BLE Here are some sample applications that you can use to test different components on the VBLUno52 board: -* :ref:`hello_world` +* :zephyr:code-sample:`hello_world` * :zephyr:code-sample:`blinky` * :zephyr:code-sample:`button` * :zephyr:code-sample:`bluetooth_beacon` diff --git a/boards/waveshare/nrf51_ble400/doc/index.rst b/boards/waveshare/nrf51_ble400/doc/index.rst index 3bfe06aa2042571..3d34f2f27f0b1c0 100644 --- a/boards/waveshare/nrf51_ble400/doc/index.rst +++ b/boards/waveshare/nrf51_ble400/doc/index.rst @@ -168,7 +168,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/waveshare/open103z/doc/index.rst b/boards/waveshare/open103z/doc/index.rst index 2cd9c7a6ac03ddf..773b60f202f830f 100644 --- a/boards/waveshare/open103z/doc/index.rst +++ b/boards/waveshare/open103z/doc/index.rst @@ -55,7 +55,7 @@ Flashing ======== Build and flash applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world @@ -66,7 +66,7 @@ Debugging ========= Debug applications as usual. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/boards/we/ophelia1ev/doc/index.rst b/boards/we/ophelia1ev/doc/index.rst index d64c32579a54312..908b0ce6889f949 100644 --- a/boards/we/ophelia1ev/doc/index.rst +++ b/boards/we/ophelia1ev/doc/index.rst @@ -82,7 +82,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/we/proteus2ev/doc/index.rst b/boards/we/proteus2ev/doc/index.rst index 5492b4159fee28c..19a7df8fbac9ec6 100644 --- a/boards/we/proteus2ev/doc/index.rst +++ b/boards/we/proteus2ev/doc/index.rst @@ -112,7 +112,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/we/proteus3ev/doc/index.rst b/boards/we/proteus3ev/doc/index.rst index dd6c5f47d6c071a..87180a801b4d5ca 100644 --- a/boards/we/proteus3ev/doc/index.rst +++ b/boards/we/proteus3ev/doc/index.rst @@ -114,7 +114,7 @@ found in :ref:`nordic_segger_flashing`. Then build and flash applications as usual (see :ref:`build_an_application` and :ref:`application_run` for more details). -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, run your favorite terminal program to listen for output. diff --git a/boards/weact/mini_stm32h743/doc/index.rst b/boards/weact/mini_stm32h743/doc/index.rst index 4a96538ac1b23f0..9b63292ad572518 100644 --- a/boards/weact/mini_stm32h743/doc/index.rst +++ b/boards/weact/mini_stm32h743/doc/index.rst @@ -168,7 +168,7 @@ the device using the west tool or the STM32CubeProgrammer. Flashing an application to MiniSTM32H743 ---------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. First, put the board in bootloader mode as described above. Then build and flash the application in the usual way. Just add ``CONFIG_BOOT_DELAY=5000`` to the diff --git a/boards/wemos/esp32s2_lolin_mini/doc/index.rst b/boards/wemos/esp32s2_lolin_mini/doc/index.rst index 70682657f8ab12f..d09dec2b5f97fe4 100644 --- a/boards/wemos/esp32s2_lolin_mini/doc/index.rst +++ b/boards/wemos/esp32s2_lolin_mini/doc/index.rst @@ -66,7 +66,7 @@ The usual ``flash`` target will work with the ``esp32s2_lolin_mini`` board configuration after putting the board into bootloader mode by holding the '0' button then pressing 'RST' and releasing the 'RST' button. -Here is an example for the :ref:`hello_world` +Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst index 86fbbeafbddfbea..a7998afe26129ea 100644 --- a/boards/witte/linum/doc/index.rst +++ b/boards/witte/linum/doc/index.rst @@ -369,7 +369,7 @@ Flashing Flashing an application to the Linum board ------------------------------------------- -Here is an example for the :ref:`hello_world` application. +Here is an example for the :zephyr:code-sample:`hello_world` application. Run a serial host program to connect with your Nucleo board. @@ -394,7 +394,7 @@ Debugging ========= You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. +:zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/doc/build/dts/howtos.rst b/doc/build/dts/howtos.rst index 8875e9cfc425922..5bd4df9fcbe43a1 100644 --- a/doc/build/dts/howtos.rst +++ b/doc/build/dts/howtos.rst @@ -23,10 +23,10 @@ application and open the :file:`zephyr.dts` file in the build directory. .. tip:: - You can build :ref:`hello_world` to see the "base" devicetree for your board + You can build :zephyr:code-sample:`hello_world` to see the "base" devicetree for your board without any additional changes from :ref:`overlay files `. -For example, using the :ref:`qemu_cortex_m3` board to build :ref:`hello_world`: +For example, using the :ref:`qemu_cortex_m3` board to build :zephyr:code-sample:`hello_world`: .. code-block:: sh diff --git a/doc/build/dts/troubleshooting.rst b/doc/build/dts/troubleshooting.rst index 71521a3026bcb2c..3cb360dd11bdf49 100644 --- a/doc/build/dts/troubleshooting.rst +++ b/doc/build/dts/troubleshooting.rst @@ -261,7 +261,7 @@ Look at the preprocessor output To save preprocessor output files, enable the :kconfig:option:`CONFIG_COMPILER_SAVE_TEMPS` option. For example, to build -:ref:`hello_world` with west with this option set, use: +:zephyr:code-sample:`hello_world` with west with this option set, use: .. code-block:: sh @@ -300,7 +300,7 @@ To prevent the compiler from doing this, you can disable the :kconfig:option:`CONFIG_COMPILER_TRACK_MACRO_EXPANSION` option. This typically reduces the output to one message per error. -For example, to build :ref:`hello_world` with west and this option disabled, +For example, to build :zephyr:code-sample:`hello_world` with west and this option disabled, use: .. code-block:: sh diff --git a/doc/build/sysbuild/index.rst b/doc/build/sysbuild/index.rst index dae7c6ab30df7da..80c11ce219139d5 100644 --- a/doc/build/sysbuild/index.rst +++ b/doc/build/sysbuild/index.rst @@ -157,7 +157,7 @@ To handle this, sysbuild has namespaces for configuration variables. You can use namespaces to direct settings either to sysbuild itself or to a specific Zephyr application managed by sysbuild using the information in these sections. -The following example shows how to build :ref:`hello_world` with MCUboot enabled, +The following example shows how to build :zephyr:code-sample:`hello_world` with MCUboot enabled, applying to both images debug optimizations: .. tabs:: diff --git a/doc/develop/application/index.rst b/doc/develop/application/index.rst index fff35bb5e83344e..64d99dc0bcc81c5 100644 --- a/doc/develop/application/index.rst +++ b/doc/develop/application/index.rst @@ -131,7 +131,7 @@ Zephyr repository application An application located within the ``zephyr`` source code repository in a Zephyr :ref:`west workspace ` is referred to as a Zephyr repository -application. In the following example, the :ref:`hello_world sample +application. In the following example, the :zephyr:code-sample:`hello_world sample ` is a Zephyr repository application: .. code-block:: none diff --git a/doc/develop/beyond-GSG.rst b/doc/develop/beyond-GSG.rst index cc5e770cd6a4735..42f1f6c5f38d754 100644 --- a/doc/develop/beyond-GSG.rst +++ b/doc/develop/beyond-GSG.rst @@ -286,7 +286,7 @@ To enable QEMU in Test Runner (Twister) on Windows, :ref:`set the environment variable ` ``QEMU_BIN_PATH`` to the path of QEMU installation folder. -For example, you can build and run the :ref:`hello_world` sample using +For example, you can build and run the :zephyr:code-sample:`hello_world` sample using the x86 emulation board configuration (``qemu_x86``), with: .. zephyr-app-commands:: diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst index 0332c9879ec8311..34f21e427cddaa3 100644 --- a/doc/develop/getting_started/index.rst +++ b/doc/develop/getting_started/index.rst @@ -402,7 +402,7 @@ Build the Blinky Sample :zephyr:code-sample:`blinky` is compatible with most, but not all, :ref:`boards`. If your board does not meet Blinky's :ref:`blinky-sample-requirements`, then - :ref:`hello_world` is a good alternative. + :zephyr:code-sample:`hello_world` is a good alternative. If you are unsure what name west uses for your board, ``west boards`` can be used to obtain a list of all boards Zephyr supports. diff --git a/doc/develop/west/build-flash-debug.rst b/doc/develop/west/build-flash-debug.rst index a7c19857dd3d73d..36a4d5ddc510feb 100644 --- a/doc/develop/west/build-flash-debug.rst +++ b/doc/develop/west/build-flash-debug.rst @@ -145,7 +145,7 @@ Setting the Build System Target To specify the build system target to run, use ``--target`` (or ``-t``). For example, on host platforms with QEMU, you can use the ``run`` target to -build and run the :ref:`hello_world` sample for the emulated :ref:`qemu_x86 +build and run the :zephyr:code-sample:`hello_world` sample for the emulated :ref:`qemu_x86 ` board in one command:: west build -b qemu_x86 -t run samples/hello_world @@ -349,7 +349,7 @@ The ``-o`` option is described further in the previous section. Build a single domain --------------------- -In a multi-domain build with :ref:`hello_world` and `MCUboot`_, you can use +In a multi-domain build with :zephyr:code-sample:`hello_world` and `MCUboot`_, you can use ``--domain hello_world`` to only build this domain:: west build --sysbuild --domain hello_world @@ -543,7 +543,7 @@ will flash all domains in the order defined by sysbuild. It is possible to flash the image from a single domain in a multi-domain project by using ``--domain``. -For example, in a multi-domain build with :ref:`hello_world` and +For example, in a multi-domain build with :zephyr:code-sample:`hello_world` and `MCUboot`_, you can use the ``--domain hello_world`` domain to only flash only the image from this domain:: diff --git a/doc/develop/west/sign.rst b/doc/develop/west/sign.rst index 355682c032dffda..7de7bf7de1dd7d0 100644 --- a/doc/develop/west/sign.rst +++ b/doc/develop/west/sign.rst @@ -22,7 +22,7 @@ If you use this feature, you don't need to run ``west sign`` yourself; the build system will do it for you. Here is an example workflow, which builds and flashes MCUboot, as well as the -:ref:`hello_world` application for chain-loading by MCUboot. Run these commands +:zephyr:code-sample:`hello_world` application for chain-loading by MCUboot. Run these commands from the :file:`zephyrproject` workspace you created in the :ref:`getting_started`. diff --git a/doc/hardware/peripherals/can/shell.rst b/doc/hardware/peripherals/can/shell.rst index 0457203438d7e93..9c0999b6e7446ca 100644 --- a/doc/hardware/peripherals/can/shell.rst +++ b/doc/hardware/peripherals/can/shell.rst @@ -35,7 +35,7 @@ The following :ref:`Kconfig ` options enable additional subcommands and well. * :kconfig:option:`CONFIG_CAN_MANUAL_RECOVERY_MODE` enables the ``can recover`` subcommand. -For example, building the :ref:`hello_world` sample for the :ref:`frdm_k64f` with the CAN shell and +For example, building the :zephyr:code-sample:`hello_world` sample for the :ref:`frdm_k64f` with the CAN shell and CAN statistics enabled: .. zephyr-app-commands:: diff --git a/doc/hardware/peripherals/eeprom/shell.rst b/doc/hardware/peripherals/eeprom/shell.rst index b1b1535e8e40e43..2b4d1825732fa93 100644 --- a/doc/hardware/peripherals/eeprom/shell.rst +++ b/doc/hardware/peripherals/eeprom/shell.rst @@ -21,7 +21,7 @@ In order to enable the EEPROM shell, the following :ref:`Kconfig ` opti * :kconfig:option:`CONFIG_EEPROM` * :kconfig:option:`CONFIG_EEPROM_SHELL` -For example, building the :ref:`hello_world` sample for the :ref:`native_sim` with the EEPROM shell: +For example, building the :zephyr:code-sample:`hello_world` sample for the :ref:`native_sim` with the EEPROM shell: .. zephyr-app-commands:: :zephyr-app: samples/hello_world diff --git a/samples/hello_world/README.rst b/samples/hello_world/README.rst index ce5423d6f04484d..25b346e90f91d68 100644 --- a/samples/hello_world/README.rst +++ b/samples/hello_world/README.rst @@ -1,4 +1,7 @@ -.. _hello_world: +.. zephyr:code-sample:: hello_world + :name: Hello World + + Print "Hello World" to the console. Hello World ########### diff --git a/samples/subsys/usb/dfu/README.rst b/samples/subsys/usb/dfu/README.rst index 9fe9fd03ea25abd..44b173184a5838f 100644 --- a/samples/subsys/usb/dfu/README.rst +++ b/samples/subsys/usb/dfu/README.rst @@ -46,7 +46,7 @@ Build and flash MCUboot bootloader for Zephyr project as it is described in the `Using MCUboot with Zephyr`_ documentation. Then build, sign and flash the USB DFU sample at the offset of SLOT-0. -Build and sign a second application image e.g. :ref:`hello_world`, +Build and sign a second application image e.g. :zephyr:code-sample:`hello_world`, which will be used as an image for the update. Do not forget to enable the required :kconfig:option:`CONFIG_BOOTLOADER_MCUBOOT` option (as described in :ref:`mcuboot`). For example: From 13ff70a6f96865c3b7bf4ebfc30050610251142f Mon Sep 17 00:00:00 2001 From: Maureen Helm Date: Wed, 11 Sep 2024 18:49:57 -0500 Subject: [PATCH 028/269] drivers: sensor: tdk: Refactor cmake and kconfig to vendor subdirectory Refactors the cmake and kconfig bits of the tdk sensor drivers into the vendor subdirectory to make them consistent with other vendor-sorted sensor drivers. The tdk driver implementations were previously moved into the vendor subdirectory in commit 41f1c3a2b7ce219bd90397d107f6163800ee40aa. Signed-off-by: Maureen Helm --- drivers/sensor/CMakeLists.txt | 7 +------ drivers/sensor/Kconfig | 7 +------ drivers/sensor/tdk/CMakeLists.txt | 11 +++++++++++ drivers/sensor/tdk/Kconfig | 11 +++++++++++ 4 files changed, 24 insertions(+), 12 deletions(-) create mode 100644 drivers/sensor/tdk/CMakeLists.txt create mode 100644 drivers/sensor/tdk/Kconfig diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt index 36b1a670450af57..fb2b72273815713 100644 --- a/drivers/sensor/CMakeLists.txt +++ b/drivers/sensor/CMakeLists.txt @@ -22,6 +22,7 @@ add_subdirectory(seeed) add_subdirectory(sensirion) add_subdirectory(silabs) add_subdirectory(st) +add_subdirectory(tdk) add_subdirectory(ti) add_subdirectory(vishay) add_subdirectory(wsen) @@ -40,10 +41,6 @@ add_subdirectory_ifdef(CONFIG_FCX_MLDX5 fcx_mldx5) add_subdirectory_ifdef(CONFIG_GROW_R502A grow_r502a) add_subdirectory_ifdef(CONFIG_HP206C hp206c) add_subdirectory_ifdef(CONFIG_HS300X hs300x) -add_subdirectory_ifdef(CONFIG_ICM42605 tdk/icm42605) -add_subdirectory_ifdef(CONFIG_ICM42670 tdk/icm42670) -add_subdirectory_ifdef(CONFIG_ICM42688 tdk/icm42688) -add_subdirectory_ifdef(CONFIG_ICP10125 tdk/icp10125) add_subdirectory_ifdef(CONFIG_IST8310 ist8310) add_subdirectory_ifdef(CONFIG_ISL29035 isl29035) add_subdirectory_ifdef(CONFIG_LM35 lm35) @@ -52,8 +49,6 @@ add_subdirectory_ifdef(CONFIG_LM77 lm77) add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a) add_subdirectory_ifdef(CONFIG_MC3419 mc3419) add_subdirectory_ifdef(CONFIG_MHZ19B mhz19b) -add_subdirectory_ifdef(CONFIG_MPU6050 tdk/mpu6050) -add_subdirectory_ifdef(CONFIG_MPU9250 tdk/mpu9250) add_subdirectory_ifdef(CONFIG_NCT75 nct75) add_subdirectory_ifdef(CONFIG_NTC_THERMISTOR ntc_thermistor) add_subdirectory_ifdef(CONFIG_PMS7003 pms7003) diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig index 23adc297f235d5c..449632c89df60a7 100644 --- a/drivers/sensor/Kconfig +++ b/drivers/sensor/Kconfig @@ -106,6 +106,7 @@ source "drivers/sensor/seeed/Kconfig" source "drivers/sensor/sensirion/Kconfig" source "drivers/sensor/silabs/Kconfig" source "drivers/sensor/st/Kconfig" +source "drivers/sensor/tdk/Kconfig" source "drivers/sensor/ti/Kconfig" source "drivers/sensor/vishay/Kconfig" source "drivers/sensor/wsen/Kconfig" @@ -124,10 +125,6 @@ source "drivers/sensor/fcx_mldx5/Kconfig" source "drivers/sensor/grow_r502a/Kconfig" source "drivers/sensor/hp206c/Kconfig" source "drivers/sensor/hs300x/Kconfig" -source "drivers/sensor/tdk/icm42605/Kconfig" -source "drivers/sensor/tdk/icm42670/Kconfig" -source "drivers/sensor/tdk/icm42688/Kconfig" -source "drivers/sensor/tdk/icp10125/Kconfig" source "drivers/sensor/isl29035/Kconfig" source "drivers/sensor/ist8310/Kconfig" source "drivers/sensor/lm35/Kconfig" @@ -136,8 +133,6 @@ source "drivers/sensor/lm77/Kconfig" source "drivers/sensor/ltrf216a/Kconfig" source "drivers/sensor/mc3419/Kconfig" source "drivers/sensor/mhz19b/Kconfig" -source "drivers/sensor/tdk/mpu6050/Kconfig" -source "drivers/sensor/tdk/mpu9250/Kconfig" source "drivers/sensor/nct75/Kconfig" source "drivers/sensor/ntc_thermistor/Kconfig" source "drivers/sensor/pms7003/Kconfig" diff --git a/drivers/sensor/tdk/CMakeLists.txt b/drivers/sensor/tdk/CMakeLists.txt new file mode 100644 index 000000000000000..0f5c85a2db0e82b --- /dev/null +++ b/drivers/sensor/tdk/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +add_subdirectory_ifdef(CONFIG_ICM42605 icm42605) +add_subdirectory_ifdef(CONFIG_ICM42670 icm42670) +add_subdirectory_ifdef(CONFIG_ICM42688 icm42688) +add_subdirectory_ifdef(CONFIG_ICP10125 icp10125) +add_subdirectory_ifdef(CONFIG_MPU6050 mpu6050) +add_subdirectory_ifdef(CONFIG_MPU9250 mpu9250) +# zephyr-keep-sorted-stop diff --git a/drivers/sensor/tdk/Kconfig b/drivers/sensor/tdk/Kconfig new file mode 100644 index 000000000000000..57d92f9faf60c54 --- /dev/null +++ b/drivers/sensor/tdk/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Analog Devices, Inc. +# SPDX-License-Identifier: Apache-2.0 + +# zephyr-keep-sorted-start +source "drivers/sensor/tdk/icm42605/Kconfig" +source "drivers/sensor/tdk/icm42670/Kconfig" +source "drivers/sensor/tdk/icm42688/Kconfig" +source "drivers/sensor/tdk/icp10125/Kconfig" +source "drivers/sensor/tdk/mpu6050/Kconfig" +source "drivers/sensor/tdk/mpu9250/Kconfig" +# zephyr-keep-sorted-stop From bdcd54e4ca8274b237021967042004ebd187218f Mon Sep 17 00:00:00 2001 From: Johan Hedberg Date: Thu, 12 Sep 2024 09:29:58 +0200 Subject: [PATCH 029/269] modules: Kconfig: Provide default definitions for modules with blobs There are HCI drivers which reference the module-specific Kconfig symbols which are auto-generated when the modules are present. Provide default definitions for these symbols in case the modules are missing, so that compliance checking doesn't stumble over seemingly non-existent Kconfig options. Signed-off-by: Johan Hedberg --- modules/Kconfig.esp32 | 6 ++++++ modules/Kconfig.silabs | 6 ++++++ modules/Kconfig.stm32 | 6 ++++++ modules/hal_infineon/Kconfig | 3 +++ 4 files changed, 21 insertions(+) diff --git a/modules/Kconfig.esp32 b/modules/Kconfig.esp32 index eec39d1dbf77bd2..24ab06dd9cc6df8 100644 --- a/modules/Kconfig.esp32 +++ b/modules/Kconfig.esp32 @@ -1,6 +1,12 @@ # Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 +config ZEPHYR_HAL_ESPRESSIF_MODULE + bool + +config ZEPHYR_HAL_ESPRESSIF_MODULE_BLOBS + bool + config HAS_ESPRESSIF_HAL bool depends on SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/modules/Kconfig.silabs b/modules/Kconfig.silabs index a0aab1bd483298e..b75796c432f4c7c 100644 --- a/modules/Kconfig.silabs +++ b/modules/Kconfig.silabs @@ -3,6 +3,12 @@ # Copyright (c) 2017, Christian Taedcke # SPDX-License-Identifier: Apache-2.0 +config ZEPHYR_HAL_SILABS_MODULE + bool + +config ZEPHYR_HAL_SILABS_MODULE_BLOBS + bool + config HAS_SILABS_GECKO bool select HAS_CMSIS_CORE diff --git a/modules/Kconfig.stm32 b/modules/Kconfig.stm32 index beab5491185959f..500e2328444f823 100644 --- a/modules/Kconfig.stm32 +++ b/modules/Kconfig.stm32 @@ -3,6 +3,12 @@ # Copyright (c) 2016 Linaro Limited. # SPDX-License-Identifier: Apache-2.0 +config ZEPHYR_HAL_STM32_MODULE + bool + +config ZEPHYR_HAL_STM32_MODULE_BLOBS + bool + config HAS_STM32LIB bool diff --git a/modules/hal_infineon/Kconfig b/modules/hal_infineon/Kconfig index bc5ee008968af01..7046c48a0fc785a 100644 --- a/modules/hal_infineon/Kconfig +++ b/modules/hal_infineon/Kconfig @@ -4,6 +4,9 @@ config ZEPHYR_HAL_INFINEON_MODULE bool +config ZEPHYR_HAL_INFINEON_MODULE_BLOBS + bool + if SOC_FAMILY_INFINEON_CAT1 || SOC_FAMILY_PSOC6_LEGACY config USE_INFINEON_ADC From d33dbdb6f9d42f9eb0586a0136e465e6db30012d Mon Sep 17 00:00:00 2001 From: Johan Hedberg Date: Thu, 12 Sep 2024 11:44:33 +0200 Subject: [PATCH 030/269] doc: modules: Document conventions for auto-generated Kconfig options Document the recommended practice regarding having default definitions for module-specific Kconfig symbols. Signed-off-by: Johan Hedberg --- doc/develop/modules.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/doc/develop/modules.rst b/doc/develop/modules.rst index 1a3107111a8522d..35fb8acaf2fbeb9 100644 --- a/doc/develop/modules.rst +++ b/doc/develop/modules.rst @@ -621,6 +621,14 @@ Zephyr modules In both Kconfig and CMake, the variable ``ZEPHYR__MODULE_DIR`` contains the absolute path to the module. +Additionally, ``ZEPHYR__MODULE`` and ``ZEPHYR__MODULE_BLOBS`` +(in case the module declares blobs) symbols are automatically generated for available +modules. These can be used e.g. to declare dependencies from other Kconfig symbols +which depend on the module or blobs from the module. To satisfy compliance checking +when building Zephyr without the module present, it's recommended for the module to +have default definitions for these symbols in its respective Kconfig file under +``modules/`` in the Zephyr main tree. + In CMake, ``ZEPHYR__CMAKE_DIR`` contains the absolute path to the directory containing the :file:`CMakeLists.txt` file that is included into CMake build system. This variable's value is empty if the From 02bca9f6f6d159f07215e92f7501fc8ccb23bb5a Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 12 Sep 2024 16:54:21 -0400 Subject: [PATCH 031/269] twister: abort on unrecognised platforms identify misnamed platforms and abort. Signed-off-by: Anas Nashif --- scripts/pylib/twister/twisterlib/testplan.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/testplan.py b/scripts/pylib/twister/twisterlib/testplan.py index 2b6b80a89f8520e..3e84a5067150251 100755 --- a/scripts/pylib/twister/twisterlib/testplan.py +++ b/scripts/pylib/twister/twisterlib/testplan.py @@ -767,8 +767,7 @@ def apply_filters(self, **kwargs): # If there isn't any overlap between the platform_allow list and the platform_scope # we set the scope to the platform_allow list if ts.platform_allow and not platform_filter and not integration and platform_config.get('increased_platform_scope', True): - self.verify_platforms_existence( - ts.platform_allow, f"{ts_name} - platform_allow") + self.verify_platforms_existence(ts.platform_allow, f"{ts_name} - platform_allow") a = set(platform_scope) b = set(filter(lambda item: item.name in ts.platform_allow, self.platforms)) c = a.intersection(b) @@ -846,6 +845,9 @@ def apply_filters(self, **kwargs): instance.add_filter("In test case arch exclude", Filters.TESTSUITE) if ts.platform_exclude and plat.name in ts.platform_exclude: + # works only when we have all platforms parsed, -p limits parsing... + if not platform_filter: + self.verify_platforms_existence(ts.platform_exclude, f"{ts_name} - platform_exclude") instance.add_filter("In test case platform exclude", Filters.TESTSUITE) if ts.toolchain_exclude and toolchain in ts.toolchain_exclude: From 0bca19588ad663c25cd1d4c922b8ff28bd26eb40 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Thu, 12 Sep 2024 17:02:02 -0400 Subject: [PATCH 032/269] tests: remove misnamed platforms from platform_exclude Few tests with wrongly names platforms. This section is now being verified for correctness like all others. Signed-off-by: Anas Nashif --- tests/kernel/obj_core/obj_core/testcase.yaml | 1 - tests/kernel/obj_core/obj_core_stats/testcase.yaml | 1 - tests/kernel/obj_core/obj_core_stats_api/testcase.yaml | 1 - tests/lib/lockfree/testcase.yaml | 1 - tests/subsys/rtio/rtio_api/testcase.yaml | 5 ++++- tests/subsys/zbus/integration/testcase.yaml | 1 - 6 files changed, 4 insertions(+), 6 deletions(-) diff --git a/tests/kernel/obj_core/obj_core/testcase.yaml b/tests/kernel/obj_core/obj_core/testcase.yaml index 6751c0bcb10a475..0f70532fbc8e42f 100644 --- a/tests/kernel/obj_core/obj_core/testcase.yaml +++ b/tests/kernel/obj_core/obj_core/testcase.yaml @@ -6,4 +6,3 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/obj_core/obj_core_stats/testcase.yaml b/tests/kernel/obj_core/obj_core_stats/testcase.yaml index 1027cac8fec4ddb..c3ee2465a6a14ac 100644 --- a/tests/kernel/obj_core/obj_core_stats/testcase.yaml +++ b/tests/kernel/obj_core/obj_core_stats/testcase.yaml @@ -6,4 +6,3 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml b/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml index 2c4ecb5bc21f48f..ae8b06b3baf18c2 100644 --- a/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml +++ b/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml @@ -6,4 +6,3 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny/ia32/768 diff --git a/tests/lib/lockfree/testcase.yaml b/tests/lib/lockfree/testcase.yaml index e541a6904a77fd2..d459b04fc39a011 100644 --- a/tests/lib/lockfree/testcase.yaml +++ b/tests/lib/lockfree/testcase.yaml @@ -1,7 +1,6 @@ tests: libraries.lockfree: platform_exclude: - - m5stack_core2 # renode times out - m2gl025_miv # renode times out tags: - lockfree diff --git a/tests/subsys/rtio/rtio_api/testcase.yaml b/tests/subsys/rtio/rtio_api/testcase.yaml index 4240ce40fb3eea5..08bc40e0b2f3881 100644 --- a/tests/subsys/rtio/rtio_api/testcase.yaml +++ b/tests/subsys/rtio/rtio_api/testcase.yaml @@ -1,7 +1,10 @@ common: # renode causes timeouts unfortunately # xtensa dc233 (with mmu) has a TLB exception for unclear reasons - platform_exclude: m2gl025_miv m5stack_core2 hifive1 qemu_xtensa/dc233c/mmu + platform_exclude: + - m2gl025_miv + - hifive1 + - qemu_xtensa/dc233c/mmu platform_key: - arch - simulation diff --git a/tests/subsys/zbus/integration/testcase.yaml b/tests/subsys/zbus/integration/testcase.yaml index ec123e9477e5cb2..242edbc6e779fc9 100644 --- a/tests/subsys/zbus/integration/testcase.yaml +++ b/tests/subsys/zbus/integration/testcase.yaml @@ -4,7 +4,6 @@ tests: - qemu_cortex_a9 - hifive_unleashed - fvp_base_revc_2xaemv8a//smp/ns - - fvp_baser_aemv8r_aarch32_smp tags: zbus integration_platforms: - native_sim From 3328d7cb015487abf3267c389e9166c25893c65b Mon Sep 17 00:00:00 2001 From: Mathieu Choplain Date: Thu, 12 Sep 2024 10:59:50 +0200 Subject: [PATCH 033/269] drivers: adc: stm32: don't fail init if pinctrl is not provided Commit 47187a9ec9693b754f09e346023d7514c76af567 made the `pinctrl` property of STM32 ADCs optional, to allow usage of internal channels without wasting GPIO pins. However, the driver was not adapted to support this new usecase. (The real bug comes from commit 93956b207386d1833d162c3ee9b71c6bd8a81da3, that transitioned from a custom `stm32_dt_pinctrl_configure` function to the standard `pinctrl_apply_state`, without accounting for the fact that the former returns 0 when pinctrl is empty, but the latter returns -ENOENT) Modify the driver to work even if no `pinctrl` is present on the ADC node. Signed-off-by: Mathieu Choplain --- drivers/adc/adc_stm32.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index 6c5fc585a677d1d..c827fecc9a644c2 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -1434,9 +1434,14 @@ static int adc_stm32_init(const struct device *dev) adc_stm32_set_clock(dev); - /* Configure dt provided device signals when available */ + /* Configure ADC inputs as specified in Device Tree, if any */ err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); - if (err < 0) { + if ((err < 0) && (err != -ENOENT)) { + /* + * If the ADC is used only with internal channels, then no pinctrl is + * provided in Device Tree, and pinctrl_apply_state returns -ENOENT, + * but this should not be treated as an error. + */ LOG_ERR("ADC pinctrl setup failed (%d)", err); return err; } From 937d4b6f67772b851d8195cb376987c7a1b92274 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Thu, 12 Sep 2024 10:58:26 +0200 Subject: [PATCH 034/269] samples: net: http_client: Fix busy-looping in case of errors The http_client sample ignored connect() errors and attempted to run HTTP query even if the connection failed. Additionally, in case the query failed, the sample called `exit(1)` directly, causing busy-looping in the sample. This prevented the logger output from being printed. Both of those issues made the sample behavior very confusing when it encountered connection problems. The sample did not print any output at all (due to busy looping) or printed several connect failures (due to ignoring connect() results). This commit fixes those problems. Signed-off-by: Robert Lubos --- samples/net/sockets/http_client/src/main.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/samples/net/sockets/http_client/src/main.c b/samples/net/sockets/http_client/src/main.c index 933f4b18484ee2e..5c89fb42b279fe8 100644 --- a/samples/net/sockets/http_client/src/main.c +++ b/samples/net/sockets/http_client/src/main.c @@ -141,6 +141,8 @@ static int connect_socket(sa_family_t family, const char *server, int port, LOG_ERR("Cannot connect to %s remote (%d)", family == AF_INET ? "IPv4" : "IPv6", -errno); + close(*sock); + *sock = -1; ret = -errno; } @@ -360,20 +362,23 @@ int main(void) { int iterations = CONFIG_NET_SAMPLE_SEND_ITERATIONS; int i = 0; - int ret; + int ret = 0; while (iterations == 0 || i < iterations) { ret = run_queries(); if (ret < 0) { - exit(1); + ret = 1; + break; } if (iterations > 0) { i++; if (i >= iterations) { + ret = 0; break; } } else { + ret = 0; break; } } @@ -382,6 +387,6 @@ int main(void) k_sleep(K_FOREVER); } - exit(0); - return 0; + exit(ret); + return ret; } From 9a722f7983120425ffc374b0d4822880dcc55efd Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Thu, 12 Sep 2024 10:31:44 +0100 Subject: [PATCH 035/269] doc: services: device_mgmt: mcumgr: Add enum mgmt to table Adds enum mgmt to the table of supported services Signed-off-by: Jamie McCrae --- doc/services/device_mgmt/mcumgr.rst | 94 ++++++++++++++--------------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/doc/services/device_mgmt/mcumgr.rst b/doc/services/device_mgmt/mcumgr.rst index 0f4f57e7954ee83..bf1afb7622ce280 100644 --- a/doc/services/device_mgmt/mcumgr.rst +++ b/doc/services/device_mgmt/mcumgr.rst @@ -48,26 +48,26 @@ project. .. table:: Tools and Libraries for MCUmgr :align: center - +--------------------------------------------------------------------------------+-------------------------------------------+--------------------------+--------------------------------------------------+---------------+------------+---------+ - | Name | OS support | Transports | Groups | Type | Language | License | - | +---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+--------+ | | | - | | Windows | Linux | mac | Mobile | Embedded | Serial | Bluetooth | UDP | OS | IMG | Stat | Settings | FS | Shell | Zephyr | | | | - +================================================================================+=========+=======+=====+========+==========+========+===========+=====+====+=====+======+==========+====+=======+========+===============+============+=========+ - | `AuTerm `_ | ✓ | ✓ | ✓ | ✕ | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | Application | C++ (Qt) | GPLv3 | - +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+--------+---------------+------------+---------+ - | `mcumgr-client `_ | ✓ | ✓ | ✓ | ✕ | ✕ | ✓ | ✕ | ✕ | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | Application | Rust | BSD | - +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+--------+---------------+------------+---------+ - | `mcumgr-web `_ | ✓ | ✓ | ✓ | ✕ | ✕ | ✕ | ✓ | ✕ | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | Web page | Javascript | MIT | - | | | | | | | | | | | | | | | | | (chrome only) | | | - +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+--------+---------------+------------+---------+ - | nRF Connect Device Manager: |br| | | | | | | | | | | | | | | | | | | | - | `Android | ✕ | ✕ | ✕ | ✓ | ✕ | ✕ | ✓ | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | Library and | Java, | Apache | - | `_ | | | | | | | | | | | | | | | | application | Kotlin, | | - | and `iOS | | | | | | | | | | | | | | | | | Swift | | - | `_ | | | | | | | | | | | | | | | | | | | - +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+--------+---------------+------------+---------+ - | Zephyr MCUmgr client (in-tree) | ✕ | ✓ | ✕ | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | Library | C | Apache | - +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+--------+---------------+------------+---------+ + +--------------------------------------------------------------------------------+-------------------------------------------+--------------------------+---------------------------------------------------------+---------------+------------+---------+ + | Name | OS support | Transports | Groups | Type | Language | License | + | +---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+------+--------+ | | | + | | Windows | Linux | mac | Mobile | Embedded | Serial | Bluetooth | UDP | OS | IMG | Stat | Settings | FS | Shell | Enum | Zephyr | | | | + +================================================================================+=========+=======+=====+========+==========+========+===========+=====+====+=====+======+==========+====+=======+======+========+===============+============+=========+ + | `AuTerm `_ | ✓ | ✓ | ✓ | ✕ | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | Application | C++ (Qt) | GPLv3 | + +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+------+--------+---------------+------------+---------+ + | `mcumgr-client `_ | ✓ | ✓ | ✓ | ✕ | ✕ | ✓ | ✕ | ✕ | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | Application | Rust | BSD | + +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+------+--------+---------------+------------+---------+ + | `mcumgr-web `_ | ✓ | ✓ | ✓ | ✕ | ✕ | ✕ | ✓ | ✕ | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | Web page | Javascript | MIT | + | | | | | | | | | | | | | | | | | | (chrome only) | | | + +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+------+--------+---------------+------------+---------+ + | nRF Connect Device Manager: |br| | | | | | | | | | | | | | | | | | | | | + | `Android | ✕ | ✕ | ✕ | ✓ | ✕ | ✕ | ✓ | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ | ✓ | Library and | Java, | Apache | + | `_ | | | | | | | | | | | | | | | | | application | Kotlin, | | + | and `iOS | | | | | | | | | | | | | | | | | | Swift | | + | `_ | | | | | | | | | | | | | | | | | | | | + +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+------+--------+---------------+------------+---------+ + | Zephyr MCUmgr client (in-tree) | ✕ | ✓ | ✕ | ✕ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | Library | C | Apache | + +--------------------------------------------------------------------------------+---------+-------+-----+--------+----------+--------+-----------+-----+----+-----+------+----------+----+-------+------+--------+---------------+------------+---------+ .. only:: latex @@ -78,33 +78,33 @@ project. .. table:: Tools and Libraries for MCUmgr :align: center - +--------------------------------------------------------------------------------+---------------+-----------------+--------------------------------------------------+---------------+------------+ - | Name | OS support | Transports | Groups | Type | Language | - | | | +----+-----+------+----------+----+-------+--------+ | | - | | | | OS | IMG | Stat | Settings | FS | Shell | Zephyr | | | - +================================================================================+===============+=================+====+=====+======+==========+====+=======+========+===============+============+ - | `AuTerm `_ | Windows, |br| | Serial, |br| | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | App | C++ (Qt) | - | | Linux, |br| | Bluetooth, |br| | | | | | | | | | | - | | macOS | UDP | | | | | | | | | | - +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+--------+---------------+------------+ - | `mcumgr-client `_ | Windows, |br| | Serial | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | App | Rust | - | | Linux, |br| | | | | | | | | | | | - | | macOS | | | | | | | | | | | - +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+--------+---------------+------------+ - | `mcumgr-web `_ | Windows, |br| | Bluetooth | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | Web (chrome | Javascript | - | | Linux, |br| | | | | | | | | | only) | | - | | macOS | | | | | | | | | | | - +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+--------+---------------+------------+ - | nRF Connect Device Manager: |br| | iOS, |br| | Bluetooth | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | Library, App | Java, | - | `Android | Android | | | | | | | | | | Kotlin, | - | `_ | | | | | | | | | | | Swift | - | and `iOS | | | | | | | | | | | | - | `_ | | | | | | | | | | | | - +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+--------+---------------+------------+ - | Zephyr MCUmgr client (in-tree) | Linux, |br| | Serial, |br| | ✓ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | Library | C | - | | Zephyr | Bluetooth, |br| | | | | | | | | | | - | | | UDP | | | | | | | | | | - +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+--------+---------------+------------+ + +--------------------------------------------------------------------------------+---------------+-----------------+---------------------------------------------------------+---------------+------------+ + | Name | OS support | Transports | Groups | Type | Language | + | | | +----+-----+------+----------+----+-------+------+--------+ | | + | | | | OS | IMG | Stat | Settings | FS | Shell | Enum | Zephyr | | | + +================================================================================+===============+=================+====+=====+======+==========+====+=======+======+========+===============+============+ + | `AuTerm `_ | Windows, |br| | Serial, |br| | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | App | C++ (Qt) | + | | Linux, |br| | Bluetooth, |br| | | | | | | | | | | | + | | macOS | UDP | | | | | | | | | | | + +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+------+--------+---------------+------------+ + | `mcumgr-client `_ | Windows, |br| | Serial | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | App | Rust | + | | Linux, |br| | | | | | | | | | | | | + | | macOS | | | | | | | | | | | | + +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+------+--------+---------------+------------+ + | `mcumgr-web `_ | Windows, |br| | Bluetooth | ✕ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | Web (chrome | Javascript | + | | Linux, |br| | | | | | | | | | | only) | | + | | macOS | | | | | | | | | | | | + +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+------+--------+---------------+------------+ + | nRF Connect Device Manager: |br| | iOS, |br| | Bluetooth | ✓ | ✓ | ✓ | ✓ | ✓ | ✓ | ✕ | ✓ | Library, App | Java, | + | `Android | Android | | | | | | | | | | | Kotlin, | + | `_ | | | | | | | | | | | | Swift | + | and `iOS | | | | | | | | | | | | | + | `_ | | | | | | | | | | | | | + +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+------+--------+---------------+------------+ + | Zephyr MCUmgr client (in-tree) | Linux, |br| | Serial, |br| | ✓ | ✓ | ✕ | ✕ | ✕ | ✕ | ✕ | ✕ | Library | C | + | | Zephyr | Bluetooth, |br| | | | | | | | | | | | + | | | UDP | | | | | | | | | | | + +--------------------------------------------------------------------------------+---------------+-----------------+----+-----+------+----------+----+-------+------+--------+---------------+------------+ .. raw:: latex From 6ce257cc76d5c9cdfa3a16d6d226319621af69e9 Mon Sep 17 00:00:00 2001 From: Alberto Escolar Piedras Date: Sat, 14 Sep 2024 08:57:56 +0200 Subject: [PATCH 036/269] lib/libc/Kconfig: Fix libC depends with NATIVE_APPlICATION NATIVE_APPlICATION (old native_posix) does not support bulding with the any other library than the host libC (EXTERNAL_LIBC). MINIMAL_LIBC_SUPPORTED defaulted to y always, and instead the depends was set in the MINIMAL_LIBC choice. This lead to the right library selected, but an incorrectly set MINIMAL_LIBC_SUPPORTED. Many tests filter based on MINIMAL_LIBC_SUPPORTED, so they were not filtered out appropriately. Let's place the depends in the right place to avoid this problem. Also remove a redundant depends on for PICOLIBC and NEWLIB_LIBC which already have the dependency in their respective _SUPPORTED option. Signed-off-by: Alberto Escolar Piedras --- lib/libc/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/lib/libc/Kconfig b/lib/libc/Kconfig index 7d793848f99bac9..d1ba54347eb8ac5 100644 --- a/lib/libc/Kconfig +++ b/lib/libc/Kconfig @@ -27,6 +27,7 @@ config FULL_LIBC_SUPPORTED config MINIMAL_LIBC_SUPPORTED bool + depends on !NATIVE_APPLICATION default y help Selected when the target has support for the minimal C library @@ -35,6 +36,7 @@ config NEWLIB_LIBC_SUPPORTED bool default y depends on "$(TOOLCHAIN_HAS_NEWLIB)" = "y" + depends on !NATIVE_APPLICATION select FULL_LIBC_SUPPORTED help Selected when the target has support for the newlib C library @@ -66,7 +68,6 @@ choice LIBC_IMPLEMENTATION config MINIMAL_LIBC bool "Minimal C library" - depends on !NATIVE_APPLICATION depends on !REQUIRES_FULL_LIBC depends on MINIMAL_LIBC_SUPPORTED imply COMPILER_FREESTANDING @@ -85,7 +86,6 @@ config PICOLIBC select LIBC_ERRNO if THREAD_LOCAL_STORAGE select NEED_LIBC_MEM_PARTITION imply COMMON_LIBC_MALLOC - depends on !NATIVE_APPLICATION depends on PICOLIBC_SUPPORTED help Build with picolibc library. The picolibc library is built as @@ -95,7 +95,6 @@ config PICOLIBC config NEWLIB_LIBC bool "Newlib C library" select COMMON_LIBC_ABORT - depends on !NATIVE_APPLICATION depends on NEWLIB_LIBC_SUPPORTED select NEED_LIBC_MEM_PARTITION imply POSIX_DEVICE_IO_ALIAS_CLOSE From d7aaf9bee335377dcb2ae7fc2d3ee3bbd96a4db8 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 15:47:42 -0700 Subject: [PATCH 037/269] tests/c_lib: Ensure TZ value is UTC for ctime/ctime_r tests When testing these functions with CONFIG_NATIVE_LIBC, force the TZ environment variable to UTC to ensure they produce the expected results. Signed-off-by: Keith Packard --- tests/lib/c_lib/common/src/main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/lib/c_lib/common/src/main.c b/tests/lib/c_lib/common/src/main.c index f7db63c0ad8609f..2e1f5cdf4cbb43a 100644 --- a/tests/lib/c_lib/common/src/main.c +++ b/tests/lib/c_lib/common/src/main.c @@ -1166,6 +1166,9 @@ ZTEST(libc_common, test_time_ctime) char buf[26] = {0}; time_t test1 = 1718260000; +#ifdef CONFIG_NATIVE_LIBC + setenv("TZ", "UTC", 1); +#endif zassert_not_null(ctime_r(&test1, buf)); zassert_equal(strncmp("Thu Jun 13 06:26:40 2024\n", buf, sizeof(buf)), 0); From 23eca6362dce63e52fcf6825f772e7ee7ae5226e Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 00:56:09 +0200 Subject: [PATCH 038/269] boards: silabs: slstk3401a: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x3e800) don't match for > /soc/flash-controller@400e0000/flash@0/partitions/partition@fe800 Signed-off-by: Reto Schneider --- boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi b/boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi index 9b1b8195a105f57..f9a6ff3da0469b6 100644 --- a/boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi +++ b/boards/silabs/starter_kits/slstk3401a/slstk3401a-common.dtsi @@ -127,7 +127,7 @@ #size-cells = <1>; /* Set 6Kb of storage at the end of the 256Kb of flash */ - storage_partition: partition@fe800 { + storage_partition: partition@3e800 { label = "storage"; reg = <0x0003e800 0x00001800>; }; From 20b218985cbc676894f1b6b416a6612c2bc0b265 Mon Sep 17 00:00:00 2001 From: Fabian Blatz Date: Mon, 16 Sep 2024 09:58:17 +0200 Subject: [PATCH 039/269] tests: drivers: stepper: stepper_api: Fix UAF of poll signal The test_target_position test used a stack allocated `poll_signal` which is kept as a refrence inside the gpio driver. Since the time for polling the signal was chosen pretty narrow, the function exited with the driver still trying to signal the stack allocated value upon movement completion. Fix by adding the structs to the test fixture and increase the timeout. Resolves #78466. Signed-off-by: Fabian Blatz --- tests/drivers/stepper/stepper_api/src/main.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/tests/drivers/stepper/stepper_api/src/main.c b/tests/drivers/stepper/stepper_api/src/main.c index 55ab3ee8c9409bd..a228b25c7dc4708 100644 --- a/tests/drivers/stepper/stepper_api/src/main.c +++ b/tests/drivers/stepper/stepper_api/src/main.c @@ -9,6 +9,8 @@ struct stepper_fixture { const struct device *dev; + struct k_poll_signal signal; + struct k_poll_event event; }; static void *stepper_setup(void) @@ -17,6 +19,10 @@ static void *stepper_setup(void) .dev = DEVICE_DT_GET(DT_NODELABEL(motor_1)), }; + k_poll_signal_init(&fixture.signal); + k_poll_event_init(&fixture.event, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, + &fixture.signal); + zassert_not_null(fixture.dev); return &fixture; } @@ -25,6 +31,7 @@ static void stepper_before(void *f) { struct stepper_fixture *fixture = f; (void)stepper_set_actual_position(fixture->dev, 0); + k_poll_signal_reset(&fixture->signal); } ZTEST_SUITE(stepper, NULL, stepper_setup, stepper_before, NULL, NULL); @@ -48,19 +55,14 @@ ZTEST_F(stepper, test_actual_position) ZTEST_F(stepper, test_target_position) { int32_t pos = 100u; - struct k_poll_signal signal; - - k_poll_signal_init(&signal); - struct k_poll_event event; - k_poll_event_init(&event, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY, &signal); (void)stepper_set_max_velocity(fixture->dev, 100u); - (void)stepper_set_target_position(fixture->dev, pos, &signal); - (void)k_poll(&event, 1, K_SECONDS(2)); + (void)stepper_set_target_position(fixture->dev, pos, &fixture->signal); + (void)k_poll(&fixture->event, 1, K_SECONDS(5)); unsigned int signaled; int result; - k_poll_signal_check(&signal, &signaled, &result); + k_poll_signal_check(&fixture->signal, &signaled, &result); zassert_equal(signaled, 1, "Signal not set"); zassert_equal(result, STEPPER_SIGNAL_STEPS_COMPLETED, "Signal not set"); (void)stepper_get_actual_position(fixture->dev, &pos); From dff5307b25213c207d64c0848a8a97d2f925608f Mon Sep 17 00:00:00 2001 From: Josuah Demangeon Date: Fri, 13 Sep 2024 21:08:38 +0200 Subject: [PATCH 040/269] samples: drivers: video: complement renaming from subsys/ to drivers/ Commit 911abc33e68b81c0490fa4b32a93d7d726640b73 did move the samples from subsys/ to drivers/, and more contribution came in parallel. This covers extra board configurations added later which also need moving. Signed-off-by: Josuah Demangeon --- .../{subsys => drivers}/video/capture/boards/mimxrt1060_evkb.conf | 0 .../{subsys => drivers}/video/capture/boards/mimxrt1064_evk.conf | 0 2 files changed, 0 insertions(+), 0 deletions(-) rename samples/{subsys => drivers}/video/capture/boards/mimxrt1060_evkb.conf (100%) rename samples/{subsys => drivers}/video/capture/boards/mimxrt1064_evk.conf (100%) diff --git a/samples/subsys/video/capture/boards/mimxrt1060_evkb.conf b/samples/drivers/video/capture/boards/mimxrt1060_evkb.conf similarity index 100% rename from samples/subsys/video/capture/boards/mimxrt1060_evkb.conf rename to samples/drivers/video/capture/boards/mimxrt1060_evkb.conf diff --git a/samples/subsys/video/capture/boards/mimxrt1064_evk.conf b/samples/drivers/video/capture/boards/mimxrt1064_evk.conf similarity index 100% rename from samples/subsys/video/capture/boards/mimxrt1064_evk.conf rename to samples/drivers/video/capture/boards/mimxrt1064_evk.conf From 9f59d899222b0067dcde249d5e7c416c7e08038b Mon Sep 17 00:00:00 2001 From: Carles Cufi Date: Fri, 13 Sep 2024 14:56:17 +0200 Subject: [PATCH 041/269] boards: nordic: nrf9280pdk: Remove doc page This board is not currently available for the general public, and the documentation page adds no value whatsoever. Remove it until the board is finally available and its features and support can be documented properly. Signed-off-by: Carles Cufi --- boards/nordic/nrf9280pdk/doc/index.rst | 102 ------------------------- 1 file changed, 102 deletions(-) delete mode 100644 boards/nordic/nrf9280pdk/doc/index.rst diff --git a/boards/nordic/nrf9280pdk/doc/index.rst b/boards/nordic/nrf9280pdk/doc/index.rst deleted file mode 100644 index 394229217f7a53f..000000000000000 --- a/boards/nordic/nrf9280pdk/doc/index.rst +++ /dev/null @@ -1,102 +0,0 @@ -.. _nrf9280pdk_nrf9280: - -nRF9280 PDK -########### - -Overview -******** - -.. note:: - - All software for the nRF9280 SiP is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF9280 PDK is a single-board development kit for evaluation and development -on the Nordic nRF9280 System-in-Package (SiP). - -The ``nrf9280pdk/nrf9280/cpuapp`` board target provides support for -the application core on the nRF9280 SiP. - -nRF9280 SiP provides support for the following devices: - -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` - -Hardware -******** - -The nRF9280 PDK has four programmable LEDs, four programmable buttons, and one reset button. - -Supported Features -================== - -The ``nrf9280pdk/nrf9280/cpuapp`` board target supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LEDs ----- - -* LED1 (green) = P9.02 -* LED2 (green) = P9.03 -* LED3 (green) = P9.04 -* LED4 (green) = P9.05 - -Push buttons ------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* BUTTON3 = P0.10 -* BUTTON4 = P0.11 -* RESET (SW1) - -Programming and Debugging -************************* - -Applications for the ``nrf9280pdk/nrf9280/cpuapp`` board target can be built, -flashed, and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world` -application. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF9280 PDK, complete the following steps: - -1. Connect the nRF9280 PDK to your computer using the IMCU USB port on the PDK. -#. Build the sample by running the following command: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9280pdk/nrf9280/cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF9280 PDK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs -on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts`. From a372220ade2b5dc83faed664675b9a29034bf14b Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Thu, 12 Sep 2024 13:59:34 -0300 Subject: [PATCH 042/269] video: esp32_dvp: change default log level to the recent CONFIG_VIDEO_LOG_LEVEL option. Signed-off-by: Felipe Neves --- drivers/video/video_esp32_dvp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/video_esp32_dvp.c b/drivers/video/video_esp32_dvp.c index fe775d6de49e613..0d9c9dc6d870c8a 100644 --- a/drivers/video/video_esp32_dvp.c +++ b/drivers/video/video_esp32_dvp.c @@ -20,7 +20,7 @@ #include #include -LOG_MODULE_REGISTER(video_esp32_lcd_cam, LOG_LEVEL_INF); +LOG_MODULE_REGISTER(video_esp32_lcd_cam, CONFIG_VIDEO_LOG_LEVEL); #define VIDEO_ESP32_DMA_BUFFER_MAX_SIZE 4095 From 7f412924d35acb47427912368b2b69c2b67ca414 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 13:27:59 -0700 Subject: [PATCH 043/269] libc/common: Define _POSIX_C_SOURCE to gain access to POSIX functions ctime.c and localtime_r_utc.c may use POSIX-only functions; to ensure those are visible from a POSIX-conforming C library, define _POSIX_C_SOURCE in these source files. Signed-off-by: Keith Packard --- lib/libc/common/source/time/ctime.c | 2 ++ lib/libc/common/source/time/localtime_r_utc.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/lib/libc/common/source/time/ctime.c b/lib/libc/common/source/time/ctime.c index 454feb363c5af7c..2b7bce985d38add 100644 --- a/lib/libc/common/source/time/ctime.c +++ b/lib/libc/common/source/time/ctime.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L #include /** diff --git a/lib/libc/common/source/time/localtime_r_utc.c b/lib/libc/common/source/time/localtime_r_utc.c index 7a17dcf442c59e9..da63a39aa3754d6 100644 --- a/lib/libc/common/source/time/localtime_r_utc.c +++ b/lib/libc/common/source/time/localtime_r_utc.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L #include struct tm *localtime_r(const time_t *timer, struct tm *result) From 40ac96aa57e3d939ebf2f791f849313eb8482957 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 15:13:08 -0700 Subject: [PATCH 044/269] net: dns: Ignore GCC warnings in mdns_responder.c GCC complains about struct sockaddr accesses due to the various address-family-specific variants being of differing sizes. Let's not mess with code (which looks correct), just silence the compiler. Signed-off-by: Keith Packard --- subsys/net/lib/dns/mdns_responder.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/subsys/net/lib/dns/mdns_responder.c b/subsys/net/lib/dns/mdns_responder.c index ae99a2d3023b97c..43b07d694c52def 100644 --- a/subsys/net/lib/dns/mdns_responder.c +++ b/subsys/net/lib/dns/mdns_responder.c @@ -35,6 +35,18 @@ LOG_MODULE_REGISTER(net_mdns_responder, CONFIG_MDNS_RESPONDER_LOG_LEVEL); #include "net_private.h" +/* + * GCC complains about struct sockaddr accesses due to the various + * address-family-specific variants being of differing sizes. Let's not + * mess with code (which looks correct), just silence the compiler. + */ +#ifdef __GNUC__ +#pragma GCC diagnostic ignored "-Wpragmas" +#pragma GCC diagnostic ignored "-Wunknown-warning-option" +#pragma GCC diagnostic ignored "-Warray-bounds" +#pragma GCC diagnostic ignored "-Wstringop-overread" +#endif + extern void dns_dispatcher_svc_handler(struct k_work *work); #define MDNS_LISTEN_PORT 5353 From 88359d998c4dc66d72edfea2a2f2a7757b3d00c3 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 20:56:11 -0700 Subject: [PATCH 045/269] subsys/llext: Allow .exported_sym to be between other data sections There's no reason for the .exported_sym data to always land at one end of a data region; the order of sections depends on the whim of the compiler and assembler. Ignore overlaps between that region and other data regions. Signed-off-by: Keith Packard --- subsys/llext/llext_load.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/subsys/llext/llext_load.c b/subsys/llext/llext_load.c index ede4e59fe757aaa..1ed6491031e5c02 100644 --- a/subsys/llext/llext_load.c +++ b/subsys/llext/llext_load.c @@ -355,6 +355,16 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext) continue; } + /* + * The export symbol table may be surrounded by + * other data sections. Ignore overlaps in that + * case. + */ + if ((i == LLEXT_MEM_DATA || i == LLEXT_MEM_RODATA) && + j == LLEXT_MEM_EXPORT) { + continue; + } + if (ldr->hdr.e_type == ET_DYN) { /* * Test all merged VMA ranges for overlaps From 94043dbefec22832de773acf8963455685346c92 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 15:14:23 -0700 Subject: [PATCH 046/269] subsys/shell: cmd_date_set uses gmtime_r, a POSIX function Define _POSIX_C_SOURCE for this file to make sure gmtime_r is visible. Signed-off-by: Keith Packard --- subsys/shell/modules/date_service.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/subsys/shell/modules/date_service.c b/subsys/shell/modules/date_service.c index 245284c973a9b0b..a7f4ec3e32b939e 100644 --- a/subsys/shell/modules/date_service.c +++ b/subsys/shell/modules/date_service.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L #include #include #include From 9da477543d13a8b9b6e65017091f2192990e38f0 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 12:11:59 -0700 Subject: [PATCH 047/269] posix: Avoid stepping on picolibc clockid_t and timer_t picolibc sets _CLOCKID_T_DECLARED and _TIMER_T_DECLARED, not __clockid_t_defined and __timer_t_defined. Signed-off-by: Keith Packard --- include/zephyr/posix/posix_types.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/zephyr/posix/posix_types.h b/include/zephyr/posix/posix_types.h index 80ec8dfe200ec99..feb3d9bcbb230ef 100644 --- a/include/zephyr/posix/posix_types.h +++ b/include/zephyr/posix/posix_types.h @@ -73,11 +73,11 @@ typedef unsigned long useconds_t; /* time related attributes */ #if !defined(CONFIG_NEWLIB_LIBC) && !defined(CONFIG_ARCMWDT_LIBC) -#ifndef __clockid_t_defined +#if !defined(__clockid_t_defined) && !defined(_CLOCKID_T_DECLARED) typedef uint32_t clockid_t; #endif #endif /* !CONFIG_NEWLIB_LIBC && !CONFIG_ARCMWDT_LIBC */ -#ifndef __timer_t_defined +#if !defined(__timer_t_defined) && !defined(_TIMER_T_DECLARED) typedef unsigned long timer_t; #endif From 5ad762f22ecef8c6b1f3a6964c73e2d0a230553e Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 13:24:15 -0700 Subject: [PATCH 048/269] posix: Avoid redefining TZNAME_MAX When _POSIX_C_SOURCE is defined by a source file, a POSIX-conforming C library will define TZNAME_MAX in limits.h. Avoid redefining this in Zephyr's posix_features.h. Signed-off-by: Keith Packard --- include/zephyr/posix/posix_features.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/zephyr/posix/posix_features.h b/include/zephyr/posix/posix_features.h index fca53b0d4479cf0..e4a91c6fc92cec4 100644 --- a/include/zephyr/posix/posix_features.h +++ b/include/zephyr/posix/posix_features.h @@ -331,7 +331,9 @@ #define SYMLOOP_MAX _POSIX_SYMLOOP_MAX #define TIMER_MAX _POSIX_TIMER_MAX #define TTY_NAME_MAX _POSIX_TTY_NAME_MAX +#ifndef TZNAME_MAX #define TZNAME_MAX _POSIX_TZNAME_MAX +#endif /* Pathname variable values */ #define FILESIZEBITS (32) From a7cfe31731953f683e641f76e7186abd1889d43e Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 13:25:41 -0700 Subject: [PATCH 049/269] posix: Don't require struct itimerspec in posix/time.h struct itimerspec is only required to be available when building with _POSIX_C_SOURCE defined. Applications including posix/time.h without defining _POSIX_C_SOURCE will need to have a forward declaration of struct itimerspec even if they don't use the functions requiring that type. Signed-off-by: Keith Packard --- include/zephyr/posix/time.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/zephyr/posix/time.h b/include/zephyr/posix/time.h index f0ca07284bc8437..e2815637143078f 100644 --- a/include/zephyr/posix/time.h +++ b/include/zephyr/posix/time.h @@ -97,6 +97,7 @@ int clock_getcpuclockid(pid_t pid, clockid_t *clock_id); /* Timer APIs */ int timer_create(clockid_t clockId, struct sigevent *evp, timer_t *timerid); int timer_delete(timer_t timerid); +struct itimerspec; int timer_gettime(timer_t timerid, struct itimerspec *its); int timer_settime(timer_t timerid, int flags, const struct itimerspec *value, struct itimerspec *ovalue); From 98debeea780dd16fdeec9532ad234412631aef2e Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 13:29:27 -0700 Subject: [PATCH 050/269] posix: Define _POSIX_C_SOURCE to gain access to POSIX functions options/fs.c and options/timer.c both use POSIX-only functions. To ensure those symbols are visible from the underlying C library, define _POSIX_C_SOURCE. Signed-off-by: Keith Packard --- lib/posix/options/fs.c | 2 ++ lib/posix/options/timer.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/lib/posix/options/fs.c b/lib/posix/options/fs.c index e925d5d79723920..08e01d092332e4d 100644 --- a/lib/posix/options/fs.c +++ b/lib/posix/options/fs.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L #include #include #include diff --git a/lib/posix/options/timer.c b/lib/posix/options/timer.c index d556c78133142c2..1493be7b20694cc 100644 --- a/lib/posix/options/timer.c +++ b/lib/posix/options/timer.c @@ -4,6 +4,8 @@ * * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L #include #include From ac3df26f0a3d85c2c7ac86634552d8e3bfca8aa4 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 13 Sep 2024 16:31:07 -0700 Subject: [PATCH 051/269] libc/common: Remove redundant Kconfig POSIX_THREAD_SAFE_FUNCTIONS uses POSIX_THREAD_SAFE_FUNCTIONS already selects POSIX_C_LANG_SUPPORT_R and POSIX_C_LANG_SUPPORT_R alread selects all of the COMMON_LIBC_*_R values. That makes the 'default y if POSIX_THREAD_SAFE_FUNCTIONS' clauses in these symbols redundant. Signed-off-by: Keith Packard --- lib/libc/common/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/libc/common/Kconfig b/lib/libc/common/Kconfig index 1e65ce3bcfd0ce6..c4ac88dbab1cd5f 100644 --- a/lib/libc/common/Kconfig +++ b/lib/libc/common/Kconfig @@ -13,7 +13,6 @@ config COMMON_LIBC_ASCTIME config COMMON_LIBC_ASCTIME_R bool "Thread-safe version of asctime()" - default y if POSIX_THREAD_SAFE_FUNCTIONS select COMMON_LIBC_ASCTIME help common implementation of asctime_r(). @@ -26,7 +25,6 @@ config COMMON_LIBC_CTIME config COMMON_LIBC_CTIME_R bool "Thread-safe version of ctime()" - default y if POSIX_THREAD_SAFE_FUNCTIONS select COMMON_LIBC_CTIME help common implementation of ctime_r(). From 3eedb20d7aadd10e9d2a559d423a539f49d6e04f Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 13 Sep 2024 16:33:21 -0700 Subject: [PATCH 052/269] lib/posix: Only enable Zephyr _r APIs when toolchain doesn't Check TC_PROVIDES_POSIX_C_LANG_SUPPORT_R before selecting the COMMON_LIBC_*_R APIs. Signed-off-by: Keith Packard --- lib/posix/options/Kconfig.c_lang_r | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/posix/options/Kconfig.c_lang_r b/lib/posix/options/Kconfig.c_lang_r index d8d0f4a27516fee..49f0f71e3f86801 100644 --- a/lib/posix/options/Kconfig.c_lang_r +++ b/lib/posix/options/Kconfig.c_lang_r @@ -5,10 +5,10 @@ config POSIX_C_LANG_SUPPORT_R bool "Thread-Safe General ISO C Library" - select COMMON_LIBC_ASCTIME_R - select COMMON_LIBC_CTIME_R - select COMMON_LIBC_GMTIME_R - select COMMON_LIBC_LOCALTIME_R_UTC + select COMMON_LIBC_ASCTIME_R if ! TC_PROVIDES_POSIX_C_LANG_SUPPORT_R + select COMMON_LIBC_CTIME_R if ! TC_PROVIDES_POSIX_C_LANG_SUPPORT_R + select COMMON_LIBC_GMTIME_R if ! TC_PROVIDES_POSIX_C_LANG_SUPPORT_R + select COMMON_LIBC_LOCALTIME_R_UTC if ! TC_PROVIDES_POSIX_C_LANG_SUPPORT_R help Select 'y' here and Zephyr will provide an implementation of the POSIX_C_LANG_SUPPORT_R Option Group, consisting of asctime_r(), ctime_r(), gmtime_r(), localtime_r(), rand_r(), From 8d176ea97daf56ca25b487718146b369ebc77bb4 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 13 Sep 2024 16:34:24 -0700 Subject: [PATCH 053/269] libc/picolibc: Don't replace picolibc time _r functions Select TC_PROVIDES_POSIX_C_LANG_SUPPORT_R to keep Zephyr from including the common libc implementation of the various _r APIs. Signed-off-by: Keith Packard --- lib/libc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/libc/Kconfig b/lib/libc/Kconfig index d1ba54347eb8ac5..3012cdadf8d4816 100644 --- a/lib/libc/Kconfig +++ b/lib/libc/Kconfig @@ -85,6 +85,7 @@ config PICOLIBC imply THREAD_LOCAL_STORAGE if ARCH_HAS_THREAD_LOCAL_STORAGE && TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE select LIBC_ERRNO if THREAD_LOCAL_STORAGE select NEED_LIBC_MEM_PARTITION + select TC_PROVIDES_POSIX_C_LANG_SUPPORT_R imply COMMON_LIBC_MALLOC depends on PICOLIBC_SUPPORTED help From ea366ecc610225cb427ba2a69e34829f1b009300 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 15:09:39 -0700 Subject: [PATCH 054/269] posix: Need sys/types.h to get suseconds_t defined Picolibc's sys/_timeval.h (which Zephyr shouldn't be using) needs sys/types.h to be included first so that __suseconds_t is defined. Signed-off-by: Keith Packard --- include/zephyr/posix/sys/time.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/zephyr/posix/sys/time.h b/include/zephyr/posix/sys/time.h index d7e108b5ff711a0..71153f7155d8209 100644 --- a/include/zephyr/posix/sys/time.h +++ b/include/zephyr/posix/sys/time.h @@ -22,6 +22,7 @@ struct timeval { #endif #else +#include #include #endif /* CONFIG_NEWLIB_LIBC */ From 5973a71e1f1953a6473aa46ea53fd81a1253a79d Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 15:11:58 -0700 Subject: [PATCH 055/269] posix: options/shm.c needs _POSIX_C_SOURCE This file uses PATH_MAX, which is defined in limits.h when _POSIX_C_SOURCE is set. Signed-off-by: Keith Packard --- lib/posix/options/shm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/posix/options/shm.c b/lib/posix/options/shm.c index 3efd9843b2cbf99..d57fff7445406d9 100644 --- a/lib/posix/options/shm.c +++ b/lib/posix/options/shm.c @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L + #include #include From dc7c20adf9fe65a90261c120949d2862accbec22 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Fri, 13 Sep 2024 09:54:01 -0700 Subject: [PATCH 056/269] posix: sysconf.c uses POSIX values We need to add _POSIX_C_SOURCE to this file as it uses POSIX values from limits.h including IOV_MAX, CHILD_MAX and ARG_MAX. Signed-off-by: Keith Packard --- lib/posix/options/sysconf.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lib/posix/options/sysconf.c b/lib/posix/options/sysconf.c index 5d3492918fb4041..881d83ceebf6ab0 100644 --- a/lib/posix/options/sysconf.c +++ b/lib/posix/options/sysconf.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L #include #include #include From 6e1210a09e1c0555991e87e8aad97c0deefe55b5 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 15:46:31 -0700 Subject: [PATCH 057/269] tests/c_lib: Don't test undefined behavior of asctime and asctime_r These functions requre non-null parameters; passing them NULL values is undefined. Remove tests which are not valid. Signed-off-by: Keith Packard --- tests/lib/c_lib/common/src/main.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/tests/lib/c_lib/common/src/main.c b/tests/lib/c_lib/common/src/main.c index 2e1f5cdf4cbb43a..d2148f8a4b7c5ed 100644 --- a/tests/lib/c_lib/common/src/main.c +++ b/tests/lib/c_lib/common/src/main.c @@ -1118,11 +1118,6 @@ ZTEST(libc_common, test_time_asctime) zassert_equal(strncmp("Fri Jun 1 14:30:10 2024\n", asctime(&tp), sizeof(buf)), 0); if (IS_ENABLED(CONFIG_COMMON_LIBC_ASCTIME_R)) { - zassert_is_null(asctime_r(NULL, buf)); - zassert_is_null(asctime(NULL)); - - zassert_is_null(asctime_r(&tp, NULL)); - tp.tm_wday = 8; zassert_is_null(asctime_r(&tp, buf)); zassert_is_null(asctime(&tp)); From 962e42cf1d34f3857ec20c6e118884708baca8c1 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 15:15:41 -0700 Subject: [PATCH 058/269] tests, samples: Define _POSIX_C_SOURCE where needed Various tests and samples use POSIX-only functions. Define _POSIX_C_SOURCE to ensure they are visible. Signed-off-by: Keith Packard --- samples/posix/gettimeofday/src/main.c | 2 ++ tests/lib/c_lib/common/src/main.c | 2 -- tests/posix/fs/src/test_fs_dir.c | 3 +++ tests/posix/fs/src/test_fs_stat.c | 3 +++ 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/samples/posix/gettimeofday/src/main.c b/samples/posix/gettimeofday/src/main.c index 182debd5f9f5d06..922be148a778916 100644 --- a/samples/posix/gettimeofday/src/main.c +++ b/samples/posix/gettimeofday/src/main.c @@ -4,6 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L #include #include #include diff --git a/tests/lib/c_lib/common/src/main.c b/tests/lib/c_lib/common/src/main.c index d2148f8a4b7c5ed..7a0e0dbd6b2e85b 100644 --- a/tests/lib/c_lib/common/src/main.c +++ b/tests/lib/c_lib/common/src/main.c @@ -15,10 +15,8 @@ * it guarantee that ALL functionality provided is working correctly. */ -#if defined(CONFIG_NATIVE_LIBC) #undef _POSIX_C_SOURCE #define _POSIX_C_SOURCE 200809L -#endif #include #include diff --git a/tests/posix/fs/src/test_fs_dir.c b/tests/posix/fs/src/test_fs_dir.c index e52741276f5de68..9cd58525ad19939 100644 --- a/tests/posix/fs/src/test_fs_dir.c +++ b/tests/posix/fs/src/test_fs_dir.c @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L + #include #include #include diff --git a/tests/posix/fs/src/test_fs_stat.c b/tests/posix/fs/src/test_fs_stat.c index 14167d3f7756c0f..469abcdca45be59 100644 --- a/tests/posix/fs/src/test_fs_stat.c +++ b/tests/posix/fs/src/test_fs_stat.c @@ -4,6 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809L + #include #include #include From 2803d4bbb47b6303a01f4a1d1d52bd6472c8a238 Mon Sep 17 00:00:00 2001 From: Keith Packard Date: Thu, 12 Sep 2024 09:48:36 -0700 Subject: [PATCH 059/269] picolibc: Update to version 1.8.7 Integrate new upstream release. Include strnlen_s and aarch64 cmake fixes. Signed-off-by: Keith Packard --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 87c90565d468acf..5d9338703ac077b 100644 --- a/west.yml +++ b/west.yml @@ -315,7 +315,7 @@ manifest: - debug - name: picolibc path: modules/lib/picolibc - revision: 764ef4e401a8f4c6a86ab723533841f072885a5b + revision: 06bde1fd7531b1f788f6e42b6f7b358c0fe4f814 - name: segger revision: b011c45b585e097d95d9cf93edf4f2e01588d3cd path: modules/debug/segger From cc6ba101428f17f257e073900ea28a5f2e48c581 Mon Sep 17 00:00:00 2001 From: Raffael Rostagno Date: Thu, 12 Sep 2024 10:11:39 -0300 Subject: [PATCH 060/269] soc: espressif: Default MCUboot mode for ESP32 family Include default MCUboot mode for all ESP32 chips Signed-off-by: Raffael Rostagno --- soc/espressif/Kconfig.sysbuild | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/espressif/Kconfig.sysbuild b/soc/espressif/Kconfig.sysbuild index c656630f937d5c9..e47a72954999321 100644 --- a/soc/espressif/Kconfig.sysbuild +++ b/soc/espressif/Kconfig.sysbuild @@ -2,5 +2,5 @@ # SPDX-License-Identifier: Apache-2.0 choice MCUBOOT_MODE - default MCUBOOT_MODE_OVERWRITE_ONLY if SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 || SOC_ESP32_PROCPU || SOC_SERIES_ESP32S2 || SOC_ESP32S3_PROCPU + default MCUBOOT_MODE_OVERWRITE_ONLY if SOC_FAMILY_ESPRESSIF_ESP32 endchoice From 0c13100797249ddac443e8c8d8a5ed19b48d4768 Mon Sep 17 00:00:00 2001 From: Mathieu Choplain Date: Thu, 12 Sep 2024 14:43:00 +0200 Subject: [PATCH 061/269] dts: bindings: power: add note on SMPS current limit for STM32WB0 Indicate in the STM32WB0 power controller binding that the SMPS output current limitation is a feature only available on STM32WB05 and STM32WB09. Signed-off-by: Mathieu Choplain --- dts/bindings/power/st,stm32wb0-pwr.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/dts/bindings/power/st,stm32wb0-pwr.yaml b/dts/bindings/power/st,stm32wb0-pwr.yaml index e5239ae80cdd044..ba71bc6009e3ced 100644 --- a/dts/bindings/power/st,stm32wb0-pwr.yaml +++ b/dts/bindings/power/st,stm32wb0-pwr.yaml @@ -28,7 +28,8 @@ properties: PRECHARGE: (also called BYPASS) - SMPS converter enabled - clock disabled - LDOs supply voltage: VDD (though SMPS) - - Supplied current limitation can be programmed + - Current supplied to LDOs can be limited + (feature only supported on STM32WB05 / STM32WB09) RUN: (also called ON) - SMPS converter enabled - clock enabled @@ -97,8 +98,12 @@ properties: description: | SMPS output current limit (in mA) - The default value corresponds to the hardware reset - configuration of 20 mA output current limit. + The default value of 20 mA corresponds to the maximal + output current allowed for the SMPS, and is also equal + to the hardware reset configuration. + + On STM32WB06 and STM32WB07, this property is ignored as + the output current limitation feature is not available. This property is only used if `smps-mode` is "PRECHARGE". enum: From 277504cfbc08e5be3260c5f22aca922aa1581772 Mon Sep 17 00:00:00 2001 From: Mathieu Choplain Date: Thu, 12 Sep 2024 14:12:56 +0200 Subject: [PATCH 062/269] soc: st: stm32wb0: support SoCs without SMPS output current limit The STM32WB06 and STM32WB07 SoCs do not support SMPS output current limit. This makes the LL_PWR_SetSMPSPrechargeLimitCurrent function and all the LL_PWR_SMPS_PRECH_LIMIT_CUR_xxx defines not visible when one of these SoCs is selected, resulting in a build failure. Fix this by only handling SMPS current limit when the feature is available. Signed-off-by: Mathieu Choplain --- soc/st/stm32/stm32wb0x/soc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/soc/st/stm32/stm32wb0x/soc.c b/soc/st/stm32/stm32wb0x/soc.c index fbc8dc212c183aa..546ae1a6195b53b 100644 --- a/soc/st/stm32/stm32wb0x/soc.c +++ b/soc/st/stm32/stm32wb0x/soc.c @@ -67,9 +67,11 @@ __used RAM_VR_TypeDef RAM_VR; (LL_PWR_SMPS_LPOPEN), \ (LL_PWR_NO_SMPS_LPOPEN)) +#if defined(PWR_CR5_SMPS_PRECH_CUR_SEL) #define SMPS_CURRENT_LIMIT \ _CONCAT(LL_PWR_SMPS_PRECH_LIMIT_CUR_, \ DT_STRING_UNQUOTED(PWRC, smps_current_limit)) +#endif /* PWR_CR5_SMPS_PRECH_CUR_SEL */ #define SMPS_OUTPUT_VOLTAGE \ _CONCAT(LL_PWR_SMPS_OUTPUT_VOLTAGE_, \ @@ -112,11 +114,15 @@ static void configure_smps(void) } if (SMPS_MODE == STM32WB0_SMPS_MODE_PRECHARGE) { +#if defined(PWR_CR5_SMPS_PRECH_CUR_SEL) /** - * SMPS should remain in PRECHARGE mode, but - * we still have to configure the current limit. + * SMPS should remain in PRECHARGE mode. + * We still have to configure the output current + * limit specified in Device Tree, though this + * can only be done if this SoC supports it. */ LL_PWR_SetSMPSPrechargeLimitCurrent(SMPS_CURRENT_LIMIT); +#endif /* PWR_CR5_SMPS_PRECH_CUR_SEL */ } else { /** * SMPS mode requested is RUN mode. Configure the output From 788d1a908ef85e918aa9a58ba3b028e3c11c6d7a Mon Sep 17 00:00:00 2001 From: Olivier Lesage Date: Thu, 12 Sep 2024 13:46:43 +0200 Subject: [PATCH 063/269] bluetooth: host: improve log for unhandled vs events Aligns the logging unhandled vs events with the regular ones. Now it prints out the code and length. Signed-off-by: Olivier Lesage --- subsys/bluetooth/host/hci_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 6a6ba4c2bfe6c13..adc215a67ea23b5 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -222,7 +222,8 @@ static void handle_vs_event(uint8_t event, struct net_buf *buf, err = handle_event_common(event, buf, handlers, num_handlers); if (err == -EOPNOTSUPP) { - LOG_WRN("Unhandled vendor-specific event: %s", bt_hex(buf->data, buf->len)); + LOG_WRN("Unhandled vendor-specific event 0x%02x len %u: %s", event, buf->len, + bt_hex(buf->data, buf->len)); } /* Other possible errors are handled by handle_event_common function */ From 14a72b5158fdf71b0f8e885b19a6b7d6aa84990e Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Thu, 12 Sep 2024 11:01:10 +0000 Subject: [PATCH 064/269] scripts: Plug TwisterStatus type gaps Some dict.get() calls did not use a TwisterStatus as a default value, thus using a NoneType where TwisterStatus should appear. Signed-off-by: Lukasz Mrugala --- scripts/ci/test_plan.py | 6 ++++-- scripts/pylib/twister/twisterlib/reports.py | 14 +++++++------- scripts/pylib/twister/twisterlib/statuses.py | 6 ++++++ scripts/pylib/twister/twisterlib/testplan.py | 6 ++---- scripts/tests/twister_blackbox/test_report.py | 3 ++- 5 files changed, 21 insertions(+), 14 deletions(-) diff --git a/scripts/ci/test_plan.py b/scripts/ci/test_plan.py index 20ab9a5772a4658..61305a75f4539c4 100755 --- a/scripts/ci/test_plan.py +++ b/scripts/ci/test_plan.py @@ -37,6 +37,8 @@ sys.path.append(os.path.join(zephyr_base, 'scripts')) import list_boards +from pylib.twister.twisterlib.statuses import TwisterStatus + def _get_match_fn(globs, regexes): # Constructs a single regex that tests for matches against the globs in @@ -469,12 +471,12 @@ def parse_args(): dup_free_set = set() logging.info(f'Total tests gathered: {len(f.all_tests)}') for ts in f.all_tests: - if ts.get('status') == 'filtered': + if TwisterStatus(ts.get('status')) == TwisterStatus.FILTER: continue n = ts.get("name") a = ts.get("arch") p = ts.get("platform") - if ts.get('status') == 'error': + if TwisterStatus(ts.get('status')) == TwisterStatus.ERROR: logging.info(f"Error found: {n} on {p} ({ts.get('reason')})") errors += 1 if (n, a, p,) not in dup_free_set: diff --git a/scripts/pylib/twister/twisterlib/reports.py b/scripts/pylib/twister/twisterlib/reports.py index 780f05f2424e177..c22310abb5f6412 100644 --- a/scripts/pylib/twister/twisterlib/reports.py +++ b/scripts/pylib/twister/twisterlib/reports.py @@ -65,7 +65,7 @@ def process_log(log_file): @staticmethod - def xunit_testcase(eleTestsuite, name, classname, status, ts_status, reason, duration, runnable, stats, log, build_only_as_skip): + def xunit_testcase(eleTestsuite, name, classname, status: TwisterStatus, ts_status: TwisterStatus, reason, duration, runnable, stats, log, build_only_as_skip): fails, passes, errors, skips = stats if status in [TwisterStatus.SKIP, TwisterStatus.FILTER]: @@ -127,7 +127,7 @@ def xunit_report_suites(self, json_file, filename): suites_to_report = all_suites # do not create entry if everything is filtered out if not self.env.options.detailed_skipped_report: - suites_to_report = list(filter(lambda d: d.get('status') != TwisterStatus.FILTER, all_suites)) + suites_to_report = list(filter(lambda d: TwisterStatus(d.get('status')) != TwisterStatus.FILTER, all_suites)) for suite in suites_to_report: duration = 0 @@ -149,9 +149,9 @@ def xunit_report_suites(self, json_file, filename): handler_time = suite.get('execution_time', 0) runnable = suite.get('runnable', 0) duration += float(handler_time) - ts_status = suite.get('status') + ts_status = TwisterStatus(suite.get('status')) for tc in suite.get("testcases", []): - status = tc.get('status') + status = TwisterStatus(tc.get('status')) reason = tc.get('reason', suite.get('reason', 'Unknown')) log = tc.get("log", suite.get("log")) @@ -197,7 +197,7 @@ def xunit_report(self, json_file, filename, selected_platform=None, full_report= suites = list(filter(lambda d: d['platform'] == platform, all_suites)) # do not create entry if everything is filtered out if not self.env.options.detailed_skipped_report: - non_filtered = list(filter(lambda d: d.get('status') != TwisterStatus.FILTER, suites)) + non_filtered = list(filter(lambda d: TwisterStatus(d.get('status')) != TwisterStatus.FILTER, suites)) if not non_filtered: continue @@ -221,13 +221,13 @@ def xunit_report(self, json_file, filename, selected_platform=None, full_report= runnable = ts.get('runnable', 0) duration += float(handler_time) - ts_status = ts.get('status') + ts_status = TwisterStatus(ts.get('status')) # Do not report filtered testcases if ts_status == TwisterStatus.FILTER and not self.env.options.detailed_skipped_report: continue if full_report: for tc in ts.get("testcases", []): - status = tc.get('status') + status = TwisterStatus(tc.get('status')) reason = tc.get('reason', ts.get('reason', 'Unknown')) log = tc.get("log", ts.get("log")) diff --git a/scripts/pylib/twister/twisterlib/statuses.py b/scripts/pylib/twister/twisterlib/statuses.py index 7297d7615d7014b..17b0709d75c4aa1 100644 --- a/scripts/pylib/twister/twisterlib/statuses.py +++ b/scripts/pylib/twister/twisterlib/statuses.py @@ -13,6 +13,12 @@ class TwisterStatus(str, Enum): def __str__(self): return str(self.value) + @classmethod + def _missing_(cls, value): + super()._missing_(value) + if value is None: + return TwisterStatus.NONE + # All statuses below this comment can be used for TestCase BLOCK = 'blocked' STARTED = 'started' diff --git a/scripts/pylib/twister/twisterlib/testplan.py b/scripts/pylib/twister/twisterlib/testplan.py index 3e84a5067150251..360040490de5439 100755 --- a/scripts/pylib/twister/twisterlib/testplan.py +++ b/scripts/pylib/twister/twisterlib/testplan.py @@ -624,8 +624,7 @@ def load_from_file(self, file, filter_platform=[]): instance.metrics['available_ram'] = ts.get('available_ram', 0) instance.metrics['available_rom'] = ts.get('available_rom', 0) - status = ts.get('status') - status = TwisterStatus(status) if status else TwisterStatus.NONE + status = TwisterStatus(ts.get('status')) reason = ts.get("reason", "Unknown") if status in [TwisterStatus.ERROR, TwisterStatus.FAIL]: if self.options.report_summary is not None: @@ -649,8 +648,7 @@ def load_from_file(self, file, filter_platform=[]): for tc in ts.get('testcases', []): identifier = tc['identifier'] - tc_status = tc.get('status') - tc_status = TwisterStatus(tc_status) if tc_status else TwisterStatus.NONE + tc_status = TwisterStatus(tc.get('status')) tc_reason = None # we set reason only if status is valid, it might have been # reset above... diff --git a/scripts/tests/twister_blackbox/test_report.py b/scripts/tests/twister_blackbox/test_report.py index d0347bbfb2d7937..523472c9e434131 100644 --- a/scripts/tests/twister_blackbox/test_report.py +++ b/scripts/tests/twister_blackbox/test_report.py @@ -19,6 +19,7 @@ # pylint: disable=no-name-in-module from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock, clear_log_in_test +from twisterlib.statuses import TwisterStatus from twisterlib.testplan import TestPlan @@ -414,7 +415,7 @@ def test_report_filtered(self, out_path, test_path, report_filtered, expected_fi testsuites = j.get('testsuites') assert testsuites, 'No testsuites found.' - statuses = [testsuite.get('status') for testsuite in testsuites] + statuses = [TwisterStatus(testsuite.get('status')) for testsuite in testsuites] filtered_status_count = statuses.count("filtered") assert filtered_status_count == expected_filtered_count, \ f'Expected {expected_filtered_count} filtered statuses, got {filtered_status_count}.' From 69d2c0f19e25fa709d4a9399d2a7290629ec332e Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Thu, 12 Sep 2024 13:06:54 +0200 Subject: [PATCH 065/269] cmake: add toolchain_ld_ macros to FindDeprecated Follow-up: #77887 The macros: - toolchain_ld_base - toolchain_ld_baremetal - toolchain_ld_cpp was deprecated in 5db1f1ae8f17a5f351e73fcc4aa45d52b2919505 but no check was added to FindDeprecated.cmake, meaning toolchains still providing those macros was not getting a proper deprecation warning. Signed-off-by: Torsten Rasmussen --- cmake/modules/FindDeprecated.cmake | 48 ++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/cmake/modules/FindDeprecated.cmake b/cmake/modules/FindDeprecated.cmake index bad0ab6ffe74a10..df0b6a3df51bf00 100644 --- a/cmake/modules/FindDeprecated.cmake +++ b/cmake/modules/FindDeprecated.cmake @@ -99,6 +99,54 @@ if("PYTHON_PREFER" IN_LIST Deprecated_FIND_COMPONENTS) endif() endif() +if("toolchain_ld_base" IN_LIST Deprecated_FIND_COMPONENTS) + # This code was deprecated after Zephyr v4.0.0 + list(REMOVE_ITEM Deprecated_FIND_COMPONENTS toolchain_ld_base) + + if(COMMAND toolchain_ld_base) + message(DEPRECATION + "The macro/function 'toolchain_ld_base' is deprecated. " + "Please use '${LINKER}/linker_flags.cmake' and define the appropriate " + "linker flags as properties instead. " + "See '${ZEPHYR_BASE}/cmake/linker/linker_flags_template.cmake' for " + "known linker properties." + ) + toolchain_ld_base() + endif() +endif() + +if("toolchain_ld_baremetal" IN_LIST Deprecated_FIND_COMPONENTS) + # This code was deprecated after Zephyr v4.0.0 + list(REMOVE_ITEM Deprecated_FIND_COMPONENTS toolchain_ld_baremetal) + + if(COMMAND toolchain_ld_baremetal) + message(DEPRECATION + "The macro/function 'toolchain_ld_baremetal' is deprecated. " + "Please use '${LINKER}/linker_flags.cmake' and define the appropriate " + "linker flags as properties instead. " + "See '${ZEPHYR_BASE}/cmake/linker/linker_flags_template.cmake' for " + "known linker properties." + ) + toolchain_ld_baremetal() + endif() +endif() + +if("toolchain_ld_cpp" IN_LIST Deprecated_FIND_COMPONENTS) + # This code was deprecated after Zephyr v4.0.0 + list(REMOVE_ITEM Deprecated_FIND_COMPONENTS toolchain_ld_cpp) + + if(COMMAND toolchain_ld_cpp) + message(DEPRECATION + "The macro/function 'toolchain_ld_cpp' is deprecated. " + "Please use '${LINKER}/linker_flags.cmake' and define the appropriate " + "linker flags as properties instead. " + "See '${ZEPHYR_BASE}/cmake/linker/linker_flags_template.cmake' for " + "known linker properties." + ) + toolchain_ld_cpp() + endif() +endif() + if(NOT "${Deprecated_FIND_COMPONENTS}" STREQUAL "") message(STATUS "The following deprecated component(s) could not be found: " "${Deprecated_FIND_COMPONENTS}") From e06c7fcbff44d38a560a7cbfe83dfd7b725ffb51 Mon Sep 17 00:00:00 2001 From: Johann Fischer Date: Thu, 12 Sep 2024 11:05:20 +0200 Subject: [PATCH 066/269] boards: nucleo_h7a3zi_q: do not force USB_DC_HAS_HS_SUPPORT SoC and the board have only full speed phy. Signed-off-by: Johann Fischer --- boards/st/nucleo_h7a3zi_q/Kconfig.defconfig | 12 ------------ 1 file changed, 12 deletions(-) delete mode 100644 boards/st/nucleo_h7a3zi_q/Kconfig.defconfig diff --git a/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig b/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig deleted file mode 100644 index e8fd3484ea72889..000000000000000 --- a/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32H7A3ZI-Q Nucleo board configuration - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H7A3ZI_Q - -config USB_DC_HAS_HS_SUPPORT - default y - depends on USB_DC_STM32 - -endif # BOARD_NUCLEO_H7A3ZI_Q From 0aec05963095ca290ac275feac5c9df57b443a2c Mon Sep 17 00:00:00 2001 From: Sylvio Alves Date: Wed, 11 Sep 2024 22:22:00 -0300 Subject: [PATCH 067/269] drivers: sdhc: esp32: remove unused code Removed unused entry in SDHC driver and initialize variables accordingly. Signed-off-by: Sylvio Alves --- drivers/sdhc/sdhc_esp32.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/sdhc/sdhc_esp32.c b/drivers/sdhc/sdhc_esp32.c index 686fd2ff8156b7c..e31fe92d9984441 100644 --- a/drivers/sdhc/sdhc_esp32.c +++ b/drivers/sdhc/sdhc_esp32.c @@ -1081,10 +1081,9 @@ static int sdhc_esp32_request(const struct device *dev, struct sdhc_command *cmd struct sdhc_data *data) { const struct sdhc_esp32_config *cfg = dev->config; - const sdmmc_dev_t *sdio_hw = cfg->sdio_hw; int retries = (int)(cmd->retries + 1); /* first try plus retries */ - uint32_t timeout_cfg; - int ret_esp; + uint32_t timeout_cfg = 0; + int ret_esp = 0; int ret = 0; /* convert command structures Zephyr vs ESP */ From 4b68043ebbe66af6d943a908d98b25fbe4aec0b9 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Mon, 9 Sep 2024 14:12:32 +0200 Subject: [PATCH 068/269] Bluetooth: MPL: Replace busy bool with atomic Replace the busy boolean flag with an atomic value. This prevents any race conditions with the MPL implementation. Modifies where the new atomic value is set and cleared so that initialization gets to finish before allowing any reads. Due to how the MPL is structured, and how a select cannot be rejected from OTS, this does not give a perfect solution. Ideally we need a separate object per OTS object, rather than a shared one, and/or the OTS implemenation would allow us to reject a select if the object is not currently available or ready. This commit does not fix the above issues, as that is a larger undertaking. Signed-off-by: Emil Gydesen --- subsys/bluetooth/audio/mpl.c | 102 ++++++++++++++++------------------- 1 file changed, 45 insertions(+), 57 deletions(-) diff --git a/subsys/bluetooth/audio/mpl.c b/subsys/bluetooth/audio/mpl.c index 6f1db9e7c0bc32b..c6a7897cbc9ee60 100644 --- a/subsys/bluetooth/audio/mpl.c +++ b/subsys/bluetooth/audio/mpl.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -279,6 +280,12 @@ enum mpl_objects { MPL_OBJ_SEARCH_RESULTS, }; +enum mpl_obj_flag { + MPL_OBJ_FLAG_BUSY, + + MPL_OBJ_FLAG_NUM_FLAGS, /* keep as last */ +}; + /* The active object */ /* Only a single object is selected or being added (active) at a time. */ /* And, except for the icon object, all objects can be created dynamically. */ @@ -287,8 +294,6 @@ struct obj_t { /* ID of the currently selected object*/ uint64_t selected_id; - bool busy; - /* Type of object being added, e.g. MPL_OBJ_ICON */ uint8_t add_type; @@ -302,15 +307,16 @@ struct obj_t { struct mpl_group *add_group; }; struct net_buf_simple *content; + + ATOMIC_DEFINE(flags, MPL_OBJ_FLAG_NUM_FLAGS); }; static struct obj_t obj = { .selected_id = 0, .add_type = MPL_OBJ_NONE, - .busy = false, .add_track = NULL, .add_group = NULL, - .content = NET_BUF_SIMPLE(CONFIG_BT_MPL_MAX_OBJ_SIZE) + .content = NET_BUF_SIMPLE(CONFIG_BT_MPL_MAX_OBJ_SIZE), }; /* Set up content buffer for the icon object */ @@ -475,13 +481,6 @@ static int add_icon_object(struct mpl_mediaplayer *pl) const struct bt_uuid *icon_type = BT_UUID_OTS_TYPE_MPL_ICON; static char *icon_name = "Icon"; - if (obj.busy) { - /* TODO: Can there be a collision between select and internal */ - /* activities, like adding new objects? */ - LOG_ERR("Object busy"); - return 0; - } - obj.busy = true; obj.add_type = MPL_OBJ_ICON; obj.desc = &created_desc; @@ -496,7 +495,6 @@ static int add_icon_object(struct mpl_mediaplayer *pl) ret = bt_ots_obj_add(bt_mcs_get_ots(), &add_param); if (ret < 0) { LOG_WRN("Unable to add icon object, error %d", ret); - obj.busy = false; return ret; } @@ -512,11 +510,6 @@ static int add_current_track_segments_object(struct mpl_mediaplayer *pl) struct bt_ots_obj_created_desc created_desc = {}; const struct bt_uuid *segs_type = BT_UUID_OTS_TYPE_TRACK_SEGMENT; - if (obj.busy) { - LOG_ERR("Object busy"); - return 0; - } - obj.busy = true; obj.add_type = MPL_OBJ_TRACK_SEGMENTS; obj.desc = &created_desc; @@ -531,7 +524,6 @@ static int add_current_track_segments_object(struct mpl_mediaplayer *pl) ret = bt_ots_obj_add(bt_mcs_get_ots(), &add_param); if (ret < 0) { LOG_WRN("Unable to add track segments object: %d", ret); - obj.busy = false; return ret; } @@ -547,17 +539,11 @@ static int add_track_object(struct mpl_track *track) const struct bt_uuid *track_type = BT_UUID_OTS_TYPE_TRACK; int ret; - if (obj.busy) { - LOG_ERR("Object busy"); - return 0; - } if (!track) { LOG_ERR("No track"); return -EINVAL; } - obj.busy = true; - obj.add_type = MPL_OBJ_TRACK; obj.add_track = track; obj.desc = &created_desc; @@ -573,7 +559,6 @@ static int add_track_object(struct mpl_track *track) ret = bt_ots_obj_add(bt_mcs_get_ots(), &add_param); if (ret < 0) { LOG_WRN("Unable to add track object: %d", ret); - obj.busy = false; return ret; } @@ -589,11 +574,6 @@ static int add_parent_group_object(struct mpl_mediaplayer *pl) struct bt_ots_obj_created_desc created_desc = {}; const struct bt_uuid *group_type = BT_UUID_OTS_TYPE_GROUP; - if (obj.busy) { - LOG_ERR("Object busy"); - return 0; - } - obj.busy = true; obj.add_type = MPL_OBJ_PARENT_GROUP; obj.desc = &created_desc; @@ -608,7 +588,6 @@ static int add_parent_group_object(struct mpl_mediaplayer *pl) ret = bt_ots_obj_add(bt_mcs_get_ots(), &add_param); if (ret < 0) { LOG_WRN("Unable to add parent group object"); - obj.busy = false; return ret; } @@ -624,18 +603,11 @@ static int add_group_object(struct mpl_group *group) const struct bt_uuid *group_type = BT_UUID_OTS_TYPE_GROUP; int ret; - if (obj.busy) { - LOG_ERR("Object busy"); - return 0; - } - if (!group) { LOG_ERR("No group"); return -EINVAL; } - obj.busy = true; - obj.add_type = MPL_OBJ_GROUP; obj.add_group = group; obj.desc = &created_desc; @@ -651,7 +623,6 @@ static int add_group_object(struct mpl_group *group) ret = bt_ots_obj_add(bt_mcs_get_ots(), &add_param); if (ret < 0) { LOG_WRN("Unable to add group object: %d", ret); - obj.busy = false; return ret; } @@ -729,13 +700,12 @@ static int on_obj_deleted(struct bt_ots *ots, struct bt_conn *conn, static void on_obj_selected(struct bt_ots *ots, struct bt_conn *conn, uint64_t id) { - if (obj.busy) { + if (atomic_test_and_set_bit(obj.flags, MPL_OBJ_FLAG_BUSY)) { /* TODO: Can there be a collision between select and internal */ /* activities, like adding new objects? */ LOG_ERR("Object busy - select not performed"); return; } - obj.busy = true; LOG_DBG_OBJ_ID("Object Id selected: ", id); @@ -764,18 +734,20 @@ static void on_obj_selected(struct bt_ots *ots, struct bt_conn *conn, (void)setup_group_object(media_player.group); } else { LOG_ERR("Unknown Object ID"); - obj.busy = false; + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); return; } obj.selected_id = id; - obj.busy = false; + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); } static int on_obj_created(struct bt_ots *ots, struct bt_conn *conn, uint64_t id, const struct bt_ots_obj_add_param *add_param, struct bt_ots_obj_created_desc *created_desc) { + /* Objects are always created locally so we do not need to check for MPL_OBJ_FLAG_BUSY */ + LOG_DBG_OBJ_ID("Object Id created: ", id); *created_desc = *obj.desc; @@ -830,24 +802,19 @@ static int on_obj_created(struct bt_ots *ots, struct bt_conn *conn, uint64_t id, LOG_DBG("Unknown Object ID"); } - if (obj.add_type == MPL_OBJ_NONE) { - obj.busy = false; - } return 0; } - static ssize_t on_object_send(struct bt_ots *ots, struct bt_conn *conn, uint64_t id, void **data, size_t len, off_t offset) { - if (obj.busy) { + if (atomic_test_and_set_bit(obj.flags, MPL_OBJ_FLAG_BUSY)) { /* TODO: Can there be a collision between select and internal */ /* activities, like adding new objects? */ LOG_ERR("Object busy"); - return 0; + return -EBUSY; } - obj.busy = true; if (IS_ENABLED(CONFIG_BT_MPL_LOG_LEVEL_DBG)) { char t[BT_OTS_OBJ_ID_STR_LEN]; @@ -857,20 +824,20 @@ static ssize_t on_object_send(struct bt_ots *ots, struct bt_conn *conn, if (id != obj.selected_id) { LOG_ERR("Read from unselected object"); - obj.busy = false; - return 0; + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); + return -EINVAL; } if (!data) { LOG_DBG("Read complete"); - obj.busy = false; + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); return 0; } if (offset >= obj.content->len) { LOG_DBG("Offset too large"); - obj.busy = false; - return 0; + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); + return -EINVAL; } if (IS_ENABLED(CONFIG_BT_MPL_LOG_LEVEL_DBG)) { @@ -880,7 +847,8 @@ static ssize_t on_object_send(struct bt_ots *ots, struct bt_conn *conn, } *data = &obj.content->data[offset]; - obj.busy = false; + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); + return MIN(len, obj.content->len - offset); } @@ -2357,14 +2325,29 @@ int media_proxy_pl_init(void) */ #ifdef CONFIG_BT_MCS #ifdef CONFIG_BT_MPL_OBJECTS + /* The test here is arguably needed as the objects cannot be accessed before bt_mcs_init is + * called, but the set is to avoid the objects being accessed before properly initialized + */ + if (atomic_test_and_set_bit(obj.flags, MPL_OBJ_FLAG_BUSY)) { + LOG_ERR("Object busy"); + return -EBUSY; + } + ret = bt_mcs_init(&ots_cbs); + if (ret < 0) { + LOG_ERR("Could not init MCS: %d", ret); + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); + + return ret; + } #else ret = bt_mcs_init(NULL); -#endif /* CONFIG_BT_MPL_OBJECTS */ if (ret < 0) { LOG_ERR("Could not init MCS: %d", ret); return ret; } +#endif /* CONFIG_BT_MPL_OBJECTS */ + /* TODO: If anything below fails we should unregister MCS */ #else LOG_WRN("MCS not configured"); #endif /* CONFIG_BT_MCS */ @@ -2380,6 +2363,7 @@ int media_proxy_pl_init(void) ret = add_icon_object(&media_player); if (ret < 0) { LOG_ERR("Unable to add icon object, error %d", ret); + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); return ret; } @@ -2387,6 +2371,7 @@ int media_proxy_pl_init(void) ret = add_group_and_track_objects(&media_player); if (ret < 0) { LOG_ERR("Error adding tracks and groups to OTS, error %d", ret); + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); return ret; } @@ -2396,8 +2381,11 @@ int media_proxy_pl_init(void) ret = add_current_track_segments_object(&media_player); if (ret < 0) { LOG_ERR("Error adding Track Segments Object to OTS, error %d", ret); + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); return ret; } + + atomic_clear_bit(obj.flags, MPL_OBJ_FLAG_BUSY); #endif /* CONFIG_BT_MPL_OBJECTS */ /* Set up the calls structure */ From 9dd25adc79442a305d33b39ae91f9f4dc5ba1696 Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Thu, 22 Aug 2024 23:22:11 +0200 Subject: [PATCH 069/269] dts: add fracn to STM32H7 PLL clocks add fracn to STM32H7 pll clock binding Signed-off-by: Nathan Olff --- dts/bindings/clock/st,stm32h7-pll-clock.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml index ab6afacb880c085..2e441876116ea19 100644 --- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml +++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml @@ -65,3 +65,9 @@ properties: description: | PLL division factor for pllx_r_ck Valid range: 1 - 128 + + fracn: + type: int + description: | + PLLx FRACN value + Valid range: 0 - 8191 From f979252ceab52f0643cfa2bc5c17d27985a7890f Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Thu, 22 Aug 2024 23:28:33 +0200 Subject: [PATCH 070/269] drivers: use fracn in clock stm32h7 driver use fracn value if defined for each PLL 1, 2 and 3 based on stm32u5 code Signed-off-by: Nathan Olff --- drivers/clock_control/clock_stm32_ll_h7.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index cb216bc59e565b5..658796385e27cf0 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -800,8 +800,11 @@ static int set_up_plls(void) LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER); - /* FRACN disable DIVP,DIVQ,DIVR enable*/ LL_RCC_PLL1FRACN_Disable(); + if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) { + LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE); + LL_RCC_PLL1FRACN_Enable(); + } if (IS_ENABLED(STM32_PLL_P_ENABLED)) { LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR); @@ -846,6 +849,10 @@ static int set_up_plls(void) LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER); LL_RCC_PLL2FRACN_Disable(); + if (IS_ENABLED(STM32_PLL2_FRACN_ENABLED)) { + LL_RCC_PLL2_SetFRACN(STM32_PLL2_FRACN_VALUE); + LL_RCC_PLL2FRACN_Enable(); + } if (IS_ENABLED(STM32_PLL2_P_ENABLED)) { LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR); @@ -896,6 +903,10 @@ static int set_up_plls(void) LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER); LL_RCC_PLL3FRACN_Disable(); + if (IS_ENABLED(STM32_PLL3_FRACN_ENABLED)) { + LL_RCC_PLL3_SetFRACN(STM32_PLL3_FRACN_VALUE); + LL_RCC_PLL3FRACN_Enable(); + } if (IS_ENABLED(STM32_PLL3_P_ENABLED)) { LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR); From 7a094e376f5327d48f9d83384016aa805e4239c5 Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Mon, 9 Sep 2024 09:09:05 +0200 Subject: [PATCH 071/269] drivers: clocks: remove check for sysclock in h7 clocks remove check for system clock frequency in clock_stm32_ll_h7 because of addition of fracn (difficult to handle) Signed-off-by: Nathan Olff --- drivers/clock_control/clock_stm32_ll_h7.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 658796385e27cf0..3e31661b58966c8 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -160,10 +160,6 @@ #error "APB4 frequency is too high!" #endif -#if SYSCLK_FREQ != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -#error "SYS clock frequency for M7 core doesn't match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC" -#endif - /* end of clock feasibility check */ #endif /* CONFIG_CPU_CORTEX_M7 */ From eb3f718b2c20526b3a38ca06a7786429ea38e4c7 Mon Sep 17 00:00:00 2001 From: Nathan Olff Date: Mon, 9 Sep 2024 13:38:16 +0200 Subject: [PATCH 072/269] tests: drivers: add fracn test for stm32h7 clock configuration tests add overlay to use fracn with HSI in clock configuration tests for stm32h7 Signed-off-by: Nathan Olff --- .../boards/pll_hsi_fracn_550.overlay | 37 +++++++++++++++++++ .../stm32h7_core/testcase.yaml | 7 ++++ 2 files changed, 44 insertions(+) create mode 100644 tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay new file mode 100644 index 000000000000000..21ba087efbf2b20 --- /dev/null +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/pll_hsi_fracn_550.overlay @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2024 Kickmaker + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Warning: This overlay performs configuration from clean sheet. + * It is assumed that it is applied after clear_clocks.overlay file. + */ + +&clk_hsi { + hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ + status = "okay"; +}; + +&pll { + div-m = <4>; + mul-n = <34>; + div-p = <1>; + div-q = <4>; + div-r = <2>; + clocks = <&clk_hsi>; + fracn = <3072>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml index 8b868d3618a82d7..795de1a64bb5b05 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/testcase.yaml @@ -46,3 +46,10 @@ tests: - stm32h735g_disco integration_platforms: - nucleo_h723zg + drivers.clock.stm32_clock_configuration.h7_core.sysclksrc_pll_hsi_fracn_550: + extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_fracn_550.overlay" + platform_allow: + - nucleo_h723zg + - stm32h735g_disco + integration_platforms: + - nucleo_h723zg From e33e997c7d32a5860ee3085b598842aff89a15d1 Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Mon, 9 Sep 2024 13:56:42 +0200 Subject: [PATCH 073/269] dts: arm: st: u0: add dac node in dtsi file all stm32u0 boards have only one and same dac peripheral. Signed-off-by: Fabrice DJIATSA --- dts/arm/st/u0/stm32u0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dts/arm/st/u0/stm32u0.dtsi b/dts/arm/st/u0/stm32u0.dtsi index 4b7284bbf742ab3..4b1ebb80b49d9eb 100644 --- a/dts/arm/st/u0/stm32u0.dtsi +++ b/dts/arm/st/u0/stm32u0.dtsi @@ -209,6 +209,14 @@ status = "disabled"; }; + dac1: dac@40007400 { + compatible = "st,stm32-dac"; + reg = <0x40007400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>; + status = "disabled"; + #io-channel-cells = <1>; + }; + i2c1: i2c@40005400 { compatible = "st,stm32-i2c-v2"; clock-frequency = ; From 1ae6e61ec0b6ea553e6b58cb9bf36eceb99f7b24 Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Mon, 9 Sep 2024 13:59:53 +0200 Subject: [PATCH 074/269] boards: st: add dac node in dts file and update docs -enable dac in nucleo_u031r8, stm32u083c_dk and nucleo_u083rc - add dac as new supported interface in docs - update yaml files Signed-off-by: Fabrice DJIATSA --- boards/st/nucleo_u031r8/doc/index.rst | 3 +++ boards/st/nucleo_u031r8/nucleo_u031r8.dts | 6 ++++++ boards/st/nucleo_u031r8/nucleo_u031r8.yaml | 1 + boards/st/nucleo_u083rc/doc/index.rst | 2 ++ boards/st/nucleo_u083rc/nucleo_u083rc.dts | 6 ++++++ boards/st/nucleo_u083rc/nucleo_u083rc.yaml | 3 +++ boards/st/stm32u083c_dk/doc/index.rst | 2 ++ boards/st/stm32u083c_dk/stm32u083c_dk.dts | 6 ++++++ boards/st/stm32u083c_dk/stm32u083c_dk.yaml | 3 +++ 9 files changed, 32 insertions(+) diff --git a/boards/st/nucleo_u031r8/doc/index.rst b/boards/st/nucleo_u031r8/doc/index.rst index 9df168c0fad291b..490012ddc819a6d 100644 --- a/boards/st/nucleo_u031r8/doc/index.rst +++ b/boards/st/nucleo_u031r8/doc/index.rst @@ -140,6 +140,8 @@ The Zephyr _nucleo_u031r8_ board configuration supports the following hardware f +-----------+------------+-------------------------------------+ | NVIC | on-chip | nested vector interrupt controller | +-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ @@ -160,6 +162,7 @@ For more details please refer to `STM32U031 User Manual`_. Default Zephyr Peripheral Mapping: ---------------------------------- +- DAC1_OUT1 : PA4 - LD1 : PA5 - UART_1_TX : PA9 - UART_1_RX : PA10 diff --git a/boards/st/nucleo_u031r8/nucleo_u031r8.dts b/boards/st/nucleo_u031r8/nucleo_u031r8.dts index 5d5a834a2fece68..e6875786e03bcd8 100644 --- a/boards/st/nucleo_u031r8/nucleo_u031r8.dts +++ b/boards/st/nucleo_u031r8/nucleo_u031r8.dts @@ -82,6 +82,12 @@ apb1-prescaler = <1>; }; +&dac1 { + status = "okay"; + pinctrl-0 = <&dac1_out1_pa4>; + pinctrl-names = "default"; +}; + &i2c1 { pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_u031r8/nucleo_u031r8.yaml b/boards/st/nucleo_u031r8/nucleo_u031r8.yaml index 2e2438871b3db81..7995c39a1c63e6d 100644 --- a/boards/st/nucleo_u031r8/nucleo_u031r8.yaml +++ b/boards/st/nucleo_u031r8/nucleo_u031r8.yaml @@ -6,6 +6,7 @@ toolchain: - zephyr supported: - arduino_gpio + - dac - gpio - i2c - usart diff --git a/boards/st/nucleo_u083rc/doc/index.rst b/boards/st/nucleo_u083rc/doc/index.rst index dd6e3db0e837520..e8e7f43e092ab13 100644 --- a/boards/st/nucleo_u083rc/doc/index.rst +++ b/boards/st/nucleo_u083rc/doc/index.rst @@ -146,6 +146,8 @@ The Zephyr nucleo_u083rc board configuration supports the following hardware fea | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.dts b/boards/st/nucleo_u083rc/nucleo_u083rc.dts index 6884bbb682a8a00..5d3bfe02f85b89d 100644 --- a/boards/st/nucleo_u083rc/nucleo_u083rc.dts +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.dts @@ -82,6 +82,12 @@ apb1-prescaler = <1>; }; +&dac1 { + status = "okay"; + pinctrl-0 = <&dac1_out1_pa4>; + pinctrl-names = "default"; +}; + &i2c1 { pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>; pinctrl-names = "default"; diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.yaml b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml index fd2abf4fb32ebbc..1dc624d55c11caf 100644 --- a/boards/st/nucleo_u083rc/nucleo_u083rc.yaml +++ b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml @@ -7,7 +7,10 @@ toolchain: - gnuarmemb - xtools supported: + - arduino_gpio + - dac - gpio - i2c + - usart ram: 40 flash: 256 diff --git a/boards/st/stm32u083c_dk/doc/index.rst b/boards/st/stm32u083c_dk/doc/index.rst index d2f098b6b60b80e..52f419f804ae076 100644 --- a/boards/st/stm32u083c_dk/doc/index.rst +++ b/boards/st/stm32u083c_dk/doc/index.rst @@ -159,6 +159,8 @@ The Zephyr stm32u083c_dk board configuration supports the following hardware fea | UART | on-chip | serial port-polling; | | | | serial port-interrupt | +-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ | I2C | on-chip | i2c | +-----------+------------+-------------------------------------+ diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.dts b/boards/st/stm32u083c_dk/stm32u083c_dk.dts index a6e545d0f6a439e..05a1485163f5328 100644 --- a/boards/st/stm32u083c_dk/stm32u083c_dk.dts +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.dts @@ -72,6 +72,12 @@ apb1-prescaler = <1>; }; +&dac1 { + status = "okay"; + pinctrl-0 = <&dac1_out1_pa4>; + pinctrl-names = "default"; +}; + &i2c1 { pinctrl-0 = <&i2c1_scl_pa9 &i2c1_sda_pa10>; pinctrl-names = "default"; diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.yaml b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml index 7c6ce1095192fc5..615f17f1c8e5ca2 100644 --- a/boards/st/stm32u083c_dk/stm32u083c_dk.yaml +++ b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml @@ -7,7 +7,10 @@ toolchain: - gnuarmemb - xtools supported: + - arduino_gpio + - dac - gpio - i2c + - usart ram: 40 flash: 256 From f7ebd61ae999403e1c72c4ca52cffc74e3bbd66a Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Mon, 9 Sep 2024 14:00:35 +0200 Subject: [PATCH 075/269] tests: drivers: dac: dac_api: src: update dac_api driver test -add nucleo_u083rc and stm32u083c_dk boards for testbench purpose. - add min_ram property to skip test on boards with little ram size. Signed-off-by: Fabrice DJIATSA --- tests/drivers/dac/dac_api/src/test_dac.c | 2 ++ tests/drivers/dac/dac_api/testcase.yaml | 1 + 2 files changed, 3 insertions(+) diff --git a/tests/drivers/dac/dac_api/src/test_dac.c b/tests/drivers/dac/dac_api/src/test_dac.c index 134b9fcc46c77a5..2cec3405838ca8e 100644 --- a/tests/drivers/dac/dac_api/src/test_dac.c +++ b/tests/drivers/dac/dac_api/src/test_dac.c @@ -26,7 +26,9 @@ defined(CONFIG_BOARD_NUCLEO_L552ZE_Q) || \ defined(CONFIG_BOARD_STM32L562E_DK) || \ defined(CONFIG_BOARD_STM32H573I_DK) || \ + defined(CONFIG_BOARD_STM32U083C_DK) || \ defined(CONFIG_BOARD_B_U585I_IOT02A) || \ + defined(CONFIG_BOARD_NUCLEO_U083RC) || \ defined(CONFIG_BOARD_NUCLEO_U575ZI_Q) || \ defined(CONFIG_BOARD_NUCLEO_U5A5ZJ_Q) || \ defined(CONFIG_BOARD_NUCLEO_WL55JC) || \ diff --git a/tests/drivers/dac/dac_api/testcase.yaml b/tests/drivers/dac/dac_api/testcase.yaml index acae79039dcb76d..3537bc3d63e340f 100644 --- a/tests/drivers/dac/dac_api/testcase.yaml +++ b/tests/drivers/dac/dac_api/testcase.yaml @@ -6,3 +6,4 @@ common: tests: drivers.dac.api: depends_on: dac + min_ram: 16 From 1bea5fcacb6b85d5a0411a126e9fb6cbbbe38d13 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Wed, 4 Sep 2024 10:09:52 +0200 Subject: [PATCH 076/269] sysbuild: fix extra kconfig targets when using sysbuild Zephyr provides a feature to hook in custom menuconfig implementations by setting EXTRA_KCONFIG_TARGETS and then defining the corresponding command to invoke as EXTRA_KCONFIG_TARGET_COMMAND_FOR_. This feature is broken with sysbuild because sysbuild will try to create multiple custom targets with identical names. This commit fix the sysbuild handling of extra kconfig targets. Signed-off-by: Torsten Rasmussen --- .../cmake/modules/sysbuild_extensions.cmake | 17 +++++++++++++++-- .../cmake/modules/sysbuild_kconfig.cmake | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake index c20fcdb1e5156da..c1b2513d192f572 100644 --- a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake +++ b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake @@ -332,7 +332,7 @@ function(ExternalZephyrProject_Add) menuconfig hardenconfig guiconfig - ${EXTRA_KCONFIG_TARGETS} + $CACHE{EXTRA_KCONFIG_TARGETS} ) if(NOT ZBUILD_APP_TYPE STREQUAL "MAIN") @@ -345,6 +345,16 @@ function(ExternalZephyrProject_Add) USES_TERMINAL ) endforeach() + + set(list_separator ",") + set(image_extra_kconfig_targets "-DEXTRA_KCONFIG_TARGETS=$CACHE{EXTRA_KCONFIG_TARGETS}") + string(REPLACE ";" "${list_separator}" image_extra_kconfig_targets "${image_extra_kconfig_targets}") + foreach(target $CACHE{EXTRA_KCONFIG_TARGETS}) + list(APPEND image_extra_kconfig_targets + -DEXTRA_KCONFIG_TARGET_COMMAND_FOR_${target}=$CACHE{EXTRA_KCONFIG_TARGET_COMMAND_FOR_${target}} + ) + endforeach() + include(ExternalProject) set(application_binary_dir ${CMAKE_BINARY_DIR}/${ZBUILD_APPLICATION}) ExternalProject_Add( @@ -352,9 +362,11 @@ function(ExternalZephyrProject_Add) SOURCE_DIR ${ZBUILD_SOURCE_DIR} BINARY_DIR ${application_binary_dir} CONFIGURE_COMMAND "" + LIST_SEPARATOR "${list_separator}" CMAKE_ARGS -DSYSBUILD:BOOL=True -DSYSBUILD_CACHE:FILEPATH=${sysbuild_cache_file} ${shared_cmake_vars_argument} + ${image_extra_kconfig_targets} BUILD_COMMAND ${CMAKE_COMMAND} --build . INSTALL_COMMAND "" BUILD_ALWAYS True @@ -453,7 +465,7 @@ function(ExternalZephyrProject_Cmake) " ${image_banner_header}\n" ) - ExternalProject_Get_Property(${ZCMAKE_APPLICATION} SOURCE_DIR BINARY_DIR CMAKE_ARGS) + ExternalProject_Get_Property(${ZCMAKE_APPLICATION} SOURCE_DIR BINARY_DIR CMAKE_ARGS LIST_SEPARATOR) get_target_property(${ZCMAKE_APPLICATION}_BOARD ${ZCMAKE_APPLICATION} BOARD) get_property(${ZCMAKE_APPLICATION}_CONF_SCRIPT TARGET ${ZCMAKE_APPLICATION} @@ -471,6 +483,7 @@ function(ExternalZephyrProject_Cmake) string(CONFIGURE "${config_content}" config_content) file(WRITE ${dotconfigsysbuild} ${config_content}) + string(REPLACE "${LIST_SEPARATOR}" "\\;" CMAKE_ARGS "${CMAKE_ARGS}") execute_process( COMMAND ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} diff --git a/share/sysbuild/cmake/modules/sysbuild_kconfig.cmake b/share/sysbuild/cmake/modules/sysbuild_kconfig.cmake index 2d563676ef61f5e..41094454116e072 100644 --- a/share/sysbuild/cmake/modules/sysbuild_kconfig.cmake +++ b/share/sysbuild/cmake/modules/sysbuild_kconfig.cmake @@ -11,6 +11,11 @@ set(EXTRA_KCONFIG_TARGET_COMMAND_FOR_sysbuild_guiconfig ) set(KCONFIG_TARGETS sysbuild_menuconfig sysbuild_guiconfig) +foreach(extra_target ${EXTRA_KCONFIG_TARGETS}) + set(EXTRA_KCONFIG_TARGET_COMMAND_FOR_sysbuild_${extra_target} + "${EXTRA_KCONFIG_TARGET_COMMAND_FOR_${extra_target}}" + ) +endforeach() list(TRANSFORM EXTRA_KCONFIG_TARGETS PREPEND "sysbuild_") zephyr_get(APPLICATION_CONFIG_DIR) From ec08e1c0e8dedc2076b44e48412cb5e68d8490ea Mon Sep 17 00:00:00 2001 From: IBEN EL HADJ MESSAOUD Marwa Date: Mon, 2 Sep 2024 21:39:26 +0200 Subject: [PATCH 077/269] drivers: ethernet: Modify RX thread creation and update KConfig This change will allow users to configure the Ethernet RX thread according to their specific real-time requirements. Adding preemptive threading helps to reduce jitter and the impact of Ethernet traffic on real-time performance. Signed-off-by: IBEN EL HADJ MESSAOUD Marwa --- drivers/ethernet/Kconfig.stm32_hal | 9 +++++++-- drivers/ethernet/eth_stm32_hal.c | 4 +++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/ethernet/Kconfig.stm32_hal b/drivers/ethernet/Kconfig.stm32_hal index 37adb49d7a23ca9..09fe20c05d5e7f8 100644 --- a/drivers/ethernet/Kconfig.stm32_hal +++ b/drivers/ethernet/Kconfig.stm32_hal @@ -46,10 +46,15 @@ config ETH_STM32_HAL_RX_THREAD_STACK_SIZE RX thread stack size config ETH_STM32_HAL_RX_THREAD_PRIO - int "RX thread priority" + int "STM32 Ethernet RX Thread Priority" default 2 help - RX thread priority + This option allows to configure the priority of the RX thread that + handles incoming Ethernet packets. + Switching between preemptive and cooperative scheduling can be done by + NET_TC_THREAD_PREEMPTIVE. + Preemptive scheduling can lead to more responsive handling of network traffic, + especially under high load. config ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER bool "Use DTCM for DMA buffers" diff --git a/drivers/ethernet/eth_stm32_hal.c b/drivers/ethernet/eth_stm32_hal.c index 3d852c85b64f97c..02ae6830f605116 100644 --- a/drivers/ethernet/eth_stm32_hal.c +++ b/drivers/ethernet/eth_stm32_hal.c @@ -1331,7 +1331,9 @@ static void eth_iface_init(struct net_if *iface) k_thread_create(&dev_data->rx_thread, dev_data->rx_thread_stack, K_KERNEL_STACK_SIZEOF(dev_data->rx_thread_stack), rx_thread, (void *) dev, NULL, NULL, - K_PRIO_COOP(CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO), + IS_ENABLED(CONFIG_NET_TC_THREAD_PREEMPTIVE) + ? K_PRIO_PREEMPT(CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO) + : K_PRIO_COOP(CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO), 0, K_NO_WAIT); k_thread_name_set(&dev_data->rx_thread, "stm_eth"); From 402f3d24c4f3b60d5319c023565ef71dcea98e7f Mon Sep 17 00:00:00 2001 From: Sven Ginka Date: Thu, 5 Sep 2024 21:03:14 +0200 Subject: [PATCH 078/269] soc: sensry: Add support for SY120-GBM and SY120-GEN1 Add soc support for Sensry's RISCV32 based SY1xx. Variants of the soc are GBM and GEN1. Signed-off-by: Sven Ginka --- dts/bindings/cpu/sensry,ganymed-sy1xx.yaml | 8 + dts/bindings/vendor-prefixes.txt | 1 + soc/sensry/CMakeLists.txt | 6 + soc/sensry/Kconfig | 8 + soc/sensry/Kconfig.defconfig | 8 + soc/sensry/Kconfig.soc | 10 + soc/sensry/ganymed/Kconfig | 11 + soc/sensry/ganymed/Kconfig.defconfig | 8 + soc/sensry/ganymed/Kconfig.soc | 4 + soc/sensry/ganymed/sy1xx/CMakeLists.txt | 16 ++ soc/sensry/ganymed/sy1xx/Kconfig | 10 + soc/sensry/ganymed/sy1xx/Kconfig.defconfig | 76 ++++++ soc/sensry/ganymed/sy1xx/Kconfig.soc | 21 ++ soc/sensry/ganymed/sy1xx/common/crt0.S | 144 ++++++++++ soc/sensry/ganymed/sy1xx/common/linker.ld | 255 ++++++++++++++++++ soc/sensry/ganymed/sy1xx/common/pad_ctrl.h | 44 +++ soc/sensry/ganymed/sy1xx/common/soc.c | 91 +++++++ soc/sensry/ganymed/sy1xx/common/soc.h | 48 ++++ soc/sensry/ganymed/sy1xx/common/udma.c | 180 +++++++++++++ soc/sensry/ganymed/sy1xx/common/udma.h | 151 +++++++++++ .../ganymed/sy1xx/common/vector_table.ld | 14 + soc/sensry/soc.yml | 10 + 22 files changed, 1124 insertions(+) create mode 100644 dts/bindings/cpu/sensry,ganymed-sy1xx.yaml create mode 100644 soc/sensry/CMakeLists.txt create mode 100644 soc/sensry/Kconfig create mode 100644 soc/sensry/Kconfig.defconfig create mode 100644 soc/sensry/Kconfig.soc create mode 100644 soc/sensry/ganymed/Kconfig create mode 100644 soc/sensry/ganymed/Kconfig.defconfig create mode 100644 soc/sensry/ganymed/Kconfig.soc create mode 100644 soc/sensry/ganymed/sy1xx/CMakeLists.txt create mode 100644 soc/sensry/ganymed/sy1xx/Kconfig create mode 100644 soc/sensry/ganymed/sy1xx/Kconfig.defconfig create mode 100644 soc/sensry/ganymed/sy1xx/Kconfig.soc create mode 100644 soc/sensry/ganymed/sy1xx/common/crt0.S create mode 100644 soc/sensry/ganymed/sy1xx/common/linker.ld create mode 100644 soc/sensry/ganymed/sy1xx/common/pad_ctrl.h create mode 100644 soc/sensry/ganymed/sy1xx/common/soc.c create mode 100644 soc/sensry/ganymed/sy1xx/common/soc.h create mode 100644 soc/sensry/ganymed/sy1xx/common/udma.c create mode 100644 soc/sensry/ganymed/sy1xx/common/udma.h create mode 100644 soc/sensry/ganymed/sy1xx/common/vector_table.ld create mode 100644 soc/sensry/soc.yml diff --git a/dts/bindings/cpu/sensry,ganymed-sy1xx.yaml b/dts/bindings/cpu/sensry,ganymed-sy1xx.yaml new file mode 100644 index 000000000000000..307716bb5201ce6 --- /dev/null +++ b/dts/bindings/cpu/sensry,ganymed-sy1xx.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +include: riscv,cpus.yaml + +description: Sensry Ganymed SY1xx Core CPU + +compatible: "sensry,sy1xx" diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index f5d378cf6ee5961..466ea9e3f3ce824 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -588,6 +588,7 @@ seirobotics Shenzhen SEI Robotics Co., Ltd semtech Semtech Corporation sensirion Sensirion AG sensortek Sensortek Technology Corporation +sensry sensry.io sff Small Form Factor Committee sgd Solomon Goldentek Display Corporation sgmicro SG Micro Corp diff --git a/soc/sensry/CMakeLists.txt b/soc/sensry/CMakeLists.txt new file mode 100644 index 000000000000000..0820b6c4468bc4b --- /dev/null +++ b/soc/sensry/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +zephyr_include_directories(${SOC_FAMILY}/${SOC_SERIES}/common) + +add_subdirectory_ifdef(CONFIG_SOC_SERIES_SY1XX ganymed/sy1xx) diff --git a/soc/sensry/Kconfig b/soc/sensry/Kconfig new file mode 100644 index 000000000000000..bc1354d83fc543a --- /dev/null +++ b/soc/sensry/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +if SOC_FAMILY_GANYMED + +rsource "*/Kconfig" + +endif # SOC_FAMILY_GANYMED diff --git a/soc/sensry/Kconfig.defconfig b/soc/sensry/Kconfig.defconfig new file mode 100644 index 000000000000000..c897a44a9347d90 --- /dev/null +++ b/soc/sensry/Kconfig.defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +if SOC_FAMILY_GANYMED + +rsource "*/Kconfig.defconfig" + +endif diff --git a/soc/sensry/Kconfig.soc b/soc/sensry/Kconfig.soc new file mode 100644 index 000000000000000..8265f00bfe27937 --- /dev/null +++ b/soc/sensry/Kconfig.soc @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config SOC_FAMILY_GANYMED + bool + +config SOC_FAMILY + default "ganymed" if SOC_FAMILY_GANYMED + +rsource "*/Kconfig.soc" diff --git a/soc/sensry/ganymed/Kconfig b/soc/sensry/ganymed/Kconfig new file mode 100644 index 000000000000000..5eaf4d8b092c03d --- /dev/null +++ b/soc/sensry/ganymed/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config SOC_FAMILY_GANYMED + select BUILD_OUTPUT_BIN + +if SOC_SERIES_SY1XX + +rsource "*/Kconfig" + +endif # SOC_SERIES_SY1XX diff --git a/soc/sensry/ganymed/Kconfig.defconfig b/soc/sensry/ganymed/Kconfig.defconfig new file mode 100644 index 000000000000000..0ea55630825c04e --- /dev/null +++ b/soc/sensry/ganymed/Kconfig.defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +if SOC_SERIES_SY1XX + +rsource "*/Kconfig.defconfig" + +endif diff --git a/soc/sensry/ganymed/Kconfig.soc b/soc/sensry/ganymed/Kconfig.soc new file mode 100644 index 000000000000000..958008661bfe613 --- /dev/null +++ b/soc/sensry/ganymed/Kconfig.soc @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +rsource "*/Kconfig.soc" diff --git a/soc/sensry/ganymed/sy1xx/CMakeLists.txt b/soc/sensry/ganymed/sy1xx/CMakeLists.txt new file mode 100644 index 000000000000000..d7fc17252295ab5 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/CMakeLists.txt @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +zephyr_include_directories(common) + +zephyr_compile_options(-march=rv32imc_zicsr -mabi=ilp32) + +zephyr_sources( + common/crt0.S + common/soc.c + common/udma.c +) + +zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors common/vector_table.ld) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sensry/ganymed/sy1xx/Kconfig b/soc/sensry/ganymed/sy1xx/Kconfig new file mode 100644 index 000000000000000..54d6d4930bb6181 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config SOC_SERIES_SY1XX + select RISCV + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_ZICSR + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_C diff --git a/soc/sensry/ganymed/sy1xx/Kconfig.defconfig b/soc/sensry/ganymed/sy1xx/Kconfig.defconfig new file mode 100644 index 000000000000000..3c60c5ce3294cb7 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/Kconfig.defconfig @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +if SOC_SERIES_SY1XX + +config RISCV_PMP + default n + +config RISCV_HAS_CLIC + default n + +config RISCV_VECTORED_MODE + default y + +config INCLUDE_RESET_VECTOR + default y + +config GEN_IRQ_VECTOR_TABLE + default y + +config RISCV_GENERIC_TOOLCHAIN + default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" + +config RV_BOOT_HART + # default cluster id 0x3e, core 0 (FC) => 0x3e0 == 992 + default 992 + +config RISCV_SOC_CONTEXT_SAVE + default n + +config RISCV_SOC_OFFSETS + default n + +config NUM_IRQS + default 32 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_SOC_HAS_ISR_STACKING + default n + +config DYNAMIC_INTERRUPTS + default y + +config GEN_ISR_TABLES + default y + +config RISCV_MCAUSE_EXCEPTION_MASK + default 0x1F + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 993 + +config USE_DT_CODE_PARTITION + default y + +config RISCV_SOC_HAS_CUSTOM_IRQ_LOCK_OPS + default n + +config RISCV_SOC_EXCEPTION_FROM_IRQ + default y + +config INIT_STACKS + default y + +config XIP + default n + +config TIMESLICE_SIZE + default 10 + +endif diff --git a/soc/sensry/ganymed/sy1xx/Kconfig.soc b/soc/sensry/ganymed/sy1xx/Kconfig.soc new file mode 100644 index 000000000000000..b117738bc1b322c --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/Kconfig.soc @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config SOC_SERIES_SY1XX + bool + select SOC_FAMILY_GANYMED + +config SOC_SERIES + default "sy1xx" if SOC_SERIES_SY1XX + +config SOC_SY120_GBM + bool + select SOC_SERIES_SY1XX + +config SOC_SY120_GEN1 + bool + select SOC_SERIES_SY1XX + +config SOC + default "sy120_gbm" if SOC_SY120_GBM + default "sy120_gen1" if SOC_SY120_GEN1 diff --git a/soc/sensry/ganymed/sy1xx/common/crt0.S b/soc/sensry/ganymed/sy1xx/common/crt0.S new file mode 100644 index 000000000000000..bbffbec92589498 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/crt0.S @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +#include + + +GTEXT(__initialize) + + # abs 0x0000 - entry point after bootloader +.section .pre_start, "ax" +.global __pre_start +__pre_start: + jal x0, __prestart_routine + + + # abs 0x0080 - will be checked by bootloader +.section .validity_marker, "ax" + .word 0xAA551234 + + # abs 0x0100 - text +.section .text, "ax" +__prestart_routine: + /* things that will be done prior to actually starting zephyr */ + csrwi mstatus, 0x00 + + /* Call into Zephyr initialization. */ + jal x0, __start + +GTEXT(__soc_is_irq) +SECTION_FUNC(exception.other, __soc_is_irq) + csrr a0, mcause + srli a0, a0, 31 + ret + +GTEXT(__soc_handle_irq) +SECTION_FUNC(exception.other, __soc_handle_irq) + ## clear pending interrupt + ret + +# we provide a "backup" isr table, if generation (ex. in tests) is disabled +.global _irq_vector_table +.weak _irq_vector_table +.section .text, "ax" +_irq_vector_table: +.option norvc; + + j __no_irq_handler0 + j __no_irq_handler1 + j __no_irq_handler2 + j __no_irq_handler3 + j __no_irq_handler4 + j __no_irq_handler5 + j __no_irq_handler6 + j __no_irq_handler7 + j __no_irq_handler8 + j __no_irq_handler9 + j __no_irq_handler10 + j __no_irq_handler11 + j __no_irq_handler12 + j __no_irq_handler13 + j __no_irq_handler14 + j __no_irq_handler15 + j __no_irq_handler16 + j __no_irq_handler17 + j __no_irq_handler18 + j __no_irq_handler19 + j __no_irq_handler20 + j __no_irq_handler21 + j __no_irq_handler22 + j __no_irq_handler23 + j __no_irq_handler24 + j __no_irq_handler25 + j __no_irq_handler26 + j __no_irq_handler27 + j __no_irq_handler28 + j __no_irq_handler29 + j __no_irq_handler30 + j __no_irq_handler31 + + +__no_irq_handler0: + j __no_irq_handler0 +__no_irq_handler1: + j __no_irq_handler1 +__no_irq_handler2: + j __no_irq_handler2 +__no_irq_handler3: + j __no_irq_handler3 +__no_irq_handler4: + j __no_irq_handler4 +__no_irq_handler5: + j __no_irq_handler5 +__no_irq_handler6: + j __no_irq_handler6 +__no_irq_handler7: + j __no_irq_handler7 +__no_irq_handler8: + j __no_irq_handler8 +__no_irq_handler9: + j __no_irq_handler9 +__no_irq_handler10: + j __no_irq_handler10 +__no_irq_handler11: + j __no_irq_handler11 +__no_irq_handler12: + j __no_irq_handler12 +__no_irq_handler13: + j __no_irq_handler13 +__no_irq_handler14: + j __no_irq_handler14 +__no_irq_handler15: + j __no_irq_handler15 +__no_irq_handler16: + j __no_irq_handler16 +__no_irq_handler17: + j __no_irq_handler17 +__no_irq_handler18: + j __no_irq_handler18 +__no_irq_handler19: + j __no_irq_handler19 +__no_irq_handler20: + j __no_irq_handler20 +__no_irq_handler21: + j __no_irq_handler21 +__no_irq_handler22: + j __no_irq_handler22 +__no_irq_handler23: + j __no_irq_handler23 +__no_irq_handler24: + j __no_irq_handler24 +__no_irq_handler25: + j __no_irq_handler25 +__no_irq_handler26: + j __no_irq_handler26 +__no_irq_handler27: + j __no_irq_handler27 +__no_irq_handler28: + j __no_irq_handler28 +__no_irq_handler29: + j __no_irq_handler29 +__no_irq_handler30: + j __no_irq_handler30 +__no_irq_handler31: + j __no_irq_handler31 diff --git a/soc/sensry/ganymed/sy1xx/common/linker.ld b/soc/sensry/ganymed/sy1xx/common/linker.ld new file mode 100644 index 000000000000000..49b38680a416035 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/linker.ld @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2013-2014 Wind River Systems, Inc. + * Copyright (c) 2016-2017 Jean-Paul Etienne + * Copyright (c) 2018 Foundries.io Ltd + * Copyright (c) 2024 sensry.io + * + * This file is based on: + * + * - include/arch/arm/cortex_m/scripts/linker.ld + * - include/arch/riscv/common/linker.ld + * - include/arch/riscv/pulpino/linker.ld + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include +#include +#include + +#define MPU_ALIGN(region_size) . = ALIGN(4) + +/* + * Extra efforts would need to be taken to ensure the IRQ handlers are within + * jumping distance of the vector table in non-XIP builds, so avoid them. + */ +#define ROMABLE_REGION ROM +#define RAMABLE_REGION RAM + +## ROM AREA ## +#define ROM_BASE 0x1C010100 +#define ROM_SIZE 0x5Fa00 + +## RAM AREA ## +#define RAM_BASE 0x1C070000 +#define RAM_SIZE 0x200000 + +MEMORY + { + L2_START (rx) : ORIGIN = 0x1c010000, LENGTH = 0x00000080 + L2_VALIDITY (rx) : ORIGIN = 0x1c010080, LENGTH = 0x00000080 + + ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE /* 392kb */ + RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE /* 2097kb */ + + L2_PRIV_CH0 : ORIGIN = 0x1c004100, LENGTH = 0x2000 /* uDMA access */ + + /* + * Special section, not included in the final binary, used + * to generate interrupt tables. See include/linker/intlist.ld. + */ + IDT_LIST : ORIGIN = 0xFFFFF7FF, LENGTH = 2K + } + +ENTRY(CONFIG_KERNEL_ENTRY) + +SECTIONS + { + + .pre_start MAX(0x1c010000,ALIGN(0x80)) : + { + KEEP(*(.pre_start)) + } > L2_START + + .validity_marker MAX(0x1c010080,ALIGN(0x80)) : + { + KEEP(*(.validity_marker)) + } > L2_VALIDITY + + /* uninitialized space for uDMA access */ + .udma_access (NOLOAD): { + . = ALIGN(4); + _udma_space_start = .; + *(.udma_access) + _udma_space_end = .; + } > L2_PRIV_CH0 + + #include + + + SECTION_PROLOGUE(.plt,,) + { + *(.plt) + } + + + SECTION_PROLOGUE(.iplt,,) + { + *(.iplt) + } + + + GROUP_START(ROM) + __rom_region_start = ROM_BASE; + + SECTION_PROLOGUE(_TEXT_SECTION_NAME,,) + { + + /* Located in generated directory. This file is populated by calling + * zephyr_linker_sources(ROM_START ...). This typically contains the vector + * table and debug information. + */ + #include + + __text_region_start = .; + + *(.text .text.*) + *(.gnu.linkonce.t.*) + *(.eh_frame) + + } GROUP_LINK_IN(ROM) + + __text_region_end = .; + + + __rodata_region_start = .; + + #include + #include + + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + { + . = ALIGN(4); + *(.srodata) + *(".srodata.*") + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ + #include + + } GROUP_LINK_IN(ROMABLE_REGION) + + #include + + __rodata_region_end = .; + + __rom_region_end = .; + GROUP_END(ROM) + + GROUP_START(RAM) + + SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,) + { + . = ALIGN(4); + _image_ram_start = .; + __data_region_start = .; + __data_start = .; + + *(.data) + *(.data.*) + *(.gnu.linkonce.s.*) + + /* https://groups.google.com/a/groups.riscv.org/d/msg/sw-dev/60IdaZj27dY/TKT3hbNlAgAJ */ + *(.sdata .sdata.* .gnu.linkonce.s.*) + *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) + + /* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ + #include + + __data_end = .; + + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + __data_size = __data_end - __data_start; + + + __data_load_start = LOADADDR(_DATA_SECTION_NAME); + + #include + #include + + /* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ + #include + + __data_region_end = .; + __data_region_load_start = LOADADDR(_DATA_SECTION_NAME); + + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + /* + * For performance, BSS section is assumed to be 4 byte aligned and + * a multiple of 4 bytes, so it can be cleared in words. + */ + . = ALIGN(4); + __bss_start = .; + + *(.bss .bss.*) + *(.sbss .sbss.*) + COMMON_SYMBOLS + + /* Ensure 4 byte alignment for the entire section. */ + . = ALIGN(4); + __bss_end = .; + } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) + + SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),) + { + /* + * This section is used for non-initialized objects that + * will not be cleared during the boot process. + */ + *(.noinit .noinit.*) + + /* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ + #include + + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ + #include + + /* Located in generated directory. This file is populated by the + * zephyr_linker_sources() Cmake function. + */ + #include + + #include + + GROUP_END(RAMABLE_REGION) + + #ifdef CONFIG_GEN_ISR_TABLES + /* Bogus section, post-processed during the build to initialize interrupts. */ + #include + #endif + + #include + + SECTION_PROLOGUE(.riscv.attributes, 0,) + { + KEEP(*(.riscv.attributes)) + KEEP(*(.gnu.attributes)) + } + + /* + * Pulpino toolchains emit these sections; we don't care about them, + * but need to avoid build system warnings about orphaned sections. + */ + SECTION_PROLOGUE(.Pulp_Chip.Info,,) + { + *(.Pulp_Chip.*) + } + + } diff --git a/soc/sensry/ganymed/sy1xx/common/pad_ctrl.h b/soc/sensry/ganymed/sy1xx/common/pad_ctrl.h new file mode 100644 index 000000000000000..2fa2656c83d6b6f --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/pad_ctrl.h @@ -0,0 +1,44 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#ifndef GANYMED_SY1XX_PAD_CTRL_H +#define GANYMED_SY1XX_PAD_CTRL_H + +#define PAD_CONFIG(pin_offset, SMT, SLEW, PULLUP, PULLDOWN, DRV, PMOD, DIR) \ + (((SMT << 7) | (SLEW << 6) | (PULLUP << 5) | (PULLDOWN << 4) | (DRV << 2) | (PMOD << 1) | \ + DIR) \ + << pin_offset) + +#define PAD_CONFIG_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET) + +#define PAD_CONFIG_ADDR_UART (PAD_CONFIG_ADDR + 0x020) +#define PAD_CONFIG_ADDR_SPI (PAD_CONFIG_ADDR + 0x02c) +#define PAD_CONFIG_ADDR_I2C (PAD_CONFIG_ADDR + 0x100) +#define PAD_CONFIG_ADDR_MAC (PAD_CONFIG_ADDR + 0x130) + +#define PAD_SMT_DISABLE 0 +#define PAD_SMT_ENABLE 1 + +#define PAD_SLEW_LOW 0 +#define PAD_SLEW_HIGH 1 + +#define PAD_PULLUP_DIS 0 +#define PAD_PULLUP_EN 1 + +#define PAD_PULLDOWN_DIS 0 +#define PAD_PULLDOWN_EN 1 + +#define PAD_DRIVE_2PF 0 +#define PAD_DRIVE_4PF 1 +#define PAD_DRIVE_8PF 2 +#define PAD_DRIVE_16PF 3 + +#define PAD_PMOD_NORMAL 0 +#define PAD_PMOD_TRISTATE 1 + +#define PAD_DIR_OUTPUT 0 +#define PAD_DIR_INPUT 1 + +#endif /* GANYMED_SY1XX_PAD_CTRL_H */ diff --git a/soc/sensry/ganymed/sy1xx/common/soc.c b/soc/sensry/ganymed/sy1xx/common/soc.c new file mode 100644 index 000000000000000..5f1ccb9ee862141 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/soc.c @@ -0,0 +1,91 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#include +#include + +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +#include +LOG_MODULE_REGISTER(soc); + +#include "soc.h" + +/* ITC */ +#define ARCHI_ITC_MASK_OFFSET 0x0 +#define ARCHI_ITC_MASK_SET_OFFSET 0x4 +#define ARCHI_ITC_MASK_CLR_OFFSET 0x8 +#define ARCHI_ITC_STATUS_OFFSET 0xc +#define ARCHI_ITC_STATUS_SET_OFFSET 0x10 +#define ARCHI_ITC_STATUS_CLR_OFFSET 0x14 +#define ARCHI_ITC_ACK_OFFSET 0x18 +#define ARCHI_ITC_ACK_SET_OFFSET 0x1c +#define ARCHI_ITC_ACK_CLR_OFFSET 0x20 +#define ARCHI_ITC_FIFO_OFFSET 0x24 + +void sys_arch_reboot(int type) +{ + ARG_UNUSED(type); +} + +#define ARCHI_REF_CLOCK (32768) +#define ARCHI_PER_CLOCK (125000000) + +uint32_t soc_get_rts_clock_frequency(void) +{ + return ARCHI_REF_CLOCK; +} + +uint32_t soc_get_peripheral_clock(void) +{ + return ARCHI_PER_CLOCK; +} + +void riscv_clic_irq_priority_set(uint32_t irq, uint32_t prio, uint32_t flags) +{ + /* we do not support priorities */ +} + +void soc_enable_irq(uint32_t idx) +{ + uint32_t current = sys_read32(ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_SET_OFFSET); + + sys_write32(current | (1 << (idx & 0x1f)), ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_SET_OFFSET); +} + +void soc_disable_irq(uint32_t idx) +{ + uint32_t current = sys_read32(ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_CLR_OFFSET); + + sys_write32(current & (~(1 << (idx & 0x1f))), + ARCHI_FC_ITC_ADDR + ARCHI_ITC_MASK_CLR_OFFSET); +} + +/* + * SoC-level interrupt initialization. Clear any pending interrupts or + * events, and find the INTMUX device if necessary. + * + * This gets called as almost the first thing z_cstart() does, so it + * will happen before any calls to the _arch_irq_xxx() routines above. + */ +void soc_interrupt_init(void) +{ +} + +/** + * @brief Perform basic hardware initialization + * + * Initializes the base clocks and LPFLL using helpers provided by the HAL. + * + * @return 0 + */ +static int soc_sy1xx_init(void) +{ + + return 0; +} + +SYS_INIT(soc_sy1xx_init, PRE_KERNEL_1, 0); diff --git a/soc/sensry/ganymed/sy1xx/common/soc.h b/soc/sensry/ganymed/sy1xx/common/soc.h new file mode 100644 index 000000000000000..fc47a3125f88a62 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/soc.h @@ -0,0 +1,48 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#ifndef GANYMED_SY1XX_SOC_H +#define GANYMED_SY1XX_SOC_H + +#ifndef _ASMLANGUAGE + +#include + +/* SOC PERIPHERALS */ + +#define ARCHI_SOC_PERIPHERALS_ADDR 0x1A100000 + +#define ARCHI_GPIO_OFFSET 0x00001000 +#define ARCHI_UDMA_OFFSET 0x00002000 +#define ARCHI_APB_SOC_CTRL_OFFSET 0x00004000 +#define ARCHI_SOC_EU_OFFSET 0x00006000 +#define ARCHI_FC_ITC_OFFSET 0x00009800 +#define ARCHI_FC_TIMER_OFFSET 0x0000B000 +#define ARCHI_STDOUT_OFFSET 0x0000F000 + +#define ARCHI_GPIO_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_GPIO_OFFSET) +#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET) +#define ARCHI_APB_SOC_CTRL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_APB_SOC_CTRL_OFFSET) +#define ARCHI_SOC_EU_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_SOC_EU_OFFSET) +#define ARCHI_FC_ITC_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET) +#define ARCHI_FC_TIMER_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET) +#define ARCHI_STDOUT_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_STDOUT_OFFSET) + +#define ARCHI_PLL_ADDR (ARCHI_SOC_PERIPHERALS_ADDR) +#define ARCHI_SECURE_MRAM_CTRL_ADDR 0x1D180000 +#define ARCHI_GLOBAL_MRAM_CTRL_ADDR 0x1E080000 +#define ARCHI_MRAM_EFUSE_ADDR 0x1D070100 +#define ARCHI_TSN_ADDR 0x1A120000 +#define ARCHI_CAN_ADDR 0x1A130000 + +uint32_t soc_get_rts_clock_frequency(void); +uint32_t soc_get_peripheral_clock(void); + +void soc_enable_irq(uint32_t idx); +void soc_disable_irq(uint32_t idx); + +#endif /* _ASMLANGUAGE */ + +#endif /* GANYMED_SY1XX_SOC_H */ diff --git a/soc/sensry/ganymed/sy1xx/common/udma.c b/soc/sensry/ganymed/sy1xx/common/udma.c new file mode 100644 index 000000000000000..752c84b91ce1aa6 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/udma.c @@ -0,0 +1,180 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#include "soc.h" +#include "udma.h" + +#define UDMA_CTRL_PER_CG (ARCHI_UDMA_ADDR + UDMA_CONF_OFFSET) + +#define DRIVERS_MAX_UART_COUNT 3 +#define DRIVERS_MAX_I2C_COUNT 4 +#define DRIVERS_MAX_SPI_COUNT 7 +#define DEVICE_MAX_ETH_COUNT 1 + +void drivers_udma_enable_clock(udma_module_t module, uint32_t instance) +{ + + uint32_t udma_ctrl_per_cg = sys_read32(UDMA_CTRL_PER_CG); + + switch (module) { + + case DRIVERS_UDMA_UART: + if (instance >= DRIVERS_MAX_UART_COUNT) { + return; + } + udma_ctrl_per_cg |= 1 << (instance + 0); + break; + + case DRIVERS_UDMA_I2C: + if (instance >= DRIVERS_MAX_I2C_COUNT) { + return; + } + udma_ctrl_per_cg |= 1 << (instance + 10); + break; + + case DRIVERS_UDMA_SPI: + if (instance >= DRIVERS_MAX_SPI_COUNT) { + return; + } + udma_ctrl_per_cg |= 1 << (instance + 3); + break; + + case DRIVERS_UDMA_MAC: + if (instance >= DEVICE_MAX_ETH_COUNT) { + return; + } + udma_ctrl_per_cg |= 1 << (instance + 20); + break; + + case DRIVERS_MAX_UDMA_COUNT: + break; + } + + sys_write32(udma_ctrl_per_cg, UDMA_CTRL_PER_CG); +} + +void drivers_udma_disable_clock(udma_module_t module, uint32_t instance) +{ + + uint32_t udma_ctrl_per_cg = sys_read32(UDMA_CTRL_PER_CG); + + switch (module) { + + case DRIVERS_UDMA_UART: + if (instance >= DRIVERS_MAX_UART_COUNT) { + return; + } + udma_ctrl_per_cg &= ~(1 << (instance + 0)); + break; + + case DRIVERS_UDMA_I2C: + if (instance >= DRIVERS_MAX_I2C_COUNT) { + return; + } + udma_ctrl_per_cg &= ~(1 << (instance + 10)); + break; + + case DRIVERS_UDMA_SPI: + if (instance >= DRIVERS_MAX_SPI_COUNT) { + return; + } + udma_ctrl_per_cg &= ~(1 << (instance + 3)); + break; + + case DRIVERS_UDMA_MAC: + if (instance >= DEVICE_MAX_ETH_COUNT) { + return; + } + udma_ctrl_per_cg &= ~(1 << (instance + 20)); + break; + + case DRIVERS_MAX_UDMA_COUNT: + break; + } + + sys_write32(udma_ctrl_per_cg, UDMA_CTRL_PER_CG); +} + +void drivers_udma_busy_delay(uint32_t msec) +{ + uint32_t sec = 250000000; + uint32_t millis = (sec / 1000) * msec; + + for (uint32_t i = 0; i < millis; i++) { + __asm__("nop"); + } +} + +int32_t drivers_udma_cancel(uint32_t base, uint32_t channel) +{ + uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; + + /* clear existing */ + UDMA_WRITE_REG(base, UDMA_CFG_REG + channel_offset, UDMA_CHANNEL_CFG_CLEAR); + return 0; +} + +int32_t drivers_udma_is_ready(uint32_t base, uint32_t channel) +{ + uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; + + int32_t isBusy = UDMA_READ_REG(base, UDMA_CFG_REG + channel_offset) & (UDMA_CHANNEL_CFG_EN); + + return isBusy ? 0 : 1; +} + +int32_t drivers_udma_wait_for_finished(uint32_t base, uint32_t channel) +{ + uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; + + volatile uint32_t timeout = 200; + + while (UDMA_READ_REG(base, UDMA_CFG_REG + channel_offset) & (UDMA_CHANNEL_CFG_EN)) { + drivers_udma_busy_delay(1); + timeout--; + if (timeout == 0) { + return -1; + } + } + + return 0; +} + +int32_t drivers_udma_wait_for_status(uint32_t base) +{ + + volatile uint32_t timeout = 200; + + while (UDMA_READ_REG(base, UDMA_STATUS) & (0x3)) { + drivers_udma_busy_delay(1); + timeout--; + if (timeout == 0) { + return -1; + } + } + + return 0; +} + +int32_t drivers_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size, + uint32_t optional_cfg) +{ + uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; + + UDMA_WRITE_REG(base, UDMA_SADDR_REG + channel_offset, saddr); + UDMA_WRITE_REG(base, UDMA_SIZE_REG + channel_offset, size); + UDMA_WRITE_REG(base, UDMA_CFG_REG + channel_offset, UDMA_CHANNEL_CFG_EN | optional_cfg); + + return 0; +} + +int32_t drivers_udma_get_remaining(uint32_t base, uint32_t channel) +{ + uint32_t channel_offset = channel == 0 ? 0x00 : 0x10; + + int32_t size = UDMA_READ_REG(base, UDMA_SIZE_REG + channel_offset); + + return size; +} diff --git a/soc/sensry/ganymed/sy1xx/common/udma.h b/soc/sensry/ganymed/sy1xx/common/udma.h new file mode 100644 index 000000000000000..cbb36b172cc20b5 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/udma.h @@ -0,0 +1,151 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#ifndef GANYMED_SY1XX_UDMA_H +#define GANYMED_SY1XX_UDMA_H + +#include +#include +#include + +/* UDMA */ +#define ARCHI_UDMA_ADDR (ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET) + +#define UDMA_PERIPH_AREA_SIZE_LOG2 7 +#define UDMA_PERIPH_OFFSET(id) (((id) << UDMA_PERIPH_AREA_SIZE_LOG2)) + +#define ARCHI_UDMA_UART_ID(id) (0 + (id)) +#define ARCHI_UDMA_SPIM_ID(id) (3 + (id)) +#define ARCHI_UDMA_I2C_ID(id) (10 + (id)) +#define ARCHI_UDMA_I2S_ID(id) (14 + (id)) +#define ARCHI_UDMA_HYPER_ID(id) (19 + (id)) +#define ARCHI_UDMA_TSN_ID(id) (20 + (id)) + +#define UDMA_CHANNEL_RX_OFFSET 0x00 +#define UDMA_CHANNEL_TX_OFFSET 0x10 +#define UDMA_CHANNEL_CUSTOM_OFFSET 0x20 + +/* + * For each channel, the RX and TX part have the following registers + * The offsets are given relative to the offset of the RX or TX part + */ + +/* Start address register */ +#define UDMA_CHANNEL_SADDR_OFFSET 0x0 +/* Size register */ +#define UDMA_CHANNEL_SIZE_OFFSET 0x4 +/* Configuration register */ +#define UDMA_CHANNEL_CFG_OFFSET 0x8 +/* Int configuration register */ +#define UDMA_CHANNEL_INTCFG_OFFSET 0xC + +/* + * The configuration register of the RX and TX parts for each channel can be accessed using the + * following bits + */ + +#define UDMA_CHANNEL_CFG_SHADOW_BIT (5) +#define UDMA_CHANNEL_CFG_CLEAR_BIT (5) +#define UDMA_CHANNEL_CFG_EN_BIT (4) +#define UDMA_CHANNEL_CFG_SIZE_BIT (1) +#define UDMA_CHANNEL_CFG_CONT_BIT (0) + +/* Indicates if a shadow transfer is there */ +#define UDMA_CHANNEL_CFG_SHADOW (1 << UDMA_CHANNEL_CFG_SHADOW_BIT) +/* Stop and clear all pending transfers */ +#define UDMA_CHANNEL_CFG_CLEAR (1 << UDMA_CHANNEL_CFG_CLEAR_BIT) +/* Start a transfer */ +#define UDMA_CHANNEL_CFG_EN (1 << UDMA_CHANNEL_CFG_EN_BIT) +/* Configure for 8-bits transfer */ +#define UDMA_CHANNEL_CFG_SIZE_8 (0 << UDMA_CHANNEL_CFG_SIZE_BIT) +/* Configure for 16-bits transfer */ +#define UDMA_CHANNEL_CFG_SIZE_16 (1 << UDMA_CHANNEL_CFG_SIZE_BIT) +/* Configure for 32-bits transfer */ +#define UDMA_CHANNEL_CFG_SIZE_32 (2 << UDMA_CHANNEL_CFG_SIZE_BIT) +/* Configure for continuous mode */ +#define UDMA_CHANNEL_CFG_CONT (1 << UDMA_CHANNEL_CFG_CONT_BIT) + +/* Configuration area offset */ +#define UDMA_CONF_OFFSET 0xF80 +/* Clock-gating control register */ +#define UDMA_CONF_CG_OFFSET 0x00 + +static inline void plp_udma_cg_set(unsigned int value) +{ + sys_write32(value, ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_UDMA_OFFSET + UDMA_CONF_OFFSET + + UDMA_CONF_CG_OFFSET); +} + +typedef enum { + DRIVERS_UDMA_UART, + DRIVERS_UDMA_I2C, + DRIVERS_UDMA_SPI, + DRIVERS_UDMA_MAC, + DRIVERS_MAX_UDMA_COUNT +} udma_module_t; + +void drivers_udma_enable_clock(udma_module_t module, uint32_t instance); +void drivers_udma_disable_clock(udma_module_t module, uint32_t instance); + +int32_t drivers_udma_cancel(uint32_t base, uint32_t channel); +int32_t drivers_udma_is_ready(uint32_t base, uint32_t channel); +int32_t drivers_udma_wait_for_finished(uint32_t base, uint32_t channel); +int32_t drivers_udma_wait_for_status(uint32_t base); +int32_t drivers_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size, + uint32_t optional_cfg); +int32_t drivers_udma_get_remaining(uint32_t base, uint32_t channel); + +typedef enum { + UDMA_SADDR_REG = 0x00, + UDMA_SIZE_REG = 0x04, + UDMA_CFG_REG = 0x08, + +} udma_regs_t; + +typedef enum { + UDMA_RX_SADDR_REG = 0x00, + UDMA_RX_SIZE_REG = 0x04, + UDMA_RX_CFG_REG = 0x08, + + UDMA_TX_SADDR_REG = 0x10, + UDMA_TX_SIZE_REG = 0x14, + UDMA_TX_CFG_REG = 0x18, + + UDMA_STATUS = 0x20, + UDMA_SETUP_REG = 0x24, +} udma_reg_t; + +#define UDMA_RX_DATA_ADDR_INC_SIZE_8 (0x0 << 1) +#define UDMA_RX_DATA_ADDR_INC_SIZE_16 (0x1 << 1) +#define UDMA_RX_DATA_ADDR_INC_SIZE_32 (0x2 << 1) + +#define UDMA_RX_CHANNEL 0 +#define UDMA_TX_CHANNEL 1 + +#define UDMA_READ_REG(udma_base, reg) sys_read32(udma_base + reg) +#define UDMA_WRITE_REG(udma_base, reg, value) sys_write32(value, udma_base + reg) + +#define UDMA_CANCEL_RX(udma_base) drivers_udma_cancel(udma_base, UDMA_RX_CHANNEL) +#define UDMA_CANCEL_TX(udma_base) drivers_udma_cancel(udma_base, UDMA_TX_CHANNEL) + +#define UDMA_IS_FINISHED_RX(udma_base) drivers_udma_is_ready(udma_base, UDMA_RX_CHANNEL) +#define UDMA_IS_FINISHED_TX(udma_base) drivers_udma_is_ready(udma_base, UDMA_TX_CHANNEL) + +#define UDMA_WAIT_FOR_FINISHED_RX(udma_base) \ + drivers_udma_wait_for_finished(udma_base, UDMA_RX_CHANNEL) +#define UDMA_WAIT_FOR_FINISHED_TX(udma_base) \ + drivers_udma_wait_for_finished(udma_base, UDMA_TX_CHANNEL) + +#define UDMA_START_RX(base, addr, size, cfg) \ + drivers_udma_start(base, UDMA_RX_CHANNEL, addr, size, cfg) +#define UDMA_START_TX(base, addr, size, cfg) \ + drivers_udma_start(base, UDMA_TX_CHANNEL, addr, size, cfg) + +#define UDMA_GET_REMAINING_RX(base) drivers_udma_get_remaining(base, UDMA_RX_CHANNEL) +#define UDMA_GET_REMAINING_TX(base) drivers_udma_get_remaining(base, UDMA_TX_CHANNEL) + +#define UDMA_WAIT_FOR_STATUS_IDLE(udma_base) drivers_udma_wait_for_status(udma_base) + +#endif /* GANYMED_SY1XX_UDMA_H */ diff --git a/soc/sensry/ganymed/sy1xx/common/vector_table.ld b/soc/sensry/ganymed/sy1xx/common/vector_table.ld new file mode 100644 index 000000000000000..374490a95c8bf87 --- /dev/null +++ b/soc/sensry/ganymed/sy1xx/common/vector_table.ld @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2019 Foundries.io Ltd + * Copyright (c) 2019 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +KEEP(*(.reset.*)) +KEEP(*(".exception.entry.*")) /* contains _isr_wrapper */ +*(".exception.other.*") + +KEEP(*(.openocd_debug)) +KEEP(*(".openocd_debug.*")) diff --git a/soc/sensry/soc.yml b/soc/sensry/soc.yml new file mode 100644 index 000000000000000..eaabb716db8c359 --- /dev/null +++ b/soc/sensry/soc.yml @@ -0,0 +1,10 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +family: + - name: ganymed + series: + - name: sy1xx + socs: + - name: sy120_gbm + - name: sy120_gen1 From 7443a2c7039763dd4d808bca364c38d65e93635a Mon Sep 17 00:00:00 2001 From: Sven Ginka Date: Thu, 5 Sep 2024 21:05:49 +0200 Subject: [PATCH 079/269] driver: serial: Add support for sy1xx Add uart driver for Sensry's RISCV32 based SY1xx. Signed-off-by: Sven Ginka --- drivers/serial/CMakeLists.txt | 1 + drivers/serial/Kconfig | 2 + drivers/serial/Kconfig.sy1xx | 10 + drivers/serial/uart_sy1xx.c | 319 +++++++++++++++++++++ dts/bindings/serial/sensry,sy1xx-uart.yaml | 21 ++ 5 files changed, 353 insertions(+) create mode 100644 drivers/serial/Kconfig.sy1xx create mode 100644 drivers/serial/uart_sy1xx.c create mode 100644 dts/bindings/serial/sensry,sy1xx-uart.yaml diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index 946f00cfddfcd1e..f264370f9a87f8e 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -79,6 +79,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c) zephyr_library_sources_ifdef(CONFIG_UART_SI32_USART uart_si32_usart.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE uart_handlers.c) zephyr_library_sources_ifdef(CONFIG_UART_SCI_RA uart_renesas_ra_sci.c) +zephyr_library_sources_ifdef(CONFIG_UART_SY1XX uart_sy1xx.c) if(CONFIG_UART_NATIVE_POSIX) zephyr_library_compile_definitions(NO_POSIX_CHEATS) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index cb4207d1200779a..673e38671f22372 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -280,6 +280,8 @@ rsource "Kconfig.rzt2m" rsource "Kconfig.renesas_ra8" +rsource "Kconfig.sy1xx" + source "drivers/serial/Kconfig.si32" endif # SERIAL diff --git a/drivers/serial/Kconfig.sy1xx b/drivers/serial/Kconfig.sy1xx new file mode 100644 index 000000000000000..2f345b6379421f4 --- /dev/null +++ b/drivers/serial/Kconfig.sy1xx @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config UART_SY1XX + bool "Sensry SY1xx driver" + default y + depends on DT_HAS_SENSRY_SY1XX_UART_ENABLED + select SERIAL_HAS_DRIVER + help + Driver for Sensry Sy1xx series uart. diff --git a/drivers/serial/uart_sy1xx.c b/drivers/serial/uart_sy1xx.c new file mode 100644 index 000000000000000..a91b93937524ba6 --- /dev/null +++ b/drivers/serial/uart_sy1xx.c @@ -0,0 +1,319 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#define DT_DRV_COMPAT sensry_sy1xx_uart + +#include +#include +#include +#include +#include +#include + +struct sy1xx_uart_config { + uint32_t base; + uint32_t inst; +}; + +typedef struct { + uint16_t data_len; + uint8_t *data; +} uartTransfer_t; + +typedef enum { + DRIVERS_UART_STOP_1, + DRIVERS_UART_STOP_1_5, + DRIVERS_UART_STOP_2 +} uart_stop_t; + +typedef enum { + DRIVERS_UART_PAR_NONE, + DRIVERS_UART_PAR_EVEN, + DRIVERS_UART_PAR_ODD, + DRIVERS_UART_PAR_MARK, + DRIVERS_UART_PAR_SPACE +} uart_parity_t; + +typedef struct { + uint32_t baudrate; + uart_stop_t stopbits; + uart_parity_t parity; +} uartConfig_t; + +#define DEVICE_MAX_BUFFER_SIZE (512) + +struct sy1xx_uart_data { + uint8_t write[DEVICE_MAX_BUFFER_SIZE]; + uint8_t read[DEVICE_MAX_BUFFER_SIZE]; +}; + +/* prototypes */ +static int32_t drivers_uart_read(const struct device *dev, uartTransfer_t *request); +static int32_t drivers_uart_write(const struct device *dev, uartTransfer_t *request); + +static int32_t drivers_uart_configure(const struct device *dev, uartConfig_t *uart_cfg) +{ + struct sy1xx_uart_config *config = (struct sy1xx_uart_config *)dev->config; + + if (uart_cfg->baudrate == 0) { + return -1; + } + + /* + * The counter in the UDMA will count from 0 to div included + * and then will restart from 0, so we must give div - 1 as + * divider + */ + int32_t divider = soc_get_peripheral_clock() / uart_cfg->baudrate - 1; + + /* + * [31:16]: clock divider (from SoC clock) + * [9]: RX enable + * [8]: TX enable + * [3]: stop bits 0 = 1 stop bit + * 1 = 2 stop bits + * [2:1]: bits 00 = 5 bits + * 01 = 6 bits + * 10 = 7 bits + * 11 = 8 bits + * [0]: parity + */ + + /* default: both tx and rx enabled; 8N1 configuration; 1 stop bits */ + volatile uint32_t setup = 0x0306 | uart_cfg->parity; + + setup |= ((divider) << 16); + UDMA_WRITE_REG(config->base, UDMA_SETUP_REG, setup); + + /* start initial reading request to get the dma running */ + uint8_t dummy_data[10]; + + uartTransfer_t dummy_request = { + .data_len = 10, + .data = (uint8_t *)dummy_data, + }; + + drivers_uart_read(dev, &dummy_request); + return 0; +} + +/** + * @return + * - < 0: Error + * - 0: OK + * - > 0: Busy + */ +int32_t drivers_uart_read(const struct device *dev, uartTransfer_t *request) +{ + struct sy1xx_uart_config *config = (struct sy1xx_uart_config *)dev->config; + struct sy1xx_uart_data *data = (struct sy1xx_uart_data *)dev->data; + + if (request == 0) { + return -1; + } + + uint32_t max_read_size = request->data_len; + + request->data_len = 0; + + if (max_read_size > DEVICE_MAX_BUFFER_SIZE) { + return -3; + } + + int32_t ret = 0; + + /* rx is ready */ + int32_t remaining_bytes = UDMA_READ_REG(config->base, UDMA_RX_SIZE_REG); + int32_t bytes_transferred = (DEVICE_MAX_BUFFER_SIZE - remaining_bytes); + + if (bytes_transferred > 0) { + /* copy data to the user buffer */ + uint32_t copy_len = + bytes_transferred > max_read_size ? max_read_size : bytes_transferred; + for (uint32_t i = 0; i < copy_len; i++) { + request->data[i] = data->read[i]; + } + + /* update actual read length */ + request->data_len = bytes_transferred; + + /* stop and restart receiving */ + UDMA_CANCEL_RX(config->base); + + /* start another read request, with maximum buffer size */ + UDMA_START_RX(config->base, (int32_t)data->read, DEVICE_MAX_BUFFER_SIZE, 0); + + /* return: some data received */ + ret = 0; + + } else { + /* return: (busy) stay in receiving mode */ + ret = 1; + } + + return ret; +} + +/** + * @return + * - < 0: Error + * - 0: OK + * - > 0: Busy + */ +int32_t drivers_uart_write(const struct device *dev, uartTransfer_t *request) +{ + struct sy1xx_uart_config *config = (struct sy1xx_uart_config *)dev->config; + struct sy1xx_uart_data *data = (struct sy1xx_uart_data *)dev->data; + + if (request == 0) { + return -1; + } + + if (request->data_len == 0) { + return -1; + } + + if (request->data_len > DEVICE_MAX_BUFFER_SIZE) { + /* more data than possible requested */ + return -2; + } + + if (0 == UDMA_IS_FINISHED_TX(config->base)) { + /* writing not finished => busy */ + return 1; + } + + uint32_t remaining_bytes = UDMA_GET_REMAINING_TX(config->base); + + if (remaining_bytes != 0) { + UDMA_CANCEL_TX(config->base); + return -3; + } + + /* copy the data to transmission buffer */ + for (uint32_t i = 0; i < request->data_len; i++) { + data->write[i] = request->data[i]; + } + + /* start new transmission */ + UDMA_START_TX(config->base, (uint32_t)data->write, request->data_len, 0); + + /* success */ + return 0; +} + +/* + * it should be avoided to read single characters only + */ +static int sensry_uart_poll_in(const struct device *dev, unsigned char *c) +{ + uartTransfer_t request = { + .data_len = 1, + .data = c, + }; + + if (0 == drivers_uart_read(dev, &request)) { + return 0; + } + + return -1; +} + +/* + * it should be avoided to write single characters only + */ +static void sensry_uart_poll_out(const struct device *dev, unsigned char c) +{ + uartTransfer_t request = { + .data_len = 1, + .data = &c, + }; + + while (1) { + if (0 == drivers_uart_write(dev, &request)) { + break; + } + } +} + +static int sensry_uart_err_check(const struct device *dev) +{ + int err = 0; + + return err; +} + +static int sy1xx_uart_init(const struct device *dev) +{ + struct sy1xx_uart_config *config = (struct sy1xx_uart_config *)dev->config; + struct sy1xx_uart_data *data = (struct sy1xx_uart_data *)dev->data; + + for (uint32_t i = 0; i < DEVICE_MAX_BUFFER_SIZE; i++) { + data->write[i] = 0xa5; + data->read[i] = 0xb4; + } + + /* UDMA clock enable */ + drivers_udma_enable_clock(DRIVERS_UDMA_UART, config->inst); + + /* PAD config */ + uint32_t pad_config_tx = + PAD_CONFIG(0, PAD_SMT_DISABLE, PAD_SLEW_LOW, PAD_PULLUP_DIS, PAD_PULLDOWN_DIS, + PAD_DRIVE_2PF, PAD_PMOD_NORMAL, PAD_DIR_OUTPUT); + + uint32_t pad_config_rx = + PAD_CONFIG(8, PAD_SMT_DISABLE, PAD_SLEW_LOW, PAD_PULLUP_DIS, PAD_PULLDOWN_DIS, + PAD_DRIVE_2PF, PAD_PMOD_NORMAL, PAD_DIR_INPUT); + + uint32_t pad_config_cts = + PAD_CONFIG(16, PAD_SMT_DISABLE, PAD_SLEW_LOW, PAD_PULLUP_EN, PAD_PULLDOWN_DIS, + PAD_DRIVE_2PF, PAD_PMOD_NORMAL, PAD_DIR_INPUT); + + uint32_t pad_config_rts = + PAD_CONFIG(24, PAD_SMT_DISABLE, PAD_SLEW_LOW, PAD_PULLUP_DIS, PAD_PULLDOWN_DIS, + PAD_DRIVE_2PF, PAD_PMOD_NORMAL, PAD_DIR_OUTPUT); + + sys_write32((pad_config_tx | pad_config_rx | pad_config_cts | pad_config_rts), + PAD_CONFIG_ADDR_UART + (config->inst * 4 + 0)); + + uartConfig_t default_config = { + .baudrate = 1000000, + .parity = DRIVERS_UART_PAR_NONE, + .stopbits = DRIVERS_UART_STOP_1, + }; + + UDMA_CANCEL_RX(config->base); + UDMA_CANCEL_TX(config->base); + + drivers_uart_configure(dev, &default_config); + + return 0; +} + +static const struct uart_driver_api sy1xx_uart_driver_api = { + + .poll_in = sensry_uart_poll_in, + .poll_out = sensry_uart_poll_out, + .err_check = sensry_uart_err_check, + +}; + +#define SYS1XX_UART_INIT(n) \ + \ + static const struct sy1xx_uart_config sy1xx_uart_##n##_cfg = { \ + .base = (uint32_t)DT_INST_REG_ADDR(n), \ + .inst = (uint32_t)DT_INST_PROP(n, instance), \ + }; \ + \ + static struct sy1xx_uart_data __attribute__((section(".udma_access"))) \ + __aligned(4) sy1xx_uart_##n##_data = { \ + \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, &sy1xx_uart_init, NULL, &sy1xx_uart_##n##_data, \ + &sy1xx_uart_##n##_cfg, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \ + &sy1xx_uart_driver_api); + +DT_INST_FOREACH_STATUS_OKAY(SYS1XX_UART_INIT) diff --git a/dts/bindings/serial/sensry,sy1xx-uart.yaml b/dts/bindings/serial/sensry,sy1xx-uart.yaml new file mode 100644 index 000000000000000..fbb98dded3c25fa --- /dev/null +++ b/dts/bindings/serial/sensry,sy1xx-uart.yaml @@ -0,0 +1,21 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +description: Sensry SY1xx UART + +compatible: "sensry,sy1xx-uart" + +include: uart-controller.yaml + +properties: + reg: + required: true + description: Base address of the uart controller. + + current-speed: + required: true + description: Default baudrate of the uart controller. + + instance: + type: int + required: true From 686cbc90f6094d87b1ebe491cbd7ad5fbf3633df Mon Sep 17 00:00:00 2001 From: Sven Ginka Date: Thu, 5 Sep 2024 21:07:36 +0200 Subject: [PATCH 080/269] driver: timer: Add support for sy1xx Add sys timer driver for Sensry's RISCV32 based SY1xx. Signed-off-by: Sven Ginka --- drivers/timer/CMakeLists.txt | 1 + drivers/timer/Kconfig | 1 + drivers/timer/Kconfig.sy1xx_sys_timer | 11 ++ drivers/timer/sy1xx_sys_timer.c | 180 ++++++++++++++++++ .../sy1xx,event-unit.yaml | 18 ++ dts/bindings/timer/sy1xx,sys-timer.yaml | 19 ++ 6 files changed, 230 insertions(+) create mode 100644 drivers/timer/Kconfig.sy1xx_sys_timer create mode 100644 drivers/timer/sy1xx_sys_timer.c create mode 100644 dts/bindings/interrupt-controller/sy1xx,event-unit.yaml create mode 100644 dts/bindings/timer/sy1xx,sys-timer.yaml diff --git a/drivers/timer/CMakeLists.txt b/drivers/timer/CMakeLists.txt index ac5bac6c244ad95..56eea917d59f58f 100644 --- a/drivers/timer/CMakeLists.txt +++ b/drivers/timer/CMakeLists.txt @@ -37,3 +37,4 @@ zephyr_library_sources_ifdef(CONFIG_XLNX_PSTTC_TIMER xlnx_psttc_timer.c) zephyr_library_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c) zephyr_library_sources_ifdef(CONFIG_SMARTBOND_TIMER smartbond_timer.c) zephyr_library_sources_ifdef(CONFIG_MTK_ADSP_TIMER mtk_adsp_timer.c) +zephyr_library_sources_ifdef(CONFIG_SY1XX_SYS_TIMER sy1xx_sys_timer.c) diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 3343f78d79ce06a..e0fbfa4b1af2726 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -96,6 +96,7 @@ source "drivers/timer/Kconfig.ti_dm_timer" source "drivers/timer/Kconfig.xlnx_psttc" source "drivers/timer/Kconfig.xtensa" source "drivers/timer/Kconfig.mtk_adsp" +source "drivers/timer/Kconfig.sy1xx_sys_timer" endmenu diff --git a/drivers/timer/Kconfig.sy1xx_sys_timer b/drivers/timer/Kconfig.sy1xx_sys_timer new file mode 100644 index 000000000000000..6770866aca53f51 --- /dev/null +++ b/drivers/timer/Kconfig.sy1xx_sys_timer @@ -0,0 +1,11 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +config SY1XX_SYS_TIMER + bool "Sensry ganymed system timer" + default y + depends on SOC_SERIES_SY1XX + depends on $(dt_nodelabel_enabled,systick) + help + This module implements a kernel device driver for the system timer + and provides the standard "system clock driver" interfaces. diff --git a/drivers/timer/sy1xx_sys_timer.c b/drivers/timer/sy1xx_sys_timer.c new file mode 100644 index 000000000000000..524b54ae2e786ba --- /dev/null +++ b/drivers/timer/sy1xx_sys_timer.c @@ -0,0 +1,180 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2024 sensry.io + */ + +#define DT_DRV_COMPAT sy1xx_sys_timer + +#include +#include +#include +#include +#include +#include + +#define SY1XX_SYS_TIMER_NODE DT_NODELABEL(systick) +#define SY1XX_SYS_TIMER_BASE_ADDR DT_REG_ADDR(SY1XX_SYS_TIMER_NODE) + +#define SY1XX_MINIMUM_ALLOWED_TICK 1000 + +#define REG_TIMER_CMP_LO_OFFS 0x10 + +/* config bits */ +#define PLP_TIMER_ENABLE_BIT 0 +#define PLP_TIMER_RESET_BIT 1 +#define PLP_TIMER_IRQ_ENABLE_BIT 2 +#define PLP_TIMER_IEM_BIT 3 +#define PLP_TIMER_CMP_CLR_BIT 4 +#define PLP_TIMER_ONE_SHOT_BIT 5 +#define PLP_TIMER_PRESCALER_ENABLE_BIT 6 +#define PLP_TIMER_CLOCK_SOURCE_BIT 7 +#define PLP_TIMER_PRESCALER_VALUE_BIT 8 +#define PLP_TIMER_PRESCALER_VALUE_BITS 8 +#define PLP_TIMER_64_BIT 31 + +/* config flags */ +#define PLP_TIMER_ACTIVE 1 +#define PLP_TIMER_IDLE 0 + +#define PLP_TIMER_RESET_ENABLED 1 +#define PLP_TIMER_RESET_DISABLED 0 + +#define PLP_TIMER_IRQ_ENABLED 1 +#define PLP_TIMER_IRQ_DISABLED 0 + +#define PLP_TIMER_IEM_ENABLED 1 +#define PLP_TIMER_IEM_DISABLED 0 + +#define PLP_TIMER_CMPCLR_ENABLED 1 +#define PLP_TIMER_CMPCLR_DISABLED 0 + +#define PLP_TIMER_ONE_SHOT_ENABLED 1 +#define PLP_TIMER_ONE_SHOT_DISABLED 0 + +#define PLP_TIMER_REFCLK_ENABLED 1 +#define PLP_TIMER_REFCLK_DISABLED 0 + +#define PLP_TIMER_PRESCALER_ENABLED 1 +#define PLP_TIMER_PRESCALER_DISABLED 0 + +#define PLP_TIMER_MODE_64_ENABLED 1 +#define PLP_TIMER_MODE_64_DISABLED 0 + +static volatile uint32_t current_sys_clock; + +struct timer_cfg { + uint32_t tick_us; +}; + +static inline unsigned int timer_conf_prep(int enable, int reset, int irq_enable, int event_mask, + int cmp_clr, int one_shot, int clk_source, + int prescaler_enable, int prescaler, int mode_64) +{ + return (enable << PLP_TIMER_ENABLE_BIT) | (reset << PLP_TIMER_RESET_BIT) | + (irq_enable << PLP_TIMER_IRQ_ENABLE_BIT) | (event_mask << PLP_TIMER_IEM_BIT) | + (cmp_clr << PLP_TIMER_CMP_CLR_BIT) | (one_shot << PLP_TIMER_ONE_SHOT_BIT) | + (clk_source << PLP_TIMER_CLOCK_SOURCE_BIT) | + (prescaler_enable << PLP_TIMER_PRESCALER_ENABLE_BIT) | + (prescaler << PLP_TIMER_PRESCALER_VALUE_BIT) | (mode_64 << PLP_TIMER_64_BIT); +} + +static void sy1xx_sys_timer_reload(uint32_t base, uint32_t reload_timer_ticks) +{ + sys_write32(reload_timer_ticks, (base + REG_TIMER_CMP_LO_OFFS)); +} + +static void sy1xx_sys_timer_cfg_auto_reload(uint32_t base) +{ + + uint32_t conf = + timer_conf_prep(PLP_TIMER_ACTIVE, PLP_TIMER_RESET_ENABLED, PLP_TIMER_IRQ_ENABLED, + PLP_TIMER_IEM_DISABLED, PLP_TIMER_CMPCLR_ENABLED, + PLP_TIMER_ONE_SHOT_DISABLED, PLP_TIMER_REFCLK_ENABLED, + PLP_TIMER_PRESCALER_DISABLED, 0, PLP_TIMER_MODE_64_DISABLED); + + sys_write32(conf, base); +} + +static void sy1xx_sys_timer_irq_enable(void) +{ + soc_enable_irq(DT_IRQN(SY1XX_SYS_TIMER_NODE)); +} + +static void sy1xx_sys_timer_irq_disable(void) +{ + soc_disable_irq(DT_IRQN(SY1XX_SYS_TIMER_NODE)); +} + +static int32_t sy1xx_sys_timer_config(uint32_t base, struct timer_cfg *cfg) +{ + + /* global irq disable */ + uint32_t isr_state = arch_irq_lock(); + + if (cfg->tick_us < SY1XX_MINIMUM_ALLOWED_TICK) { + cfg->tick_us = SY1XX_MINIMUM_ALLOWED_TICK; + } + + /* expect 1.0ms resolution => tick_us = 1000 */ + uint32_t us = cfg->tick_us; + volatile double ticks_f = + (((double)us / (double)1000000) * (double)soc_get_rts_clock_frequency()) + 1.0; + + volatile uint32_t timer_ticks = (uint32_t)ticks_f; + + printk("timer [%d] expected %u (%d)\n", soc_get_rts_clock_frequency(), cfg->tick_us, + timer_ticks); + + sy1xx_sys_timer_reload(base, timer_ticks); + + sy1xx_sys_timer_cfg_auto_reload(base); + + /* we always start timer irq disabled */ + sy1xx_sys_timer_irq_disable(); + + /* restore global irq */ + arch_irq_unlock(isr_state); + + return 0; +} + +uint32_t sys_clock_elapsed(void) +{ + return 0; +} + +uint32_t sys_clock_cycle_get_32(void) +{ + return current_sys_clock; +} + +void sy1xx_sys_timer_callback(const void *user_data) +{ + current_sys_clock += 1; + + sys_clock_announce(1); +} + +static int sy1xx_sys_timer_init(void) +{ + printk("starting sys_timer\n"); + + struct timer_cfg timerCfg0 = { + .tick_us = DT_PROP(SY1XX_SYS_TIMER_NODE, ticks_us), + }; + + sy1xx_sys_timer_config(SY1XX_SYS_TIMER_BASE_ADDR, &timerCfg0); + + uint32_t irq = arch_irq_lock(); + + /* register interrupt routine with zephyr */ + irq_connect_dynamic(DT_IRQN(SY1XX_SYS_TIMER_NODE), 0, sy1xx_sys_timer_callback, NULL, 0); + + sy1xx_sys_timer_irq_enable(); + + arch_irq_unlock(irq | 0x1); + + return 0; +} + +SYS_INIT(sy1xx_sys_timer_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY); diff --git a/dts/bindings/interrupt-controller/sy1xx,event-unit.yaml b/dts/bindings/interrupt-controller/sy1xx,event-unit.yaml new file mode 100644 index 000000000000000..4dba6bbbde55f84 --- /dev/null +++ b/dts/bindings/interrupt-controller/sy1xx,event-unit.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +description: Sensry sy1xx event unit + +compatible: "sensry,sy1xx-event-unit" + +include: [interrupt-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#interrupt-cells": + const: 1 + +interrupt-cells: + - irq diff --git a/dts/bindings/timer/sy1xx,sys-timer.yaml b/dts/bindings/timer/sy1xx,sys-timer.yaml new file mode 100644 index 000000000000000..b87fbd775641a8b --- /dev/null +++ b/dts/bindings/timer/sy1xx,sys-timer.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +description: Sensry ganymed timer peripheral + +compatible: "sensry,sy1xx-sys-timer" + +include: base.yaml + +properties: + reg: + required: true + + interrupts: + required: true + + ticks_us: + type: int + required: true From d2bded5efb1b5776ab5f4df2958c05f3270388f6 Mon Sep 17 00:00:00 2001 From: Sven Ginka Date: Thu, 5 Sep 2024 21:18:29 +0200 Subject: [PATCH 081/269] board: sensry: Add support for sy1xx Add board support for eval board ganymed_bob, which is a break-out-board for both soc variants. Variants of the soc are GBM and GEN1. Signed-off-by: Sven Ginka --- boards/sensry/ganymed_bob/Kconfig.ganymed_bob | 6 + boards/sensry/ganymed_bob/board.yml | 9 ++ .../doc/img/ganymed_bob_sy120_gbm.webp | Bin 0 -> 47206 bytes .../doc/img/ganymed_bob_sy120_gen1.webp | Bin 0 -> 47238 bytes boards/sensry/ganymed_bob/doc/index.rst | 144 ++++++++++++++++++ .../ganymed_bob/ganymed_bob_sy120_gbm.dts | 17 +++ .../ganymed_bob/ganymed_bob_sy120_gbm.yaml | 15 ++ .../ganymed_bob_sy120_gbm_defconfig | 6 + .../ganymed_bob/ganymed_bob_sy120_gen1.dts | 17 +++ .../ganymed_bob/ganymed_bob_sy120_gen1.yaml | 15 ++ .../ganymed_bob_sy120_gen1_defconfig | 6 + boards/sensry/index.rst | 10 ++ dts/riscv/sensry/ganymed-sy1xx.dtsi | 91 +++++++++++ 13 files changed, 336 insertions(+) create mode 100644 boards/sensry/ganymed_bob/Kconfig.ganymed_bob create mode 100644 boards/sensry/ganymed_bob/board.yml create mode 100644 boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gbm.webp create mode 100644 boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gen1.webp create mode 100644 boards/sensry/ganymed_bob/doc/index.rst create mode 100644 boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts create mode 100644 boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.yaml create mode 100644 boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm_defconfig create mode 100644 boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts create mode 100644 boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.yaml create mode 100644 boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1_defconfig create mode 100644 boards/sensry/index.rst create mode 100644 dts/riscv/sensry/ganymed-sy1xx.dtsi diff --git a/boards/sensry/ganymed_bob/Kconfig.ganymed_bob b/boards/sensry/ganymed_bob/Kconfig.ganymed_bob new file mode 100644 index 000000000000000..bc5dfc46a844cf7 --- /dev/null +++ b/boards/sensry/ganymed_bob/Kconfig.ganymed_bob @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2024 sensry.io + +config BOARD_GANYMED_BOB + select SOC_SY120_GBM if BOARD_GANYMED_BOB_SY120_GBM + select SOC_SY120_GEN1 if BOARD_GANYMED_BOB_SY120_GEN1 diff --git a/boards/sensry/ganymed_bob/board.yml b/boards/sensry/ganymed_bob/board.yml new file mode 100644 index 000000000000000..cc6591f62535834 --- /dev/null +++ b/boards/sensry/ganymed_bob/board.yml @@ -0,0 +1,9 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +board: + name: ganymed_bob + vendor: sensry + socs: + - name: sy120_gbm + - name: sy120_gen1 diff --git a/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gbm.webp b/boards/sensry/ganymed_bob/doc/img/ganymed_bob_sy120_gbm.webp new file mode 100644 index 0000000000000000000000000000000000000000..e6d081f79af403bbd86c1277af3eb9b45186c31c GIT binary patch literal 47206 zcmV)CK*GOLNk&FqxBviGMM6+kP&gn`xBvifKLVWrDgXmx0Y05Vn@K1sCZa4>96+!W ziDhor@6h|TKUY-c)0RKGQ^?;FsB?lUVmbYw~S>HSRp zbNI*kAKv|_|2_Xx{I`$)Bfri63+xg3ul8U0zu$d${=@c%zAtqDOaFWPhx%V|k7~ZZ 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b/boards/sensry/ganymed_bob/doc/index.rst @@ -0,0 +1,144 @@ +.. _ganymed_bob: + +Ganymed Break-Out-Board (BOB) +############################# + +Overview +******** + +.. note:: + + All software for the Ganymed Break-Out-Board (BOB) is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The Ganymed board hardware provides support for the Ganymed sy1xx series IoT multicore +RISC-V SoC with optional sensor level. + +The SoC has the following core features: + +* 32-Bit RSIC-V 1+8-core processor, up to 500MHz + + * 1x Data Acquisition Unit + * 8x Data Processing Unit + * Event Bus + * MicroDMA + +* 4096 KB Global SRAM +* 64 KB Secure SRAM +* 512 KB Global MRAM +* 512 KB Secure MRAM +* CLOCK +* RAM +* :abbr:`32x GPIO (General Purpose Input Output)` +* :abbr:`4x TWIM (I2C-compatible two-wire interface with MicroDMA)` +* 4x I2S +* :abbr:`7x SPI (Serial Peripheral Interface with MicroDMA)` +* :abbr:`3x UART (Universal receiver-transmitter with MicroDMA)` +* :abbr:`1x TSN (Time sensitive networking ethernet MAC with MicroDMA)` +* 1x CAN-FD +* 3x ADC + +.. figure:: img/ganymed_bob_sy120_gbm.webp + :align: center + :alt: Ganymed Break-Out-Board (BOB) equipped with SY120 GBM + + Ganymed Break-Out-Board (BOB) equipped with SY120 GBM (Credit: Sensry) + +.. figure:: img/ganymed_bob_sy120_gen1.webp + :align: center + :alt: Ganymed Break-Out-Board (BOB) equipped with SY120 GEN1 + + Ganymed Break-Out-Board (BOB) equipped with SY120 GEN1 (Credit: Sensry) + +Hardware +******** + +The Ganymed BOB has: + +* Assembly options for the SoC include + + * SY120-GBM - Generic Base Module without top level sensors + * SY120-GEN1 - Generic Module type 1 with top level sensors (Bosch BME680 - SPI1 , Bosch BMA456 - SPI0, Bosch BMG250 - SPI2, STMicro MIS2DH - I2C0) + +* power section for on-board power generation and power measurement (selectable) +* 40-pin JTAG connector (compatible to Olimex ARM-JTAG-OCD-H) +* USB over FTDI (connected to UART0) +* Header for I/Os and additional configuration + +Supported Features +================== + +The ``ganymed-bob/sy120-gbm`` board supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| SAADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| MRAM | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| TWIM | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| GRTC | on-chip | counter | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| TSN | on-chip | ethernet MAC | ++-----------+------------+----------------------+ +| CAN | on-chip | CAN | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +The ``ganymed-bob/sy120-gen1`` board includes all hardware features of the ``ganymed-bob/sy120-gbm`` board and comes additionally +with these features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| BME680 | on-chip | environment sensor | ++-----------+------------+----------------------+ +| BMA456 | on-chip | acceleration sensor | ++-----------+------------+----------------------+ +| BMG250 | on-chip | gyrosope sensor | ++-----------+------------+----------------------+ +| MIS2DH | on-chip | vibration sensor | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Power +***** + +* USB type-C +* external 5V power source + +Programming and Debugging +************************* + +Applications for the ``ganymed-bob/sy120-gbm`` board can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Testing the Ganymed BreakOut Board +********************************** + +Test the Ganymed with a :zephyr:code-sample:`blinky` sample. +The sample output should be: + +.. code-block:: console + + Hello World! ganymed-bob/sy120-gbm diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts new file mode 100644 index 000000000000000..f0c4e8c30bf23f4 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 sensry.io */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include + +/ { + + chosen { + zephyr,code-partition = &l2_ram_text; + zephyr,sram = &l2_ram_data; + + zephyr,console = &uart0; + }; + +}; diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.yaml b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.yaml new file mode 100644 index 000000000000000..9dd2c6e5d226df0 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +identifier: ganymed_bob/sy120_gbm +vendor: sensry +name: Ganymed family breakout board with SY120_GBM chip equipped +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - uart + - spi + - i2c diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm_defconfig b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm_defconfig new file mode 100644 index 000000000000000..04f3794d6325e43 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts new file mode 100644 index 000000000000000..f0c4e8c30bf23f4 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts @@ -0,0 +1,17 @@ +/* Copyright (c) 2024 sensry.io */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include + +/ { + + chosen { + zephyr,code-partition = &l2_ram_text; + zephyr,sram = &l2_ram_data; + + zephyr,console = &uart0; + }; + +}; diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.yaml b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.yaml new file mode 100644 index 000000000000000..1e45a8c297f2102 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +identifier: ganymed_bob/sy120_gen1 +vendor: sensry +name: Ganymed family breakout board with SY120_GBM chip equipped +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - gpio + - uart + - spi + - i2c diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1_defconfig b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1_defconfig new file mode 100644 index 000000000000000..04f3794d6325e43 --- /dev/null +++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 sensry.io +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/sensry/index.rst b/boards/sensry/index.rst new file mode 100644 index 000000000000000..93151a9da0d9e70 --- /dev/null +++ b/boards/sensry/index.rst @@ -0,0 +1,10 @@ +.. _boards-sensry: + +Sensry +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/dts/riscv/sensry/ganymed-sy1xx.dtsi b/dts/riscv/sensry/ganymed-sy1xx.dtsi new file mode 100644 index 000000000000000..ad2df617b285cd6 --- /dev/null +++ b/dts/riscv/sensry/ganymed-sy1xx.dtsi @@ -0,0 +1,91 @@ +/* Copyright (c) 2024 sensry.io */ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <0>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "sensry,sy1xx", "riscv"; + reg = <0>; + riscv,isa = "rv32imc_zicsr"; + status = "okay"; + }; + + }; + + l2_ram_text: memory@1c010200 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mmio-sram"; + reg = <0x1c010200 0x5fe00>; + status = "okay"; + }; + + l2_ram_data: memory@1c070000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mmio-sram"; + reg = <0x1c070000 0x200000>; + status = "okay"; + }; + + soc { + #address-cells = <1>; + #size-cells = <0>; + + event0: interrupt-controller@1000 { + compatible = "sensry,sy1xx-event-unit"; + reg = <0x1000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + systick: timer@1a10b040 { + compatible = "sensry,sy1xx-sys-timer"; + reg = <0x1a10b040>; + interrupt-parent = <&event0>; + interrupts = <10 0>; + ticks_us = <1000>; + }; + + timer1: timer@1a10b044 { + compatible = "sensry,sy1xx-sys-timer"; + reg = <0x1a10b044>; + interrupt-parent = <&event0>; + interrupts = <11 0>; + ticks_us = <1000>; + }; + + uart0: uart@1a102000 { + compatible = "sensry,sy1xx-uart"; + reg = <0x1a102000>; + instance = <0>; + current-speed = <1000000>; + status = "okay"; + }; + + uart1: uart@1a102080 { + compatible = "sensry,sy1xx-uart"; + reg = <0x1a102080>; + instance = <1>; + current-speed = <1000000>; + status = "okay"; + }; + + uart2: uart@1a102100 { + compatible = "sensry,sy1xx-uart"; + reg = <0x1a102100>; + instance = <2>; + current-speed = <1000000>; + status = "okay"; + }; + + }; +}; From 4385785f0295c794beafe90d47eae5c67220f148 Mon Sep 17 00:00:00 2001 From: Lucas Tamborrino Date: Thu, 29 Aug 2024 12:42:39 -0300 Subject: [PATCH 082/269] drivers: i2c: esp32: Fix DT node instance. DT_INST macros were not getting the info from the correct node. Signed-off-by: Lucas Tamborrino --- drivers/i2c/i2c_esp32.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/i2c/i2c_esp32.c b/drivers/i2c/i2c_esp32.c index 5364cbd5b291dd2..3c1381722090e70 100644 --- a/drivers/i2c/i2c_esp32.c +++ b/drivers/i2c/i2c_esp32.c @@ -800,8 +800,8 @@ static int IRAM_ATTR i2c_esp32_init(const struct device *dev) #endif /* SOC_I2C_SUPPORT_HW_CLR_BUS */ #define I2C_ESP32_TIMEOUT(inst) \ - COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, scl_timeout_us), \ - (DT_INST_PROP(inst, scl_timeout_us)), (0)) + COND_CODE_1(DT_NODE_HAS_PROP(I2C(inst), scl_timeout_us), \ + (DT_PROP(I2C(inst), scl_timeout_us)), (0)) #define I2C_ESP32_FREQUENCY(bitrate) \ (bitrate == I2C_BITRATE_STANDARD ? KHZ(100) \ @@ -833,9 +833,9 @@ static int IRAM_ATTR i2c_esp32_init(const struct device *dev) .tx_lsb_first = DT_PROP(I2C(idx), tx_lsb), \ .rx_lsb_first = DT_PROP(I2C(idx), rx_lsb), \ }, \ - .irq_source = DT_INST_IRQ_BY_IDX(idx, 0, irq), \ - .irq_priority = DT_INST_IRQ_BY_IDX(idx, 0, priority), \ - .irq_flags = DT_INST_IRQ_BY_IDX(idx, 0, flags), \ + .irq_source = DT_IRQ_BY_IDX(I2C(idx), 0, irq), \ + .irq_priority = DT_IRQ_BY_IDX(I2C(idx), 0, priority), \ + .irq_flags = DT_IRQ_BY_IDX(I2C(idx), 0, flags), \ .bitrate = I2C_FREQUENCY(idx), \ .scl_timeout = I2C_ESP32_TIMEOUT(idx), \ }; \ From 7510a17c183d9c77a6100ba4d8adf682d1c2ecaa Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Thu, 15 Aug 2024 18:45:11 -0400 Subject: [PATCH 083/269] spi: mcux_lpspi: Refactor driver to extract common RTIO functionality As a step to make them common code: spi_rtio.c. Verified this refactorization builds and passes spi_loopback, both with CONFIG_SPI_RTIO enabled, as well as disabled. Tested on mimxrt1010_evk. Signed-off-by: Luis Ubieda --- drivers/spi/spi_mcux_lpspi.c | 137 +++++++++++++++++++++++++++++------ 1 file changed, 114 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c index 4cbf21d77eb9b70..ba3eb2cd7aaec9c 100644 --- a/drivers/spi/spi_mcux_lpspi.c +++ b/drivers/spi/spi_mcux_lpspi.c @@ -574,6 +574,62 @@ static int transceive_dma(const struct device *dev, } #endif +#ifdef CONFIG_SPI_RTIO + +int spi_rtio_transceive(const struct device *dev, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + struct spi_mcux_data *data = dev->data; + struct spi_dt_spec *dt_spec = &data->dt_spec; + struct rtio_sqe *sqe; + struct rtio_cqe *cqe; + int err = 0; + int ret; + + dt_spec->config = *config; + + ret = spi_rtio_copy(data->r, &data->iodev, tx_bufs, rx_bufs, &sqe); + if (ret < 0) { + return ret; + } + + /** Submit request and wait */ + rtio_submit(data->r, ret); + + while (ret > 0) { + cqe = rtio_cqe_consume(data->r); + if (cqe->result < 0) { + err = cqe->result; + } + + rtio_cqe_release(data->r, cqe); + ret--; + } + + return err; +} + +static inline int transceive_rtio(const struct device *dev, + const struct spi_config *spi_cfg, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + struct spi_mcux_data *data = dev->data; + int ret; + + spi_context_lock(&data->ctx, false, NULL, NULL, spi_cfg); + + ret = spi_rtio_transceive(dev, spi_cfg, tx_bufs, rx_bufs); + + spi_context_release(&data->ctx, ret); + + return ret; +} + +#else + static int transceive(const struct device *dev, const struct spi_config *spi_cfg, const struct spi_buf_set *tx_bufs, @@ -608,12 +664,16 @@ static int transceive(const struct device *dev, return ret; } +#endif /* CONFIG_SPI_RTIO */ static int spi_mcux_transceive(const struct device *dev, const struct spi_config *spi_cfg, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs) { +#ifdef CONFIG_SPI_RTIO + return transceive_rtio(dev, spi_cfg, tx_bufs, rx_bufs); +#else #ifdef CONFIG_SPI_MCUX_LPSPI_DMA const struct spi_mcux_data *data = dev->data; @@ -623,6 +683,7 @@ static int spi_mcux_transceive(const struct device *dev, #endif /* CONFIG_SPI_MCUX_LPSPI_DMA */ return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL); +#endif /* CONFIG_SPI_RTIO */ } #ifdef CONFIG_SPI_ASYNC @@ -731,8 +792,20 @@ static inline void spi_spin_unlock(const struct device *dev, k_spinlock_key_t ke k_spin_unlock(&data->lock, key); } +static inline void spi_mcux_iodev_prepare_start(const struct device *dev) +{ + struct spi_mcux_data *data = dev->data; + struct spi_dt_spec *spi_dt_spec = data->txn_curr->sqe.iodev->data; + struct spi_config *spi_config = &spi_dt_spec->config; + int err; + + err = spi_mcux_configure(dev, spi_config); + __ASSERT(!err, "%d", err); -static void spi_mcux_iodev_next(const struct device *dev, bool completion); + spi_context_cs_control(&data->ctx, true); +} + +static bool spi_rtio_next(const struct device *dev, bool completion); static void spi_mcux_iodev_start(const struct device *dev) { @@ -773,10 +846,7 @@ static void spi_mcux_iodev_start(const struct device *dev) break; default: LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe); - - spi_mcux_iodev_next(dev, true); - rtio_iodev_sqe_err(txn_head, -EINVAL); - spi_mcux_iodev_complete(dev, 0); + spi_mcux_iodev_complete(dev, -EINVAL); return; } @@ -793,7 +863,7 @@ static void spi_mcux_iodev_start(const struct device *dev) } } -static void spi_mcux_iodev_next(const struct device *dev, bool completion) +static bool spi_rtio_next(const struct device *dev, bool completion) { struct spi_mcux_data *data = dev->data; @@ -801,7 +871,7 @@ static void spi_mcux_iodev_next(const struct device *dev, bool completion) if (!completion && data->txn_curr != NULL) { spi_spin_unlock(dev, key); - return; + return false; } struct mpsc_node *next = mpsc_pop(&data->io_q); @@ -818,42 +888,63 @@ static void spi_mcux_iodev_next(const struct device *dev, bool completion) spi_spin_unlock(dev, key); - if (data->txn_curr != NULL) { - struct spi_dt_spec *spi_dt_spec = data->txn_curr->sqe.iodev->data; - struct spi_config *spi_cfg = &spi_dt_spec->config; + return (data->txn_curr != NULL); +} - spi_mcux_configure(dev, spi_cfg); - spi_context_cs_control(&data->ctx, true); - spi_mcux_iodev_start(dev); +static bool spi_rtio_submit(const struct device *dev, + struct rtio_iodev_sqe *iodev_sqe) +{ + struct spi_mcux_data *data = dev->data; + + mpsc_push(&data->io_q, &iodev_sqe->q); + + return spi_rtio_next(dev, false); +} + +static bool spi_rtio_complete(const struct device *dev, int status) +{ + struct spi_mcux_data *data = dev->data; + struct rtio_iodev_sqe *txn_head = data->txn_head; + bool result; + + result = spi_rtio_next(dev, true); + + if (status < 0) { + rtio_iodev_sqe_err(txn_head, status); + } else { + rtio_iodev_sqe_ok(txn_head, status); } + + return result; } static void spi_mcux_iodev_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe) { - struct spi_mcux_data *data = dev->data; - - mpsc_push(&data->io_q, &iodev_sqe->q); - spi_mcux_iodev_next(dev, false); + if (spi_rtio_submit(dev, iodev_sqe)) { + spi_mcux_iodev_prepare_start(dev); + spi_mcux_iodev_start(dev); + } } static void spi_mcux_iodev_complete(const struct device *dev, int status) { struct spi_mcux_data *data = dev->data; - if (data->txn_curr->sqe.flags & RTIO_SQE_TRANSACTION) { + if (!status && data->txn_curr->sqe.flags & RTIO_SQE_TRANSACTION) { data->txn_curr = rtio_txn_next(data->txn_curr); spi_mcux_iodev_start(dev); } else { - struct rtio_iodev_sqe *txn_head = data->txn_head; - + /** De-assert CS-line to space from next transaction */ spi_context_cs_control(&data->ctx, false); - spi_mcux_iodev_next(dev, true); - rtio_iodev_sqe_ok(txn_head, status); + + if (spi_rtio_complete(dev, status)) { + spi_mcux_iodev_prepare_start(dev); + spi_mcux_iodev_start(dev); + } } } - #endif From b135cc5e46705db78c35fefcc9ec8d7196bc989b Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Fri, 16 Aug 2024 15:53:20 -0400 Subject: [PATCH 084/269] spi: spi_mcux_lpspi: Removed spin lock from iodev_start Does not seem to be required. This allows hiding away the spin lock APIs. Signed-off-by: Luis Ubieda --- drivers/spi/spi_mcux_lpspi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c index ba3eb2cd7aaec9c..2257794dbee099e 100644 --- a/drivers/spi/spi_mcux_lpspi.c +++ b/drivers/spi/spi_mcux_lpspi.c @@ -852,11 +852,8 @@ static void spi_mcux_iodev_start(const struct device *dev) data->transfer_len = transfer.dataSize; - k_spinlock_key_t key = spi_spin_lock(dev); - status = LPSPI_MasterTransferNonBlocking(base, &data->handle, &transfer); - spi_spin_unlock(dev, key); if (status != kStatus_Success) { LOG_ERR("Transfer could not start"); rtio_iodev_sqe_err(txn_head, -EIO); From bd8a23f719e2c144630516feee2b23cf897cc315 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Wed, 14 Aug 2024 21:42:56 -0400 Subject: [PATCH 085/269] spi: rtio: Extract common APIs into separate file Extracted common SPI RTIO operations from the spi_mcux_lpspi driver into spi_rtio, which should be common across RTIO drivers. Tested with spi_loopback with and without CONFIG_SPI_RTIO. Ran on mimxrt1010_evk. Also, verified the other SPI RTIO driver (spi_sam) is not broken by these changes (tested building for target: robokit1 with the same conditions as above). Signed-off-by: Luis Ubieda --- drivers/spi/spi_mcux_lpspi.c | 163 +++++------------------------- drivers/spi/spi_rtio.c | 131 ++++++++++++++++++++++++ include/zephyr/drivers/spi/rtio.h | 77 ++++++++++++++ 3 files changed, 236 insertions(+), 135 deletions(-) diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c index 2257794dbee099e..10b72c9ba0fe04b 100644 --- a/drivers/spi/spi_mcux_lpspi.c +++ b/drivers/spi/spi_mcux_lpspi.c @@ -21,6 +21,7 @@ #include #ifdef CONFIG_SPI_RTIO #include +#include #include #endif @@ -74,13 +75,7 @@ struct spi_mcux_data { size_t transfer_len; #ifdef CONFIG_SPI_RTIO - struct rtio *r; - struct mpsc io_q; - struct rtio_iodev iodev; - struct rtio_iodev_sqe *txn_head; - struct rtio_iodev_sqe *txn_curr; - struct spi_dt_spec dt_spec; - struct k_spinlock lock; + struct spi_rtio *rtio_ctx; #endif #ifdef CONFIG_SPI_MCUX_LPSPI_DMA @@ -181,7 +176,9 @@ static void spi_mcux_master_transfer_callback(LPSPI_Type *base, struct spi_mcux_data *data = userData; #ifdef CONFIG_SPI_RTIO - if (data->txn_head != NULL) { + struct spi_rtio *rtio_ctx = data->rtio_ctx; + + if (rtio_ctx->txn_head != NULL) { spi_mcux_iodev_complete(data->dev, status); return; } @@ -576,59 +573,25 @@ static int transceive_dma(const struct device *dev, #ifdef CONFIG_SPI_RTIO -int spi_rtio_transceive(const struct device *dev, - const struct spi_config *config, - const struct spi_buf_set *tx_bufs, - const struct spi_buf_set *rx_bufs) -{ - struct spi_mcux_data *data = dev->data; - struct spi_dt_spec *dt_spec = &data->dt_spec; - struct rtio_sqe *sqe; - struct rtio_cqe *cqe; - int err = 0; - int ret; - - dt_spec->config = *config; - - ret = spi_rtio_copy(data->r, &data->iodev, tx_bufs, rx_bufs, &sqe); - if (ret < 0) { - return ret; - } - - /** Submit request and wait */ - rtio_submit(data->r, ret); - - while (ret > 0) { - cqe = rtio_cqe_consume(data->r); - if (cqe->result < 0) { - err = cqe->result; - } - - rtio_cqe_release(data->r, cqe); - ret--; - } - - return err; -} - static inline int transceive_rtio(const struct device *dev, const struct spi_config *spi_cfg, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs) { struct spi_mcux_data *data = dev->data; + struct spi_rtio *rtio_ctx = data->rtio_ctx; int ret; spi_context_lock(&data->ctx, false, NULL, NULL, spi_cfg); - ret = spi_rtio_transceive(dev, spi_cfg, tx_bufs, rx_bufs); + ret = spi_rtio_transceive(rtio_ctx, spi_cfg, tx_bufs, rx_bufs); spi_context_release(&data->ctx, ret); return ret; } -#else +#endif /* CONFIG_SPI_RTIO */ static int transceive(const struct device *dev, const struct spi_config *spi_cfg, @@ -664,8 +627,6 @@ static int transceive(const struct device *dev, return ret; } -#endif /* CONFIG_SPI_RTIO */ - static int spi_mcux_transceive(const struct device *dev, const struct spi_config *spi_cfg, const struct spi_buf_set *tx_bufs, @@ -673,7 +634,8 @@ static int spi_mcux_transceive(const struct device *dev, { #ifdef CONFIG_SPI_RTIO return transceive_rtio(dev, spi_cfg, tx_bufs, rx_bufs); -#else +#endif /* CONFIG_SPI_RTIO */ + #ifdef CONFIG_SPI_MCUX_LPSPI_DMA const struct spi_mcux_data *data = dev->data; @@ -683,7 +645,6 @@ static int spi_mcux_transceive(const struct device *dev, #endif /* CONFIG_SPI_MCUX_LPSPI_DMA */ return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL); -#endif /* CONFIG_SPI_RTIO */ } #ifdef CONFIG_SPI_ASYNC @@ -761,10 +722,7 @@ static int spi_mcux_init(const struct device *dev) #endif /* CONFIG_SPI_MCUX_LPSPI_DMA */ #ifdef CONFIG_SPI_RTIO - data->dt_spec.bus = dev; - data->iodev.api = &spi_iodev_api; - data->iodev.data = &data->dt_spec; - mpsc_init(&data->io_q); + spi_rtio_init(data->rtio_ctx, dev); #endif err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT); @@ -778,24 +736,12 @@ static int spi_mcux_init(const struct device *dev) } #ifdef CONFIG_SPI_RTIO -static inline k_spinlock_key_t spi_spin_lock(const struct device *dev) -{ - struct spi_mcux_data *data = dev->data; - - return k_spin_lock(&data->lock); -} - -static inline void spi_spin_unlock(const struct device *dev, k_spinlock_key_t key) -{ - struct spi_mcux_data *data = dev->data; - - k_spin_unlock(&data->lock, key); -} static inline void spi_mcux_iodev_prepare_start(const struct device *dev) { struct spi_mcux_data *data = dev->data; - struct spi_dt_spec *spi_dt_spec = data->txn_curr->sqe.iodev->data; + struct spi_rtio *rtio_ctx = data->rtio_ctx; + struct spi_dt_spec *spi_dt_spec = rtio_ctx->txn_curr->sqe.iodev->data; struct spi_config *spi_config = &spi_dt_spec->config; int err; @@ -805,16 +751,14 @@ static inline void spi_mcux_iodev_prepare_start(const struct device *dev) spi_context_cs_control(&data->ctx, true); } -static bool spi_rtio_next(const struct device *dev, bool completion); static void spi_mcux_iodev_start(const struct device *dev) { - /* const struct spi_mcux_config *config = dev->config; */ struct spi_mcux_data *data = dev->data; - struct rtio_sqe *sqe = &data->txn_curr->sqe; + struct spi_rtio *rtio_ctx = data->rtio_ctx; + struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe; struct spi_dt_spec *spi_dt_spec = sqe->iodev->data; struct spi_config *spi_cfg = &spi_dt_spec->config; - struct rtio_iodev_sqe *txn_head = data->txn_head; LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); lpspi_transfer_t transfer; @@ -856,69 +800,17 @@ static void spi_mcux_iodev_start(const struct device *dev) &transfer); if (status != kStatus_Success) { LOG_ERR("Transfer could not start"); - rtio_iodev_sqe_err(txn_head, -EIO); + spi_mcux_iodev_complete(dev, -EIO); } } -static bool spi_rtio_next(const struct device *dev, bool completion) -{ - struct spi_mcux_data *data = dev->data; - - k_spinlock_key_t key = spi_spin_lock(dev); - - if (!completion && data->txn_curr != NULL) { - spi_spin_unlock(dev, key); - return false; - } - - struct mpsc_node *next = mpsc_pop(&data->io_q); - - if (next != NULL) { - struct rtio_iodev_sqe *next_sqe = CONTAINER_OF(next, struct rtio_iodev_sqe, q); - - data->txn_head = next_sqe; - data->txn_curr = next_sqe; - } else { - data->txn_head = NULL; - data->txn_curr = NULL; - } - - spi_spin_unlock(dev, key); - - return (data->txn_curr != NULL); -} - -static bool spi_rtio_submit(const struct device *dev, - struct rtio_iodev_sqe *iodev_sqe) -{ - struct spi_mcux_data *data = dev->data; - - mpsc_push(&data->io_q, &iodev_sqe->q); - - return spi_rtio_next(dev, false); -} - -static bool spi_rtio_complete(const struct device *dev, int status) -{ - struct spi_mcux_data *data = dev->data; - struct rtio_iodev_sqe *txn_head = data->txn_head; - bool result; - - result = spi_rtio_next(dev, true); - - if (status < 0) { - rtio_iodev_sqe_err(txn_head, status); - } else { - rtio_iodev_sqe_ok(txn_head, status); - } - - return result; -} - static void spi_mcux_iodev_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe) { - if (spi_rtio_submit(dev, iodev_sqe)) { + struct spi_mcux_data *data = dev->data; + struct spi_rtio *rtio_ctx = data->rtio_ctx; + + if (spi_rtio_submit(rtio_ctx, iodev_sqe)) { spi_mcux_iodev_prepare_start(dev); spi_mcux_iodev_start(dev); } @@ -927,15 +819,16 @@ static void spi_mcux_iodev_submit(const struct device *dev, static void spi_mcux_iodev_complete(const struct device *dev, int status) { struct spi_mcux_data *data = dev->data; + struct spi_rtio *rtio_ctx = data->rtio_ctx; - if (!status && data->txn_curr->sqe.flags & RTIO_SQE_TRANSACTION) { - data->txn_curr = rtio_txn_next(data->txn_curr); + if (!status && rtio_ctx->txn_curr->sqe.flags & RTIO_SQE_TRANSACTION) { + rtio_ctx->txn_curr = rtio_txn_next(rtio_ctx->txn_curr); spi_mcux_iodev_start(dev); } else { /** De-assert CS-line to space from next transaction */ spi_context_cs_control(&data->ctx, false); - if (spi_rtio_complete(dev, status)) { + if (spi_rtio_complete(rtio_ctx, status)) { spi_mcux_iodev_prepare_start(dev); spi_mcux_iodev_start(dev); } @@ -956,9 +849,9 @@ static const struct spi_driver_api spi_mcux_driver_api = { .release = spi_mcux_release, }; - -#define SPI_MCUX_RTIO_DEFINE(n) RTIO_DEFINE(spi_mcux_rtio_##n, CONFIG_SPI_MCUX_RTIO_SQ_SIZE, \ - CONFIG_SPI_MCUX_RTIO_SQ_SIZE) +#define SPI_MCUX_RTIO_DEFINE(n) SPI_RTIO_DEFINE(spi_mcux_rtio_##n, \ + CONFIG_SPI_MCUX_RTIO_SQ_SIZE, \ + CONFIG_SPI_MCUX_RTIO_SQ_SIZE) #ifdef CONFIG_SPI_MCUX_LPSPI_DMA #define SPI_DMA_CHANNELS(n) \ @@ -1050,7 +943,7 @@ static const struct spi_driver_api spi_mcux_driver_api = { SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \ SPI_DMA_CHANNELS(n) \ IF_ENABLED(CONFIG_SPI_RTIO, \ - (.r = &spi_mcux_rtio_##n,)) \ + (.rtio_ctx = &spi_mcux_rtio_##n,)) \ \ }; \ \ diff --git a/drivers/spi/spi_rtio.c b/drivers/spi/spi_rtio.c index 4d4589026a1790e..2852eb9df6e09ce 100644 --- a/drivers/spi/spi_rtio.c +++ b/drivers/spi/spi_rtio.c @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include LOG_MODULE_DECLARE(spi_rtio, CONFIG_SPI_LOG_LEVEL); @@ -106,3 +108,132 @@ void spi_rtio_iodev_default_submit(const struct device *dev, rtio_work_req_submit(req, iodev_sqe, spi_rtio_iodev_default_submit_sync); } + +/** + * @brief Lock the SPI RTIO spinlock + * + * This is used internally for controlling the SPI RTIO context, and is + * exposed to the user as it's required for safely implementing + * iodev_start API, specific to each driver. + * + * @param ctx SPI RTIO context + * + * @retval Spinlock key + */ +static inline k_spinlock_key_t spi_spin_lock(struct spi_rtio *ctx) +{ + return k_spin_lock(&ctx->lock); +} + +/** + * @brief Unlock the previously obtained SPI RTIO spinlock + * + * @param ctx SPI RTIO context + * @param key Spinlock key + */ +static inline void spi_spin_unlock(struct spi_rtio *ctx, k_spinlock_key_t key) +{ + k_spin_unlock(&ctx->lock, key); +} + +void spi_rtio_init(struct spi_rtio *ctx, + const struct device *dev) +{ + mpsc_init(&ctx->io_q); + ctx->txn_head = NULL; + ctx->txn_curr = NULL; + ctx->dt_spec.bus = dev; + ctx->iodev.data = &ctx->dt_spec; + ctx->iodev.api = &spi_iodev_api; +} + +/** + * @private + * @brief Setup the next transaction (could be a single op) if needed + * + * @retval true New transaction to start with the hardware is setup + * @retval false No new transaction to start + */ +static bool spi_rtio_next(struct spi_rtio *ctx, bool completion) +{ + k_spinlock_key_t key = spi_spin_lock(ctx); + + if (!completion && ctx->txn_curr != NULL) { + spi_spin_unlock(ctx, key); + return false; + } + + struct mpsc_node *next = mpsc_pop(&ctx->io_q); + + if (next != NULL) { + struct rtio_iodev_sqe *next_sqe = CONTAINER_OF(next, struct rtio_iodev_sqe, q); + + ctx->txn_head = next_sqe; + ctx->txn_curr = next_sqe; + } else { + ctx->txn_head = NULL; + ctx->txn_curr = NULL; + } + + spi_spin_unlock(ctx, key); + + return (ctx->txn_curr != NULL); +} + +bool spi_rtio_complete(struct spi_rtio *ctx, int status) +{ + struct rtio_iodev_sqe *txn_head = ctx->txn_head; + bool result; + + result = spi_rtio_next(ctx, true); + + if (status < 0) { + rtio_iodev_sqe_err(txn_head, status); + } else { + rtio_iodev_sqe_ok(txn_head, status); + } + + return result; +} + +bool spi_rtio_submit(struct spi_rtio *ctx, + struct rtio_iodev_sqe *iodev_sqe) +{ + /** Done */ + mpsc_push(&ctx->io_q, &iodev_sqe->q); + return spi_rtio_next(ctx, false); +} + +int spi_rtio_transceive(struct spi_rtio *ctx, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + struct spi_dt_spec *dt_spec = &ctx->dt_spec; + struct rtio_sqe *sqe; + struct rtio_cqe *cqe; + int err = 0; + int ret; + + dt_spec->config = *config; + + ret = spi_rtio_copy(ctx->r, &ctx->iodev, tx_bufs, rx_bufs, &sqe); + if (ret < 0) { + return ret; + } + + /** Submit request and wait */ + rtio_submit(ctx->r, ret); + + while (ret > 0) { + cqe = rtio_cqe_consume(ctx->r); + if (cqe->result < 0) { + err = cqe->result; + } + + rtio_cqe_release(ctx->r, cqe); + ret--; + } + + return err; +} diff --git a/include/zephyr/drivers/spi/rtio.h b/include/zephyr/drivers/spi/rtio.h index b5e2629a4924dfc..91726655c85e3a7 100644 --- a/include/zephyr/drivers/spi/rtio.h +++ b/include/zephyr/drivers/spi/rtio.h @@ -7,6 +7,79 @@ #ifndef ZEPHYR_DRIVERS_SPI_RTIO_H_ #define ZEPHYR_DRIVERS_SPI_RTIO_H_ +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Driver context for implementing SPI with RTIO + */ +struct spi_rtio { + struct k_spinlock lock; + struct rtio *r; + struct mpsc io_q; + struct rtio_iodev iodev; + struct rtio_iodev_sqe *txn_head; + struct rtio_iodev_sqe *txn_curr; + struct spi_dt_spec dt_spec; +}; + +/** + * @brief Statically define a spi_rtio context + * + * @param _name Symbolic name of the context + * @param _sq_sz Submission queue entry pool size + * @param _cq_sz Completion queue entry pool size + */ +#define SPI_RTIO_DEFINE(_name, _sq_sz, _cq_sz) \ + RTIO_DEFINE(CONCAT(_name, _r), _sq_sz, _cq_sz); \ + static struct spi_rtio _name = { \ + .r = &CONCAT(_name, _r), \ + }; + +/** + * @brief Initialize a SPI RTIO context + * + * @param ctx SPI RTIO driver context + * @param dev SPI bus + */ +void spi_rtio_init(struct spi_rtio *ctx, const struct device *dev); + +/** + * @brief Signal that the current (ctx->txn_curr) submission has been completed + * + * @param ctx SPI RTIO driver context + * @param status Completion status, negative values are errors + * + * @retval true Next submission is ready to start + * @retval false No more submissions to work on + */ +bool spi_rtio_complete(struct spi_rtio *ctx, int status); + +/** + * @brief Submit, atomically, a submission to work on at some point + * + * @retval true Next submission is ready to start + * @retval false No new submission to start or submissions are in progress already + */ +bool spi_rtio_submit(struct spi_rtio *ctx, struct rtio_iodev_sqe *iodev_sqe); + +/** + * @brief Perform a SPI Transfer (transceive) in a blocking call + * + * Provides a compatible API for the existing spi_transceive API by blocking + * the caller until the operation is complete. + * For details see @ref spi_transceive. + */ +int spi_rtio_transceive(struct spi_rtio *ctx, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs); + /** * @brief Fallback SPI RTIO submit implementation. * @@ -16,4 +89,8 @@ void spi_rtio_iodev_default_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe); +#ifdef __cplusplus +} +#endif + #endif /* ZEPHYR_DRIVERS_SPI_RTIO_H_ */ From 00abc5a66133f311e9f71ccd5318e2dac61d42d1 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Sat, 17 Aug 2024 08:36:52 -0400 Subject: [PATCH 086/269] spi: rtio: Move spi_rtio_copy to spi_rtio To group all common APIs for SPI RTIO. Signed-off-by: Luis Ubieda --- drivers/spi/spi_rtio.c | 158 ++++++++++++++++++++++++++++++ drivers/spi/spi_sam.c | 1 + include/zephyr/drivers/spi.h | 158 ------------------------------ include/zephyr/drivers/spi/rtio.h | 18 ++++ 4 files changed, 177 insertions(+), 158 deletions(-) diff --git a/drivers/spi/spi_rtio.c b/drivers/spi/spi_rtio.c index 2852eb9df6e09ce..c514b5acad63e2b 100644 --- a/drivers/spi/spi_rtio.c +++ b/drivers/spi/spi_rtio.c @@ -109,6 +109,164 @@ void spi_rtio_iodev_default_submit(const struct device *dev, rtio_work_req_submit(req, iodev_sqe, spi_rtio_iodev_default_submit_sync); } +/** + * @brief Copy the tx_bufs and rx_bufs into a set of RTIO requests + * + * @param[in] r rtio context + * @param[in] iodev iodev to transceive with + * @param[in] tx_bufs transmit buffer set + * @param[in] rx_bufs receive buffer set + * @param[out] last_sqe last sqe submitted, NULL if not enough memory + * + * @retval Number of submission queue entries + * @retval -ENOMEM out of memory + */ +int spi_rtio_copy(struct rtio *r, + struct rtio_iodev *iodev, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + struct rtio_sqe **last_sqe) +{ + int ret = 0; + size_t tx_count = tx_bufs ? tx_bufs->count : 0; + size_t rx_count = rx_bufs ? rx_bufs->count : 0; + + uint32_t tx = 0, tx_len = 0; + uint32_t rx = 0, rx_len = 0; + uint8_t *tx_buf, *rx_buf; + + struct rtio_sqe *sqe = NULL; + + if (tx < tx_count) { + tx_buf = tx_bufs->buffers[tx].buf; + tx_len = tx_bufs->buffers[tx].len; + } else { + tx_buf = NULL; + tx_len = rx_bufs->buffers[rx].len; + } + + if (rx < rx_count) { + rx_buf = rx_bufs->buffers[rx].buf; + rx_len = rx_bufs->buffers[rx].len; + } else { + rx_buf = NULL; + rx_len = tx_bufs->buffers[tx].len; + } + + + while ((tx < tx_count || rx < rx_count) && (tx_len > 0 || rx_len > 0)) { + sqe = rtio_sqe_acquire(r); + + if (sqe == NULL) { + ret = -ENOMEM; + rtio_sqe_drop_all(r); + goto out; + } + + ret++; + + /* If tx/rx len are same, we can do a simple transceive */ + if (tx_len == rx_len) { + if (tx_buf == NULL) { + rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, + rx_buf, rx_len, NULL); + } else if (rx_buf == NULL) { + rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, + tx_buf, tx_len, NULL); + } else { + rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, + tx_buf, rx_buf, rx_len, NULL); + } + tx++; + rx++; + if (rx < rx_count) { + rx_buf = rx_bufs->buffers[rx].buf; + rx_len = rx_bufs->buffers[rx].len; + } else { + rx_buf = NULL; + rx_len = 0; + } + if (tx < tx_count) { + tx_buf = tx_bufs->buffers[tx].buf; + tx_len = tx_bufs->buffers[tx].len; + } else { + tx_buf = NULL; + tx_len = 0; + } + } else if (tx_len == 0) { + rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, + (uint8_t *)rx_buf, + (uint32_t)rx_len, + NULL); + rx++; + if (rx < rx_count) { + rx_buf = rx_bufs->buffers[rx].buf; + rx_len = rx_bufs->buffers[rx].len; + } else { + rx_buf = NULL; + rx_len = 0; + } + } else if (rx_len == 0) { + rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, + (uint8_t *)tx_buf, + (uint32_t)tx_len, + NULL); + tx++; + if (tx < tx_count) { + tx_buf = rx_bufs->buffers[rx].buf; + tx_len = rx_bufs->buffers[rx].len; + } else { + tx_buf = NULL; + tx_len = 0; + } + } else if (tx_len > rx_len) { + rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, + (uint8_t *)tx_buf, + (uint8_t *)rx_buf, + (uint32_t)rx_len, + NULL); + tx_len -= rx_len; + tx_buf += rx_len; + rx++; + if (rx < rx_count) { + rx_buf = rx_bufs->buffers[rx].buf; + rx_len = rx_bufs->buffers[rx].len; + } else { + rx_buf = NULL; + rx_len = tx_len; + } + } else if (rx_len > tx_len) { + rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, + (uint8_t *)tx_buf, + (uint8_t *)rx_buf, + (uint32_t)tx_len, + NULL); + rx_len -= tx_len; + rx_buf += tx_len; + tx++; + if (tx < tx_count) { + tx_buf = tx_bufs->buffers[tx].buf; + tx_len = tx_bufs->buffers[tx].len; + } else { + tx_buf = NULL; + tx_len = rx_len; + } + } else { + __ASSERT(false, "Invalid %s state", __func__); + } + + sqe->flags = RTIO_SQE_TRANSACTION; + } + + if (sqe != NULL) { + sqe->flags = 0; + *last_sqe = sqe; + } + +out: + return ret; +} + /** * @brief Lock the SPI RTIO spinlock * diff --git a/drivers/spi/spi_sam.c b/drivers/spi/spi_sam.c index fc8e296194ef0c8..e8fd42375ab082e 100644 --- a/drivers/spi/spi_sam.c +++ b/drivers/spi/spi_sam.c @@ -17,6 +17,7 @@ LOG_MODULE_REGISTER(spi_sam); #include #include #include +#include #include #include #include diff --git a/include/zephyr/drivers/spi.h b/include/zephyr/drivers/spi.h index 56d2cd3d925382b..958211e8294d03f 100644 --- a/include/zephyr/drivers/spi.h +++ b/include/zephyr/drivers/spi.h @@ -1085,164 +1085,6 @@ static inline bool spi_is_ready_iodev(const struct rtio_iodev *spi_iodev) return spi_is_ready_dt(spec); } -/** - * @brief Copy the tx_bufs and rx_bufs into a set of RTIO requests - * - * @param[in] r rtio context - * @param[in] iodev iodev to transceive with - * @param[in] tx_bufs transmit buffer set - * @param[in] rx_bufs receive buffer set - * @param[out] last_sqe last sqe submitted, NULL if not enough memory - * - * @retval Number of submission queue entries - * @retval -ENOMEM out of memory - */ -static inline int spi_rtio_copy(struct rtio *r, - struct rtio_iodev *iodev, - const struct spi_buf_set *tx_bufs, - const struct spi_buf_set *rx_bufs, - struct rtio_sqe **last_sqe) -{ - int ret = 0; - size_t tx_count = tx_bufs ? tx_bufs->count : 0; - size_t rx_count = rx_bufs ? rx_bufs->count : 0; - - uint32_t tx = 0, tx_len = 0; - uint32_t rx = 0, rx_len = 0; - uint8_t *tx_buf, *rx_buf; - - struct rtio_sqe *sqe = NULL; - - if (tx < tx_count) { - tx_buf = tx_bufs->buffers[tx].buf; - tx_len = tx_bufs->buffers[tx].len; - } else { - tx_buf = NULL; - tx_len = rx_bufs->buffers[rx].len; - } - - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = tx_bufs->buffers[tx].len; - } - - - while ((tx < tx_count || rx < rx_count) && (tx_len > 0 || rx_len > 0)) { - sqe = rtio_sqe_acquire(r); - - if (sqe == NULL) { - ret = -ENOMEM; - rtio_sqe_drop_all(r); - goto out; - } - - ret++; - - /* If tx/rx len are same, we can do a simple transceive */ - if (tx_len == rx_len) { - if (tx_buf == NULL) { - rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, - rx_buf, rx_len, NULL); - } else if (rx_buf == NULL) { - rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, - tx_buf, tx_len, NULL); - } else { - rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, - tx_buf, rx_buf, rx_len, NULL); - } - tx++; - rx++; - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = 0; - } - if (tx < tx_count) { - tx_buf = tx_bufs->buffers[tx].buf; - tx_len = tx_bufs->buffers[tx].len; - } else { - tx_buf = NULL; - tx_len = 0; - } - } else if (tx_len == 0) { - rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)rx_buf, - (uint32_t)rx_len, - NULL); - rx++; - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = 0; - } - } else if (rx_len == 0) { - rtio_sqe_prep_write(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)tx_buf, - (uint32_t)tx_len, - NULL); - tx++; - if (tx < tx_count) { - tx_buf = rx_bufs->buffers[rx].buf; - tx_len = rx_bufs->buffers[rx].len; - } else { - tx_buf = NULL; - tx_len = 0; - } - } else if (tx_len > rx_len) { - rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)tx_buf, - (uint8_t *)rx_buf, - (uint32_t)rx_len, - NULL); - tx_len -= rx_len; - tx_buf += rx_len; - rx++; - if (rx < rx_count) { - rx_buf = rx_bufs->buffers[rx].buf; - rx_len = rx_bufs->buffers[rx].len; - } else { - rx_buf = NULL; - rx_len = tx_len; - } - } else if (rx_len > tx_len) { - rtio_sqe_prep_transceive(sqe, iodev, RTIO_PRIO_NORM, - (uint8_t *)tx_buf, - (uint8_t *)rx_buf, - (uint32_t)tx_len, - NULL); - rx_len -= tx_len; - rx_buf += tx_len; - tx++; - if (tx < tx_count) { - tx_buf = tx_bufs->buffers[tx].buf; - tx_len = tx_bufs->buffers[tx].len; - } else { - tx_buf = NULL; - tx_len = rx_len; - } - } else { - __ASSERT_NO_MSG("Invalid spi_rtio_copy state"); - } - - sqe->flags = RTIO_SQE_TRANSACTION; - } - - if (sqe != NULL) { - sqe->flags = 0; - *last_sqe = sqe; - } - -out: - return ret; -} - #endif /* CONFIG_SPI_RTIO */ /** diff --git a/include/zephyr/drivers/spi/rtio.h b/include/zephyr/drivers/spi/rtio.h index 91726655c85e3a7..04d5bad8e691190 100644 --- a/include/zephyr/drivers/spi/rtio.h +++ b/include/zephyr/drivers/spi/rtio.h @@ -41,6 +41,24 @@ struct spi_rtio { .r = &CONCAT(_name, _r), \ }; +/** + * @brief Copy the tx_bufs and rx_bufs into a set of RTIO requests + * + * @param[in] r rtio context + * @param[in] iodev iodev to transceive with + * @param[in] tx_bufs transmit buffer set + * @param[in] rx_bufs receive buffer set + * @param[out] last_sqe last sqe submitted, NULL if not enough memory + * + * @retval Number of submission queue entries + * @retval -ENOMEM out of memory + */ +int spi_rtio_copy(struct rtio *r, + struct rtio_iodev *iodev, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs, + struct rtio_sqe **last_sqe); + /** * @brief Initialize a SPI RTIO context * From 3c3487ae07456ff135acf8b90bb4dd6a4269cd1d Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Tue, 27 Aug 2024 17:28:11 +0200 Subject: [PATCH 087/269] drivers: clock_control: Expose enabled_clock for clock driver library Expose the helper function enabled_clock so that it can be used in other clock library sources. Signed-off-by: Joakim Andersson --- drivers/clock_control/clock_stm32_ll_common.c | 3 +-- drivers/clock_control/clock_stm32_ll_common.h | 1 + drivers/clock_control/clock_stm32_ll_h5.c | 2 +- drivers/clock_control/clock_stm32_ll_h7.c | 2 +- drivers/clock_control/clock_stm32_ll_u5.c | 2 +- drivers/clock_control/clock_stm32_ll_wba.c | 3 +-- 6 files changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 3188725cc408c03..dc81015949e3851 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -113,8 +113,7 @@ static uint32_t get_msi_frequency(void) } /** @brief Verifies clock is part of active clock configuration */ -__unused -static int enabled_clock(uint32_t src_clk) +int enabled_clock(uint32_t src_clk) { int r = 0; diff --git a/drivers/clock_control/clock_stm32_ll_common.h b/drivers/clock_control/clock_stm32_ll_common.h index a97d01337acac66..e13fb34c2d3e1fc 100644 --- a/drivers/clock_control/clock_stm32_ll_common.h +++ b/drivers/clock_control/clock_stm32_ll_common.h @@ -50,6 +50,7 @@ void config_plli2s(void); #endif void config_enable_default_clocks(void); void config_regulator_voltage(uint32_t hclk_freq); +int enabled_clock(uint32_t src_clk); /* functions exported to the soc power.c */ int stm32_clock_control_init(const struct device *dev); diff --git a/drivers/clock_control/clock_stm32_ll_h5.c b/drivers/clock_control/clock_stm32_ll_h5.c index 385ee9098635801..c7ecfe081235542 100644 --- a/drivers/clock_control/clock_stm32_ll_h5.c +++ b/drivers/clock_control/clock_stm32_ll_h5.c @@ -117,7 +117,7 @@ static uint32_t get_sysclk_frequency(void) } /** @brief Verifies clock is part of active clock configuration */ -static int enabled_clock(uint32_t src_clk) +int enabled_clock(uint32_t src_clk) { if ((src_clk == STM32_SRC_SYSCLK) || ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) || diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 3e31661b58966c8..e82dc42d5695843 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -356,7 +356,7 @@ static uint32_t get_vco_output_range(uint32_t vco_input_range) #endif /* ! CONFIG_CPU_CORTEX_M4 */ /** @brief Verifies clock is part of active clock configuration */ -static int enabled_clock(uint32_t src_clk) +int enabled_clock(uint32_t src_clk) { if ((src_clk == STM32_SRC_SYSCLK) || diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c index 0c5d587c4bd2d0a..8d1ba380cf3f5a8 100644 --- a/drivers/clock_control/clock_stm32_ll_u5.c +++ b/drivers/clock_control/clock_stm32_ll_u5.c @@ -121,7 +121,7 @@ static uint32_t get_sysclk_frequency(void) } /** @brief Verifies clock is part of active clock configuration */ -static int enabled_clock(uint32_t src_clk) +int enabled_clock(uint32_t src_clk) { if ((src_clk == STM32_SRC_SYSCLK) || ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) || diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c index 37d96a8078ad55a..3000120a2b7d6e5 100644 --- a/drivers/clock_control/clock_stm32_ll_wba.c +++ b/drivers/clock_control/clock_stm32_ll_wba.c @@ -41,8 +41,7 @@ static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler) } /** @brief Verifies clock is part of active clock configuration */ -__unused -static int enabled_clock(uint32_t src_clk) +int enabled_clock(uint32_t src_clk) { if ((src_clk == STM32_SRC_SYSCLK) || ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) || From 807ccf5b0337975fad7f3c6ca1312f0dd132a99b Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Tue, 3 Sep 2024 16:09:04 +0200 Subject: [PATCH 088/269] drivers: clock_control: Add clock sources to common enabled_clock check Add clock sources PLL2CLK, PLL3CLK and EXT_HSE. Needed to check that these clocks are enabled in MCO code. Signed-off-by: Joakim Andersson --- drivers/clock_control/clock_stm32_ll_common.c | 21 +++++++++++++++++++ drivers/clock_control/clock_stm32f1.c | 9 ++++++++ 2 files changed, 30 insertions(+) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index dc81015949e3851..de185f026ec9745 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -133,6 +133,13 @@ int enabled_clock(uint32_t src_clk) } break; #endif /* STM32_SRC_HSE */ +#if defined(STM32_SRC_EXT_HSE) + case STM32_SRC_EXT_HSE: + /* EXT_HSE is the raw OSC_IN signal, so it is always + * available, regardless of the clocks configuration. + */ + break; +#endif /* STM32_SRC_HSE */ #if defined(STM32_SRC_HSI) case STM32_SRC_HSI: if (!IS_ENABLED(STM32_HSI_ENABLED)) { @@ -210,6 +217,20 @@ int enabled_clock(uint32_t src_clk) } break; #endif /* STM32_SRC_PLLI2S_R */ +#if defined(STM32_SRC_PLL2CLK) + case STM32_SRC_PLL2CLK: + if (!IS_ENABLED(STM32_PLL2_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif +#if defined(STM32_SRC_PLL3CLK) + case STM32_SRC_PLL3CLK: + if (!IS_ENABLED(STM32_PLL3_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif default: return -ENOTSUP; } diff --git a/drivers/clock_control/clock_stm32f1.c b/drivers/clock_control/clock_stm32f1.c index 760e417eaab0e38..752d29aba9f2220 100644 --- a/drivers/clock_control/clock_stm32f1.c +++ b/drivers/clock_control/clock_stm32f1.c @@ -23,6 +23,15 @@ #if defined(STM32_PLL_ENABLED) +uint32_t get_pllout_frequency(void) +{ + /* Stub implementation for compatibility with clock_stm32_ll_common. + * The PLL domain clock is only used for MCO configuration, but the + * MCO driver never queries the PLL output clock frequency. + */ + return 0; +} + /* * Select PLL source for STM32F1 Connectivity line devices (STM32F105xx and * STM32F107xx). From efe72a3c7ae7e9900e13a73432a73fa47328ad4a Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 31 Jul 2024 15:47:56 +0200 Subject: [PATCH 089/269] dt-bindings: clock: Add clock sources for stm32f1x/10x for MCO Add clock sources that can be output by the MCO on the stm32f1x and stm32f10 connectivity line devices. Signed-off-by: Joakim Andersson --- dts/arm/st/f1/stm32f105.dtsi | 1 + .../clock_control/stm32_clock_control.h | 4 ++++ .../dt-bindings/clock/stm32f10x_clock.h | 21 +++++++++++++++++++ .../zephyr/dt-bindings/clock/stm32f1_clock.h | 6 +++--- 4 files changed, 29 insertions(+), 3 deletions(-) create mode 100644 include/zephyr/dt-bindings/clock/stm32f10x_clock.h diff --git a/dts/arm/st/f1/stm32f105.dtsi b/dts/arm/st/f1/stm32f105.dtsi index 6d62e2ce658f53f..6df7f92f9e60a6d 100644 --- a/dts/arm/st/f1/stm32f105.dtsi +++ b/dts/arm/st/f1/stm32f105.dtsi @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include / { diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index e9a2685623f2346..ca575f373a07da4 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -17,7 +17,11 @@ #elif defined(CONFIG_SOC_SERIES_STM32F0X) #include #elif defined(CONFIG_SOC_SERIES_STM32F1X) +#if defined(CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE) +#include +#else #include +#endif #elif defined(CONFIG_SOC_SERIES_STM32F3X) #include #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \ diff --git a/include/zephyr/dt-bindings/clock/stm32f10x_clock.h b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h new file mode 100644 index 000000000000000..ea93e6a746d4603 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h @@ -0,0 +1,21 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2024, Joakim Andersson + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ + +#include "stm32_common_clocks.h" +/* Ensure correct order by including generic F1 definitions first. */ +#include "stm32f1_clock.h" + +/** Fixed clocks */ +/* Low speed clocks defined in stm32_common_clocks.h */ +/* Common clocks with stm32f1x defined in stm32f1_clock.h */ +#define STM32_SRC_PLL2CLK (STM32_SRC_PLLCLK + 1) +#define STM32_SRC_PLL3CLK (STM32_SRC_PLL2CLK + 1) +#define STM32_SRC_EXT_HSE (STM32_SRC_PLL3CLK + 1) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f1_clock.h b/include/zephyr/dt-bindings/clock/stm32f1_clock.h index 571014dd2f09722..aa0377e7059b36a 100644 --- a/include/zephyr/dt-bindings/clock/stm32f1_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f1_clock.h @@ -23,9 +23,9 @@ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ -#define STM32_SRC_HSI (STM32_SRC_LSI + 1) -#define STM32_SRC_HSE (STM32_SRC_HSI + 1) - +#define STM32_SRC_HSI (STM32_SRC_LSI + 1) +#define STM32_SRC_HSE (STM32_SRC_HSI + 1) +#define STM32_SRC_PLLCLK (STM32_SRC_HSE + 1) #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U From 9925ce792ea9a3c5a744c4ef17bcfb8265d7d171 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Tue, 27 Aug 2024 18:48:24 +0200 Subject: [PATCH 090/269] include: dt-bindings: Add MCO select and prescaler macros for CFGR reg Add MCO select and prescaler macros to set bits in the RCC CFGRx register. The set of supported boards are chosen to replace what is currently supported in Kconfig. Signed-off-by: Joakim Andersson --- include/zephyr/dt-bindings/clock/stm32f0_clock.h | 5 +++++ include/zephyr/dt-bindings/clock/stm32f10x_clock.h | 5 +++++ include/zephyr/dt-bindings/clock/stm32f1_clock.h | 7 ++++++- include/zephyr/dt-bindings/clock/stm32f3_clock.h | 2 ++ include/zephyr/dt-bindings/clock/stm32f4_clock.h | 6 +++++- include/zephyr/dt-bindings/clock/stm32f7_clock.h | 4 ++++ include/zephyr/dt-bindings/clock/stm32h5_clock.h | 9 +++++++++ include/zephyr/dt-bindings/clock/stm32h7_clock.h | 8 ++++++++ include/zephyr/dt-bindings/clock/stm32h7rs_clock.h | 9 +++++++++ include/zephyr/dt-bindings/clock/stm32l4_clock.h | 6 ++++++ include/zephyr/dt-bindings/clock/stm32u5_clock.h | 7 +++++++ 11 files changed, 66 insertions(+), 2 deletions(-) diff --git a/include/zephyr/dt-bindings/clock/stm32f0_clock.h b/include/zephyr/dt-bindings/clock/stm32f0_clock.h index 116457358305c82..0ddf7aff909660d 100644 --- a/include/zephyr/dt-bindings/clock/stm32f0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f0_clock.h @@ -59,6 +59,7 @@ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) /** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x04 #define CFGR3_REG 0x30 /** @brief RCC_BDCR register offset */ @@ -75,4 +76,8 @@ /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f10x_clock.h b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h index ea93e6a746d4603..3570327cb9f0871 100644 --- a/include/zephyr/dt-bindings/clock/stm32f10x_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h @@ -18,4 +18,9 @@ #define STM32_SRC_PLL3CLK (STM32_SRC_PLL2CLK + 1) #define STM32_SRC_EXT_HSE (STM32_SRC_PLL3CLK + 1) +/** CFGR1 devices */ +#undef MCO1_SEL /* Need to redefine generic F1 MCO_SEL for connectivity line devices. */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) +/* No MCO prescaler support on STM32F1 series. */ + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f1_clock.h b/include/zephyr/dt-bindings/clock/stm32f1_clock.h index aa0377e7059b36a..31e7d99b8303edf 100644 --- a/include/zephyr/dt-bindings/clock/stm32f1_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f1_clock.h @@ -55,7 +55,8 @@ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) -/** @brief RCC_CFGR2 register offset */ +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x04 #define CFGR2_REG 0x2C /** @brief RCC_BDCR register offset */ @@ -68,4 +69,8 @@ /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) +/* No MCO prescaler support on STM32F1 series. */ + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32f3_clock.h b/include/zephyr/dt-bindings/clock/stm32f3_clock.h index 377eb4fdaad73cb..eb7f5780ad97b77 100644 --- a/include/zephyr/dt-bindings/clock/stm32f3_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f3_clock.h @@ -69,6 +69,8 @@ /** @brief Device domain clocks selection helpers) */ /** CFGR devices */ #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG) /** CFGR3 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CFGR3_REG) #define I2C1_SEL(val) STM32_CLOCK(val, 1, 4, CFGR3_REG) diff --git a/include/zephyr/dt-bindings/clock/stm32f4_clock.h b/include/zephyr/dt-bindings/clock/stm32f4_clock.h index 93355865fdd0660..975f90bea39a2d2 100644 --- a/include/zephyr/dt-bindings/clock/stm32f4_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f4_clock.h @@ -66,7 +66,7 @@ (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) -/** @brief RCC_CFGR register offset */ +/** @brief RCC_CFGRx register offset */ #define CFGR_REG 0x08 /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 @@ -74,6 +74,10 @@ /** @brief Device domain clocks selection helpers */ /** CFGR devices */ #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) diff --git a/include/zephyr/dt-bindings/clock/stm32f7_clock.h b/include/zephyr/dt-bindings/clock/stm32f7_clock.h index 92d3b7e12211a1f..e2cf539ef3bfc33 100644 --- a/include/zephyr/dt-bindings/clock/stm32f7_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f7_clock.h @@ -75,6 +75,10 @@ /** @brief Device domain clocks selection helpers */ /** CFGR devices */ #define I2S_SEL(val) STM32_CLOCK(val, 1, 23, CFGR_REG) +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) diff --git a/include/zephyr/dt-bindings/clock/stm32h5_clock.h b/include/zephyr/dt-bindings/clock/stm32h5_clock.h index 070f3b3aad469f8..197d26ccea67234 100644 --- a/include/zephyr/dt-bindings/clock/stm32h5_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h5_clock.h @@ -84,6 +84,9 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0xF0 +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x1C + /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 7, 0, CCIPR1_REG) @@ -142,4 +145,10 @@ /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0xF, 18, CFGR1_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR1_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR1_REG) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H5_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32h7_clock.h b/include/zephyr/dt-bindings/clock/stm32h7_clock.h index 02ed14f2a7bc40a..e38ac61e2b3c22f 100644 --- a/include/zephyr/dt-bindings/clock/stm32h7_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h7_clock.h @@ -95,6 +95,9 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 +/** @brief RCC_CFGRx register offset */ +#define CFGR_REG 0x10 + /** @brief Device domain clocks selection helpers (RM0399.pdf) */ /** D1CCIPR devices */ #define FMC_SEL(val) STM32_CLOCK(val, 3, 0, D1CCIPR_REG) @@ -132,5 +135,10 @@ #define SPI6_SEL(val) STM32_CLOCK(val, 7, 28, D3CCIPR_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 18, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h index 579ae56b0e250e8..d16f8208152323b 100644 --- a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h @@ -91,6 +91,9 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x70 +/** @brief RCC_CFGRx register offset */ +#define CFGR_REG 0x10 + /** @brief Device domain clocks selection helpers (RM0477.pdf) */ /* TODO to be completed */ @@ -128,4 +131,10 @@ /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0xF, 18, CFGR_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 29, CFGR_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0xF, 25, CFGR_REG) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32l4_clock.h b/include/zephyr/dt-bindings/clock/stm32l4_clock.h index 8249a1bf17155e9..806939580f800ea 100644 --- a/include/zephyr/dt-bindings/clock/stm32l4_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32l4_clock.h @@ -72,6 +72,9 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0x90 +/** @brief RCC_CFGRx register offset */ +#define CFGR_REG 0x08 + /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) @@ -102,5 +105,8 @@ #define OSPI_SEL(val) STM32_CLOCK(val, 3, 20, CCIPR2_REG) /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/stm32u5_clock.h b/include/zephyr/dt-bindings/clock/stm32u5_clock.h index 6f240fb37b30b42..5c5d5344a686753 100644 --- a/include/zephyr/dt-bindings/clock/stm32u5_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32u5_clock.h @@ -83,6 +83,9 @@ /** @brief RCC_BDCR register offset */ #define BDCR_REG 0xF0 +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x1C + /** @brief Device domain clocks selection helpers */ /** CCIPR1 devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR1_REG) @@ -127,4 +130,8 @@ /** BDCR devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, BDCR_REG) +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U5_CLOCK_H_ */ From bd592fac8ba5d6aeef781a4d30fd7e4bc69ee124 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Fri, 6 Sep 2024 11:20:48 +0200 Subject: [PATCH 091/269] dts: bindings: Add stm32 microcontroller clock output binding Add stm32 microcontroller clock output binding. Signed-off-by: Joakim Andersson --- dts/bindings/clock/st,stm32-clock-mco.yaml | 39 ++++++++++++++++++++ dts/bindings/clock/st,stm32f1-clock-mco.yaml | 38 +++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 dts/bindings/clock/st,stm32-clock-mco.yaml create mode 100644 dts/bindings/clock/st,stm32f1-clock-mco.yaml diff --git a/dts/bindings/clock/st,stm32-clock-mco.yaml b/dts/bindings/clock/st,stm32-clock-mco.yaml new file mode 100644 index 000000000000000..6e27ebccf7519f1 --- /dev/null +++ b/dts/bindings/clock/st,stm32-clock-mco.yaml @@ -0,0 +1,39 @@ +# +# Copyright (c) 2024, Joakim Andersson +# +# SPDX-License-Identifier: Apache-2.0 +# + +compatible: "st,stm32-clock-mco" + +description: | + STM32 Microcontroller Clock Output (MCO) + + Used to output a clock signal from the MCU to a GPIO pin. + The selected signal goes through a configurable prescaler before output. + + Example: + &mco1 { + clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>; + prescaler = ; + pinctrl-0 = <&rcc_mco_pa8>; + pinctrl-names = "default"; + status = "okay"; + }; + +include: [base.yaml, pinctrl-device.yaml] + +properties: + + clocks: + required: true + + prescaler: + type: int + required: true + + pinctrl-0: + required: true + + pinctrl-names: + required: true diff --git a/dts/bindings/clock/st,stm32f1-clock-mco.yaml b/dts/bindings/clock/st,stm32f1-clock-mco.yaml new file mode 100644 index 000000000000000..5024a8166023f11 --- /dev/null +++ b/dts/bindings/clock/st,stm32f1-clock-mco.yaml @@ -0,0 +1,38 @@ +# +# Copyright (c) 2024, Joakim Andersson +# +# SPDX-License-Identifier: Apache-2.0 +# + +compatible: "st,stm32f1-clock-mco" + +description: | + STM32 F1 series Microcontroller Clock Output (MCO) + + The STM32F1 MCO is similar to other series but has no configurable + prescaler before the output. However, note that certain inputs of + the MCO are fitted with a fixed prescaler, making it possible to + output a slowed down variation of certain clocks. + + Example: + &mco1 { + clocks = <&rcc STM32_SRC_LSE MCO1_SEL(7)>; + pinctrl-0 = <&rcc_mco_pa8>; + pinctrl-names = "default"; + status = "okay"; + }; + + Note: in the `clocks` property, the domain clock source cell should + use the value representing the base clock, regardless of whether or + not the selected input is fitted with a prescaler. + + Example: + /* PLL3 clock divided by 2 */ + clocks = <&rcc STM32_SRC_PLL3CLK MCO1_SEL(9)>; + /* PLL3 clock */ + clocks = <&rcc STM32_SRC_PLL3CLK MCO1_SEL(11)>; + +include: + - name: st,stm32-clock-mco.yaml + property-blocklist: + - prescaler From 4b9dfe2a16f15c3d77ee4bf10c001847c06b595a Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Fri, 6 Sep 2024 11:24:34 +0200 Subject: [PATCH 092/269] include: Add STM32_MCO_CFGR bit encoding and decoding Add macro for encoding MCO bit values into the CFGR register of RCC. Add macros for decoding and extracting the different fields. Signed-off-by: Joakim Andersson --- .../clock_control/stm32_clock_control.h | 32 +++++++++++++++++++ .../dt-bindings/clock/stm32_common_clocks.h | 30 +++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index ca575f373a07da4..c33714be97629e9 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -493,6 +493,38 @@ struct stm32_pclken { #define STM32_CLOCK_VAL_GET(clock) \ (((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK) +/** + * @brief Obtain register field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_REG_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_REG_SHIFT) & STM32_MCO_CFGR_REG_MASK) + +/** + * @brief Obtain position field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_SHIFT_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_SHIFT_SHIFT) & STM32_MCO_CFGR_SHIFT_MASK) + +/** + * @brief Obtain mask field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_MASK_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_MASK_SHIFT) & STM32_MCO_CFGR_MASK_MASK) + +/** + * @brief Obtain value field from MCO configuration. + * + * @param mco_cfgr MCO configuration bit field value. + */ +#define STM32_MCO_CFGR_VAL_GET(mco_cfgr) \ + (((mco_cfgr) >> STM32_MCO_CFGR_VAL_SHIFT) & STM32_MCO_CFGR_VAL_MASK) + #if defined(STM32_HSE_CSS) /** * @brief Called if the HSE clock security system detects a clock fault. diff --git a/include/zephyr/dt-bindings/clock/stm32_common_clocks.h b/include/zephyr/dt-bindings/clock/stm32_common_clocks.h index 030ec2d939bbe85..721904cce777320 100644 --- a/include/zephyr/dt-bindings/clock/stm32_common_clocks.h +++ b/include/zephyr/dt-bindings/clock/stm32_common_clocks.h @@ -15,4 +15,34 @@ /** Dummy: Add a specifier when no selection is possible */ #define NO_SEL 0xFF +/** STM32 MCO configuration values */ +#define STM32_MCO_CFGR_REG_MASK 0xFFFFU +#define STM32_MCO_CFGR_REG_SHIFT 0U +#define STM32_MCO_CFGR_SHIFT_MASK 0x3FU +#define STM32_MCO_CFGR_SHIFT_SHIFT 16U +#define STM32_MCO_CFGR_MASK_MASK 0x1FU +#define STM32_MCO_CFGR_MASK_SHIFT 22U +#define STM32_MCO_CFGR_VAL_MASK 0x1FU +#define STM32_MCO_CFGR_VAL_SHIFT 27U + +/** + * @brief STM32 MCO configuration register bit field + * + * @param reg Offset to RCC register holding MCO configuration + * @param shift Position of field within RCC register (= field LSB's index) + * @param mask Mask of register field in RCC register + * @param val Clock configuration field value (0~0x1F) + * + * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ] + * @note 'shift' range: 0~63 [ 16 : 21 ] + * @note 'mask' range: 0x00~0x1F [ 22 : 26 ] + * @note 'val' range: 0x00~0x1F [ 27 : 31 ] + * + */ +#define STM32_MCO_CFGR(val, mask, shift, reg) \ + ((((reg) & STM32_MCO_CFGR_REG_MASK) << STM32_MCO_CFGR_REG_SHIFT) | \ + (((shift) & STM32_MCO_CFGR_SHIFT_MASK) << STM32_MCO_CFGR_SHIFT_SHIFT) | \ + (((mask) & STM32_MCO_CFGR_MASK_MASK) << STM32_MCO_CFGR_MASK_SHIFT) | \ + (((val) & STM32_MCO_CFGR_VAL_MASK) << STM32_MCO_CFGR_VAL_SHIFT)) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32_COMMON_CLOCKS_H_ */ From 929c4507fcc06c6965cbab72e07a5c9f985b9d99 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 31 Jul 2024 11:58:53 +0200 Subject: [PATCH 093/269] drivers: Add driver for STM32 MCO peripheral Add device driver for STM32 MCO peripheral which takes configures the MCO clock source and prescaler, and outputs it on one of the GPIO pins. Signed-off-by: Joakim Andersson --- drivers/clock_control/CMakeLists.txt | 1 + drivers/clock_control/Kconfig.stm32 | 9 ++- drivers/clock_control/clock_stm32_mco.c | 84 +++++++++++++++++++++++++ 3 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 drivers/clock_control/clock_stm32_mco.c diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index 10fcc33f01a7065..ffc19a3b729c08e 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -46,6 +46,7 @@ endif() if(CONFIG_CLOCK_CONTROL_STM32_CUBE) zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MUX clock_stm32_mux.c) + zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MCO clock_stm32_mco.c) if(CONFIG_SOC_SERIES_STM32MP1X) zephyr_library_sources(clock_stm32_ll_mp1.c) elseif(CONFIG_SOC_SERIES_STM32H7X) diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32 index 487fc00541fd36c..38f7bc25e4b5aac 100644 --- a/drivers/clock_control/Kconfig.stm32 +++ b/drivers/clock_control/Kconfig.stm32 @@ -92,7 +92,14 @@ config STM32WB0_LSI_RUNTIME_MEASUREMENT_INTERVAL endmenu # DT_HAS_ST_STM32WB0_LSI_CLOCK_ENABLED -# Micro-controller Clock output configuration options +# Micro-controller Clock Output (MCO) configuration options +config CLOCK_STM32_MCO + bool + default y + depends on DT_HAS_ST_STM32_CLOCK_MCO_ENABLED || DT_HAS_ST_STM32F1_CLOCK_MCO_ENABLED + # MCO configuration via Kconfig takes priority over Device Tree. + # Prevent DT-based MCO driver from compiling when Kconfig is used. + depends on CLOCK_STM32_MCO1_SRC_NOCLOCK && CLOCK_STM32_MCO2_SRC_NOCLOCK choice prompt "STM32 MCO1 Clock Source" diff --git a/drivers/clock_control/clock_stm32_mco.c b/drivers/clock_control/clock_stm32_mco.c new file mode 100644 index 000000000000000..0e8d6faec266152 --- /dev/null +++ b/drivers/clock_control/clock_stm32_mco.c @@ -0,0 +1,84 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (C) 2024, Joakim Andersson + */ + +#include +#include +#include +#include +#include +#include "clock_stm32_ll_common.h" + +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_clock_mco) +#define DT_DRV_COMPAT st_stm32_clock_mco +#define HAS_PRESCALER 1 +#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_clock_mco) +#define DT_DRV_COMPAT st_stm32f1_clock_mco +#endif + +struct stm32_mco_config { + const struct pinctrl_dev_config *pcfg; +#if defined(HAS_PRESCALER) + uint32_t prescaler; +#endif + /* clock subsystem driving this peripheral */ + const struct stm32_pclken pclken[1]; +}; + +static int stm32_mco_init(const struct device *dev) +{ + const struct stm32_mco_config *config = dev->config; + const struct stm32_pclken *pclken = &config->pclken[0]; + int err; + + err = enabled_clock(pclken->bus); + if (err < 0) { + /* Attempt to configure a src clock not available or not valid */ + return err; + } + + /* MCO source */ + sys_clear_bits( + DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr), + STM32_MCO_CFGR_MASK_GET(pclken->enr) << + STM32_MCO_CFGR_SHIFT_GET(pclken->enr)); + sys_set_bits( + DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr), + STM32_MCO_CFGR_VAL_GET(pclken->enr) << + STM32_MCO_CFGR_SHIFT_GET(pclken->enr)); + +#if defined(HAS_PRESCALER) + /* MCO prescaler */ + sys_clear_bits( + DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(config->prescaler), + STM32_MCO_CFGR_MASK_GET(config->prescaler) << + STM32_MCO_CFGR_SHIFT_GET(config->prescaler)); + sys_set_bits( + DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(config->prescaler), + STM32_MCO_CFGR_VAL_GET(config->prescaler) << + STM32_MCO_CFGR_SHIFT_GET(config->prescaler)); +#endif + + return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); +} + +#define STM32_MCO_INIT(inst) \ + \ +PINCTRL_DT_INST_DEFINE(inst); \ + \ +const static struct stm32_mco_config stm32_mco_config_##inst = { \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \ + .pclken = STM32_DT_INST_CLOCKS(inst), \ + IF_ENABLED(HAS_PRESCALER, \ + (.prescaler = DT_PROP(DT_DRV_INST(inst), prescaler),)) \ +}; \ + \ +DEVICE_DT_INST_DEFINE(inst, stm32_mco_init, NULL, \ + NULL, \ + &stm32_mco_config_##inst, \ + PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ + NULL); + +DT_INST_FOREACH_STATUS_OKAY(STM32_MCO_INIT); From 3b9c34d085cea4dce96b8c3d9fb8bd9a52b76882 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 31 Jul 2024 11:59:08 +0200 Subject: [PATCH 094/269] dts: st: Add MCO node to STM32 boards Add MCO device nodes to the STM32 boards. The set of supported boards are chosen to replace what is currently supported in Kconfig. Signed-off-by: Joakim Andersson --- dts/arm/st/f1/stm32f1.dtsi | 7 +++++++ dts/arm/st/f4/stm32f4.dtsi | 12 ++++++++++++ dts/arm/st/f7/stm32f7.dtsi | 12 ++++++++++++ dts/arm/st/h5/stm32h5.dtsi | 12 ++++++++++++ dts/arm/st/h7/stm32h7.dtsi | 12 ++++++++++++ dts/arm/st/h7rs/stm32h7rs.dtsi | 12 ++++++++++++ dts/arm/st/l4/stm32l4.dtsi | 7 +++++++ dts/arm/st/u5/stm32u5.dtsi | 7 +++++++ 8 files changed, 81 insertions(+) diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi index dc9f140370ec1c1..1f213353c0cacce 100644 --- a/dts/arm/st/f1/stm32f1.dtsi +++ b/dts/arm/st/f1/stm32f1.dtsi @@ -72,6 +72,13 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32f1-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@40022000 { diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index b69d32d6cf30197..2757295f6d8c7ab 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -92,6 +92,18 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + + mco2: mco2 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@40023c00 { compatible = "st,stm32-flash-controller", "st,stm32f4-flash-controller"; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index 439bc560a7d5eb7..d5f7288c5a5f088 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -88,6 +88,18 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + + mco2: mco2 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { fmc: memory-controller@a0000000 { compatible = "st,stm32-fmc"; diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index e659aee6b4152b5..2a086d3ff256fc7 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -98,6 +98,18 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + + mco2: mco2 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@40022000 { compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index c9b8d5e4f968d10..9d7bb3d7c66e8ac 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -127,6 +127,18 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + + mco2: mco2 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@52002000 { compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index 35432a9b9151017..3df6d5398a52ce9 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -158,6 +158,18 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + + mco2: mco2 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@52002000 { compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index 03e7734f7594257..0c4f3c2d576c06c 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -106,6 +106,13 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@40022000 { compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller"; diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index 00eb5f75fd28ce0..b3d22db073960f9 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -148,6 +148,13 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@40022000 { compatible = "st,stm32-flash-controller", "st,stm32l5-flash-controller"; From 0a2c6a00230b790b1bc7ee5eed079ffb46e5dcbe Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Tue, 27 Aug 2024 17:22:18 +0200 Subject: [PATCH 095/269] include: dt-bindings: clock: fix stm32f7 missing HSE and PLLI2S_R source Fix stm32f7 missing the definition for HSE and PLLI2S_R clock source. Signed-off-by: Joakim Andersson --- include/zephyr/dt-bindings/clock/stm32f7_clock.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/zephyr/dt-bindings/clock/stm32f7_clock.h b/include/zephyr/dt-bindings/clock/stm32f7_clock.h index e2cf539ef3bfc33..c20ba27c3a92880 100644 --- a/include/zephyr/dt-bindings/clock/stm32f7_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f7_clock.h @@ -30,13 +30,16 @@ /** Fixed clocks */ /* Low speed clocks defined in stm32_common_clocks.h */ #define STM32_SRC_HSI (STM32_SRC_LSI + 1) +#define STM32_SRC_HSE (STM32_SRC_HSI + 1) /** PLL clock outputs */ -#define STM32_SRC_PLL_P (STM32_SRC_HSI + 1) +#define STM32_SRC_PLL_P (STM32_SRC_HSE + 1) #define STM32_SRC_PLL_Q (STM32_SRC_PLL_P + 1) #define STM32_SRC_PLL_R (STM32_SRC_PLL_Q + 1) /** Peripheral bus clock */ #define STM32_SRC_PCLK (STM32_SRC_PLL_R + 1) +#define STM32_SRC_PLLI2S_R (STM32_SRC_PCLK + 1) + #define STM32_CLOCK_REG_MASK 0xFFU #define STM32_CLOCK_REG_SHIFT 0U From a624fe0f3d71bd86dfdd9a326237b586c35865da Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 28 Aug 2024 10:00:45 +0200 Subject: [PATCH 096/269] boards: Add MCO support for the stm32c0xx family Add MCO support for the stm32c0xx family. Signed-off-by: Joakim Andersson --- dts/arm/st/c0/stm32c0.dtsi | 12 ++++++++++++ include/zephyr/dt-bindings/clock/stm32c0_clock.h | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/dts/arm/st/c0/stm32c0.dtsi b/dts/arm/st/c0/stm32c0.dtsi index f7e58c7b6991933..a18e10c251fcdf0 100644 --- a/dts/arm/st/c0/stm32c0.dtsi +++ b/dts/arm/st/c0/stm32c0.dtsi @@ -67,6 +67,18 @@ }; }; + mcos { + mco1: mco1 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + + mco2: mco2 { + compatible = "st,stm32-clock-mco"; + status = "disabled"; + }; + }; + soc { flash: flash-controller@40022000 { compatible = "st,stm32-flash-controller"; diff --git a/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/include/zephyr/dt-bindings/clock/stm32c0_clock.h index 224bd1517d5e7e0..861543f0ae46b32 100644 --- a/include/zephyr/dt-bindings/clock/stm32c0_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32c0_clock.h @@ -63,6 +63,9 @@ /** @brief RCC_CSR1 register offset */ #define CSR1_REG 0x5C +/** @brief RCC_CFGRx register offset */ +#define CFGR1_REG 0x08 + /** @brief Device domain clocks selection helpers */ /** CCIPR devices */ #define USART1_SEL(val) STM32_CLOCK(val, 3, 0, CCIPR_REG) @@ -72,4 +75,10 @@ /** CSR1 devices */ #define RTC_SEL(val) STM32_CLOCK(val, 3, 8, CSR1_REG) +/** CFGR1 devices */ +#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG) +#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG) +#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG) +#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG) + #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32C0_CLOCK_H_ */ From 438ed892384a4cd019d53a1f3d23bcac4105f359 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 31 Jul 2024 12:00:15 +0200 Subject: [PATCH 097/269] samples: stm32: mco: Update sample to use dts instead of Kconfig Update MCO board sample to use devicetree information instead of Kconfig configurations. Signed-off-by: Joakim Andersson --- samples/boards/st/mco/README.rst | 2 +- .../st/mco/boards/nucleo_u5a5zj_q.overlay | 22 +++++++++++++----- samples/boards/st/mco/prj.conf | 4 +--- samples/boards/st/mco/src/main.c | 23 +++++++++++++------ 4 files changed, 34 insertions(+), 17 deletions(-) diff --git a/samples/boards/st/mco/README.rst b/samples/boards/st/mco/README.rst index d90e512cd39fc12..cb3c1d9e927194f 100644 --- a/samples/boards/st/mco/README.rst +++ b/samples/boards/st/mco/README.rst @@ -14,7 +14,7 @@ Requirements ************ The SoC should support MCO functionality and use a pin that has the MCO alternate function. -To support another board, add an overlay in boards folder. +To support another board, add a dts overlay file in boards folder. Make sure that the output clock is enabled in dts overlay file. diff --git a/samples/boards/st/mco/boards/nucleo_u5a5zj_q.overlay b/samples/boards/st/mco/boards/nucleo_u5a5zj_q.overlay index 9550a1db39e47c4..acff74efdc3b9d0 100644 --- a/samples/boards/st/mco/boards/nucleo_u5a5zj_q.overlay +++ b/samples/boards/st/mco/boards/nucleo_u5a5zj_q.overlay @@ -3,10 +3,20 @@ status = "okay"; }; -/ { - zephyr,user { - /* Select MCO pin to use. */ - pinctrl-0 = <&rcc_mco_pa8>; - pinctrl-names = "default"; - }; +/* See reference manual (RM0456): + * 0b0111: LSE clock selected + */ +#define MCO1_SEL_LSE 7 + +/* See reference manual (RM0456): + * 0b001: MCO divided by 2 + */ +#define MCO1_PRE_DIV_2 1 + +&mco1 { + status = "okay"; + clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO1_SEL_LSE)>; + prescaler = ; + pinctrl-0 = <&rcc_mco_pa8>; + pinctrl-names = "default"; }; diff --git a/samples/boards/st/mco/prj.conf b/samples/boards/st/mco/prj.conf index 4a6f627ff3b80da..b7db25411d06ab7 100644 --- a/samples/boards/st/mco/prj.conf +++ b/samples/boards/st/mco/prj.conf @@ -1,3 +1 @@ -# Set MCO1 source to desired clock. -CONFIG_CLOCK_STM32_MCO1_SRC_LSE=y -CONFIG_CLOCK_STM32_MCO1_DIV=1 +# Empty diff --git a/samples/boards/st/mco/src/main.c b/samples/boards/st/mco/src/main.c index edabdfa67625d87..17554e84c8ade12 100644 --- a/samples/boards/st/mco/src/main.c +++ b/samples/boards/st/mco/src/main.c @@ -7,15 +7,24 @@ #include #include -/* Define the pinctrl information for the MCO pin. */ -PINCTRL_DT_DEFINE(DT_PATH(zephyr_user)); - int main(void) { - /* Configure the MCO pin using pinctrl in order to set the alternate function of the pin. */ - const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_PATH(zephyr_user)); - (void)pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT); + const struct device *dev; + + /* This sample demonstrates MCO usage via Device Tree. + * MCO configuration is performed in the Device Tree overlay files. + * Each MCO will be enabled automatically by the driver during device + * initialization. This sample checks that all MCOs are ready - if so, + * the selected clock should be visible on the chosen GPIO pin. + */ + dev = DEVICE_DT_GET(DT_NODELABEL(mco1)); + if (device_is_ready(dev)) { + printk("MCO1 device successfully configured\n"); + } else { + printk("MCO1 device not ready\n"); + return -1; + } - printk("\nMCO pin configured, end of example.\n"); + printk("\nDisplayed the status of all MCO devices - end of example.\n"); return 0; } From b4ada0dbd14f9f67e9fda0027c7d5b1975c93fc5 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Tue, 27 Aug 2024 17:49:14 +0200 Subject: [PATCH 098/269] samples: stm32: mco: Add disco board which has 2 MCO instances Add stm32f746g_disco board to MCO sample. This board has 2 MCO instances so useful to show multiple instances as well as checking the implementation. Signed-off-by: Joakim Andersson --- .../st/mco/boards/stm32f746g_disco.overlay | 44 +++++++++++++++++++ samples/boards/st/mco/sample.yaml | 2 +- samples/boards/st/mco/src/main.c | 10 +++++ 3 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 samples/boards/st/mco/boards/stm32f746g_disco.overlay diff --git a/samples/boards/st/mco/boards/stm32f746g_disco.overlay b/samples/boards/st/mco/boards/stm32f746g_disco.overlay new file mode 100644 index 000000000000000..a69e0d147b5e48d --- /dev/null +++ b/samples/boards/st/mco/boards/stm32f746g_disco.overlay @@ -0,0 +1,44 @@ +/* The clock that is output must be enabled. */ +&clk_lse { + status = "okay"; +}; + +&clk_hse { + status = "okay"; +}; + +/* See reference manual (RM0385): + * 0b01: LSE oscillator selected + */ +#define MCO1_SEL_LSE 1 + +/* See reference manual (RM0385): + * 0b100: division by 2 + */ +#define MCO1_PRE_DIV_2 4 + +&mco1 { + status = "okay"; + clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO1_SEL_LSE)>; + prescaler = ; + pinctrl-0 = <&rcc_mco_1_pa8>; /* D10 (CN7) */ + pinctrl-names = "default"; +}; + +/* See reference manual (RM0385): + * 0b10: HSE oscillator clock selected + */ +#define MCO2_SEL_HSE 2 + +/* See reference manual (RM0385): + * 0b111: division by 5 + */ +#define MCO2_PRE_DIV_5 7 + +&mco2 { + status = "okay"; + clocks = <&rcc STM32_SRC_HSE MCO2_SEL(MCO2_SEL_HSE)>; + prescaler = ; + pinctrl-0 = <&rcc_mco_2_pc9>; /* uSD_D1 (CN3 pin 8) */ + pinctrl-names = "default"; +}; diff --git a/samples/boards/st/mco/sample.yaml b/samples/boards/st/mco/sample.yaml index 51e41058d486db6..bf8a97cad2a27ef 100644 --- a/samples/boards/st/mco/sample.yaml +++ b/samples/boards/st/mco/sample.yaml @@ -2,5 +2,5 @@ sample: name: STM32 microcontroller clock output (MCO) example tests: sample.board.stm32.mco: - platform_allow: nucleo_u5a5zj_q + platform_allow: nucleo_u5a5zj_q stm32f746g_disco tags: board diff --git a/samples/boards/st/mco/src/main.c b/samples/boards/st/mco/src/main.c index 17554e84c8ade12..966e80f8525b4d9 100644 --- a/samples/boards/st/mco/src/main.c +++ b/samples/boards/st/mco/src/main.c @@ -25,6 +25,16 @@ int main(void) return -1; } +#if DT_NODE_HAS_STATUS(DT_NODELABEL(mco2), okay) + dev = DEVICE_DT_GET(DT_NODELABEL(mco2)); + if (device_is_ready(dev)) { + printk("MCO2 device successfully configured\n"); + } else { + printk("MCO2 device not ready\n"); + return -1; + } +#endif + printk("\nDisplayed the status of all MCO devices - end of example.\n"); return 0; } From e67f629094b2974e266d88ee0c96bb216dfe02b9 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 31 Jul 2024 15:47:25 +0200 Subject: [PATCH 099/269] drivers: clock_control: Deprecate Kconfig for MCO configuration Deprecate support for configuring the MCO source and prescaler from Kconfig configurations. This is now done by devicetree and an MCO driver instead, which also configures the pin to be used by the MCO peripheral. Signed-off-by: Joakim Andersson --- drivers/clock_control/Kconfig.stm32 | 54 ++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32 index 38f7bc25e4b5aac..e5c652b04092e9f 100644 --- a/drivers/clock_control/Kconfig.stm32 +++ b/drivers/clock_control/Kconfig.stm32 @@ -97,7 +97,7 @@ config CLOCK_STM32_MCO bool default y depends on DT_HAS_ST_STM32_CLOCK_MCO_ENABLED || DT_HAS_ST_STM32F1_CLOCK_MCO_ENABLED - # MCO configuration via Kconfig takes priority over Device Tree. + # Although deprecated, MCO configuration via Kconfig takes priority over Device Tree. # Prevent DT-based MCO driver from compiling when Kconfig is used. depends on CLOCK_STM32_MCO1_SRC_NOCLOCK && CLOCK_STM32_MCO2_SRC_NOCLOCK @@ -113,8 +113,10 @@ config CLOCK_STM32_MCO1_SRC_NOCLOCK config CLOCK_STM32_MCO1_SRC_EXT_HSE bool "EXT_HSE" depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + select DEPRECATED help Use EXT_HSE as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_LSE bool "LSE" @@ -125,8 +127,10 @@ config CLOCK_STM32_MCO1_SRC_LSE SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X || \ SOC_SERIES_STM32U5X + select DEPRECATED help Use LSE as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_HSE bool "HSE" @@ -138,33 +142,43 @@ config CLOCK_STM32_MCO1_SRC_HSE SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X || \ SOC_SERIES_STM32U5X + select DEPRECATED help Use HSE as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_LSI bool "LSI" depends on SOC_SERIES_STM32L4X || \ SOC_SERIES_STM32U5X + select DEPRECATED help Use LSI as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_MSI bool "MSI" depends on SOC_SERIES_STM32L4X + select DEPRECATED help Use MSI as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_MSIK bool "MSIK" depends on SOC_SERIES_STM32U5X + select DEPRECATED help Use MSIK as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_MSIS bool "MSIS" depends on SOC_SERIES_STM32U5X + select DEPRECATED help Use MSIS as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_HSI bool "HSI" @@ -174,15 +188,19 @@ config CLOCK_STM32_MCO1_SRC_HSI SOC_SERIES_STM32H7X || \ SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X + select DEPRECATED help Use HSI as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_HSI16 bool "HSI16" depends on SOC_SERIES_STM32L4X || \ SOC_SERIES_STM32U5X + select DEPRECATED help Use HSI16 as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_HSI48 bool "HSI48" @@ -191,8 +209,10 @@ config CLOCK_STM32_MCO1_SRC_HSI48 SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X || \ SOC_SERIES_STM32U5X + select DEPRECATED help Use HSI48 as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_PLLCLK bool "PLLCLK" @@ -200,48 +220,63 @@ config CLOCK_STM32_MCO1_SRC_PLLCLK SOC_SERIES_STM32F7X || \ SOC_SERIES_STM32L4X || \ SOC_SERIES_STM32U5X + select DEPRECATED help Use PLLCLK as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_PLLQCLK bool "PLLQ" depends on SOC_SERIES_STM32H7X || \ SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X + select DEPRECATED help Use PLLQ as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_PLLCLK_DIV2 bool "PLLCLK_DIV2" depends on SOC_SERIES_STM32F1X + select DEPRECATED help Use PLLCLK/2 as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_PLL2CLK bool "PLL2CLK" depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + select DEPRECATED help Use PLL2CLK as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_PLLI2SCLK bool "PLLI2SCLK" depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + select DEPRECATED help Use PLLI2SCLK as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_PLLI2SCLK_DIV2 bool "PLLI2SCLK_DIV2" depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + select DEPRECATED help Use PLLI2SCLK/2 as source of MCO1 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO1_SRC_SYSCLK bool "SYSCLK" depends on SOC_SERIES_STM32F1X || \ SOC_SERIES_STM32L4X || \ SOC_SERIES_STM32U5X + select DEPRECATED help Use SYSCLK as source of MCO1 + This option is deprecated, please use devicetree instead. + endchoice config CLOCK_STM32_MCO1_DIV @@ -261,6 +296,7 @@ config CLOCK_STM32_MCO1_DIV range 1 16 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32U5X help Prescaler for MCO1 output clock + This option is deprecated, please use devicetree instead. choice prompt "STM32 MCO2 Clock Source" @@ -278,14 +314,18 @@ config CLOCK_STM32_MCO2_SRC_SYSCLK SOC_SERIES_STM32H7X || \ SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X + select DEPRECATED help Use SYSCLK as source of MCO2 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO2_SRC_PLLI2S bool "PLLI2S" depends on SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X + select DEPRECATED help Use PLLI2S as source of MCO2 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO2_SRC_HSE bool "HSE" @@ -294,8 +334,10 @@ config CLOCK_STM32_MCO2_SRC_HSE SOC_SERIES_STM32H7X || \ SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X + select DEPRECATED help Use HSE as source of MCO2 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO2_SRC_LSI bool "LSI" @@ -304,36 +346,46 @@ config CLOCK_STM32_MCO2_SRC_LSI SOC_SERIES_STM32H5X help Use LSI as source of MCO2 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO2_SRC_CSI bool "CSI" depends on SOC_SERIES_STM32H7X || \ SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X + select DEPRECATED help Use CSI as source of MCO2 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO2_SRC_PLLCLK bool "PLLCLK" depends on SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X + select DEPRECATED help Use PLLCLK as source of MCO2 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO2_SRC_PLLPCLK bool "PLLPCLK" depends on SOC_SERIES_STM32H7X || \ SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X + select DEPRECATED help Use PLLPCLK as source of MC02 + This option is deprecated, please use devicetree instead. config CLOCK_STM32_MCO2_SRC_PLL2PCLK bool "PLL2PCLK" depends on SOC_SERIES_STM32H7X || \ SOC_SERIES_STM32H7RSX || \ SOC_SERIES_STM32H5X + select DEPRECATED help Use PLL2PCLK as source of MC02 + This option is deprecated, please use devicetree instead. + endchoice config CLOCK_STM32_MCO2_DIV From f5e047e8c37f4f89b2f242d7e504458247470966 Mon Sep 17 00:00:00 2001 From: Joakim Andersson Date: Wed, 28 Aug 2024 14:22:10 +0200 Subject: [PATCH 100/269] doc: Document deprecated stm32 MCO kconfig options for MCO Document deprecated stm32 MCO Kconfig options in favour of setting MCO through devicetree. Signed-off-by: Joakim Andersson --- doc/releases/release-notes-4.0.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index 841e4eaadb41938..574b52915323ff1 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -111,6 +111,8 @@ Boards & SoC Support * :ref:`native_posix` has been deprecated in favour of :ref:`native_sim`. * Support for Google Kukui EC board (``google_kukui``) has been dropped. + * STM32: Deprecated MCO configuration via Kconfig in favour of setting it through devicetree. + See ``samples/boards/stm32/mco`` sample. * Added support for the following shields: From 6cf12c1aa9820fce5494f39a6a0601a86552faf3 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 16 Sep 2024 10:31:00 -0400 Subject: [PATCH 101/269] tests: gen_isr_table: remove misnamed platform This platform does not exist, causing ci failures due to recent additional checks added. Signed-off-by: Anas Nashif --- tests/kernel/gen_isr_table/testcase.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/kernel/gen_isr_table/testcase.yaml b/tests/kernel/gen_isr_table/testcase.yaml index a4d3a58c2303793..b5ab3f3eb78041e 100644 --- a/tests/kernel/gen_isr_table/testcase.yaml +++ b/tests/kernel/gen_isr_table/testcase.yaml @@ -20,7 +20,7 @@ tests: arch.interrupt.gen_isr_table.arm_mainline: &arm-mainline platform_allow: qemu_cortex_m3 platform_exclude: - - stmf103_mini + - stm32f103_mini - nucleo_f103rb - olimexino_stm32 - stm32_min_dev@black From f438696281fecea674c1db4c0da7a5624a6ba01c Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Sat, 14 Sep 2024 04:55:30 -0400 Subject: [PATCH 102/269] soc: mcxa156: use soc hooks Use SoC hooks instead of legacy z_arm_platform_init. Fixes #78386 Signed-off-by: Anas Nashif --- soc/nxp/mcx/mcxa/Kconfig | 2 +- soc/nxp/mcx/mcxa/soc.c | 6 ++---- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/soc/nxp/mcx/mcxa/Kconfig b/soc/nxp/mcx/mcxa/Kconfig index 4897a68a540eb4e..a123cfa4fa87fdc 100644 --- a/soc/nxp/mcx/mcxa/Kconfig +++ b/soc/nxp/mcx/mcxa/Kconfig @@ -8,7 +8,7 @@ config SOC_SERIES_MCXA select HAS_MCUX select CPU_CORTEX_M_HAS_SYSTICK select CPU_CORTEX_M_HAS_DWT - select PLATFORM_SPECIFIC_INIT + select SOC_RESET_HOOK config SOC_MCXA156 select CPU_CORTEX_M33 diff --git a/soc/nxp/mcx/mcxa/soc.c b/soc/nxp/mcx/mcxa/soc.c index ec4500fa7b127a9..363a9dad44e0125 100644 --- a/soc/nxp/mcx/mcxa/soc.c +++ b/soc/nxp/mcx/mcxa/soc.c @@ -17,11 +17,9 @@ #include #include -#ifdef CONFIG_PLATFORM_SPECIFIC_INIT - -void z_arm_platform_init(void) +#ifdef CONFIG_SOC_RESET_HOOK +void soc_reset_hook(void) { SystemInit(); } - #endif From fc6cb6700a1825b70340c4fa1e70ea74beef9f09 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 16 Sep 2024 13:14:20 -0400 Subject: [PATCH 103/269] manifest: update to sha with fix to PLATFORM_SPECIFIC_INIT PLATFORM_SPECIFIC_INIT is deprecated. Update nxp hal to sha 77815705c465627b8436cbac51f0bf0594bbeba2 Signed-off-by: Anas Nashif --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 5d9338703ac077b..3dbc398e3af591c 100644 --- a/west.yml +++ b/west.yml @@ -198,7 +198,7 @@ manifest: groups: - hal - name: hal_nxp - revision: f91541b8a4c39395a4ab9445fee69eeeaa050d6c + revision: 77815705c465627b8436cbac51f0bf0594bbeba2 path: modules/hal/nxp groups: - hal From a056b608f20c392dccc7e15c4c43bfb202a7060f Mon Sep 17 00:00:00 2001 From: Gerard Marull-Paretas Date: Mon, 16 Sep 2024 11:49:43 +0200 Subject: [PATCH 104/269] arch: arm: do not enable PLATFORM_SPECIFIC_INIT if SOC_RESET_HOOK=y Otherwise we can't escape from DEPRECATED being selected, and so getting build warnings. It doesn't make sense that the option replacing the deprecated one is used to automatically enable it. Signed-off-by: Gerard Marull-Paretas --- arch/arm/core/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/core/Kconfig b/arch/arm/core/Kconfig index e0653653a78679d..2573ca2cac6bc20 100644 --- a/arch/arm/core/Kconfig +++ b/arch/arm/core/Kconfig @@ -167,7 +167,6 @@ config RUNTIME_NMI config PLATFORM_SPECIFIC_INIT bool "Platform (SOC) specific startup hook [DEPRECATED]" - default y if SOC_RESET_HOOK select DEPRECATED help The platform specific initialization code (z_arm_platform_init) is From 48a077f2d93b9f29e56b80e994f961b0723ce73e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Mon, 16 Sep 2024 21:14:48 +0200 Subject: [PATCH 105/269] doc: update references to video capture sample MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Video samples have moved from samples/subsys/video to samples/drivers/video. Signed-off-by: Benjamin Cabé --- boards/shields/dvp_fpc24_mt9m114/doc/index.rst | 2 +- boards/shields/nxp_btb44_ov5640/doc/index.rst | 2 +- samples/drivers/video/capture/README.rst | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/shields/dvp_fpc24_mt9m114/doc/index.rst b/boards/shields/dvp_fpc24_mt9m114/doc/index.rst index b149605a565202b..0470da7a58936a1 100644 --- a/boards/shields/dvp_fpc24_mt9m114/doc/index.rst +++ b/boards/shields/dvp_fpc24_mt9m114/doc/index.rst @@ -78,7 +78,7 @@ Programming Set ``--shield dvp_fpc24_mt9m114`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: samples/subsys/video/capture + :zephyr-app: samples/drivers/video/capture :board: mimxrt1064_evk :shield: dvp_fpc24_mt9m114 :goals: build diff --git a/boards/shields/nxp_btb44_ov5640/doc/index.rst b/boards/shields/nxp_btb44_ov5640/doc/index.rst index f20f1c96b87f5de..07a7d24e7d1a34a 100644 --- a/boards/shields/nxp_btb44_ov5640/doc/index.rst +++ b/boards/shields/nxp_btb44_ov5640/doc/index.rst @@ -120,7 +120,7 @@ Programming Set ``--shield nxp_btb44_ov5640`` when you invoke ``west build``. For example: .. zephyr-app-commands:: - :zephyr-app: samples/subsys/video/capture + :zephyr-app: samples/drivers/video/capture :board: mimxrt1170_evk/mimxrt1176/cm7 :shield: nxp_btb44_ov5640 :goals: build diff --git a/samples/drivers/video/capture/README.rst b/samples/drivers/video/capture/README.rst index ff1d3514db62115..eace71ecff06229 100644 --- a/samples/drivers/video/capture/README.rst +++ b/samples/drivers/video/capture/README.rst @@ -50,7 +50,7 @@ For :ref:`mimxrt1064_evk`, build this sample application with the following comm For :ref:`mimxrt1170_evk`, build this sample application with the following commands: .. zephyr-app-commands:: - :zephyr-app: samples/subsys/video/capture + :zephyr-app: samples/drivers/video/capture :board: mimxrt1170_evk/mimxrt1176/cm7 :shield: nxp_btb44_ov5640,rk055hdmipi4ma0 :goals: build From 48ff46d61615b744e777d4902cc42170ead6f341 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Mon, 16 Sep 2024 11:03:53 +0200 Subject: [PATCH 106/269] doc: ipc: icmsg: fix numbered list in bonding section To correctly render the list the continuation line must be indented with thee spaces. Signed-off-by: Pavel Vasilyev --- .../ipc/ipc_service/backends/ipc_service_icmsg.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst b/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst index 2fd67bff195dea7..1b1298df49b1de2 100644 --- a/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst +++ b/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst @@ -70,15 +70,15 @@ When the endpoint is registered, the following happens on each domain (or CPU) connected through the IPC instance: 1. The domain (or CPU) writes a magic number to its ``tx-region`` of the shared -memory. + memory. #. It then sends a signal to the other domain or CPU, informing that the data -has been written. Sending the signal to the other domain or CPU is repeated -with timeout specified by -:kconfig:option:`CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS` option. + has been written. Sending the signal to the other domain or CPU is repeated + with timeout specified by + :kconfig:option:`CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS` option. #. When the signal from the other domain or CPU is received, the magic number -is read from ``rx-region``. If it is correct, the bonding process is finished -and the backend informs the application by calling -:c:member:`ipc_service_cb.bound` callback. + is read from ``rx-region``. If it is correct, the bonding process is finished + and the backend informs the application by calling + :c:member:`ipc_service_cb.bound` callback. Samples ======= From 4278d0a8d6634729ce471223d74d49cd42db8fec Mon Sep 17 00:00:00 2001 From: Paul He Date: Thu, 12 Sep 2024 22:50:48 +0800 Subject: [PATCH 107/269] boards: nxp: mimxrt1050: add LinkServer runner support for qspi board override the default flash driver with MIMXRT1050_SFDP_QSPI.cfx to support LinkServer runner for qspi board. Signed-off-by: Paul He --- boards/nxp/mimxrt1050_evk/board.cmake | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/boards/nxp/mimxrt1050_evk/board.cmake b/boards/nxp/mimxrt1050_evk/board.cmake index 3e42ddc78feaa53..c53e6474ca1bc78 100644 --- a/boards/nxp/mimxrt1050_evk/board.cmake +++ b/boards/nxp/mimxrt1050_evk/board.cmake @@ -4,15 +4,16 @@ # SPDX-License-Identifier: Apache-2.0 # board_runner_args(jlink "--device=MCIMXRT1052") +board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") if("${BOARD_REVISION}" STREQUAL "qspi") board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") board_runner_args(pyocd "--target=mimxrt1050_quadspi") + board_runner_args(linkserver "--override=/device/memory/3/flash-driver=MIMXRT1050_SFDP_QSPI.cfx") else() board_runner_args(pyocd "--target=mimxrt1050_hyperflash") - board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") - include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) endif() +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) From 2b437afaecc122e9b7cb933895802e29b7c7777a Mon Sep 17 00:00:00 2001 From: Lucas Tamborrino Date: Tue, 10 Sep 2024 14:11:57 -0300 Subject: [PATCH 108/269] dts: pinctrl: esp32s3: Add lcd_cam support Add pinctrl for LCD_CAM peripheral. Signed-off-by: Lucas Tamborrino --- .../dt-bindings/pinctrl/esp32s3-pinctrl.h | 10969 +++++++++------- 1 file changed, 6308 insertions(+), 4661 deletions(-) diff --git a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h index 97592a0b08cd74f..0ea854985809113 100644 --- a/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h +++ b/include/zephyr/dt-bindings/pinctrl/esp32s3-pinctrl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -1647,8551 +1647,10197 @@ #define I2S1_O_WS_GPIO48 ESP32_PINMUX(48, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT) -/* LEDC_CH0 */ -#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +/* LCD_CAM_CAM_CLK */ +#define LCD_CAM_CAM_CLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_CAM_CLK) -#define LEDC_CH0_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) +#define LCD_CAM_CAM_CLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_CAM_CLK) -/* LEDC_CH1 */ -#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +/* LCD_CAM_CAM_PCLK */ +#define LCD_CAM_CAM_PCLK_GPIO0 ESP32_PINMUX(0, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO1 ESP32_PINMUX(1, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO2 ESP32_PINMUX(2, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO3 ESP32_PINMUX(3, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO4 ESP32_PINMUX(4, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO5 ESP32_PINMUX(5, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO6 ESP32_PINMUX(6, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO7 ESP32_PINMUX(7, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO8 ESP32_PINMUX(8, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO9 ESP32_PINMUX(9, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO10 ESP32_PINMUX(10, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO11 ESP32_PINMUX(11, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO12 ESP32_PINMUX(12, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO13 ESP32_PINMUX(13, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO14 ESP32_PINMUX(14, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO15 ESP32_PINMUX(15, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO16 ESP32_PINMUX(16, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO17 ESP32_PINMUX(17, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO18 ESP32_PINMUX(18, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO19 ESP32_PINMUX(19, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO20 ESP32_PINMUX(20, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO21 ESP32_PINMUX(21, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO26 ESP32_PINMUX(26, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO27 ESP32_PINMUX(27, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO28 ESP32_PINMUX(28, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO29 ESP32_PINMUX(29, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO30 ESP32_PINMUX(30, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO31 ESP32_PINMUX(31, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO32 ESP32_PINMUX(32, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO33 ESP32_PINMUX(33, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO34 ESP32_PINMUX(34, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO35 ESP32_PINMUX(35, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO36 ESP32_PINMUX(36, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO37 ESP32_PINMUX(37, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO38 ESP32_PINMUX(38, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO39 ESP32_PINMUX(39, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO40 ESP32_PINMUX(40, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO41 ESP32_PINMUX(41, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO42 ESP32_PINMUX(42, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO43 ESP32_PINMUX(43, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO44 ESP32_PINMUX(44, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO45 ESP32_PINMUX(45, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO46 ESP32_PINMUX(46, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO47 ESP32_PINMUX(47, ESP_CAM_PCLK, ESP_NOSIG) -#define LEDC_CH1_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) +#define LCD_CAM_CAM_PCLK_GPIO48 ESP32_PINMUX(48, ESP_CAM_PCLK, ESP_NOSIG) -/* LEDC_CH2 */ -#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +/* LCD_CAM_DATA_IN0 */ +#define LCD_CAM_DATA_IN0_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN0, ESP_NOSIG) -#define LEDC_CH2_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) +#define LCD_CAM_DATA_IN0_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN0, ESP_NOSIG) -/* LEDC_CH3 */ -#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +/* LCD_CAM_DATA_IN1 */ +#define LCD_CAM_DATA_IN1_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN1, ESP_NOSIG) -#define LEDC_CH3_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) +#define LCD_CAM_DATA_IN1_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN1, ESP_NOSIG) -/* LEDC_CH4 */ -#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +/* LCD_CAM_DATA_IN10 */ +#define LCD_CAM_DATA_IN10_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN10, ESP_NOSIG) -#define LEDC_CH4_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) +#define LCD_CAM_DATA_IN10_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN10, ESP_NOSIG) -/* LEDC_CH5 */ -#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +/* LCD_CAM_DATA_IN11 */ +#define LCD_CAM_DATA_IN11_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN11, ESP_NOSIG) -#define LEDC_CH5_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) +#define LCD_CAM_DATA_IN11_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN11, ESP_NOSIG) -/* LEDC_CH6 */ -#define LEDC_CH6_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +/* LCD_CAM_DATA_IN12 */ +#define LCD_CAM_DATA_IN12_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN12, ESP_NOSIG) -#define LEDC_CH6_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) +#define LCD_CAM_DATA_IN12_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN12, ESP_NOSIG) -/* LEDC_CH7 */ -#define LEDC_CH7_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +/* LCD_CAM_DATA_IN13 */ +#define LCD_CAM_DATA_IN13_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN13, ESP_NOSIG) -#define LEDC_CH7_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) +#define LCD_CAM_DATA_IN13_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN13, ESP_NOSIG) -/* MCPWM0_CAP0 */ -#define MCPWM0_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP0_IN, ESP_NOSIG) +/* LCD_CAM_DATA_IN14 */ +#define LCD_CAM_DATA_IN14_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN14, ESP_NOSIG) -#define MCPWM0_CAP0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN14_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN14, ESP_NOSIG) -/* MCPWM0_CAP1 */ -#define MCPWM0_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP1_IN, ESP_NOSIG) +/* LCD_CAM_DATA_IN15 */ +#define LCD_CAM_DATA_IN15_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN15, ESP_NOSIG) -#define MCPWM0_CAP1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN15_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN15, ESP_NOSIG) -/* MCPWM0_CAP2 */ -#define MCPWM0_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP2_IN, ESP_NOSIG) +/* LCD_CAM_DATA_IN2 */ +#define LCD_CAM_DATA_IN2_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN2, ESP_NOSIG) -#define MCPWM0_CAP2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN2_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN2, ESP_NOSIG) -/* MCPWM0_FAULT0 */ -#define MCPWM0_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F0_IN, ESP_NOSIG) +/* LCD_CAM_DATA_IN3 */ +#define LCD_CAM_DATA_IN3_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN3, ESP_NOSIG) -#define MCPWM0_FAULT0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN3_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN3, ESP_NOSIG) -/* MCPWM0_FAULT1 */ -#define MCPWM0_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F1_IN, ESP_NOSIG) +/* LCD_CAM_DATA_IN4 */ +#define LCD_CAM_DATA_IN4_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN4, ESP_NOSIG) -#define MCPWM0_FAULT1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN4_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN4, ESP_NOSIG) -/* MCPWM0_FAULT2 */ -#define MCPWM0_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F2_IN, ESP_NOSIG) +/* LCD_CAM_DATA_IN5 */ +#define LCD_CAM_DATA_IN5_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN5, ESP_NOSIG) -#define MCPWM0_FAULT2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_IN5_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN5, ESP_NOSIG) -/* MCPWM0_OUT0A */ -#define MCPWM0_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0A) +/* LCD_CAM_DATA_IN6 */ +#define LCD_CAM_DATA_IN6_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN6, ESP_NOSIG) -#define MCPWM0_OUT0A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0A) +#define LCD_CAM_DATA_IN6_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN6, ESP_NOSIG) -/* MCPWM0_OUT0B */ -#define MCPWM0_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0B) +/* LCD_CAM_DATA_IN7 */ +#define LCD_CAM_DATA_IN7_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN7, ESP_NOSIG) -#define MCPWM0_OUT0B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0B) +#define LCD_CAM_DATA_IN7_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN7, ESP_NOSIG) -/* MCPWM0_OUT1A */ -#define MCPWM0_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1A) +/* LCD_CAM_DATA_IN8 */ +#define LCD_CAM_DATA_IN8_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN8, ESP_NOSIG) -#define MCPWM0_OUT1A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1A) +#define LCD_CAM_DATA_IN8_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN8, ESP_NOSIG) -/* MCPWM0_OUT1B */ -#define MCPWM0_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1B) +/* LCD_CAM_DATA_IN9 */ +#define LCD_CAM_DATA_IN9_GPIO0 ESP32_PINMUX(0, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO1 ESP32_PINMUX(1, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO2 ESP32_PINMUX(2, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO3 ESP32_PINMUX(3, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO4 ESP32_PINMUX(4, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO5 ESP32_PINMUX(5, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO6 ESP32_PINMUX(6, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO7 ESP32_PINMUX(7, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO8 ESP32_PINMUX(8, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO9 ESP32_PINMUX(9, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO10 ESP32_PINMUX(10, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO11 ESP32_PINMUX(11, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO12 ESP32_PINMUX(12, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO13 ESP32_PINMUX(13, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO14 ESP32_PINMUX(14, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO15 ESP32_PINMUX(15, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO16 ESP32_PINMUX(16, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO17 ESP32_PINMUX(17, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO18 ESP32_PINMUX(18, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO19 ESP32_PINMUX(19, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO20 ESP32_PINMUX(20, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO21 ESP32_PINMUX(21, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO26 ESP32_PINMUX(26, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO27 ESP32_PINMUX(27, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO28 ESP32_PINMUX(28, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO29 ESP32_PINMUX(29, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO30 ESP32_PINMUX(30, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO31 ESP32_PINMUX(31, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO32 ESP32_PINMUX(32, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO33 ESP32_PINMUX(33, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO34 ESP32_PINMUX(34, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO35 ESP32_PINMUX(35, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO36 ESP32_PINMUX(36, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO37 ESP32_PINMUX(37, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO38 ESP32_PINMUX(38, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO39 ESP32_PINMUX(39, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO40 ESP32_PINMUX(40, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO41 ESP32_PINMUX(41, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO42 ESP32_PINMUX(42, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO43 ESP32_PINMUX(43, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO44 ESP32_PINMUX(44, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO45 ESP32_PINMUX(45, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO46 ESP32_PINMUX(46, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO47 ESP32_PINMUX(47, ESP_CAM_DATA_IN9, ESP_NOSIG) -#define MCPWM0_OUT1B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1B) +#define LCD_CAM_DATA_IN9_GPIO48 ESP32_PINMUX(48, ESP_CAM_DATA_IN9, ESP_NOSIG) -/* MCPWM0_OUT2A */ -#define MCPWM0_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2A) +/* LCD_CAM_DATA_OUT0 */ +#define LCD_CAM_DATA_OUT0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT0) -#define MCPWM0_OUT2A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2A) +#define LCD_CAM_DATA_OUT0_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT0) -/* MCPWM0_OUT2B */ -#define MCPWM0_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2B) +/* LCD_CAM_DATA_OUT1 */ +#define LCD_CAM_DATA_OUT1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT1) -#define MCPWM0_OUT2B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2B) +#define LCD_CAM_DATA_OUT1_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT1) -/* MCPWM0_SYNC0 */ -#define MCPWM0_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT10 */ +#define LCD_CAM_DATA_OUT10_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT10) -#define MCPWM0_SYNC0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT10_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT10) -/* MCPWM0_SYNC1 */ -#define MCPWM0_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT11 */ +#define LCD_CAM_DATA_OUT11_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT11) -#define MCPWM0_SYNC1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT11_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT11) -/* MCPWM0_SYNC2 */ -#define MCPWM0_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT12 */ +#define LCD_CAM_DATA_OUT12_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT12) -#define MCPWM0_SYNC2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT12_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT12) -/* MCPWM1_CAP0 */ -#define MCPWM1_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP0_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT13 */ +#define LCD_CAM_DATA_OUT13_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT13) -#define MCPWM1_CAP0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT13_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT13) -/* MCPWM1_CAP1 */ -#define MCPWM1_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP1_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT14 */ +#define LCD_CAM_DATA_OUT14_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT14) -#define MCPWM1_CAP1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT14_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT14) -/* MCPWM1_CAP2 */ -#define MCPWM1_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP2_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT15 */ +#define LCD_CAM_DATA_OUT15_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT15) -#define MCPWM1_CAP2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT15_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT15) -/* MCPWM1_FAULT0 */ -#define MCPWM1_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F0_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT2 */ +#define LCD_CAM_DATA_OUT2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT2) -#define MCPWM1_FAULT0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F0_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT2_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT2) -/* MCPWM1_FAULT1 */ -#define MCPWM1_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F1_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT3 */ +#define LCD_CAM_DATA_OUT3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT3) -#define MCPWM1_FAULT1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F1_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT3_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT3) -/* MCPWM1_FAULT2 */ -#define MCPWM1_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F2_IN, ESP_NOSIG) +/* LCD_CAM_DATA_OUT4 */ +#define LCD_CAM_DATA_OUT4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT4) -#define MCPWM1_FAULT2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F2_IN, ESP_NOSIG) +#define LCD_CAM_DATA_OUT4_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT4) -/* MCPWM1_OUT0A */ -#define MCPWM1_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0A) +/* LCD_CAM_DATA_OUT5 */ +#define LCD_CAM_DATA_OUT5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT5) -#define MCPWM1_OUT0A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0A) +#define LCD_CAM_DATA_OUT5_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT5) -/* MCPWM1_OUT0B */ -#define MCPWM1_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0B) +/* LCD_CAM_DATA_OUT6 */ +#define LCD_CAM_DATA_OUT6_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT6) -#define MCPWM1_OUT0B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0B) +#define LCD_CAM_DATA_OUT6_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT6) -/* MCPWM1_OUT1A */ -#define MCPWM1_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1A) +/* LCD_CAM_DATA_OUT7 */ +#define LCD_CAM_DATA_OUT7_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT7) -#define MCPWM1_OUT1A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1A) +#define LCD_CAM_DATA_OUT7_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT7) -/* MCPWM1_OUT1B */ -#define MCPWM1_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1B) +/* LCD_CAM_DATA_OUT8 */ +#define LCD_CAM_DATA_OUT8_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT8) -#define MCPWM1_OUT1B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1B) +#define LCD_CAM_DATA_OUT8_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT8) -/* MCPWM1_OUT2A */ -#define MCPWM1_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2A) +/* LCD_CAM_DATA_OUT9 */ +#define LCD_CAM_DATA_OUT9_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DATA_OUT9) -#define MCPWM1_OUT2A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2A) +#define LCD_CAM_DATA_OUT9_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DATA_OUT9) -/* MCPWM1_OUT2B */ -#define MCPWM1_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2B) +/* LCD_CAM_DC */ +#define LCD_CAM_DC_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_DC) -#define MCPWM1_OUT2B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2B) +#define LCD_CAM_DC_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_DC) -/* MCPWM1_SYNC0 */ -#define MCPWM1_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +/* LCD_CAM_H_ENABLE_CAM */ +#define LCD_CAM_H_ENABLE_CAM_GPIO0 ESP32_PINMUX(0, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO1 ESP32_PINMUX(1, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO2 ESP32_PINMUX(2, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO3 ESP32_PINMUX(3, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO4 ESP32_PINMUX(4, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO5 ESP32_PINMUX(5, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO6 ESP32_PINMUX(6, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO7 ESP32_PINMUX(7, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO8 ESP32_PINMUX(8, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO9 ESP32_PINMUX(9, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO10 ESP32_PINMUX(10, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO11 ESP32_PINMUX(11, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO12 ESP32_PINMUX(12, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO13 ESP32_PINMUX(13, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO14 ESP32_PINMUX(14, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO15 ESP32_PINMUX(15, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO16 ESP32_PINMUX(16, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO17 ESP32_PINMUX(17, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO18 ESP32_PINMUX(18, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO19 ESP32_PINMUX(19, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO20 ESP32_PINMUX(20, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO21 ESP32_PINMUX(21, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO26 ESP32_PINMUX(26, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO27 ESP32_PINMUX(27, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO28 ESP32_PINMUX(28, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO29 ESP32_PINMUX(29, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO30 ESP32_PINMUX(30, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO31 ESP32_PINMUX(31, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO32 ESP32_PINMUX(32, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO33 ESP32_PINMUX(33, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO34 ESP32_PINMUX(34, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO35 ESP32_PINMUX(35, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO36 ESP32_PINMUX(36, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO37 ESP32_PINMUX(37, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO38 ESP32_PINMUX(38, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO39 ESP32_PINMUX(39, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO40 ESP32_PINMUX(40, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO41 ESP32_PINMUX(41, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO42 ESP32_PINMUX(42, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO43 ESP32_PINMUX(43, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO44 ESP32_PINMUX(44, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO45 ESP32_PINMUX(45, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO46 ESP32_PINMUX(46, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO47 ESP32_PINMUX(47, ESP_CAM_H_ENABLE, ESP_NOSIG) -#define MCPWM1_SYNC0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC0_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_CAM_GPIO48 ESP32_PINMUX(48, ESP_CAM_H_ENABLE, ESP_NOSIG) -/* MCPWM1_SYNC1 */ -#define MCPWM1_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +/* LCD_CAM_H_ENABLE_LCD */ +#define LCD_CAM_H_ENABLE_LCD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_H_ENABLE) -#define MCPWM1_SYNC1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC1_IN, ESP_NOSIG) +#define LCD_CAM_H_ENABLE_LCD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_H_ENABLE) -/* MCPWM1_SYNC2 */ -#define MCPWM1_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +/* LCD_CAM_H_SYNC_CAM */ +#define LCD_CAM_H_SYNC_CAM_GPIO0 ESP32_PINMUX(0, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO1 ESP32_PINMUX(1, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO2 ESP32_PINMUX(2, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO3 ESP32_PINMUX(3, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO4 ESP32_PINMUX(4, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO5 ESP32_PINMUX(5, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO6 ESP32_PINMUX(6, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO7 ESP32_PINMUX(7, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO8 ESP32_PINMUX(8, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO9 ESP32_PINMUX(9, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO10 ESP32_PINMUX(10, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO11 ESP32_PINMUX(11, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO12 ESP32_PINMUX(12, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO13 ESP32_PINMUX(13, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO14 ESP32_PINMUX(14, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO15 ESP32_PINMUX(15, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO16 ESP32_PINMUX(16, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO17 ESP32_PINMUX(17, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO18 ESP32_PINMUX(18, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO19 ESP32_PINMUX(19, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO20 ESP32_PINMUX(20, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO21 ESP32_PINMUX(21, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO26 ESP32_PINMUX(26, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO27 ESP32_PINMUX(27, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO28 ESP32_PINMUX(28, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO29 ESP32_PINMUX(29, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO30 ESP32_PINMUX(30, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO31 ESP32_PINMUX(31, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO32 ESP32_PINMUX(32, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO33 ESP32_PINMUX(33, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO34 ESP32_PINMUX(34, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO35 ESP32_PINMUX(35, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO36 ESP32_PINMUX(36, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO37 ESP32_PINMUX(37, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO38 ESP32_PINMUX(38, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO39 ESP32_PINMUX(39, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO40 ESP32_PINMUX(40, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO41 ESP32_PINMUX(41, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO42 ESP32_PINMUX(42, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO43 ESP32_PINMUX(43, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO44 ESP32_PINMUX(44, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO45 ESP32_PINMUX(45, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO46 ESP32_PINMUX(46, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO47 ESP32_PINMUX(47, ESP_CAM_H_SYNC, ESP_NOSIG) -#define MCPWM1_SYNC2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC2_IN, ESP_NOSIG) +#define LCD_CAM_H_SYNC_CAM_GPIO48 ESP32_PINMUX(48, ESP_CAM_H_SYNC, ESP_NOSIG) -/* PCNT0_CH0CTRL */ -#define PCNT0_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +/* LCD_CAM_H_SYNC_LCD */ +#define LCD_CAM_H_SYNC_LCD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_H_SYNC) -#define PCNT0_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_H_SYNC_LCD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_H_SYNC) -/* PCNT0_CH0SIG */ -#define PCNT0_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +/* LCD_CAM_LCD_CLK */ +#define LCD_CAM_LCD_CLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_PCLK) -#define PCNT0_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) +#define LCD_CAM_LCD_CLK_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_PCLK) -/* PCNT0_CH1CTRL */ -#define PCNT0_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +/* LCD_CAM_V_SYNC_CAM */ +#define LCD_CAM_V_SYNC_CAM_GPIO0 ESP32_PINMUX(0, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO1 ESP32_PINMUX(1, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO2 ESP32_PINMUX(2, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO3 ESP32_PINMUX(3, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO4 ESP32_PINMUX(4, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO5 ESP32_PINMUX(5, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO6 ESP32_PINMUX(6, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO7 ESP32_PINMUX(7, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO8 ESP32_PINMUX(8, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO9 ESP32_PINMUX(9, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO10 ESP32_PINMUX(10, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO11 ESP32_PINMUX(11, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO12 ESP32_PINMUX(12, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO13 ESP32_PINMUX(13, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO14 ESP32_PINMUX(14, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO15 ESP32_PINMUX(15, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO16 ESP32_PINMUX(16, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO17 ESP32_PINMUX(17, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO18 ESP32_PINMUX(18, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO19 ESP32_PINMUX(19, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO20 ESP32_PINMUX(20, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO21 ESP32_PINMUX(21, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO26 ESP32_PINMUX(26, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO27 ESP32_PINMUX(27, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO28 ESP32_PINMUX(28, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO29 ESP32_PINMUX(29, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO30 ESP32_PINMUX(30, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO31 ESP32_PINMUX(31, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO32 ESP32_PINMUX(32, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO33 ESP32_PINMUX(33, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO34 ESP32_PINMUX(34, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO35 ESP32_PINMUX(35, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO36 ESP32_PINMUX(36, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO37 ESP32_PINMUX(37, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO38 ESP32_PINMUX(38, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO39 ESP32_PINMUX(39, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO40 ESP32_PINMUX(40, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO41 ESP32_PINMUX(41, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO42 ESP32_PINMUX(42, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO43 ESP32_PINMUX(43, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO44 ESP32_PINMUX(44, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO45 ESP32_PINMUX(45, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO46 ESP32_PINMUX(46, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO47 ESP32_PINMUX(47, ESP_CAM_V_SYNC, ESP_NOSIG) -#define PCNT0_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_CAM_GPIO48 ESP32_PINMUX(48, ESP_CAM_V_SYNC, ESP_NOSIG) -/* PCNT0_CH1SIG */ -#define PCNT0_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +/* LCD_CAM_V_SYNC_LCD */ +#define LCD_CAM_V_SYNC_LCD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LCD_V_SYNC) -#define PCNT0_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) +#define LCD_CAM_V_SYNC_LCD_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LCD_V_SYNC) -/* PCNT1_CH0CTRL */ -#define PCNT1_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +/* LEDC_CH0 */ +#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -#define PCNT1_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) +#define LEDC_CH0_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0) -/* PCNT1_CH0SIG */ -#define PCNT1_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +/* LEDC_CH1 */ +#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) -#define PCNT1_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define LEDC_CH1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +#define LEDC_CH1_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1) + +/* LEDC_CH2 */ +#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +#define LEDC_CH2_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2) + +/* LEDC_CH3 */ +#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +#define LEDC_CH3_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3) + +/* LEDC_CH4 */ +#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +#define LEDC_CH4_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4) + +/* LEDC_CH5 */ +#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +#define LEDC_CH5_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5) + +/* LEDC_CH6 */ +#define LEDC_CH6_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +#define LEDC_CH6_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6) + +/* LEDC_CH7 */ +#define LEDC_CH7_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +#define LEDC_CH7_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7) + +/* MCPWM0_CAP0 */ +#define MCPWM0_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +#define MCPWM0_CAP0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP0_IN, ESP_NOSIG) + +/* MCPWM0_CAP1 */ +#define MCPWM0_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +#define MCPWM0_CAP1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP1_IN, ESP_NOSIG) + +/* MCPWM0_CAP2 */ +#define MCPWM0_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +#define MCPWM0_CAP2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_CAP2_IN, ESP_NOSIG) + +/* MCPWM0_FAULT0 */ +#define MCPWM0_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F0_IN, ESP_NOSIG) + +#define MCPWM0_FAULT0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F0_IN, ESP_NOSIG) + +/* MCPWM0_FAULT1 */ +#define MCPWM0_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F1_IN, ESP_NOSIG) + +#define MCPWM0_FAULT1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F1_IN, ESP_NOSIG) + +/* MCPWM0_FAULT2 */ +#define MCPWM0_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_F2_IN, ESP_NOSIG) + +#define MCPWM0_FAULT2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_F2_IN, ESP_NOSIG) + +/* MCPWM0_OUT0A */ +#define MCPWM0_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0A) + +#define MCPWM0_OUT0A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0A) + +/* MCPWM0_OUT0B */ +#define MCPWM0_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT0B) + +#define MCPWM0_OUT0B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT0B) + +/* MCPWM0_OUT1A */ +#define MCPWM0_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1A) + +#define MCPWM0_OUT1A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1A) + +/* MCPWM0_OUT1B */ +#define MCPWM0_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT1B) + +#define MCPWM0_OUT1B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT1B) + +/* MCPWM0_OUT2A */ +#define MCPWM0_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2A) + +#define MCPWM0_OUT2A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2A) + +/* MCPWM0_OUT2B */ +#define MCPWM0_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM0_OUT2B) + +#define MCPWM0_OUT2B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM0_OUT2B) + +/* MCPWM0_SYNC0 */ +#define MCPWM0_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +#define MCPWM0_SYNC0_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC0_IN, ESP_NOSIG) + +/* MCPWM0_SYNC1 */ +#define MCPWM0_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +#define MCPWM0_SYNC1_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC1_IN, ESP_NOSIG) + +/* MCPWM0_SYNC2 */ +#define MCPWM0_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO28 ESP32_PINMUX(28, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO29 ESP32_PINMUX(29, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO30 ESP32_PINMUX(30, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO31 ESP32_PINMUX(31, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO40 ESP32_PINMUX(40, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO41 ESP32_PINMUX(41, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO42 ESP32_PINMUX(42, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO43 ESP32_PINMUX(43, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO44 ESP32_PINMUX(44, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO45 ESP32_PINMUX(45, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO46 ESP32_PINMUX(46, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO47 ESP32_PINMUX(47, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +#define MCPWM0_SYNC2_GPIO48 ESP32_PINMUX(48, ESP_PWM0_SYNC2_IN, ESP_NOSIG) + +/* MCPWM1_CAP0 */ +#define MCPWM1_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +#define MCPWM1_CAP0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP0_IN, ESP_NOSIG) + +/* MCPWM1_CAP1 */ +#define MCPWM1_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +#define MCPWM1_CAP1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP1_IN, ESP_NOSIG) + +/* MCPWM1_CAP2 */ +#define MCPWM1_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_CAP2_IN, ESP_NOSIG) + +#define MCPWM1_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_CAP2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_CAP2_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +/* MCPWM1_FAULT0 */ +#define MCPWM1_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F0_IN, ESP_NOSIG) -/* PCNT1_CH1CTRL */ -#define PCNT1_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F0_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F0_IN, ESP_NOSIG) + +#define MCPWM1_FAULT0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F0_IN, ESP_NOSIG) + +#define MCPWM1_FAULT0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F0_IN, ESP_NOSIG) + +#define MCPWM1_FAULT0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F0_IN, ESP_NOSIG) + +#define MCPWM1_FAULT0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F0_IN, ESP_NOSIG) + +#define MCPWM1_FAULT0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F0_IN, ESP_NOSIG) + +#define MCPWM1_FAULT0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F0_IN, ESP_NOSIG) + +#define MCPWM1_FAULT0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F0_IN, ESP_NOSIG) + +/* MCPWM1_FAULT1 */ +#define MCPWM1_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F1_IN, ESP_NOSIG) + +#define MCPWM1_FAULT1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F1_IN, ESP_NOSIG) + +/* MCPWM1_FAULT2 */ +#define MCPWM1_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F2_IN, ESP_NOSIG) + +#define MCPWM1_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_F2_IN, ESP_NOSIG) -/* PCNT1_CH1SIG */ -#define PCNT1_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_FAULT2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_F2_IN, ESP_NOSIG) -#define PCNT1_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +/* MCPWM1_OUT0A */ +#define MCPWM1_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT1_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0A) -/* PCNT2_CH0CTRL */ -#define PCNT2_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0A) -#define PCNT2_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +/* MCPWM1_OUT0B */ +#define MCPWM1_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT0B) -/* PCNT2_CH0SIG */ -#define PCNT2_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT0B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT0B) -#define PCNT2_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +/* MCPWM1_OUT1A */ +#define MCPWM1_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1A) -/* PCNT2_CH1CTRL */ -#define PCNT2_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1A) -#define PCNT2_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +/* MCPWM1_OUT1B */ +#define MCPWM1_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT1B) -/* PCNT2_CH1SIG */ -#define PCNT2_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT1B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT1B) -#define PCNT2_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +/* MCPWM1_OUT2A */ +#define MCPWM1_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT2_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2A) -/* PCNT3_CH0CTRL */ -#define PCNT3_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2A_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2A) -#define PCNT3_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +/* MCPWM1_OUT2B */ +#define MCPWM1_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_PWM1_OUT2B) -/* PCNT3_CH0SIG */ -#define PCNT3_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_OUT2B_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_PWM1_OUT2B) -#define PCNT3_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +/* MCPWM1_SYNC0 */ +#define MCPWM1_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -/* PCNT3_CH1CTRL */ -#define PCNT3_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC0_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC0_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +/* MCPWM1_SYNC1 */ +#define MCPWM1_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC1_IN, ESP_NOSIG) + +#define MCPWM1_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -#define PCNT3_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC1_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC1_IN, ESP_NOSIG) -/* PCNT3_CH1SIG */ -#define PCNT3_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +/* MCPWM1_SYNC2 */ +#define MCPWM1_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO28 ESP32_PINMUX(28, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO29 ESP32_PINMUX(29, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO30 ESP32_PINMUX(30, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO31 ESP32_PINMUX(31, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO40 ESP32_PINMUX(40, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO41 ESP32_PINMUX(41, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO42 ESP32_PINMUX(42, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO43 ESP32_PINMUX(43, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO44 ESP32_PINMUX(44, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO45 ESP32_PINMUX(45, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO46 ESP32_PINMUX(46, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO47 ESP32_PINMUX(47, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -#define PCNT3_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) +#define MCPWM1_SYNC2_GPIO48 ESP32_PINMUX(48, ESP_PWM1_SYNC2_IN, ESP_NOSIG) -/* SDHC0_CD */ -#define SDHC0_CD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +/* PCNT0_CH0CTRL */ +#define PCNT0_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -#define SDHC0_CD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define PCNT0_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG) -/* SDHC0_CLKOUT */ -#define SDHC0_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +/* PCNT0_CH0SIG */ +#define PCNT0_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -#define SDHC0_CLKOUT_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define PCNT0_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG) -/* SDHC0_CMD */ -#define SDHC0_CMD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +/* PCNT0_CH1CTRL */ +#define PCNT0_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -#define SDHC0_CMD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define PCNT0_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG) -/* SDHC0_DATA0 */ -#define SDHC0_DATA0_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +/* PCNT0_CH1SIG */ +#define PCNT0_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -#define SDHC0_DATA0_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define PCNT0_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG) -/* SDHC0_DATA1 */ -#define SDHC0_DATA1_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +/* PCNT1_CH0CTRL */ +#define PCNT1_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA1_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define PCNT1_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG) -/* SDHC0_DATA2 */ -#define SDHC0_DATA2_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +/* PCNT1_CH0SIG */ +#define PCNT1_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -#define SDHC0_DATA2_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define PCNT1_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG) -/* SDHC0_DATA3 */ -#define SDHC0_DATA3_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +/* PCNT1_CH1CTRL */ +#define PCNT1_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -#define SDHC0_DATA3_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define PCNT1_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG) -/* SDHC0_WP */ -#define SDHC0_WP_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +/* PCNT1_CH1SIG */ +#define PCNT1_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -#define SDHC0_WP_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define PCNT1_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG) -/* SDHC1_CD */ -#define SDHC1_CD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +/* PCNT2_CH0CTRL */ +#define PCNT2_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -#define SDHC1_CD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define PCNT2_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG) -/* SDHC1_CLKOUT */ -#define SDHC1_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +/* PCNT2_CH0SIG */ +#define PCNT2_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_CLKOUT_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define PCNT2_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -/* SDHC1_CMD */ -#define SDHC1_CMD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +/* PCNT2_CH1CTRL */ +#define PCNT2_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -#define SDHC1_CMD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define PCNT2_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG) -/* SDHC1_DATA0 */ -#define SDHC1_DATA0_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +/* PCNT2_CH1SIG */ +#define PCNT2_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -#define SDHC1_DATA0_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define PCNT2_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG) -/* SDHC1_DATA1 */ -#define SDHC1_DATA1_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +/* PCNT3_CH0CTRL */ +#define PCNT3_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA1_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define PCNT3_CH0CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG) -/* SDHC1_DATA2 */ -#define SDHC1_DATA2_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +/* PCNT3_CH0SIG */ +#define PCNT3_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -#define SDHC1_DATA2_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define PCNT3_CH0SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG) -/* SDHC1_DATA3 */ -#define SDHC1_DATA3_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +/* PCNT3_CH1CTRL */ +#define PCNT3_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO47 ESP32_PINMUX(47, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -#define SDHC1_DATA3_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define PCNT3_CH1CTRL_GPIO48 ESP32_PINMUX(48, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG) -/* SDHC1_WP */ -#define SDHC1_WP_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +/* PCNT3_CH1SIG */ +#define PCNT3_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO47 ESP32_PINMUX(47, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) -#define SDHC1_WP_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define PCNT3_CH1SIG_GPIO48 ESP32_PINMUX(48, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG) /* SDHC0_CD */ -#define SDHC0_CD_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) -#define SDHC0_CD_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) +#define SDHC0_CD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_1, ESP_NOSIG) /* SDHC0_CLKOUT */ -#define SDHC0_CLKOUT_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) -#define SDHC0_CLKOUT_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) +#define SDHC0_CLKOUT_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_1) /* SDHC0_CMD */ -#define SDHC0_CMD_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) -#define SDHC0_CMD_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) +#define SDHC0_CMD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_1, ESP_SDHOST_CCMD_OUT_1) /* SDHC0_DATA0 */ -#define SDHC0_DATA0_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) -#define SDHC0_DATA0_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) +#define SDHC0_DATA0_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_10, ESP_SDHOST_CDATA_OUT_10) /* SDHC0_DATA1 */ -#define SDHC0_DATA1_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) -#define SDHC0_DATA1_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) +#define SDHC0_DATA1_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_11, ESP_SDHOST_CDATA_OUT_11) /* SDHC0_DATA2 */ -#define SDHC0_DATA2_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) -#define SDHC0_DATA2_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) +#define SDHC0_DATA2_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_12, ESP_SDHOST_CDATA_OUT_12) /* SDHC0_DATA3 */ -#define SDHC0_DATA3_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) -#define SDHC0_DATA3_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) +#define SDHC0_DATA3_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_13, ESP_SDHOST_CDATA_OUT_13) /* SDHC0_WP */ -#define SDHC0_WP_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) -#define SDHC0_WP_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) +#define SDHC0_WP_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_1, ESP_NOSIG) /* SDHC1_CD */ -#define SDHC1_CD_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) -#define SDHC1_CD_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) +#define SDHC1_CD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_DETECT_N_2, ESP_NOSIG) /* SDHC1_CLKOUT */ -#define SDHC1_CLKOUT_GPIO0 \ - ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO1 \ - ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO2 \ - ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO3 \ - ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO4 \ - ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO5 \ - ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO6 \ - ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO7 \ - ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO8 \ - ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO9 \ - ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO10 \ - ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO11 \ - ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO12 \ - ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO13 \ - ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO14 \ - ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO15 \ - ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO16 \ - ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO17 \ - ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO18 \ - ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO19 \ - ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO20 \ - ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO21 \ - ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO26 \ - ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO27 \ - ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO28 \ - ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO29 \ - ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO30 \ - ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO31 \ - ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO32 \ - ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO33 \ - ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO34 \ - ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO35 \ - ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO36 \ - ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO37 \ - ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO38 \ - ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO39 \ - ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO40 \ - ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO41 \ - ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO42 \ - ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO43 \ - ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO44 \ - ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO45 \ - ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO46 \ - ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO47 \ - ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO47 ESP32_PINMUX(47, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) -#define SDHC1_CLKOUT_GPIO48 \ - ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) +#define SDHC1_CLKOUT_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_SDHOST_CCLK_OUT_2) /* SDHC1_CMD */ -#define SDHC1_CMD_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) -#define SDHC1_CMD_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) +#define SDHC1_CMD_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CCMD_IN_2, ESP_SDHOST_CCMD_OUT_2) /* SDHC1_DATA0 */ -#define SDHC1_DATA0_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) -#define SDHC1_DATA0_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) +#define SDHC1_DATA0_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_20, ESP_SDHOST_CDATA_OUT_20) /* SDHC1_DATA1 */ -#define SDHC1_DATA1_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) -#define SDHC1_DATA1_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) +#define SDHC1_DATA1_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_21, ESP_SDHOST_CDATA_OUT_21) /* SDHC1_DATA2 */ -#define SDHC1_DATA2_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) -#define SDHC1_DATA2_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) +#define SDHC1_DATA2_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_22, ESP_SDHOST_CDATA_OUT_22) /* SDHC1_DATA3 */ -#define SDHC1_DATA3_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) -#define SDHC1_DATA3_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) +#define SDHC1_DATA3_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CDATA_IN_23, ESP_SDHOST_CDATA_OUT_23) /* SDHC1_WP */ -#define SDHC1_WP_GPIO0 \ - ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO0 ESP32_PINMUX(0, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO1 \ - ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO1 ESP32_PINMUX(1, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO2 \ - ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO2 ESP32_PINMUX(2, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO3 \ - ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO3 ESP32_PINMUX(3, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO4 \ - ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO4 ESP32_PINMUX(4, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO5 \ - ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO5 ESP32_PINMUX(5, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO6 \ - ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO6 ESP32_PINMUX(6, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO7 \ - ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO7 ESP32_PINMUX(7, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO8 \ - ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO8 ESP32_PINMUX(8, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO9 \ - ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO9 ESP32_PINMUX(9, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO10 \ - ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO10 ESP32_PINMUX(10, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO11 \ - ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO11 ESP32_PINMUX(11, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO12 \ - ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO12 ESP32_PINMUX(12, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO13 \ - ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO13 ESP32_PINMUX(13, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO14 \ - ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO14 ESP32_PINMUX(14, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO15 \ - ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO15 ESP32_PINMUX(15, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO16 \ - ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO16 ESP32_PINMUX(16, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO17 \ - ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO17 ESP32_PINMUX(17, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO18 \ - ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO18 ESP32_PINMUX(18, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO19 \ - ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO19 ESP32_PINMUX(19, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO20 \ - ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO20 ESP32_PINMUX(20, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO21 \ - ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO21 ESP32_PINMUX(21, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO26 \ - ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO26 ESP32_PINMUX(26, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO27 \ - ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO27 ESP32_PINMUX(27, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO28 \ - ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO28 ESP32_PINMUX(28, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO29 \ - ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO29 ESP32_PINMUX(29, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO30 \ - ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO30 ESP32_PINMUX(30, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO31 \ - ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO31 ESP32_PINMUX(31, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO32 \ - ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO32 ESP32_PINMUX(32, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO33 \ - ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO33 ESP32_PINMUX(33, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO34 \ - ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO34 ESP32_PINMUX(34, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO35 \ - ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO35 ESP32_PINMUX(35, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO36 \ - ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO36 ESP32_PINMUX(36, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO37 \ - ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO37 ESP32_PINMUX(37, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO38 \ - ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO38 ESP32_PINMUX(38, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO39 \ - ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO39 ESP32_PINMUX(39, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO40 \ - ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO40 ESP32_PINMUX(40, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO41 \ - ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO41 ESP32_PINMUX(41, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO42 \ - ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO42 ESP32_PINMUX(42, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO43 \ - ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO43 ESP32_PINMUX(43, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO44 \ - ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO44 ESP32_PINMUX(44, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO45 \ - ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO45 ESP32_PINMUX(45, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO46 \ - ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO46 ESP32_PINMUX(46, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO47 \ - ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO47 ESP32_PINMUX(47, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) -#define SDHC1_WP_GPIO48 \ - ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) +#define SDHC1_WP_GPIO48 ESP32_PINMUX(48, ESP_SDHOST_CARD_WRITE_PRT_2, ESP_NOSIG) /* SPIM2_CSEL */ #define SPIM2_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT) @@ -13378,4 +15024,5 @@ #define UART2_TX_GPIO48 ESP32_PINMUX(48, ESP_NOSIG, ESP_U2TXD_OUT) + #endif /* INC_DT_BINDS_PINCTRL_ESP32S3_PINCTRL_HAL_H_ */ From e0f45cce52bb64623393d6fc9d41447bb03e33ca Mon Sep 17 00:00:00 2001 From: Lucas Tamborrino Date: Tue, 10 Sep 2024 14:13:09 -0300 Subject: [PATCH 109/269] boards: espressif: add esp32s3-eye board support Add support for ESP32S3-EYE dev board. Signed-off-by: Lucas Tamborrino --- .../esp32s3_devkitm_procpu.yaml | 1 + .../espressif/esp32s3_eye/Kconfig.defconfig | 25 ++ .../espressif/esp32s3_eye/Kconfig.esp32s3_eye | 7 + boards/espressif/esp32s3_eye/Kconfig.sysbuild | 10 + boards/espressif/esp32s3_eye/board.cmake | 9 + boards/espressif/esp32s3_eye/board.yml | 5 + .../doc/img/ESP32-S3-EYE-isometric.webp | Bin 0 -> 8068 bytes ...ESP32-S3-EYE_20210913_V03_SystemBlock.webp | Bin 0 -> 12058 bytes .../img/ESP32-S3-EYE_MB-annotated-photo.webp | Bin 0 -> 5094 bytes .../img/ESP32-S3-EYE_SUB-annotated-photo.webp | Bin 0 -> 4604 bytes boards/espressif/esp32s3_eye/doc/index.rst | 284 ++++++++++++++++++ .../esp32s3_eye/esp32s3_eye-pinctrl.dtsi | 55 ++++ .../esp32s3_eye/esp32s3_eye_appcpu.dts | 65 ++++ .../esp32s3_eye/esp32s3_eye_appcpu.yaml | 27 ++ .../esp32s3_eye/esp32s3_eye_appcpu_defconfig | 4 + .../esp32s3_eye/esp32s3_eye_procpu.dts | 244 +++++++++++++++ .../esp32s3_eye/esp32s3_eye_procpu.yaml | 23 ++ .../esp32s3_eye/esp32s3_eye_procpu_defconfig | 11 + .../espressif/esp32s3_eye/support/openocd.cfg | 7 + 19 files changed, 777 insertions(+) create mode 100644 boards/espressif/esp32s3_eye/Kconfig.defconfig create mode 100644 boards/espressif/esp32s3_eye/Kconfig.esp32s3_eye create mode 100644 boards/espressif/esp32s3_eye/Kconfig.sysbuild create mode 100644 boards/espressif/esp32s3_eye/board.cmake create mode 100644 boards/espressif/esp32s3_eye/board.yml create mode 100644 boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE-isometric.webp create mode 100644 boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_20210913_V03_SystemBlock.webp create mode 100644 boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_MB-annotated-photo.webp create mode 100644 boards/espressif/esp32s3_eye/doc/img/ESP32-S3-EYE_SUB-annotated-photo.webp create mode 100644 boards/espressif/esp32s3_eye/doc/index.rst create mode 100644 boards/espressif/esp32s3_eye/esp32s3_eye-pinctrl.dtsi create mode 100644 boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts create mode 100644 boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.yaml create mode 100644 boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig create mode 100644 boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts create mode 100644 boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml create mode 100644 boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig create mode 100644 boards/espressif/esp32s3_eye/support/openocd.cfg diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml index 84bc4206e3552aa..084f6f7539e4b90 100644 --- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.yaml @@ -17,6 +17,7 @@ supported: - pwm - dma - input + - video testing: ignore_tags: - net diff --git a/boards/espressif/esp32s3_eye/Kconfig.defconfig b/boards/espressif/esp32s3_eye/Kconfig.defconfig new file mode 100644 index 000000000000000..71c7374e095933d --- /dev/null +++ b/boards/espressif/esp32s3_eye/Kconfig.defconfig @@ -0,0 +1,25 @@ +# ESP32S3 EYE board configuration + +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32S3_EYE_ESP32S3_PROCPU + +config LV_COLOR_16_SWAP + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +endif # BOARD_ESP32S3_EYE_ESP32S3_PROCPU + +if BOARD_ESP32S3_EYE_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_ESP32S3_EYE_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_eye/Kconfig.esp32s3_eye b/boards/espressif/esp32s3_eye/Kconfig.esp32s3_eye new file mode 100644 index 000000000000000..6aa4ac4ef1ed904 --- /dev/null +++ b/boards/espressif/esp32s3_eye/Kconfig.esp32s3_eye @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_EYE + select SOC_ESP32S3_WROOM_N8R8 + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_EYE_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_EYE_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_eye/Kconfig.sysbuild b/boards/espressif/esp32s3_eye/Kconfig.sysbuild new file mode 100644 index 000000000000000..8d3acb9e11d7c74 --- /dev/null +++ b/boards/espressif/esp32s3_eye/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/espressif/esp32s3_eye/board.cmake b/boards/espressif/esp32s3_eye/board.cmake new file mode 100644 index 000000000000000..2f04d1fe8861ea6 --- /dev/null +++ b/boards/espressif/esp32s3_eye/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*") + set(OPENOCD OPENOCD-NOTFOUND) +endif() +find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH) + +include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/espressif/esp32s3_eye/board.yml b/boards/espressif/esp32s3_eye/board.yml new file mode 100644 index 000000000000000..b16a5a1605cccaf --- /dev/null +++ b/boards/espressif/esp32s3_eye/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s3_eye + vendor: espressif + socs: + - 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HcmV?d00001 diff --git a/boards/espressif/esp32s3_eye/doc/index.rst b/boards/espressif/esp32s3_eye/doc/index.rst new file mode 100644 index 000000000000000..bbe95728e94da00 --- /dev/null +++ b/boards/espressif/esp32s3_eye/doc/index.rst @@ -0,0 +1,284 @@ +.. _esp32s3_eye: + +ESP32-S3-EYE +############ + +Overview +******** + +The ESP32-S3-EYE is a small-sized AI development board produced by [Espressif](https://espressif.com). +It is based on the [ESP32-S3](https://www.espressif.com/en/products/socs/esp32-s3) SoC. +It features a 2-Megapixel camera, an LCD display, and a microphone, which are used for image +recognition and audio processing. ESP32-S3-EYE offers plenty of storage, with an 8 MB Octal PSRAM +and a 8 MB flash. + +Hardware +******** + +The ESP32-S3-EYE board consists of two parts: the main board (ESP32-S3-EYE-MB) that integrates the +ESP32-S3-WROOM-1 module, camera, SD card slot, digital microphone, USB port, and function buttons; +and the sub board (ESP32-S3-EYE-SUB) that contains an LCD display. +The main board and sub board are connected through pin headers. + +.. figure:: img/ESP32-S3-EYE-isometric.webp + :align: center + :alt: ESP32-S3-EYE + +Block Diagram +------------- + +The block diagram below presents main components of the ESP32-S3-EYE-MB main board (on the left) +and the ESP32-S3-EYE-SUB sub board (on the right), as well as the interconnections between +components. + +.. figure:: img/ESP32-S3-EYE_20210913_V03_SystemBlock.webp + :align: center + :alt: ESP32-S3-EYE Block Diagram + +Components on the ESP32-S3-EYE-MB Main Board +-------------------------------------------- + +.. figure:: img/ESP32-S3-EYE_MB-annotated-photo.webp + :align: center + :alt: ESP32-S3-EYE_MB + +.. list-table:: Key Components MB + :header-rows: 1 + + * - No. + - Key Component + - Description + * - 1 + - Camera + - The camera OV2640 with 2 million pixels has a 66.5° field of view and a maximum resolution of 1600x1200. You can change the resolution when developing applications. + * - 2 + - Module Power LED + - The LED (green) turns on when USB power is connected to the board. If it is not turned on, it indicates either the USB power is not supplied, or the 5 V to 3.3 V LDO is broken. Software can configure GPIO3 to set different LED statuses (turned on/off, flashing) for different statuses of the board. Note that GPIO3 must be set up in open-drain mode. Pulling GPIO3 up may burn the LED. + * - 3 + - Pin Headers + - Connect the female headers on the sub board. + * - 4 + - 5 V to 3.3 V LDO + - Power regulator that converts a 5 V supply into a 3.3 V output for the module. + * - 5 + - Digital Microphone + - The digital I2S MEMS microphone features 61 dB SNR and –26 dBFS sensitivity, working at 3.3 V. + * - 6 + - FPC Connector + - Connects the main board and the sub board. + * - 7 + - Function Button + - There are six function buttons on the board. Users can configure any functions as needed except for the RST button. + * - 8 + - ESP32-S3-WROOM-1 + - The ESP32-S3-WROOM-1 module embeds the ESP32-S3R8 chip variant that provides Wi-Fi and Bluetooth 5 (LE) connectivity, as well as dedicated vector instructions for accelerating neural network computing and signal processing. On top of the integrated 8 MB Octal SPI PSRAM offered by the SoC, the module also comes with 8 MB flash, allowing for fast data access. ESP32-S3-WROOM-1U module is also supported. + * - 9 + - MicroSD Card Slot + - Used for inserting a MicroSD card to expand memory capacity. + * - 10 + - 3.3 V to 1.5 V LDO + - Power regulator that converts a 3.3 V supply into a 1.5 V output for the camera. + * - 11 + - 3.3 V to 2.8 V LDO + - Power regulator that converts a 3.3 V supply into a 2.8 V output for the camera. + * - 12 + - USB Port + - A Micro-USB port used for 5 V power supply to the board, as well as for communication with the chip via GPIO19 and GPIO20. + * - 13 + - Battery Soldering Points + - Used for soldering a battery socket to connect an external Li-ion battery that can serve as an alternative power supply to the board. If you use an external battery, make sure it has built-in protection circuit and fuse. The recommended specifications of the battery: capacity > 1000 mAh, output voltage 3.7 V, input voltage 4.2 V – 5 V. + * - 14 + - Battery Charger Chip + - 1 A linear Li-ion battery charger (ME4054BM5G-N) in ThinSOT package. The power source for charging is the **USB Port**. + * - 15 + - Battery Red LED + - When the USB power is connected to the board and a battery is not connected, the red LED blinks. If a battery is connected and being charged, the red LED turns on. When the battery is fully charged, it turns off. + * - 16 + - Accelerometer + - Three-axis accelerometer (QMA7981) for screen rotation, etc. + +Components on the ESP32-S3-EYE-SUB Sub Board +-------------------------------------------- + +.. figure:: img/ESP32-S3-EYE_SUB-annotated-photo.webp + :align: center + :alt: ESP32-S3-EYE_SUB + +.. list-table:: Key Components SUB + :header-rows: 1 + + * - Key Component + - Description + * - LCD Display + - 1.3” LCD display, connected to ESP32-S3 over the SPI bus. + * - Strapping Pins + - Four strapping pins led out from the main board. They can be used as testing points. + * - Female Headers + - Used for mounting onto the pin headers on the main board. + * - LCD FPC Connector + - Connects the sub board and the LCD display. + * - LCD_RST + - LCD_RST testing point. You can use it to reset the LCD display with control signals. + +Prerequisites +************* + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +----------- + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +------------------ + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be built (and flashed) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +-------- + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +------------ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be built one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_eye/esp32s3/procpu`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_eye/esp32s3/procpu + +Debugging +********* + +ESP32-S3 modules require patches to OpenOCD that are not upstreamed yet. +Espressif maintains their own fork of the project. The custom OpenOCD can be obtained at +`OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. +You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_eye/esp32s3/procpu + :goals: debug + +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye-pinctrl.dtsi b/boards/espressif/esp32s3_eye/esp32s3_eye-pinctrl.dtsi new file mode 100644 index 000000000000000..aba99bbe549d57c --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye-pinctrl.dtsi @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + lcd_cam_default: lcd_cam_default{ + group1 { + pinmux = ; + output-enable; + }; + group2 { + pinmux = , + , + , + , + , + , + , + , + , + , + ; + input-enable; + bias-disable; + }; + + }; +}; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts new file mode 100644 index 000000000000000..4b5d624018513d5 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Espressif ESP32S3-EYE APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.yaml b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.yaml new file mode 100644 index 000000000000000..787fcd46a10793c --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_eye/esp32s3/appcpu +name: ESP32-S3 EYE APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig new file mode 100644 index 000000000000000..9abf2ff0430aba3 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts new file mode 100644 index 000000000000000..fab93cbcf6d1ea7 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "espressif/esp32s3/esp32s3_wroom_n8r8.dtsi" +#include "esp32s3_eye-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Espressif ESP32S3-EYE PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + sw0 = &button0; + led0 = &green_led; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + zephyr,display = &st7789v; + zephyr,camera = &lcd_cam; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&adc0 0>; + keyup-threshold-mv = <3300>; + sample-period-ms = <50>; + + menu_key { + press-thresholds-mv = <2800>; + zephyr,code = ; + }; + + play_key { + press-thresholds-mv = <1920>; + zephyr,code = ; + }; + + up_key { + press-thresholds-mv = <350>; + zephyr,code = ; + }; + + down_key { + press-thresholds-mv = <800>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + green_led: led0 { + gpios = <&gpio0 3 GPIO_OPEN_DRAIN>; + label = "Power LED"; + }; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + mipi-max-frequency = <20000000>; + reg = <0>; + width = <240>; + height = <240>; + x-offset = <0>; + y-offset = <0>; + vcom = <0x19>; + gctrl = <0x35>; + vrhs = <0x12>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x2c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 01]; + pwctrl1-param = [a4 a1]; + pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23]; + nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23]; + ram-param = [00 F0]; + rgb-param = [CD 08 14]; + mipi-mode = ; + }; + }; +}; + +&dma { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + ov2640: ov2640@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + status = "okay"; + clock-rate-control = <0x80>; + port { + ov2640_ep_out: endpoint { + remote-endpoint = <&dvp_ep_in>; + }; + }; + }; +}; + +&lcd_cam { + status = "okay"; + cam-clk = < 10000000 >; + pinctrl-0 = <&lcd_cam_default>; + pinctrl-names = "default"; + source = <&ov2640>; + dmas = <&dma 2>; + dma-names = "rx"; + port { + dvp_ep_in: endpoint { + remote-endpoint = <&ov2640_ep_out>; + }; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&adc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1_4"; + zephyr,reference = "ADC_REF_INTERNAL"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml new file mode 100644 index 000000000000000..adddce2e59e7ea5 --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.yaml @@ -0,0 +1,23 @@ +identifier: esp32s3_eye/esp32s3/procpu +name: ESP32-S3 EYE PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig new file mode 100644 index 000000000000000..6c24dead95bf82c --- /dev/null +++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=4096 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y +CONFIG_ADC=y +CONFIG_ESP_SPIRAM=y +CONFIG_SPIRAM_MODE_OCT=y diff --git a/boards/espressif/esp32s3_eye/support/openocd.cfg b/boards/espressif/esp32s3_eye/support/openocd.cfg new file mode 100644 index 000000000000000..2f740b4a36ab1f4 --- /dev/null +++ b/boards/espressif/esp32s3_eye/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] From 88f6851a3dc5786bff76e0e98ffbe0f534c8152f Mon Sep 17 00:00:00 2001 From: Weiwei Guo Date: Tue, 13 Aug 2024 18:09:07 +0800 Subject: [PATCH 110/269] arch: common: Add user can specify the nocache location nocache ram is usually used by DMA to transfer data between peripherals and ram. Some chips use isolated nocache ram, which does not necessarily have to be in RAMABLE-REGION. By specifying the zephyr,nocache-ram options, users can specify the region where nocache-ram is located. If the user does not specify it, it defaults to RAMABLE-REGION. Signed-off-by: Weiwei Guo --- arch/common/nocache.ld | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/common/nocache.ld b/arch/common/nocache.ld index a4e500e8b17b3c1..24e81cdefcf8fb1 100644 --- a/arch/common/nocache.ld +++ b/arch/common/nocache.ld @@ -7,6 +7,12 @@ /* Copied from linker.ld */ +#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_nocache_ram), okay) +#define NOCACHE_REGION LINKER_DT_NODE_REGION_NAME_TOKEN(DT_CHOSEN(zephyr_nocache_ram)) +#else +#define NOCACHE_REGION RAMABLE_REGION +#endif + /* Non-cached region of RAM */ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) { @@ -27,5 +33,5 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),) MPU_ALIGN(_nocache_ram_size); #endif _nocache_ram_end = .; -} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION) +} GROUP_DATA_LINK_IN(NOCACHE_REGION, NOCACHE_REGION) _nocache_ram_size = _nocache_ram_end - _nocache_ram_start; From 4ec67271ab55327855cfc8d1d97d8a225b0301ac Mon Sep 17 00:00:00 2001 From: Georgij Cernysiov Date: Thu, 6 Jun 2024 11:13:24 +0200 Subject: [PATCH 111/269] drivers: flash: stm32 ospi correct lines on writes Correct used lines based on write opcode regardless of the data mode. The write opcode is set during init for all modes and can be overwritten in DT. Add lines correction for PP_1_1_2. Signed-off-by: Georgij Cernysiov --- drivers/flash/flash_stm32_ospi.c | 61 ++++++++++++++++---------------- 1 file changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c index e852f743fdb5863..93c31c84d2ee65e 100644 --- a/drivers/flash/flash_stm32_ospi.c +++ b/drivers/flash/flash_stm32_ospi.c @@ -1463,36 +1463,37 @@ static int flash_stm32_ospi_write(const struct device *dev, off_t addr, /* using 32bits address also in SPI/STR mode */ cmd_pp.Instruction = dev_data->write_opcode; - if (dev_cfg->data_mode != OSPI_OPI_MODE) { - switch (cmd_pp.Instruction) { - case SPI_NOR_CMD_PP_4B: - __fallthrough; - case SPI_NOR_CMD_PP: { - cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; - cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE; - cmd_pp.DataMode = HAL_OSPI_DATA_1_LINE; - break; - } - case SPI_NOR_CMD_PP_1_1_4_4B: - __fallthrough; - case SPI_NOR_CMD_PP_1_1_4: { - cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; - cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE; - cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES; - break; - } - case SPI_NOR_CMD_PP_1_4_4_4B: - __fallthrough; - case SPI_NOR_CMD_PP_1_4_4: { - cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; - cmd_pp.AddressMode = HAL_OSPI_ADDRESS_4_LINES; - cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES; - break; - } - default: - /* use the mode from ospi_prepare_cmd */ - break; - } + /* Adapt lines based on write_opcode */ + switch (cmd_pp.Instruction) { + case SPI_NOR_CMD_PP_4B: + __fallthrough; + case SPI_NOR_CMD_PP: + cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; + cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE; + cmd_pp.DataMode = HAL_OSPI_DATA_1_LINE; + break; + case SPI_NOR_CMD_PP_1_1_2: + cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; + cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE; + cmd_pp.DataMode = HAL_OSPI_DATA_2_LINES; + break; + case SPI_NOR_CMD_PP_1_1_4_4B: + __fallthrough; + case SPI_NOR_CMD_PP_1_1_4: + cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; + cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE; + cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES; + break; + case SPI_NOR_CMD_PP_1_4_4_4B: + __fallthrough; + case SPI_NOR_CMD_PP_1_4_4: + cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; + cmd_pp.AddressMode = HAL_OSPI_ADDRESS_4_LINES; + cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES; + break; + default: + /* Use lines based on data mode set in ospi_prepare_cmd */ + break; } cmd_pp.Address = addr; From eb22e1fc983d2d1b2c5e318d96151d66500da621 Mon Sep 17 00:00:00 2001 From: Emil Gydesen Date: Wed, 10 Jul 2024 15:10:39 +0200 Subject: [PATCH 112/269] Bluetooth: TBS: Make GTBS mandatory Any places that checked for GTBS is now always enabled as GTBS is mandatory to support, and the Kconfig option was removed. Also removed a duplicate Kconfig option for TBS, BT_TBS_SERVICE_COUNT, as it was unused. The other Kconfig option BT_TBS_BEARER_COUNT is used instead exclusively to set it if needed. Since GTBS can now exist alone, it must also support having its own calls and other values. This means that the GTBS and TBS instances now share the same underlying struct. Signed-off-by: Emil Gydesen --- .../bluetooth/api/audio/shell/ccp.rst | 4 +- samples/bluetooth/tmap_central/prj.conf | 1 - subsys/bluetooth/audio/Kconfig.tbs | 28 +- subsys/bluetooth/audio/shell/bap.c | 4 +- subsys/bluetooth/audio/shell/tbs.c | 14 +- subsys/bluetooth/audio/tbs.c | 950 ++++++++---------- tests/bluetooth/shell/audio.conf | 1 + tests/bluetooth/shell/testcase.yaml | 6 + tests/bluetooth/tester/overlay-le-audio.conf | 4 +- .../bluetooth/tester/src/audio/CMakeLists.txt | 2 +- tests/bluetooth/tester/src/btp_core.c | 4 +- tests/bsim/bluetooth/audio/prj.conf | 1 + 12 files changed, 444 insertions(+), 575 deletions(-) diff --git a/doc/connectivity/bluetooth/api/audio/shell/ccp.rst b/doc/connectivity/bluetooth/api/audio/shell/ccp.rst index 023e8515aa9c798..b03a46aeeba2d78 100644 --- a/doc/connectivity/bluetooth/api/audio/shell/ccp.rst +++ b/doc/connectivity/bluetooth/api/audio/shell/ccp.rst @@ -31,7 +31,7 @@ Since a server may have multiple TBS instances, most of the tbs_client commands will take an index (starting from 0) as input. Joining calls require at least 2 call IDs, and all call indexes shall be on the same TBS instance. -A server may also have a GTBS instance, which is an abstraction layer for all +A server will also have a GTBS instance, which is an abstraction layer for all the telephone bearers on the server. If the server has both GTBS and TBS, the client may subscribe and use either when sending requests if :code:`BT_TBS_CLIENT_GTBS` is enabled. @@ -169,6 +169,8 @@ TBS can be controlled locally, or by a remote device (when in a call). For example a remote device may initiate a call to the device with the TBS server, or the TBS server may initiate a call to remote device, without a TBS_CLIENT client. The TBS implementation is capable of fully controlling any call. +Omitting an index for commands where a :code:`` can be supplied, defaults to the +GTBS bearer. .. code-block:: console diff --git a/samples/bluetooth/tmap_central/prj.conf b/samples/bluetooth/tmap_central/prj.conf index a9a5c02eca3052b..d9c67f30b764aca 100644 --- a/samples/bluetooth/tmap_central/prj.conf +++ b/samples/bluetooth/tmap_central/prj.conf @@ -32,7 +32,6 @@ CONFIG_MCTL=y # CCP support CONFIG_BT_TBS=y -CONFIG_BT_GTBS=y CONFIG_BT_TBS_SUPPORTED_FEATURES=3 # Support an ISO channel per ASE diff --git a/subsys/bluetooth/audio/Kconfig.tbs b/subsys/bluetooth/audio/Kconfig.tbs index 2958d134366fb6a..01de630df7631ec 100644 --- a/subsys/bluetooth/audio/Kconfig.tbs +++ b/subsys/bluetooth/audio/Kconfig.tbs @@ -1,6 +1,7 @@ # Bluetooth Audio - Call control configuration options # # Copyright (c) 2020 Bose Corporation +# Copyright (c) 2024 Nordic Semiconductor ASA # # SPDX-License-Identifier: Apache-2.0 # @@ -15,18 +16,12 @@ config BT_TBS select BT_GATT_DYNAMIC_DB depends on UTF8 help - This option enables support for Telephone Bearer Service. + This option enables support for Telephone Bearer Service. By default this only + initializes the GTBS service. If specific TBS services are wanted, they need to be + enabled by setting BT_TBS_BEARER_COUNT to a non-zero value. if BT_TBS -# TODO: BT_GTBS is mandatory if you support the call control server role. -# Need to enforce this. -config BT_GTBS - bool "Generic Telephone Bearer Service Support" - default y - help - This option enables support for Generic Telephone Bearer Service. - config BT_TBS_PROVIDER_NAME string "Telephone Bearer Service Provider Name" default "Unknown" @@ -101,26 +96,17 @@ config BT_TBS_MAX_CALLS config BT_TBS_BEARER_COUNT int "How many bearer instances the device instantiates" - default 1 - range 1 $(UINT8_MAX) + default 0 + range 0 $(UINT8_MAX) help Sets the number of TBS instances that are instantiated -config BT_TBS_SERVICE_COUNT - int "Number of instantiated bearer service instances" - default BT_TBS_BEARER_COUNT - range 0 BT_TBS_BEARER_COUNT if BT_GTBS - range BT_TBS_BEARER_COUNT BT_TBS_BEARER_COUNT - help - Sets the number of TBS service instances that are instantiated - config BT_TBS_MAX_SCHEME_LIST_LENGTH int "The maximum length of the URI scheme list" default 30 range 0 512 help - Sets the maximum length of the URI scheme list. If BT_GTBS is enabled, - then the maximum length should be maximum 512 / BT_TBS_BEARER_COUNT. + Sets the maximum length of the URI scheme list. config BT_TBS_AUTHORIZATION bool "TBS authorization requirement" diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c index 0cb175ec2eed838..f442dd512dace2f 100644 --- a/subsys/bluetooth/audio/shell/bap.c +++ b/subsys/bluetooth/audio/shell/bap.c @@ -4136,8 +4136,8 @@ static ssize_t connectable_ad_data_add(struct bt_data *data_array, IF_ENABLED(CONFIG_BT_ASCS, (BT_UUID_16_ENCODE(BT_UUID_ASCS_VAL),)) IF_ENABLED(CONFIG_BT_BAP_SCAN_DELEGATOR, (BT_UUID_16_ENCODE(BT_UUID_BASS_VAL),)) IF_ENABLED(CONFIG_BT_PACS, (BT_UUID_16_ENCODE(BT_UUID_PACS_VAL),)) - IF_ENABLED(CONFIG_BT_GTBS, (BT_UUID_16_ENCODE(BT_UUID_GTBS_VAL),)) - IF_ENABLED(CONFIG_BT_TBS, (BT_UUID_16_ENCODE(BT_UUID_TBS_VAL),)) + IF_ENABLED(CONFIG_BT_TBS, (BT_UUID_16_ENCODE(BT_UUID_GTBS_VAL),)) + IF_ENABLED(CONFIG_BT_TBS_BEARER_COUNT, (BT_UUID_16_ENCODE(BT_UUID_TBS_VAL),)) IF_ENABLED(CONFIG_BT_VCP_VOL_REND, (BT_UUID_16_ENCODE(BT_UUID_VCS_VAL),)) IF_ENABLED(CONFIG_BT_HAS, (BT_UUID_16_ENCODE(BT_UUID_HAS_VAL),)) /* Shall be last */ }; diff --git a/subsys/bluetooth/audio/shell/tbs.c b/subsys/bluetooth/audio/shell/tbs.c index fb8e2c639544960..479422dc2b4cbe9 100644 --- a/subsys/bluetooth/audio/shell/tbs.c +++ b/subsys/bluetooth/audio/shell/tbs.c @@ -209,7 +209,7 @@ static int cmd_tbs_originate(const struct shell *sh, size_t argc, char *argv[]) return -ENOEXEC; } } else { - service_index = 0U; + service_index = BT_TBS_GTBS_INDEX; } result = bt_tbs_originate((uint8_t)service_index, argv[argc - 1], @@ -402,7 +402,7 @@ static int cmd_tbs_incoming(const struct shell *sh, size_t argc, char *argv[]) } } } else { - service_index = 0U; + service_index = BT_TBS_GTBS_INDEX; } result = bt_tbs_remote_incoming((uint8_t)service_index, @@ -445,7 +445,7 @@ static int cmd_tbs_set_bearer_provider_name(const struct shell *sh, size_t argc, } } } else { - service_index = 0U; + service_index = BT_TBS_GTBS_INDEX; } result = bt_tbs_set_bearer_provider_name((uint8_t)service_index, @@ -485,7 +485,7 @@ static int cmd_tbs_set_bearer_technology(const struct shell *sh, size_t argc, } } } else { - service_index = 0U; + service_index = BT_TBS_GTBS_INDEX; } technology = shell_strtoul(argv[argc - 1], 0, &result); @@ -538,7 +538,7 @@ static int cmd_tbs_set_bearer_signal_strength(const struct shell *sh, } } } else { - service_index = 0U; + service_index = BT_TBS_GTBS_INDEX; } signal_strength = shell_strtoul(argv[argc - 1], 0, &result); @@ -592,7 +592,7 @@ static int cmd_tbs_set_status_flags(const struct shell *sh, size_t argc, } } } else { - service_index = 0U; + service_index = BT_TBS_GTBS_INDEX; } status_flags = shell_strtoul(argv[argc - 1], 0, &result); @@ -644,7 +644,7 @@ static int cmd_tbs_set_uri_scheme_list(const struct shell *sh, size_t argc, } } } else { - service_index = 0U; + service_index = BT_TBS_GTBS_INDEX; } result = bt_tbs_set_uri_scheme_list((uint8_t)service_index, diff --git a/subsys/bluetooth/audio/tbs.c b/subsys/bluetooth/audio/tbs.c index c34810ecf9ccd0b..af958bd0462f2e5 100644 --- a/subsys/bluetooth/audio/tbs.c +++ b/subsys/bluetooth/audio/tbs.c @@ -1,7 +1,7 @@ /* Bluetooth TBS - Telephone Bearer Service * * Copyright (c) 2020 Bose Corporation - * Copyright (c) 2021 Nordic Semiconductor ASA + * Copyright (c) 2021-2024 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ @@ -36,9 +36,10 @@ LOG_MODULE_REGISTER(bt_tbs, CONFIG_BT_TBS_LOG_LEVEL); -#define BT_TBS_VALID_STATUS_FLAGS(val) ((val) <= (BIT(0) | BIT(1))) +#define BT_TBS_VALID_STATUS_FLAGS(val) ((val) <= (BIT(0) | BIT(1))) -struct service_inst { +/* A service instance can either be a GTBS or a TBS instance */ +struct tbs_inst { /* Attribute values */ char provider_name[CONFIG_BT_TBS_MAX_PROVIDER_NAME_LENGTH]; char uci[BT_TBS_MAX_UCI_SIZE]; @@ -51,6 +52,9 @@ struct service_inst { struct bt_tbs_in_uri incoming_uri; struct bt_tbs_in_uri friendly_name; struct bt_tbs_in_uri in_call; + char uri_scheme_list[CONFIG_BT_TBS_MAX_SCHEME_LIST_LENGTH]; + struct bt_tbs_terminate_reason terminate_reason; + struct bt_tbs_call calls[CONFIG_BT_TBS_MAX_CALLS]; bool notify_current_calls; bool notify_call_states; @@ -63,48 +67,32 @@ struct service_inst { size_t attr_count; }; -struct tbs_service_inst { - struct service_inst inst; - - /* Attribute values */ - char uri_scheme_list[CONFIG_BT_TBS_MAX_SCHEME_LIST_LENGTH]; - struct bt_tbs_terminate_reason terminate_reason; - - /* Instance values */ - struct bt_tbs_call calls[CONFIG_BT_TBS_MAX_CALLS]; -}; +static struct tbs_inst svc_insts[CONFIG_BT_TBS_BEARER_COUNT]; +static struct tbs_inst gtbs_inst; -struct gtbs_service_inst { - struct service_inst inst; -}; - -#if defined(CONFIG_BT_GTBS) -#define READ_BUF_SIZE (CONFIG_BT_TBS_MAX_CALLS * \ - sizeof(struct bt_tbs_current_call_item) * \ - CONFIG_BT_TBS_BEARER_COUNT) -#else -#define READ_BUF_SIZE (CONFIG_BT_TBS_MAX_CALLS * \ - sizeof(struct bt_tbs_current_call_item)) -#endif /* defined(CONFIG_BT_GTBS) */ +#define READ_BUF_SIZE \ + MAX(BT_ATT_MAX_ATTRIBUTE_LEN, \ + (CONFIG_BT_TBS_MAX_CALLS * sizeof(struct bt_tbs_current_call_item) * \ + (1U + ARRAY_SIZE(svc_insts)))) NET_BUF_SIMPLE_DEFINE_STATIC(read_buf, READ_BUF_SIZE); -static struct tbs_service_inst svc_insts[CONFIG_BT_TBS_BEARER_COUNT]; -static struct gtbs_service_inst gtbs_inst; - /* Used to notify app with held calls in case of join */ static struct bt_tbs_call *held_calls[CONFIG_BT_TBS_MAX_CALLS]; static uint8_t held_calls_cnt; static struct bt_tbs_cb *tbs_cbs; -static bool inst_is_gtbs(const struct service_inst *inst) +static bool inst_is_gtbs(const struct tbs_inst *inst) { - return IS_ENABLED(CONFIG_BT_GTBS) && inst == >bs_inst.inst; + if (CONFIG_BT_TBS_BEARER_COUNT > 0) { + return inst == >bs_inst; + } else { + return true; + } } -static uint8_t inst_index(const struct service_inst *inst) +static uint8_t inst_index(const struct tbs_inst *inst) { - const struct tbs_service_inst *tbs; ptrdiff_t index = 0; __ASSERT_NO_MSG(inst); @@ -113,29 +101,26 @@ static uint8_t inst_index(const struct service_inst *inst) return BT_TBS_GTBS_INDEX; } - tbs = CONTAINER_OF(inst, struct tbs_service_inst, inst); - - index = tbs - svc_insts; + index = inst - svc_insts; __ASSERT(index >= 0 && index < ARRAY_SIZE(svc_insts), "Invalid tbs_inst pointer"); return (uint8_t)index; } -static struct service_inst *inst_lookup_index(uint8_t index) +static struct tbs_inst *inst_lookup_index(uint8_t index) { - if (IS_ENABLED(CONFIG_BT_GTBS) && index == BT_TBS_GTBS_INDEX) { - return >bs_inst.inst; + if (index == BT_TBS_GTBS_INDEX) { + return >bs_inst; } - if (index < CONFIG_BT_TBS_BEARER_COUNT) { - return &svc_insts[index].inst; + if (ARRAY_SIZE(svc_insts) > 0U && index < ARRAY_SIZE(svc_insts)) { + return &svc_insts[index]; } return NULL; } -static struct bt_tbs_call *lookup_call_in_inst(struct tbs_service_inst *inst, - uint8_t call_index) +static struct bt_tbs_call *lookup_call_in_inst(struct tbs_inst *inst, uint8_t call_index) { if (call_index == BT_TBS_FREE_CALL_INDEX) { return NULL; @@ -158,15 +143,19 @@ static struct bt_tbs_call *lookup_call_in_inst(struct tbs_service_inst *inst, */ static struct bt_tbs_call *lookup_call(uint8_t call_index) { + struct bt_tbs_call *call; if (call_index == BT_TBS_FREE_CALL_INDEX) { return NULL; } - for (int i = 0; i < ARRAY_SIZE(svc_insts); i++) { - struct bt_tbs_call *call = lookup_call_in_inst(&svc_insts[i], - call_index); + call = lookup_call_in_inst(>bs_inst, call_index); + if (call != NULL) { + return call; + } + for (size_t i = 0; i < ARRAY_SIZE(svc_insts); i++) { + call = lookup_call_in_inst(&svc_insts[i], call_index); if (call != NULL) { return call; } @@ -175,7 +164,7 @@ static struct bt_tbs_call *lookup_call(uint8_t call_index) return NULL; } -static bool inst_check_attr(struct service_inst *inst, const struct bt_gatt_attr *attr) +static bool inst_check_attr(struct tbs_inst *inst, const struct bt_gatt_attr *attr) { for (size_t j = 0; j < inst->attr_count; j++) { if (&inst->attrs[j] == attr) { @@ -186,31 +175,35 @@ static bool inst_check_attr(struct service_inst *inst, const struct bt_gatt_attr return false; } -static struct service_inst *lookup_inst_by_attr(const struct bt_gatt_attr *attr) +static struct tbs_inst *lookup_inst_by_attr(const struct bt_gatt_attr *attr) { if (attr == NULL) { return NULL; } for (int i = 0; i < ARRAY_SIZE(svc_insts); i++) { - if (inst_check_attr(&svc_insts[i].inst, attr)) { - return &svc_insts[i].inst; + if (inst_check_attr(&svc_insts[i], attr)) { + return &svc_insts[i]; } } - if (IS_ENABLED(CONFIG_BT_GTBS) && inst_check_attr(>bs_inst.inst, attr)) { - return >bs_inst.inst; + if (inst_check_attr(>bs_inst, attr)) { + return >bs_inst; } return NULL; } -static struct tbs_service_inst *lookup_inst_by_call_index(uint8_t call_index) +static struct tbs_inst *lookup_inst_by_call_index(uint8_t call_index) { if (call_index == BT_TBS_FREE_CALL_INDEX) { return NULL; } + if (lookup_call_in_inst(>bs_inst, call_index) != NULL) { + return >bs_inst; + } + for (size_t i = 0; i < ARRAY_SIZE(svc_insts); i++) { if (lookup_call_in_inst(&svc_insts[i], call_index) != NULL) { return &svc_insts[i]; @@ -233,8 +226,7 @@ static bool is_authorized(struct bt_conn *conn) return true; } -static bool uri_scheme_in_list(const char *uri_scheme, - const char *uri_scheme_list) +static bool uri_scheme_in_list(const char *uri_scheme, const char *uri_scheme_list) { const size_t scheme_len = strlen(uri_scheme); const size_t scheme_list_len = strlen(uri_scheme_list); @@ -262,9 +254,9 @@ static bool uri_scheme_in_list(const char *uri_scheme, return false; } -static struct tbs_service_inst *lookup_inst_by_uri_scheme(const uint8_t *uri, uint8_t uri_len) +static struct tbs_inst *lookup_inst_by_uri_scheme(const uint8_t *uri, uint8_t uri_len) { - char uri_scheme[CONFIG_BT_TBS_MAX_URI_LENGTH] = { 0 }; + char uri_scheme[CONFIG_BT_TBS_MAX_URI_LENGTH] = {0}; if (uri_len == 0) { return NULL; @@ -285,35 +277,29 @@ static struct tbs_service_inst *lookup_inst_by_uri_scheme(const uint8_t *uri, ui for (size_t i = 0; i < ARRAY_SIZE(svc_insts); i++) { for (size_t j = 0; j < ARRAY_SIZE(svc_insts[i].calls); j++) { - if (uri_scheme_in_list(uri_scheme, - svc_insts[i].uri_scheme_list)) { + if (uri_scheme_in_list(uri_scheme, svc_insts[i].uri_scheme_list)) { return &svc_insts[i]; } } } + /* If not found in any TBS instance, check GTBS */ + if (uri_scheme_in_list(uri_scheme, gtbs_inst.uri_scheme_list)) { + return >bs_inst; + } + return NULL; } -static void tbs_set_terminate_reason(struct tbs_service_inst *inst, - uint8_t call_index, uint8_t reason) +static void tbs_set_terminate_reason(struct tbs_inst *inst, uint8_t call_index, uint8_t reason) { inst->terminate_reason.call_index = call_index; inst->terminate_reason.reason = reason; - LOG_DBG("Index %u: call index 0x%02x, reason %s", inst_index(&inst->inst), call_index, + LOG_DBG("Index %u: call index 0x%02x, reason %s", inst_index(inst), call_index, bt_tbs_term_reason_str(reason)); - bt_gatt_notify_uuid(NULL, BT_UUID_TBS_TERMINATE_REASON, - inst->inst.attrs, - (void *)&inst->terminate_reason, - sizeof(inst->terminate_reason)); - - if (IS_ENABLED(CONFIG_BT_GTBS)) { - bt_gatt_notify_uuid(NULL, BT_UUID_TBS_TERMINATE_REASON, - gtbs_inst.inst.attrs, - (void *)&inst->terminate_reason, - sizeof(inst->terminate_reason)); - } + bt_gatt_notify_uuid(NULL, BT_UUID_TBS_TERMINATE_REASON, inst->attrs, + (void *)&inst->terminate_reason, sizeof(inst->terminate_reason)); } /** @@ -322,6 +308,9 @@ static void tbs_set_terminate_reason(struct tbs_service_inst *inst, * For each new call, the call index should be incremented and wrap at 255. * However, the index = 0 is reserved for outgoing calls * + * Call indexes are shared among all bearers, so there is always a 1:1 between a call index and a + * bearer + * * @return uint8_t The next free call index */ static uint8_t next_free_call_index(void) @@ -349,8 +338,8 @@ static uint8_t next_free_call_index(void) return BT_TBS_FREE_CALL_INDEX; } -static struct bt_tbs_call *call_alloc(struct tbs_service_inst *inst, uint8_t state, - const uint8_t *uri, uint16_t uri_len) +static struct bt_tbs_call *call_alloc(struct tbs_inst *inst, uint8_t state, const uint8_t *uri, + uint16_t uri_len) { struct bt_tbs_call *free_call = NULL; @@ -385,8 +374,7 @@ static void call_free(struct bt_tbs_call *call) call->index = BT_TBS_FREE_CALL_INDEX; } -static void net_buf_put_call_states_by_inst(const struct tbs_service_inst *inst, - struct net_buf_simple *buf) +static void net_buf_put_call_states_by_inst(const struct tbs_inst *inst, struct net_buf_simple *buf) { const struct bt_tbs_call *call; const struct bt_tbs_call *calls; @@ -401,30 +389,34 @@ static void net_buf_put_call_states_by_inst(const struct tbs_service_inst *inst, continue; } + if (buf->len + 3U > buf->size) { + LOG_WRN("Not able to store all call states in buffer"); + return; + } + net_buf_simple_add_u8(buf, call->index); net_buf_simple_add_u8(buf, call->state); net_buf_simple_add_u8(buf, call->flags); } } -static void net_buf_put_call_states(const struct service_inst *inst, struct net_buf_simple *buf) +static void net_buf_put_call_states(const struct tbs_inst *inst, struct net_buf_simple *buf) { net_buf_simple_reset(buf); + net_buf_put_call_states_by_inst(inst, buf); + + /* For GTBS we add all the calls the GTBS bearer has itself, as well as all the other + * bearers + */ if (inst_is_gtbs(inst)) { for (size_t i = 0; i < ARRAY_SIZE(svc_insts); i++) { net_buf_put_call_states_by_inst(&svc_insts[i], buf); } - } else { - struct tbs_service_inst *service_inst; - - service_inst = CONTAINER_OF(inst, struct tbs_service_inst, inst); - - net_buf_put_call_states_by_inst(service_inst, buf); } } -static void net_buf_put_current_calls_by_inst(const struct tbs_service_inst *inst, +static void net_buf_put_current_calls_by_inst(const struct tbs_inst *inst, struct net_buf_simple *buf) { const struct bt_tbs_call *call; @@ -445,7 +437,15 @@ static void net_buf_put_current_calls_by_inst(const struct tbs_service_inst *ins uri_length = strlen(call->remote_uri); item_len = sizeof(call->index) + sizeof(call->state) + sizeof(call->flags) + uri_length; - net_buf_simple_add_u8(buf, item_len); + + __ASSERT_NO_MSG(item_len <= UINT8_MAX); + + if (buf->len + sizeof(uint8_t) + item_len > buf->size) { + LOG_WRN("Not able to store all calls in buffer"); + return; + } + + net_buf_simple_add_u8(buf, (uint8_t)item_len); net_buf_simple_add_u8(buf, call->index); net_buf_simple_add_u8(buf, call->state); net_buf_simple_add_u8(buf, call->flags); @@ -453,32 +453,31 @@ static void net_buf_put_current_calls_by_inst(const struct tbs_service_inst *ins } } -static void net_buf_put_current_calls(const struct service_inst *inst, struct net_buf_simple *buf) +static void net_buf_put_current_calls(const struct tbs_inst *inst, struct net_buf_simple *buf) { net_buf_simple_reset(buf); + net_buf_put_current_calls_by_inst(inst, buf); + + /* For GTBS we add all the calls the GTBS bearer has itself, as well as all the other + * bearers + */ if (inst_is_gtbs(inst)) { for (size_t i = 0; i < ARRAY_SIZE(svc_insts); i++) { net_buf_put_current_calls_by_inst(&svc_insts[i], buf); } - } else { - struct tbs_service_inst *service_inst; - - service_inst = CONTAINER_OF(inst, struct tbs_service_inst, inst); - - net_buf_put_current_calls_by_inst(service_inst, buf); } } -static int inst_notify_calls(const struct service_inst *inst) +static int inst_notify_calls(const struct tbs_inst *inst) { int err; if (inst->notify_call_states) { net_buf_put_call_states(inst, &read_buf); - err = bt_gatt_notify_uuid(NULL, BT_UUID_TBS_CALL_STATE, inst->attrs, - read_buf.data, read_buf.len); + err = bt_gatt_notify_uuid(NULL, BT_UUID_TBS_CALL_STATE, inst->attrs, read_buf.data, + read_buf.len); if (err != 0) { return err; } @@ -497,87 +496,91 @@ static int inst_notify_calls(const struct service_inst *inst) return 0; } -static int notify_calls(const struct tbs_service_inst *inst) +static int notify_calls(const struct tbs_inst *inst) { + int err; + if (inst == NULL) { return -EINVAL; } - if (IS_ENABLED(CONFIG_BT_GTBS)) { - int err; + /* Notify TBS */ + err = inst_notify_calls(inst); + if (err != 0) { + return err; + } - err = inst_notify_calls(>bs_inst.inst); + if (!inst_is_gtbs(inst)) { + /* If the instance is different than the GTBS notify on the GTBS instance as well */ + err = inst_notify_calls(>bs_inst); if (err != 0) { return err; } } - return inst_notify_calls(&inst->inst); + return 0; } -static ssize_t read_provider_name(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_provider_name(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); LOG_DBG("Index %u, Provider name %s", inst_index(inst), inst->provider_name); - return bt_gatt_attr_read(conn, attr, buf, len, offset, - inst->provider_name, strlen(inst->provider_name)); + return bt_gatt_attr_read(conn, attr, buf, len, offset, inst->provider_name, + strlen(inst->provider_name)); } -static void provider_name_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void provider_name_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_uci(struct bt_conn *conn, const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_uci(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); LOG_DBG("Index %u: UCI %s", inst_index(inst), inst->uci); return bt_gatt_attr_read(conn, attr, buf, len, offset, inst->uci, strlen(inst->uci)); } -static ssize_t read_technology(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_technology(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); LOG_DBG("Index %u: Technology 0x%02x", inst_index(inst), inst->technology); - return bt_gatt_attr_read(conn, attr, buf, len, offset, - &inst->technology, sizeof(inst->technology)); + return bt_gatt_attr_read(conn, attr, buf, len, offset, &inst->technology, + sizeof(inst->technology)); } -static void technology_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void technology_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_uri_scheme_list(struct bt_conn *conn, - const struct bt_gatt_attr *attr, +static ssize_t read_uri_scheme_list(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) { - const struct service_inst *inst_p = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); net_buf_simple_reset(&read_buf); - if (inst_is_gtbs(inst_p)) { + net_buf_simple_add_mem(&read_buf, inst->uri_scheme_list, strlen(inst->uri_scheme_list)); + + if (inst_is_gtbs(inst)) { /* TODO: Make uri schemes unique */ for (size_t i = 0; i < ARRAY_SIZE(svc_insts); i++) { size_t uri_len = strlen(svc_insts[i].uri_scheme_list); @@ -588,85 +591,67 @@ static ssize_t read_uri_scheme_list(struct bt_conn *conn, break; } - net_buf_simple_add_mem(&read_buf, - svc_insts[i].uri_scheme_list, - uri_len); + net_buf_simple_add_mem(&read_buf, svc_insts[i].uri_scheme_list, uri_len); } LOG_DBG("GTBS: URI scheme %.*s", read_buf.len, read_buf.data); } else { - const struct tbs_service_inst *inst; - - inst = CONTAINER_OF(inst_p, struct tbs_service_inst, inst); - - net_buf_simple_add_mem(&read_buf, inst->uri_scheme_list, - strlen(inst->uri_scheme_list)); - - LOG_DBG("Index %u: URI scheme %.*s", - inst_index(inst_p), read_buf.len, read_buf.data); + LOG_DBG("Index %u: URI scheme %.*s", inst_index(inst), read_buf.len, read_buf.data); } - return bt_gatt_attr_read(conn, attr, buf, len, offset, - read_buf.data, read_buf.len); + return bt_gatt_attr_read(conn, attr, buf, len, offset, read_buf.data, read_buf.len); } -static void uri_scheme_list_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void uri_scheme_list_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_signal_strength(struct bt_conn *conn, - const struct bt_gatt_attr *attr, +static ssize_t read_signal_strength(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); LOG_DBG("Index %u: Signal strength 0x%02x", inst_index(inst), inst->signal_strength); - return bt_gatt_attr_read(conn, attr, buf, len, offset, - &inst->signal_strength, sizeof(inst->signal_strength)); + return bt_gatt_attr_read(conn, attr, buf, len, offset, &inst->signal_strength, + sizeof(inst->signal_strength)); } -static void signal_strength_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void signal_strength_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_signal_strength_interval(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, - uint16_t offset) +static ssize_t read_signal_strength_interval(struct bt_conn *conn, const struct bt_gatt_attr *attr, + void *buf, uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); if (!is_authorized(conn)) { return BT_GATT_ERR(BT_ATT_ERR_AUTHORIZATION); } - LOG_DBG("Index %u: Signal strength interval 0x%02x", - inst_index(inst), inst->signal_strength_interval); + LOG_DBG("Index %u: Signal strength interval 0x%02x", inst_index(inst), + inst->signal_strength_interval); - return bt_gatt_attr_read(conn, attr, buf, len, offset, - &inst->signal_strength_interval, + return bt_gatt_attr_read(conn, attr, buf, len, offset, &inst->signal_strength_interval, sizeof(inst->signal_strength_interval)); } -static ssize_t write_signal_strength_interval(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - const void *buf, uint16_t len, - uint16_t offset, uint8_t flags) +static ssize_t write_signal_strength_interval(struct bt_conn *conn, const struct bt_gatt_attr *attr, + const void *buf, uint16_t len, uint16_t offset, + uint8_t flags) { - struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); struct net_buf_simple net_buf; uint8_t signal_strength_interval; @@ -691,10 +676,9 @@ static ssize_t write_signal_strength_interval(struct bt_conn *conn, return len; } -static void current_calls_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void current_calls_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - struct service_inst *inst = lookup_inst_by_attr(attr); + struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); @@ -702,11 +686,10 @@ static void current_calls_cfg_changed(const struct bt_gatt_attr *attr, } } -static ssize_t read_current_calls(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_current_calls(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); LOG_DBG("Index %u", inst_index(inst)); @@ -716,26 +699,23 @@ static ssize_t read_current_calls(struct bt_conn *conn, LOG_HEXDUMP_DBG(read_buf.data, read_buf.len, "Current calls"); } - return bt_gatt_attr_read(conn, attr, buf, len, offset, - read_buf.data, read_buf.len); + return bt_gatt_attr_read(conn, attr, buf, len, offset, read_buf.data, read_buf.len); } -static ssize_t read_ccid(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_ccid(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); LOG_DBG("Index %u: CCID 0x%02x", inst_index(inst), inst->ccid); return bt_gatt_attr_read(conn, attr, buf, len, offset, &inst->ccid, sizeof(inst->ccid)); } -static ssize_t read_status_flags(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_status_flags(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); const uint16_t status_flags_le = sys_cpu_to_le16(inst->optional_opcodes); LOG_DBG("Index %u: status_flags 0x%04x", inst_index(inst), inst->status_flags); @@ -744,22 +724,19 @@ static ssize_t read_status_flags(struct bt_conn *conn, sizeof(status_flags_le)); } -static void status_flags_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void status_flags_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_incoming_uri(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, - uint16_t offset) +static ssize_t read_incoming_uri(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); const struct bt_tbs_in_uri *inc_call_target; size_t val_len; @@ -774,28 +751,24 @@ static ssize_t read_incoming_uri(struct bt_conn *conn, return bt_gatt_attr_read(conn, attr, buf, len, offset, NULL, 0); } - val_len = sizeof(inc_call_target->call_index) + - strlen(inc_call_target->uri); + val_len = sizeof(inc_call_target->call_index) + strlen(inc_call_target->uri); - return bt_gatt_attr_read(conn, attr, buf, len, offset, - inc_call_target, val_len); + return bt_gatt_attr_read(conn, attr, buf, len, offset, inc_call_target, val_len); } -static void incoming_uri_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void incoming_uri_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_call_state(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_call_state(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); LOG_DBG("Index %u", inst_index(inst)); @@ -805,14 +778,12 @@ static ssize_t read_call_state(struct bt_conn *conn, LOG_HEXDUMP_DBG(read_buf.data, read_buf.len, "Call state"); } - return bt_gatt_attr_read(conn, attr, buf, len, offset, - read_buf.data, read_buf.len); + return bt_gatt_attr_read(conn, attr, buf, len, offset, read_buf.data, read_buf.len); } -static void call_state_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void call_state_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - struct service_inst *inst = lookup_inst_by_attr(attr); + struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); @@ -820,14 +791,11 @@ static void call_state_cfg_changed(const struct bt_gatt_attr *attr, } } -static int notify_ccp(struct bt_conn *conn, const struct bt_gatt_attr *attr, - uint8_t call_index, uint8_t opcode, uint8_t status) +static int notify_ccp(struct bt_conn *conn, const struct bt_gatt_attr *attr, uint8_t call_index, + uint8_t opcode, uint8_t status) { const struct bt_tbs_call_cp_notify ccp_not = { - .call_index = call_index, - .opcode = opcode, - .status = status - }; + .call_index = call_index, .opcode = opcode, .status = status}; LOG_DBG("Notifying CCP: Call index %u, %s opcode and status %s", call_index, bt_tbs_opcode_str(opcode), bt_tbs_status_str(status)); @@ -835,8 +803,7 @@ static int notify_ccp(struct bt_conn *conn, const struct bt_gatt_attr *attr, return bt_gatt_notify(conn, attr, &ccp_not, sizeof(ccp_not)); } -static void hold_other_calls(struct tbs_service_inst *inst, - uint8_t call_index_cnt, +static void hold_other_calls(struct tbs_inst *inst, uint8_t call_index_cnt, const uint8_t *call_indexes) { held_calls_cnt = 0; @@ -861,15 +828,13 @@ static void hold_other_calls(struct tbs_service_inst *inst, inst->calls[i].state = BT_TBS_CALL_STATE_LOCALLY_HELD; held_calls[held_calls_cnt++] = &inst->calls[i]; } else if (call_state == BT_TBS_CALL_STATE_REMOTELY_HELD) { - inst->calls[i].state = - BT_TBS_CALL_STATE_LOCALLY_AND_REMOTELY_HELD; + inst->calls[i].state = BT_TBS_CALL_STATE_LOCALLY_AND_REMOTELY_HELD; held_calls[held_calls_cnt++] = &inst->calls[i]; } } } -static uint8_t accept_call(struct tbs_service_inst *inst, - const struct bt_tbs_call_cp_acc *ccp) +static uint8_t accept_call(struct tbs_inst *inst, const struct bt_tbs_call_cp_acc *ccp) { struct bt_tbs_call *call = lookup_call_in_inst(inst, ccp->call_index); @@ -888,8 +853,7 @@ static uint8_t accept_call(struct tbs_service_inst *inst, } } -static uint8_t terminate_call(struct tbs_service_inst *inst, - const struct bt_tbs_call_cp_term *ccp, +static uint8_t terminate_call(struct tbs_inst *inst, const struct bt_tbs_call_cp_term *ccp, uint8_t reason) { struct bt_tbs_call *call = lookup_call_in_inst(inst, ccp->call_index); @@ -901,15 +865,21 @@ static uint8_t terminate_call(struct tbs_service_inst *inst, call_free(call); tbs_set_terminate_reason(inst, ccp->call_index, reason); + if (!inst_is_gtbs(inst)) { + /* If the instance is different than the GTBS we set the termination reason and + * notify on the GTBS instance as well + */ + tbs_set_terminate_reason(>bs_inst, ccp->call_index, reason); + } + return BT_TBS_RESULT_CODE_SUCCESS; } -static uint8_t tbs_hold_call(struct tbs_service_inst *inst, - const struct bt_tbs_call_cp_hold *ccp) +static uint8_t tbs_hold_call(struct tbs_inst *inst, const struct bt_tbs_call_cp_hold *ccp) { struct bt_tbs_call *call = lookup_call_in_inst(inst, ccp->call_index); - if ((inst->inst.optional_opcodes & BT_TBS_FEATURE_HOLD) == 0) { + if ((inst->optional_opcodes & BT_TBS_FEATURE_HOLD) == 0) { return BT_TBS_RESULT_CODE_OPCODE_NOT_SUPPORTED; } @@ -930,12 +900,11 @@ static uint8_t tbs_hold_call(struct tbs_service_inst *inst, return BT_TBS_RESULT_CODE_SUCCESS; } -static uint8_t retrieve_call(struct tbs_service_inst *inst, - const struct bt_tbs_call_cp_retrieve *ccp) +static uint8_t retrieve_call(struct tbs_inst *inst, const struct bt_tbs_call_cp_retrieve *ccp) { struct bt_tbs_call *call = lookup_call_in_inst(inst, ccp->call_index); - if ((inst->inst.optional_opcodes & BT_TBS_FEATURE_HOLD) == 0) { + if ((inst->optional_opcodes & BT_TBS_FEATURE_HOLD) == 0) { return BT_TBS_RESULT_CODE_OPCODE_NOT_SUPPORTED; } @@ -956,8 +925,7 @@ static uint8_t retrieve_call(struct tbs_service_inst *inst, return BT_TBS_RESULT_CODE_SUCCESS; } -static int originate_call(struct tbs_service_inst *inst, - const struct bt_tbs_call_cp_originate *ccp, +static int originate_call(struct tbs_inst *inst, const struct bt_tbs_call_cp_originate *ccp, uint16_t uri_len, uint8_t *call_index) { struct bt_tbs_call *call; @@ -992,14 +960,13 @@ static int originate_call(struct tbs_service_inst *inst, return BT_TBS_RESULT_CODE_SUCCESS; } -static uint8_t join_calls(struct tbs_service_inst *inst, - const struct bt_tbs_call_cp_join *ccp, +static uint8_t join_calls(struct tbs_inst *inst, const struct bt_tbs_call_cp_join *ccp, uint16_t call_index_cnt) { struct bt_tbs_call *joined_calls[CONFIG_BT_TBS_MAX_CALLS]; uint8_t call_state; - if ((inst->inst.optional_opcodes & BT_TBS_FEATURE_JOIN) == 0) { + if ((inst->optional_opcodes & BT_TBS_FEATURE_JOIN) == 0) { return BT_TBS_RESULT_CODE_OPCODE_NOT_SUPPORTED; } @@ -1019,8 +986,7 @@ static uint8_t join_calls(struct tbs_service_inst *inst, /* Validate that all calls are in a joinable state */ for (int i = 0; i < call_index_cnt; i++) { - joined_calls[i] = lookup_call_in_inst(inst, - ccp->call_indexes[i]); + joined_calls[i] = lookup_call_in_inst(inst, ccp->call_indexes[i]); if (joined_calls[i] == NULL) { return BT_TBS_RESULT_CODE_INVALID_CALL_INDEX; } @@ -1044,10 +1010,8 @@ static uint8_t join_calls(struct tbs_service_inst *inst, if (call_state == BT_TBS_CALL_STATE_LOCALLY_HELD) { joined_calls[i]->state = BT_TBS_CALL_STATE_ACTIVE; - } else if (call_state == - BT_TBS_CALL_STATE_LOCALLY_AND_REMOTELY_HELD) { - joined_calls[i]->state = - BT_TBS_CALL_STATE_REMOTELY_HELD; + } else if (call_state == BT_TBS_CALL_STATE_LOCALLY_AND_REMOTELY_HELD) { + joined_calls[i]->state = BT_TBS_CALL_STATE_REMOTELY_HELD; } else if (call_state == BT_TBS_CALL_STATE_INCOMING) { joined_calls[i]->state = BT_TBS_CALL_STATE_ACTIVE; } @@ -1059,7 +1023,7 @@ static uint8_t join_calls(struct tbs_service_inst *inst, return BT_TBS_RESULT_CODE_SUCCESS; } -static void notify_app(struct bt_conn *conn, struct tbs_service_inst *inst, uint16_t len, +static void notify_app(struct bt_conn *conn, struct tbs_inst *inst, uint16_t len, const union bt_tbs_call_cp_t *ccp, uint8_t status, uint8_t call_index) { if (tbs_cbs == NULL) { @@ -1074,8 +1038,7 @@ static void notify_app(struct bt_conn *conn, struct tbs_service_inst *inst, uint break; case BT_TBS_CALL_OPCODE_TERMINATE: if (tbs_cbs->terminate_call != NULL) { - tbs_cbs->terminate_call(conn, call_index, - inst->terminate_reason.reason); + tbs_cbs->terminate_call(conn, call_index, inst->terminate_reason.reason); } break; case BT_TBS_CALL_OPCODE_HOLD: @@ -1088,8 +1051,7 @@ static void notify_app(struct bt_conn *conn, struct tbs_service_inst *inst, uint tbs_cbs->retrieve_call(conn, call_index); } break; - case BT_TBS_CALL_OPCODE_ORIGINATE: - { + case BT_TBS_CALL_OPCODE_ORIGINATE: { char uri[CONFIG_BT_TBS_MAX_URI_LENGTH + 1]; const uint16_t uri_len = len - sizeof(ccp->originate); bool remote_party_alerted = false; @@ -1105,18 +1067,14 @@ static void notify_app(struct bt_conn *conn, struct tbs_service_inst *inst, uint (void)memcpy(uri, ccp->originate.uri, uri_len); uri[uri_len] = '\0'; if (tbs_cbs->originate_call != NULL) { - remote_party_alerted = tbs_cbs->originate_call(conn, - call_index, - uri); + remote_party_alerted = tbs_cbs->originate_call(conn, call_index, uri); } if (remote_party_alerted) { call->state = BT_TBS_CALL_STATE_ALERTING; } else { const struct bt_tbs_call_cp_term term = { - .call_index = call_index, - .opcode = BT_TBS_CALL_OPCODE_TERMINATE - }; + .call_index = call_index, .opcode = BT_TBS_CALL_OPCODE_TERMINATE}; /* Terminate and remove call */ terminate_call(inst, &term, BT_TBS_REASON_CALL_FAILED); @@ -1126,14 +1084,12 @@ static void notify_app(struct bt_conn *conn, struct tbs_service_inst *inst, uint break; } - case BT_TBS_CALL_OPCODE_JOIN: - { + case BT_TBS_CALL_OPCODE_JOIN: { const uint16_t call_index_cnt = len - sizeof(ccp->join); /* Let the app know about joined calls */ if (tbs_cbs->join_calls != NULL) { - tbs_cbs->join_calls(conn, call_index_cnt, - ccp->join.call_indexes); + tbs_cbs->join_calls(conn, call_index_cnt, ccp->join.call_indexes); } break; } @@ -1149,14 +1105,12 @@ static void notify_app(struct bt_conn *conn, struct tbs_service_inst *inst, uint } } -static ssize_t write_call_cp(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - const void *buf, uint16_t len, - uint16_t offset, uint8_t flags) +static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf, + uint16_t len, uint16_t offset, uint8_t flags) { - struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); const union bt_tbs_call_cp_t *ccp = (union bt_tbs_call_cp_t *)buf; - struct tbs_service_inst *tbs = NULL; + struct tbs_inst *tbs = NULL; uint8_t status; uint8_t call_index = 0; const bool is_gtbs = inst_is_gtbs(inst); @@ -1173,8 +1127,8 @@ static ssize_t write_call_cp(struct bt_conn *conn, return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN); } - LOG_DBG("Index %u: Processing the %s opcode", - inst_index(inst), bt_tbs_opcode_str(ccp->opcode)); + LOG_DBG("Index %u: Processing the %s opcode", inst_index(inst), + bt_tbs_opcode_str(ccp->opcode)); switch (ccp->opcode) { case BT_TBS_CALL_OPCODE_ACCEPT: @@ -1191,7 +1145,7 @@ static ssize_t write_call_cp(struct bt_conn *conn, break; } } else { - tbs = CONTAINER_OF(inst, struct tbs_service_inst, inst); + tbs = inst; } status = accept_call(tbs, &ccp->accept); @@ -1210,7 +1164,7 @@ static ssize_t write_call_cp(struct bt_conn *conn, break; } } else { - tbs = CONTAINER_OF(inst, struct tbs_service_inst, inst); + tbs = inst; } status = terminate_call(tbs, &ccp->terminate, BT_TBS_REASON_CLIENT_TERMINATED); @@ -1229,7 +1183,7 @@ static ssize_t write_call_cp(struct bt_conn *conn, break; } } else { - tbs = CONTAINER_OF(inst, struct tbs_service_inst, inst); + tbs = inst; } status = tbs_hold_call(tbs, &ccp->hold); @@ -1248,13 +1202,12 @@ static ssize_t write_call_cp(struct bt_conn *conn, break; } } else { - tbs = CONTAINER_OF(inst, struct tbs_service_inst, inst); + tbs = inst; } status = retrieve_call(tbs, &ccp->retrieve); break; - case BT_TBS_CALL_OPCODE_ORIGINATE: - { + case BT_TBS_CALL_OPCODE_ORIGINATE: { const uint16_t uri_len = len - sizeof(ccp->originate); if (len < sizeof(ccp->originate) + BT_TBS_MIN_URI_LEN) { @@ -1264,22 +1217,17 @@ static ssize_t write_call_cp(struct bt_conn *conn, if (is_gtbs) { tbs = lookup_inst_by_uri_scheme(ccp->originate.uri, uri_len); if (tbs == NULL) { - /* TODO: Couldn't find fitting TBS instance; - * use the first. If we want to be - * restrictive about URIs, return - * Invalid Caller ID instead - */ - tbs = &svc_insts[0]; + status = BT_TBS_RESULT_CODE_INVALID_URI; + break; } } else { - tbs = CONTAINER_OF(inst, struct tbs_service_inst, inst); + tbs = inst; } status = originate_call(tbs, &ccp->originate, uri_len, &call_index); break; } - case BT_TBS_CALL_OPCODE_JOIN: - { + case BT_TBS_CALL_OPCODE_JOIN: { const uint16_t call_index_cnt = len - sizeof(ccp->join); if (len < sizeof(ccp->join) + 1) { /* at least 1 call index */ @@ -1295,7 +1243,7 @@ static ssize_t write_call_cp(struct bt_conn *conn, break; } } else { - tbs = CONTAINER_OF(inst, struct tbs_service_inst, inst); + tbs = inst; } status = join_calls(tbs, &ccp->join, call_index_cnt); @@ -1342,18 +1290,17 @@ static ssize_t write_call_cp(struct bt_conn *conn, static void call_cp_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_optional_opcodes(struct bt_conn *conn, - const struct bt_gatt_attr *attr, +static ssize_t read_optional_opcodes(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); const uint16_t optional_opcodes_le = sys_cpu_to_le16(inst->optional_opcodes); LOG_DBG("Index %u: Supported opcodes 0x%02x", inst_index(inst), inst->optional_opcodes); @@ -1362,59 +1309,53 @@ static ssize_t read_optional_opcodes(struct bt_conn *conn, sizeof(optional_opcodes_le)); } -static void terminate_reason_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void terminate_reason_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_friendly_name(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_friendly_name(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); const struct bt_tbs_in_uri *friendly_name = &inst->friendly_name; size_t val_len; - LOG_DBG("Index: 0x%02x call index 0x%02x, URI %s", - inst_index(inst), friendly_name->call_index, friendly_name->uri); + LOG_DBG("Index: 0x%02x call index 0x%02x, URI %s", inst_index(inst), + friendly_name->call_index, friendly_name->uri); if (friendly_name->call_index == BT_TBS_FREE_CALL_INDEX) { LOG_DBG("URI not set"); return bt_gatt_attr_read(conn, attr, buf, len, offset, NULL, 0); } - val_len = sizeof(friendly_name->call_index) + - strlen(friendly_name->uri); + val_len = sizeof(friendly_name->call_index) + strlen(friendly_name->uri); - return bt_gatt_attr_read(conn, attr, buf, len, offset, - friendly_name, val_len); + return bt_gatt_attr_read(conn, attr, buf, len, offset, friendly_name, val_len); } -static void friendly_name_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void friendly_name_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -static ssize_t read_incoming_call(struct bt_conn *conn, - const struct bt_gatt_attr *attr, - void *buf, uint16_t len, uint16_t offset) +static ssize_t read_incoming_call(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf, + uint16_t len, uint16_t offset) { - const struct service_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); + const struct tbs_inst *inst = BT_AUDIO_CHRC_USER_DATA(attr); const struct bt_tbs_in_uri *remote_uri = &inst->in_call; size_t val_len; - LOG_DBG("Index: 0x%02x call index 0x%02x, URI %s", - inst_index(inst), remote_uri->call_index, remote_uri->uri); + LOG_DBG("Index: 0x%02x call index 0x%02x, URI %s", inst_index(inst), remote_uri->call_index, + remote_uri->uri); if (remote_uri->call_index == BT_TBS_FREE_CALL_INDEX) { LOG_DBG("URI not set"); @@ -1424,159 +1365,116 @@ static ssize_t read_incoming_call(struct bt_conn *conn, val_len = sizeof(remote_uri->call_index) + strlen(remote_uri->uri); - return bt_gatt_attr_read(conn, attr, buf, len, offset, - remote_uri, val_len); + return bt_gatt_attr_read(conn, attr, buf, len, offset, remote_uri, val_len); } -static void in_call_cfg_changed(const struct bt_gatt_attr *attr, - uint16_t value) +static void in_call_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value) { - const struct service_inst *inst = lookup_inst_by_attr(attr); + const struct tbs_inst *inst = lookup_inst_by_attr(attr); if (inst != NULL) { LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value); } } -#define BT_TBS_CHR_PROVIDER_NAME(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_PROVIDER_NAME, \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_provider_name, NULL, inst), \ - BT_AUDIO_CCC(provider_name_cfg_changed) - -#define BT_TBS_CHR_UCI(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_UCI, \ - BT_GATT_CHRC_READ, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_uci, NULL, inst) - -#define BT_TBS_CHR_TECHNOLOGY(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_TECHNOLOGY, \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_technology, NULL, inst), \ - BT_AUDIO_CCC(technology_cfg_changed) - -#define BT_TBS_CHR_URI_LIST(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_URI_LIST, \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_uri_scheme_list, NULL, inst), \ - BT_AUDIO_CCC(uri_scheme_list_cfg_changed) - -#define BT_TBS_CHR_SIGNAL_STRENGTH(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_SIGNAL_STRENGTH, /* Optional */ \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_signal_strength, NULL, inst), \ - BT_AUDIO_CCC(signal_strength_cfg_changed) - -#define BT_TBS_CHR_SIGNAL_INTERVAL(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_SIGNAL_INTERVAL, /* Conditional */ \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, \ - BT_GATT_PERM_READ_ENCRYPT | BT_GATT_PERM_WRITE_ENCRYPT, \ +#define BT_TBS_CHR_PROVIDER_NAME(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_PROVIDER_NAME, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, read_provider_name, NULL, inst), \ + BT_AUDIO_CCC(provider_name_cfg_changed) + +#define BT_TBS_CHR_UCI(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_UCI, BT_GATT_CHRC_READ, BT_GATT_PERM_READ_ENCRYPT, read_uci, \ + NULL, inst) + +#define BT_TBS_CHR_TECHNOLOGY(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_TECHNOLOGY, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, read_technology, NULL, inst), \ + BT_AUDIO_CCC(technology_cfg_changed) + +#define BT_TBS_CHR_URI_LIST(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_URI_LIST, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, read_uri_scheme_list, NULL, inst), \ + BT_AUDIO_CCC(uri_scheme_list_cfg_changed) + +#define BT_TBS_CHR_SIGNAL_STRENGTH(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_SIGNAL_STRENGTH, /* Optional */ \ + BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, BT_GATT_PERM_READ_ENCRYPT, \ + read_signal_strength, NULL, inst), \ + BT_AUDIO_CCC(signal_strength_cfg_changed) + +#define BT_TBS_CHR_SIGNAL_INTERVAL(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_SIGNAL_INTERVAL, /* Conditional */ \ + BT_GATT_CHRC_READ | BT_GATT_CHRC_WRITE | BT_GATT_CHRC_WRITE_WITHOUT_RESP, \ + BT_GATT_PERM_READ_ENCRYPT | BT_GATT_PERM_WRITE_ENCRYPT, \ read_signal_strength_interval, write_signal_strength_interval, inst) -#define BT_TBS_CHR_CURRENT_CALLS(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_LIST_CURRENT_CALLS, \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_current_calls, NULL, inst), \ - BT_AUDIO_CCC(current_calls_cfg_changed) - -#define BT_TBS_CHR_CCID(inst) \ - BT_AUDIO_CHRC(BT_UUID_CCID, \ - BT_GATT_CHRC_READ, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_ccid, NULL, inst) - -#define BT_TBS_CHR_STATUS_FLAGS(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_STATUS_FLAGS, \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_status_flags, NULL, inst), \ - BT_AUDIO_CCC(status_flags_cfg_changed) - -#define BT_TBS_CHR_INCOMING_URI(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_INCOMING_URI, /* Optional */ \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_incoming_uri, NULL, inst), \ - BT_AUDIO_CCC(incoming_uri_cfg_changed) - -#define BT_TBS_CHR_CALL_STATE(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_CALL_STATE, \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_call_state, NULL, inst), \ - BT_AUDIO_CCC(call_state_cfg_changed) - -#define BT_TBS_CHR_CONTROL_POINT(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_CALL_CONTROL_POINT, \ - BT_GATT_CHRC_WRITE | BT_GATT_CHRC_NOTIFY | BT_GATT_CHRC_WRITE_WITHOUT_RESP, \ - BT_GATT_PERM_WRITE_ENCRYPT, \ - NULL, write_call_cp, inst), \ - BT_AUDIO_CCC(call_cp_cfg_changed) - -#define BT_TBS_CHR_OPTIONAL_OPCODES(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_OPTIONAL_OPCODES, \ - BT_GATT_CHRC_READ, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_optional_opcodes, NULL, inst) \ - -#define BT_TBS_CHR_TERMINATE_REASON(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_TERMINATE_REASON, \ - BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - NULL, NULL, inst), \ - BT_AUDIO_CCC(terminate_reason_cfg_changed) - -#define BT_TBS_CHR_INCOMING_CALL(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_INCOMING_CALL, \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_incoming_call, NULL, inst), \ - BT_AUDIO_CCC(in_call_cfg_changed) - -#define BT_TBS_CHR_FRIENDLY_NAME(inst) \ - BT_AUDIO_CHRC(BT_UUID_TBS_FRIENDLY_NAME, /* Optional */ \ - BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ - BT_GATT_PERM_READ_ENCRYPT, \ - read_friendly_name, NULL, inst), \ - BT_AUDIO_CCC(friendly_name_cfg_changed) +#define BT_TBS_CHR_CURRENT_CALLS(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_LIST_CURRENT_CALLS, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, read_current_calls, NULL, inst), \ + BT_AUDIO_CCC(current_calls_cfg_changed) + +#define BT_TBS_CHR_CCID(inst) \ + BT_AUDIO_CHRC(BT_UUID_CCID, BT_GATT_CHRC_READ, BT_GATT_PERM_READ_ENCRYPT, read_ccid, NULL, \ + inst) + +#define BT_TBS_CHR_STATUS_FLAGS(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_STATUS_FLAGS, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, read_status_flags, NULL, inst), \ + BT_AUDIO_CCC(status_flags_cfg_changed) + +#define BT_TBS_CHR_INCOMING_URI(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_INCOMING_URI, /* Optional */ \ + BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, BT_GATT_PERM_READ_ENCRYPT, \ + read_incoming_uri, NULL, inst), \ + BT_AUDIO_CCC(incoming_uri_cfg_changed) + +#define BT_TBS_CHR_CALL_STATE(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_CALL_STATE, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, read_call_state, NULL, inst), \ + BT_AUDIO_CCC(call_state_cfg_changed) + +#define BT_TBS_CHR_CONTROL_POINT(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_CALL_CONTROL_POINT, \ + BT_GATT_CHRC_WRITE | BT_GATT_CHRC_NOTIFY | BT_GATT_CHRC_WRITE_WITHOUT_RESP, \ + BT_GATT_PERM_WRITE_ENCRYPT, NULL, write_call_cp, inst), \ + BT_AUDIO_CCC(call_cp_cfg_changed) + +#define BT_TBS_CHR_OPTIONAL_OPCODES(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_OPTIONAL_OPCODES, BT_GATT_CHRC_READ, BT_GATT_PERM_READ_ENCRYPT, \ + read_optional_opcodes, NULL, inst) + +#define BT_TBS_CHR_TERMINATE_REASON(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_TERMINATE_REASON, BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, NULL, NULL, inst), \ + BT_AUDIO_CCC(terminate_reason_cfg_changed) + +#define BT_TBS_CHR_INCOMING_CALL(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_INCOMING_CALL, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, \ + BT_GATT_PERM_READ_ENCRYPT, read_incoming_call, NULL, inst), \ + BT_AUDIO_CCC(in_call_cfg_changed) + +#define BT_TBS_CHR_FRIENDLY_NAME(inst) \ + BT_AUDIO_CHRC(BT_UUID_TBS_FRIENDLY_NAME, /* Optional */ \ + BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY, BT_GATT_PERM_READ_ENCRYPT, \ + read_friendly_name, NULL, inst), \ + BT_AUDIO_CCC(friendly_name_cfg_changed) #define BT_TBS_SERVICE_DEFINE(_uuid, _inst) \ - BT_GATT_PRIMARY_SERVICE(_uuid), \ - BT_TBS_CHR_PROVIDER_NAME(_inst), \ - BT_TBS_CHR_UCI(_inst), \ - BT_TBS_CHR_TECHNOLOGY(_inst), \ - BT_TBS_CHR_URI_LIST(_inst), \ - BT_TBS_CHR_SIGNAL_STRENGTH(_inst), \ - BT_TBS_CHR_SIGNAL_INTERVAL(_inst), \ - BT_TBS_CHR_CURRENT_CALLS(_inst), \ - BT_TBS_CHR_CCID(_inst), \ - BT_TBS_CHR_STATUS_FLAGS(_inst), \ - BT_TBS_CHR_INCOMING_URI(_inst), \ - BT_TBS_CHR_CALL_STATE(_inst), \ - BT_TBS_CHR_CONTROL_POINT(_inst), \ - BT_TBS_CHR_OPTIONAL_OPCODES(_inst), \ - BT_TBS_CHR_TERMINATE_REASON(_inst), \ - BT_TBS_CHR_INCOMING_CALL(_inst), \ - BT_TBS_CHR_FRIENDLY_NAME(_inst) - -#define BT_TBS_SERVICE_DEFINITION(_inst) { BT_TBS_SERVICE_DEFINE(BT_UUID_TBS, &(_inst).inst) } - -/* - * Defining this as extern make it possible to link code that otherwise would - * give "unknown identifier" linking errors. - */ -extern const struct bt_gatt_service_static gtbs_svc; + BT_GATT_PRIMARY_SERVICE(_uuid), BT_TBS_CHR_PROVIDER_NAME(_inst), BT_TBS_CHR_UCI(_inst), \ + BT_TBS_CHR_TECHNOLOGY(_inst), BT_TBS_CHR_URI_LIST(_inst), \ + BT_TBS_CHR_SIGNAL_STRENGTH(_inst), BT_TBS_CHR_SIGNAL_INTERVAL(_inst), \ + BT_TBS_CHR_CURRENT_CALLS(_inst), BT_TBS_CHR_CCID(_inst), \ + BT_TBS_CHR_STATUS_FLAGS(_inst), BT_TBS_CHR_INCOMING_URI(_inst), \ + BT_TBS_CHR_CALL_STATE(_inst), BT_TBS_CHR_CONTROL_POINT(_inst), \ + BT_TBS_CHR_OPTIONAL_OPCODES(_inst), BT_TBS_CHR_TERMINATE_REASON(_inst), \ + BT_TBS_CHR_INCOMING_CALL(_inst), BT_TBS_CHR_FRIENDLY_NAME(_inst) + +#define BT_TBS_SERVICE_DEFINITION(_inst) \ + { \ + BT_TBS_SERVICE_DEFINE(BT_UUID_TBS, &(_inst)) \ + } -/* TODO: Can we make the multiple service instance more generic? */ -#if CONFIG_BT_GTBS -BT_GATT_SERVICE_DEFINE(gtbs_svc, BT_TBS_SERVICE_DEFINE(BT_UUID_GTBS, >bs_inst.inst)); -#endif /* CONFIG_BT_GTBS */ +BT_GATT_SERVICE_DEFINE(gtbs_svc, BT_TBS_SERVICE_DEFINE(BT_UUID_GTBS, >bs_inst)); BT_GATT_SERVICE_INSTANCE_DEFINE(tbs_service_list, svc_insts, CONFIG_BT_TBS_BEARER_COUNT, BT_TBS_SERVICE_DEFINITION); @@ -1584,8 +1482,7 @@ BT_GATT_SERVICE_INSTANCE_DEFINE(tbs_service_list, svc_insts, CONFIG_BT_TBS_BEARE static void signal_interval_timeout(struct k_work *work) { struct k_work_delayable *dwork = k_work_delayable_from_work(work); - struct service_inst *inst = CONTAINER_OF(dwork, struct service_inst, - reporting_interval_work); + struct tbs_inst *inst = CONTAINER_OF(dwork, struct tbs_inst, reporting_interval_work); if (!inst->pending_signal_strength_notification) { return; @@ -1602,7 +1499,7 @@ static void signal_interval_timeout(struct k_work *work) inst->pending_signal_strength_notification = false; } -static void tbs_inst_init(struct service_inst *inst, const struct bt_gatt_attr *attrs, +static void tbs_inst_init(struct tbs_inst *inst, const struct bt_gatt_attr *attrs, size_t attr_count, const char *provider_name) { LOG_DBG("inst %p index 0x%02x provider_name %s", inst, inst_index(inst), provider_name); @@ -1620,22 +1517,23 @@ static void tbs_inst_init(struct service_inst *inst, const struct bt_gatt_attr * k_work_init_delayable(&inst->reporting_interval_work, signal_interval_timeout); } -static void gtbs_service_inst_init(struct gtbs_service_inst *inst, +static void gtbs_service_inst_init(struct tbs_inst *inst, const struct bt_gatt_service_static *service) { - tbs_inst_init(&inst->inst, service->attrs, service->attr_count, "Generic TBS"); + tbs_inst_init(inst, service->attrs, service->attr_count, "Generic TBS"); } -static void tbs_service_inst_init(struct tbs_service_inst *inst, struct bt_gatt_service *service) +static void tbs_service_inst_init(struct tbs_inst *inst, struct bt_gatt_service *service) { - tbs_inst_init(&inst->inst, service->attrs, service->attr_count, - CONFIG_BT_TBS_PROVIDER_NAME); + tbs_inst_init(inst, service->attrs, service->attr_count, CONFIG_BT_TBS_PROVIDER_NAME); (void)utf8_lcpy(inst->uri_scheme_list, CONFIG_BT_TBS_URI_SCHEMES_LIST, sizeof(inst->uri_scheme_list)); } static int bt_tbs_init(void) { + gtbs_service_inst_init(>bs_inst, >bs_svc); + for (size_t i = 0; i < ARRAY_SIZE(svc_insts); i++) { int err; @@ -1647,10 +1545,6 @@ static int bt_tbs_init(void) tbs_service_inst_init(&svc_insts[i], &tbs_service_list[i]); } - if (IS_ENABLED(CONFIG_BT_GTBS)) { - gtbs_service_inst_init(>bs_inst, >bs_svc); - } - return 0; } @@ -1659,12 +1553,10 @@ SYS_INIT(bt_tbs_init, APPLICATION, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); /***************************** Profile API *****************************/ int bt_tbs_accept(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); int status = -EINVAL; - const struct bt_tbs_call_cp_acc ccp = { - .call_index = call_index, - .opcode = BT_TBS_CALL_OPCODE_ACCEPT - }; + const struct bt_tbs_call_cp_acc ccp = {.call_index = call_index, + .opcode = BT_TBS_CALL_OPCODE_ACCEPT}; if (inst != NULL) { status = accept_call(inst, &ccp); @@ -1679,12 +1571,10 @@ int bt_tbs_accept(uint8_t call_index) int bt_tbs_hold(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); int status = -EINVAL; - const struct bt_tbs_call_cp_hold ccp = { - .call_index = call_index, - .opcode = BT_TBS_CALL_OPCODE_HOLD - }; + const struct bt_tbs_call_cp_hold ccp = {.call_index = call_index, + .opcode = BT_TBS_CALL_OPCODE_HOLD}; if (inst != NULL) { status = tbs_hold_call(inst, &ccp); @@ -1697,12 +1587,10 @@ int bt_tbs_hold(uint8_t call_index) int bt_tbs_retrieve(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); int status = -EINVAL; - const struct bt_tbs_call_cp_retrieve ccp = { - .call_index = call_index, - .opcode = BT_TBS_CALL_OPCODE_RETRIEVE - }; + const struct bt_tbs_call_cp_retrieve ccp = {.call_index = call_index, + .opcode = BT_TBS_CALL_OPCODE_RETRIEVE}; if (inst != NULL) { status = retrieve_call(inst, &ccp); @@ -1715,16 +1603,13 @@ int bt_tbs_retrieve(uint8_t call_index) int bt_tbs_terminate(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); int status = -EINVAL; - const struct bt_tbs_call_cp_term ccp = { - .call_index = call_index, - .opcode = BT_TBS_CALL_OPCODE_TERMINATE - }; + const struct bt_tbs_call_cp_term ccp = {.call_index = call_index, + .opcode = BT_TBS_CALL_OPCODE_TERMINATE}; if (inst != NULL) { - status = terminate_call(inst, &ccp, - BT_TBS_REASON_SERVER_ENDED_CALL); + status = terminate_call(inst, &ccp, BT_TBS_REASON_SERVER_ENDED_CALL); } notify_calls(inst); @@ -1732,18 +1617,15 @@ int bt_tbs_terminate(uint8_t call_index) return status; } -int bt_tbs_originate(uint8_t bearer_index, char *remote_uri, - uint8_t *call_index) +int bt_tbs_originate(uint8_t bearer_index, char *remote_uri, uint8_t *call_index) { - struct service_inst *tbs = inst_lookup_index(bearer_index); - struct tbs_service_inst *inst; - uint8_t buf[CONFIG_BT_TBS_MAX_URI_LENGTH + - sizeof(struct bt_tbs_call_cp_originate)]; - struct bt_tbs_call_cp_originate *ccp = - (struct bt_tbs_call_cp_originate *)buf; + struct tbs_inst *tbs = inst_lookup_index(bearer_index); + uint8_t buf[CONFIG_BT_TBS_MAX_URI_LENGTH + sizeof(struct bt_tbs_call_cp_originate)]; + struct bt_tbs_call_cp_originate *ccp = (struct bt_tbs_call_cp_originate *)buf; size_t uri_len; - if (tbs == NULL || inst_is_gtbs(tbs)) { + if (tbs == NULL) { + LOG_DBG("Could not find TBS instance from index %u", bearer_index); return -EINVAL; } else if (!bt_tbs_valid_uri((uint8_t *)remote_uri, strlen(remote_uri))) { LOG_DBG("Invalid URI %s", remote_uri); @@ -1752,19 +1634,16 @@ int bt_tbs_originate(uint8_t bearer_index, char *remote_uri, uri_len = strlen(remote_uri); - inst = CONTAINER_OF(tbs, struct tbs_service_inst, inst); - ccp->opcode = BT_TBS_CALL_OPCODE_ORIGINATE; (void)memcpy(ccp->uri, remote_uri, uri_len); - return originate_call(inst, ccp, uri_len, call_index); + return originate_call(tbs, ccp, uri_len, call_index); } int bt_tbs_join(uint8_t call_index_cnt, uint8_t *call_indexes) { - struct tbs_service_inst *inst; - uint8_t buf[CONFIG_BT_TBS_MAX_CALLS + - sizeof(struct bt_tbs_call_cp_join)]; + struct tbs_inst *inst; + uint8_t buf[CONFIG_BT_TBS_MAX_CALLS + sizeof(struct bt_tbs_call_cp_join)]; struct bt_tbs_call_cp_join *ccp = (struct bt_tbs_call_cp_join *)buf; int status = -EINVAL; @@ -1777,7 +1656,7 @@ int bt_tbs_join(uint8_t call_index_cnt, uint8_t *call_indexes) if (inst != NULL) { ccp->opcode = BT_TBS_CALL_OPCODE_JOIN; (void)memcpy(ccp->call_indexes, call_indexes, - MIN(call_index_cnt, CONFIG_BT_TBS_MAX_CALLS)); + MIN(call_index_cnt, CONFIG_BT_TBS_MAX_CALLS)); status = join_calls(inst, ccp, call_index_cnt); } @@ -1787,7 +1666,7 @@ int bt_tbs_join(uint8_t call_index_cnt, uint8_t *call_indexes) int bt_tbs_remote_answer(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); struct bt_tbs_call *call; if (inst == NULL) { @@ -1811,7 +1690,7 @@ int bt_tbs_remote_answer(uint8_t call_index) int bt_tbs_remote_hold(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); struct bt_tbs_call *call; uint8_t status; @@ -1844,7 +1723,7 @@ int bt_tbs_remote_hold(uint8_t call_index) int bt_tbs_remote_retrieve(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); struct bt_tbs_call *call; int status; @@ -1877,16 +1756,13 @@ int bt_tbs_remote_retrieve(uint8_t call_index) int bt_tbs_remote_terminate(uint8_t call_index) { - struct tbs_service_inst *inst = lookup_inst_by_call_index(call_index); + struct tbs_inst *inst = lookup_inst_by_call_index(call_index); int status = -EINVAL; - const struct bt_tbs_call_cp_term ccp = { - .call_index = call_index, - .opcode = BT_TBS_CALL_OPCODE_TERMINATE - }; + const struct bt_tbs_call_cp_term ccp = {.call_index = call_index, + .opcode = BT_TBS_CALL_OPCODE_TERMINATE}; if (inst != NULL) { - status = terminate_call(inst, &ccp, - BT_TBS_REASON_REMOTE_ENDED_CALL); + status = terminate_call(inst, &ccp, BT_TBS_REASON_REMOTE_ENDED_CALL); } notify_calls(inst); @@ -1894,7 +1770,7 @@ int bt_tbs_remote_terminate(uint8_t call_index) return status; } -static void tbs_inst_remote_incoming(struct service_inst *inst, const char *to, const char *from, +static void tbs_inst_remote_incoming(struct tbs_inst *inst, const char *to, const char *from, const char *friendly_name, const struct bt_tbs_call *call) { size_t local_uri_ind_len; @@ -1932,14 +1808,14 @@ static void tbs_inst_remote_incoming(struct service_inst *inst, const char *to, } } -int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, - const char *from, const char *friendly_name) +int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, const char *from, + const char *friendly_name) { - struct service_inst *inst = inst_lookup_index(bearer_index); - struct tbs_service_inst *service_inst; + struct tbs_inst *inst = inst_lookup_index(bearer_index); struct bt_tbs_call *call = NULL; - if (inst == NULL || inst_is_gtbs(inst)) { + if (inst == NULL) { + LOG_DBG("Could not find TBS instance from index %u", bearer_index); return -EINVAL; } else if (!bt_tbs_valid_uri((uint8_t *)to, strlen(to))) { LOG_DBG("Invalid \"to\" URI: %s", to); @@ -1949,22 +1825,24 @@ int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, return -EINVAL; } - service_inst = CONTAINER_OF(inst, struct tbs_service_inst, inst); - - call = call_alloc(service_inst, BT_TBS_CALL_STATE_INCOMING, (uint8_t *)from, strlen(from)); + call = call_alloc(inst, BT_TBS_CALL_STATE_INCOMING, (uint8_t *)from, strlen(from)); if (call == NULL) { return -ENOMEM; } BT_TBS_CALL_FLAG_SET_INCOMING(call->flags); + /* Notify TBS*/ tbs_inst_remote_incoming(inst, to, from, friendly_name, call); - if (IS_ENABLED(CONFIG_BT_GTBS)) { - tbs_inst_remote_incoming(>bs_inst.inst, to, from, friendly_name, call); + if (!inst_is_gtbs(inst)) { + /* If the instance is different than the GTBS we set the remote incoming and + * notify on the GTBS instance as well + */ + tbs_inst_remote_incoming(>bs_inst, to, from, friendly_name, call); } - notify_calls(service_inst); + notify_calls(inst); LOG_DBG("New call with call index %u", call->index); @@ -1973,7 +1851,7 @@ int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, int bt_tbs_set_bearer_provider_name(uint8_t bearer_index, const char *name) { - struct service_inst *inst = inst_lookup_index(bearer_index); + struct tbs_inst *inst = inst_lookup_index(bearer_index); const size_t len = strlen(name); if (len >= CONFIG_BT_TBS_MAX_PROVIDER_NAME_LENGTH || len == 0) { @@ -1995,7 +1873,7 @@ int bt_tbs_set_bearer_provider_name(uint8_t bearer_index, const char *name) int bt_tbs_set_bearer_technology(uint8_t bearer_index, uint8_t new_technology) { - struct service_inst *inst = inst_lookup_index(bearer_index); + struct tbs_inst *inst = inst_lookup_index(bearer_index); if (new_technology < BT_TBS_TECHNOLOGY_3G || new_technology > BT_TBS_TECHNOLOGY_WCDMA) { return -EINVAL; @@ -2015,10 +1893,9 @@ int bt_tbs_set_bearer_technology(uint8_t bearer_index, uint8_t new_technology) return 0; } -int bt_tbs_set_signal_strength(uint8_t bearer_index, - uint8_t new_signal_strength) +int bt_tbs_set_signal_strength(uint8_t bearer_index, uint8_t new_signal_strength) { - struct service_inst *inst = inst_lookup_index(bearer_index); + struct tbs_inst *inst = inst_lookup_index(bearer_index); uint32_t timer_status; if (new_signal_strength > BT_TBS_SIGNAL_STRENGTH_MAX && @@ -2047,7 +1924,7 @@ int bt_tbs_set_signal_strength(uint8_t bearer_index, int bt_tbs_set_status_flags(uint8_t bearer_index, uint16_t status_flags) { - struct service_inst *inst = inst_lookup_index(bearer_index); + struct tbs_inst *inst = inst_lookup_index(bearer_index); if (!BT_TBS_VALID_STATUS_FLAGS(status_flags)) { return -EINVAL; @@ -2061,19 +1938,20 @@ int bt_tbs_set_status_flags(uint8_t bearer_index, uint16_t status_flags) inst->status_flags = status_flags; - bt_gatt_notify_uuid(NULL, BT_UUID_TBS_STATUS_FLAGS, - inst->attrs, &status_flags, sizeof(status_flags)); + bt_gatt_notify_uuid(NULL, BT_UUID_TBS_STATUS_FLAGS, inst->attrs, &status_flags, + sizeof(status_flags)); return 0; } -int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, - uint8_t uri_count) +int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, uint8_t uri_count) { char uri_scheme_list[CONFIG_BT_TBS_MAX_SCHEME_LIST_LENGTH]; size_t len = 0; - struct tbs_service_inst *inst; + struct tbs_inst *inst; - if (bearer_index >= CONFIG_BT_TBS_BEARER_COUNT) { + NET_BUF_SIMPLE_DEFINE(uri_scheme_buf, READ_BUF_SIZE); + + if (bearer_index >= ARRAY_SIZE(svc_insts)) { return -EINVAL; } @@ -2083,7 +1961,7 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, for (int i = 0; i < uri_count; i++) { if (len) { len++; - if (len > sizeof(uri_scheme_list) - 1) { + if (len > sizeof(uri_scheme_list) - 1) { return -ENOMEM; } @@ -2091,7 +1969,7 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, } len += strlen(uri_list[i]); - if (len > sizeof(uri_scheme_list) - 1) { + if (len > sizeof(uri_scheme_list) - 1) { return -ENOMEM; } @@ -2109,15 +1987,16 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, LOG_DBG("TBS instance %u uri prefix list is now %s", bearer_index, inst->uri_scheme_list); - bt_gatt_notify_uuid(NULL, BT_UUID_TBS_URI_LIST, - inst->inst.attrs, &inst->uri_scheme_list, + bt_gatt_notify_uuid(NULL, BT_UUID_TBS_URI_LIST, inst->attrs, &inst->uri_scheme_list, strlen(inst->uri_scheme_list)); - if (IS_ENABLED(CONFIG_BT_GTBS)) { - NET_BUF_SIMPLE_DEFINE(uri_scheme_buf, READ_BUF_SIZE); + if (!inst_is_gtbs(inst)) { + /* If the instance is different than the GTBS notify on the GTBS instance as well */ + net_buf_simple_add_mem(&uri_scheme_buf, gtbs_inst.uri_scheme_list, + strlen(gtbs_inst.uri_scheme_list)); /* TODO: Make uri schemes unique */ - for (int i = 0; i < ARRAY_SIZE(svc_insts); i++) { + for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) { const size_t uri_len = strlen(svc_insts[i].uri_scheme_list); if (uri_scheme_buf.len + uri_len >= uri_scheme_buf.size) { @@ -2126,18 +2005,15 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, break; } - net_buf_simple_add_mem(&uri_scheme_buf, - svc_insts[i].uri_scheme_list, + net_buf_simple_add_mem(&uri_scheme_buf, svc_insts[i].uri_scheme_list, uri_len); } LOG_DBG("GTBS: URI scheme %.*s", uri_scheme_buf.len, uri_scheme_buf.data); - bt_gatt_notify_uuid(NULL, BT_UUID_TBS_URI_LIST, - inst->inst.attrs, + bt_gatt_notify_uuid(NULL, BT_UUID_TBS_URI_LIST, gtbs_inst.attrs, uri_scheme_buf.data, uri_scheme_buf.len); } - return 0; } @@ -2149,7 +2025,7 @@ void bt_tbs_register_cb(struct bt_tbs_cb *cbs) #if defined(CONFIG_BT_TBS_LOG_LEVEL_DBG) void bt_tbs_dbg_print_calls(void) { - for (int i = 0; i < CONFIG_BT_TBS_BEARER_COUNT; i++) { + for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) { LOG_DBG("Bearer #%u", i); for (int j = 0; j < ARRAY_SIZE(svc_insts[i].calls); j++) { struct bt_tbs_call *call = &svc_insts[i].calls[j]; diff --git a/tests/bluetooth/shell/audio.conf b/tests/bluetooth/shell/audio.conf index 404a04c885279bd..6998b335ea10d27 100644 --- a/tests/bluetooth/shell/audio.conf +++ b/tests/bluetooth/shell/audio.conf @@ -122,6 +122,7 @@ CONFIG_BT_MPL_TRACK_MAX_SIZE=50 # Telephone bearer service CONFIG_BT_TBS=y +CONFIG_BT_TBS_BEARER_COUNT=1 CONFIG_BT_TBS_SUPPORTED_FEATURES=3 CONFIG_BT_TBS_CLIENT_TBS=y CONFIG_BT_TBS_CLIENT_GTBS=y diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml index 129792ee63f0479..a19dfa3f4560e34 100644 --- a/tests/bluetooth/shell/testcase.yaml +++ b/tests/bluetooth/shell/testcase.yaml @@ -325,6 +325,12 @@ tests: extra_configs: - CONFIG_BT_TBS=n tags: bluetooth + bluetooth.shell.audio.only_gtbs: + extra_args: CONF_FILE="audio.conf" + build_only: true + extra_configs: + - CONFIG_BT_TBS_BEARER_COUNT=0 + tags: bluetooth bluetooth.shell.audio.no_tbs_client: extra_args: CONF_FILE="audio.conf" build_only: true diff --git a/tests/bluetooth/tester/overlay-le-audio.conf b/tests/bluetooth/tester/overlay-le-audio.conf index d0c40206f0a8c03..a4a88dd941ab694 100644 --- a/tests/bluetooth/tester/overlay-le-audio.conf +++ b/tests/bluetooth/tester/overlay-le-audio.conf @@ -25,8 +25,6 @@ CONFIG_BT_L2CAP_TX_BUF_COUNT=10 # CAP CONFIG_BT_CAP_INITIATOR=y -# To have multiple CCIDs -CONFIG_BT_TBS=y # MICP CONFIG_BT_MICP_MIC_DEV=y @@ -142,8 +140,8 @@ CONFIG_BT_MPL=y CONFIG_UTF8=y #TBS -CONFIG_BT_GTBS=y CONFIG_BT_TBS=y +CONFIG_BT_TBS_BEARER_COUNT=1 CONFIG_BT_TBS_MAX_CALLS=10 CONFIG_BT_TBS_SUPPORTED_FEATURES=3 diff --git a/tests/bluetooth/tester/src/audio/CMakeLists.txt b/tests/bluetooth/tester/src/audio/CMakeLists.txt index 38b4cac11cbe4d0..072819eeca4fe03 100644 --- a/tests/bluetooth/tester/src/audio/CMakeLists.txt +++ b/tests/bluetooth/tester/src/audio/CMakeLists.txt @@ -60,7 +60,7 @@ if(CONFIG_BT_CAP_INITIATOR) target_sources(app PRIVATE btp_cap.c) endif() -if(CONFIG_BT_TBS OR CONFIG_BT_GTBS) +if(CONFIG_BT_TBS) target_sources(app PRIVATE btp_ccp.c) endif() diff --git a/tests/bluetooth/tester/src/btp_core.c b/tests/bluetooth/tester/src/btp_core.c index f89f08c782096d2..8b1b571792d6d69 100644 --- a/tests/bluetooth/tester/src/btp_core.c +++ b/tests/bluetooth/tester/src/btp_core.c @@ -101,7 +101,7 @@ static uint8_t supported_services(const void *cmd, uint16_t cmd_len, #if defined(CONFIG_BT_HAS) tester_set_bit(rp->data, BTP_SERVICE_ID_HAP); #endif /* CONFIG_BT_HAS */ -#if defined(CONFIG_BT_TBS) || defined(CONFIG_BT_GTBS) +#if defined(CONFIG_BT_TBS) tester_set_bit(rp->data, BTP_SERVICE_ID_TBS); #endif /*CONFIG_BT_TBS */ #if defined(CONFIG_BT_TMAP) @@ -235,7 +235,7 @@ static uint8_t register_service(const void *cmd, uint16_t cmd_len, status = tester_init_hap(); break; #endif /* CONFIG_BT_HAS */ -#if defined(CONFIG_BT_TBS) || defined(CONFIG_BT_GTBS) +#if defined(CONFIG_BT_TBS) case BTP_SERVICE_ID_TBS: status = tester_init_tbs(); break; diff --git a/tests/bsim/bluetooth/audio/prj.conf b/tests/bsim/bluetooth/audio/prj.conf index f10854441e2332a..27749c09a952320 100644 --- a/tests/bsim/bluetooth/audio/prj.conf +++ b/tests/bsim/bluetooth/audio/prj.conf @@ -80,6 +80,7 @@ CONFIG_BT_CSIP_SET_COORDINATOR_TEST_SAMPLE_DATA=y # Telephone bearer service CONFIG_BT_TBS=y +CONFIG_BT_TBS_BEARER_COUNT=1 CONFIG_BT_TBS_CLIENT_TBS=y CONFIG_BT_TBS_CLIENT_GTBS=y CONFIG_BT_TBS_CLIENT_MAX_CALLS=4 From 709c006b58fe6ab0a181d5255ca8a30a0e120834 Mon Sep 17 00:00:00 2001 From: Ingar Kulbrandstad Date: Fri, 28 Jun 2024 13:37:44 +0200 Subject: [PATCH 113/269] Bluetooth: Mesh: Bridge Configuration Client/Server API Adding documentation and function calles for the API's in Bridge Configuration Client model and Bridge Configuration Server model. Signed-off-by: Ingar Kulbrandstad --- include/zephyr/bluetooth/mesh.h | 2 + include/zephyr/bluetooth/mesh/access.h | 4 + include/zephyr/bluetooth/mesh/brg_cfg.h | 92 ++++++ include/zephyr/bluetooth/mesh/brg_cfg_cli.h | 316 ++++++++++++++++++++ include/zephyr/bluetooth/mesh/brg_cfg_srv.h | 47 +++ subsys/bluetooth/mesh/CMakeLists.txt | 4 + subsys/bluetooth/mesh/Kconfig | 13 + subsys/bluetooth/mesh/brg_cfg_cli.c | 77 +++++ subsys/bluetooth/mesh/brg_cfg_srv.c | 35 +++ tests/bsim/bluetooth/mesh/prj.conf | 2 + 10 files changed, 592 insertions(+) create mode 100644 include/zephyr/bluetooth/mesh/brg_cfg.h create mode 100644 include/zephyr/bluetooth/mesh/brg_cfg_cli.h create mode 100644 include/zephyr/bluetooth/mesh/brg_cfg_srv.h create mode 100644 subsys/bluetooth/mesh/brg_cfg_cli.c create mode 100644 subsys/bluetooth/mesh/brg_cfg_srv.c diff --git a/include/zephyr/bluetooth/mesh.h b/include/zephyr/bluetooth/mesh.h index fe1fd728fa3f190..c4a211d690a3904 100644 --- a/include/zephyr/bluetooth/mesh.h +++ b/include/zephyr/bluetooth/mesh.h @@ -48,6 +48,8 @@ #include #include #include +#include +#include #include #endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_H_ */ diff --git a/include/zephyr/bluetooth/mesh/access.h b/include/zephyr/bluetooth/mesh/access.h index f1fca02783e87e6..db477ee6206bf94 100644 --- a/include/zephyr/bluetooth/mesh/access.h +++ b/include/zephyr/bluetooth/mesh/access.h @@ -187,6 +187,10 @@ struct bt_mesh_elem { #define BT_MESH_MODEL_ID_REMOTE_PROV_SRV 0x0004 /** Remote Provisioning Client */ #define BT_MESH_MODEL_ID_REMOTE_PROV_CLI 0x0005 +/** Bridge Configuration Sever */ +#define BT_MESH_MODEL_ID_BRG_CFG_SRV 0x0008 +/** Bridge Configuration Client */ +#define BT_MESH_MODEL_ID_BRG_CFG_CLI 0x0009 /** Private Beacon Server */ #define BT_MESH_MODEL_ID_PRIV_BEACON_SRV 0x000a /** Private Beacon Client */ diff --git a/include/zephyr/bluetooth/mesh/brg_cfg.h b/include/zephyr/bluetooth/mesh/brg_cfg.h new file mode 100644 index 000000000000000..51a863e497b274e --- /dev/null +++ b/include/zephyr/bluetooth/mesh/brg_cfg.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_H__ +#define ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bt_mesh_brg_cfg Bridge Configuration common header + * @ingroup bt_mesh + * @{ + */ + +/** Subnet Bridge states */ +enum bt_mesh_subnet_bridge_state { + /** Subnet bridge functionality is disabled. */ + BT_MESH_SUBNET_BRIDGE_DISABLED, + /** Subnet bridge state functionality is enabled. */ + BT_MESH_SUBNET_BRIDGE_ENABLED, +}; + +/** Bridging Table state entry corresponding to a entry in the Bridging Table. */ +struct bridging_table_entry { + /** Allowed directions for the bridged traffic (or bridged traffic not allowed) */ + uint8_t directions; + /** NetKey Index of the first subnet */ + uint16_t net_idx1; + /** NetKey Index of the second subnet */ + uint16_t net_idx2; + /** Address of the node in the first subnet */ + uint16_t addr1; + /** Address of the node in the second subnet */ + uint16_t addr2; +}; + +/** Bridging Table Status response */ +struct bt_mesh_bridging_table_status { + /** Status Code of the requesting message */ + enum bt_mesh_subnet_bridge_state status; + /** Requested Bridging Table entry */ + struct bridging_table_entry entry; +}; + +/** Used to filter set of pairs of NetKey Indexes from the Bridging Table */ +struct bt_mesh_filter_netkey { + uint16_t filter:2, /* Filter applied to the set of pairs of NetKey Indexes */ + prohibited:2, /* Prohibited */ + net_idx:12; /* NetKey Index used for filtering or ignored */ +}; + +/** Bridged Subnets List response */ +struct bt_mesh_bridged_subnets_list { + /** Filter applied NetKey Indexes, and NetKey Index used for filtering. */ + struct bt_mesh_filter_netkey net_idx_filter; + /** Start offset in units of bridges */ + uint8_t start_idx; + /** Pointer to allocated buffer for storing filtered of NetKey Indexes */ + struct net_buf_simple *list; +}; + +/** Bridging Table List response */ +struct bt_mesh_bridging_table_list { + /** Status Code of the requesting message */ + uint8_t status; + /** NetKey Index of the first subnet */ + uint16_t net_idx1; + /** NetKey Index of the second subnet */ + uint16_t net_idx2; + /** Start offset in units of bridging table state entries */ + uint16_t start_idx; + /** Pointer to allocated buffer for storing list of bridged addresses and directions */ + struct net_buf_simple *list; +}; + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_H__ */ diff --git a/include/zephyr/bluetooth/mesh/brg_cfg_cli.h b/include/zephyr/bluetooth/mesh/brg_cfg_cli.h new file mode 100644 index 000000000000000..2c71e133f92baf0 --- /dev/null +++ b/include/zephyr/bluetooth/mesh/brg_cfg_cli.h @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_CLI_H__ +#define ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_CLI_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bt_mesh_brg_cfg_cli Bridge Configuration Client Model + * @ingroup bt_mesh + * @{ + * @brief API for the Bluetooth Mesh Bridge Configuration Client model + */ + +struct bt_mesh_brg_cfg_cli; + +/** + * @brief Bridge Configuration Client model Composition Data entry. + * + * @param _cli Pointer to a @ref bt_mesh_brg_cfg_cli instance. + */ +#define BT_MESH_MODEL_BRG_CFG_CLI(_cli) \ + BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_CLI, _bt_mesh_brg_cfg_cli_op, NULL, _cli, \ + &_bt_mesh_brg_cfg_cli_cb) + +/** Mesh Bridge Configuration Client Status messages callback */ +struct bt_mesh_brg_cfg_cli_cb { + /** @brief Optional callback for Subnet Bridge Status message. + * + * Handles received Subnet Bridge Status messages from a Bridge + * Configuration Server. + + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param status Status received from the server. + */ + void (*subnet_bridge_status)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + enum bt_mesh_subnet_bridge_state status); + + /** @brief Optional callback for Bridging Table Size Status message. + * + * Handles received Bridging Table Size Status messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param size Size received from the server. + */ + void (*bridging_table_size_status)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + uint16_t size); + + /** @brief Optional callback for Bridging Table Status message. + * + * Handles received Bridging Table status messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param rsp Response received from the Bridging Configuration Server. + */ + void (*bridging_table_status)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + struct bt_mesh_bridging_table_status *rsp); + + /** @brief Optional callback for Bridged Subnets List message. + * + * Handles received Bridged Subnets List messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param rsp Response received from the Bridging Configuration Server. + */ + void (*bridged_subnets_list)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + struct bt_mesh_bridged_subnets_list *rsp); + + /** @brief Optional callback for Bridging Table List message. + * + * Handles received Bridging Table List messages from a Bridge + * Configuration Server. + * + * @param cli Bridge Configuration Client context. + * @param addr Address of the sender. + * @param rsp Response received from the Bridging Configuration Server. + */ + void (*bridging_table_list)(struct bt_mesh_brg_cfg_cli *cli, uint16_t addr, + struct bt_mesh_bridging_table_list *rsp); +}; + +/** Bridge Configuration Client Model Context */ +struct bt_mesh_brg_cfg_cli { + /** Bridge Configuration model entry pointer */ + const struct bt_mesh_model *model; + + /** Event handler callbacks */ + const struct bt_mesh_bdg_cfg_cli_cb *cb; + + /* Internal parameters for tracking message responses. */ + struct bt_mesh_msg_ack_ctx ack_ctx; +}; + +/** @brief Sends a Subnet Bridge Get message to the given destination address + * + * This function sends a Subnet Bridge Get message to the given destination + * address to query the value of the Subnet Bridge state of a subnet. The + * Subnet Bridge state indicates whether the subnet bridged feature is enabled + * or not. The function expects a Subnet Bridge Status message as a response + * from the destination node. + * + * This method can be used asynchronously by setting @p status as NULL. This + * way the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param status Status response parameter, returns one of + * @ref BT_MESH_SUBNET_BRIDGE_DISABLED or + * @ref BT_MESH_SUBNET_BRIDGE_ENABLED on success. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_subnet_bridge_get(uint16_t net_idx, uint16_t addr, + enum bt_mesh_subnet_bridge_state *status); + +/** @brief Sends a Subnet Bridge Set message to the given destination address + * with the given parameters + * + * This function sends a Subnet Bridge Set message to the given destination + * address with the given parameters to set the value of the Subnet Bridge + * state of a subnet. The Subnet Bridge state indicates whether the subnet + * bridge feature is enabled or not. The function expects a Subnet Bridge + * Status message as a response from the destination node. + * + * This method can be used asynchronously by setting @p status as NULL. This + * way the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param val Value to set the Subnet Bridge state to. Must be one of + * @ref BT_MESH_SUBNET_BRIDGE_DISABLED or + * @ref BT_MESH_SUBNET_BRIDGE_ENABLED. + * @param status Status response parameter, returns one of + * @ref BT_MESH_SUBNET_BRIDGE_DISABLED or + * @ref BT_MESH_SUBNET_BRIDGE_ENABLED on success. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_subnet_bridge_set(uint16_t net_idx, uint16_t addr, + enum bt_mesh_subnet_bridge_state val, + enum bt_mesh_subnet_bridge_state *status); + +/** @brief Sends a Bridging Table Size Get message to the given destination + * address with the given parameters + * + * This function sends a Bridging Table Size Get message to the given + * destination address with the given parameters to get the size of the Bridging + * Table of the node. The Bridging Table size indicates the maximum number of + * entries that can be stored in the Bridging Table. The function expects a + * Bridging Table Size Status message as a response from the destination node. + * + * This method can be used asynchronously by setting @p size as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param size Bridging Table size response parameter. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_bridging_table_size_get(uint16_t net_idx, uint16_t addr, uint16_t *size); + +/** @brief Sends a Bridging Table Add message to the given destination address + * with the given parameters + * + * This function sends a Bridging Table Add message to the given destination + * address with the given parameters to add an entry to the Bridging Table. The + * Bridging Table contains the net keys and addresses that are authorized to be + * bridged by the node. The function expects a Bridging Table Status message as + * a response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param directions Allowed directions for the bridged traffic + * @param net_idx1 NetKey Index of the first subnet + * @param net_idx2 NetKey Index of the second subnet + * @param addr1 Address of the node in the first subnet + * @param addr2 Address of the node in the second subnet + * @param rsp Status response parameter + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_bridging_table_add(uint16_t net_idx, uint16_t addr, uint8_t directions, + uint16_t net_idx1, uint16_t net_idx2, + uint16_t addr1, uint16_t addr2, + struct bt_mesh_bridging_table_status *rsp); + +/** @brief Sends a Bridging Table Remove message to the given destination + * address with the given parameters + * + * This function sends a Bridging Table Remove message to the given destination + * address with the given parameters to remove an entry from the Bridging + * Table. The Bridging Table contains the net keys and addresses that are + * authorized to be bridged by the node. The function expects a Bridging Table + * Status message as a response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param net_idx1 NetKey Index of the first subnet + * @param net_idx2 NetKey Index of the second subnet + * @param addr1 Address of the node in the first subnet + * @param addr2 Address of the node in the second subnet + * @param rsp Pointer to a struct storing the received response from the + * server, or NULL to not wait for a response. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_bridging_table_remove(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, + uint16_t net_idx2, uint16_t addr1, uint16_t addr2, + struct bt_mesh_bridging_table_status *rsp); + +/** @brief Sends a Bridged Subnets Get message to the given destination address + * with the given parameters + * + * This function sends a Bridged Subnets Get message to the given destination + * address with the given parameters to get the list of subnets that are + * bridged by the node. The function expects a Bridged Subnets List message as + * a response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * When @c rsp is set, the user is responsible for providing a buffer for the + * filtered set of N pairs of NetKey Indexes in + * @ref bt_mesh_bridged_subnets_list::list. If a buffer is not provided, the + * bridged subnets won't be copied. + + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param filter_net_idx Filter and NetKey Index used for filtering + * @param start_idx Start offset to read in units of Bridging Table state entries + * @param rsp Pointer to a struct storing the received response + * from the server, or NULL to not wait for a response. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_bridged_subnets_get(uint16_t net_idx, uint16_t addr, + struct bt_mesh_filter_netkey filter_net_idx, + uint8_t start_idx, + struct bt_mesh_bridged_subnets_list *rsp); + +/** @brief Sends a Bridging Table Get message to the given destination address + * with the given parameters + * + * This function sends a Bridging Table Get message to the given destination + * address with the given parameters to get the contents of the Bridging Table. + * The Bridging Table contains the addresses that are authorized to be bridged + * by the node. The function expects a Bridging Table List message as a + * response from the destination node. + * + * This method can be used asynchronously by setting @p rsp as NULL. This way + * the method will not wait for response and will return immediately after + * sending the command. + * + * When @c rsp is set, the user is responsible for providing a buffer for the + * filtered set of N pairs of NetKey Indexes in + * @ref bt_mesh_bridging_table_list::list. If a buffer is not provided, the + * bridged addresses won't be copied. If a buffer size is shorter than received + * list, only those many entries that fit in the buffer will be copied from the + * list, and rest will be discarded. + * + * @param net_idx Network index to encrypt the message with. + * @param addr Target node address. + * @param net_idx1 NetKey Index of the first subnet. + * @param net_idx2 NetKey Index of the second subnet. + * @param start_idx Start offset to read in units of Bridging Table state entries. + * @param rsp Pointer to a struct storing the received response from the + * server, or NULL to not wait for a response. + * + * @return 0 on success, or (negative) error code on failure. + */ +int bt_mesh_brg_cfg_cli_bridging_table_get(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, + uint16_t net_idx2, uint16_t start_idx, + struct bt_mesh_bridging_table_list *rsp); + +/** @cond INTERNAL_HIDDEN */ +extern const struct bt_mesh_model_op _bt_mesh_brg_cfg_cli_op[]; +extern const struct bt_mesh_model_cb _bt_mesh_brg_cfg_cli_cb; +/** @endcond */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_CLI_H__ */ diff --git a/include/zephyr/bluetooth/mesh/brg_cfg_srv.h b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h new file mode 100644 index 000000000000000..b642cc78b42a0f1 --- /dev/null +++ b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Bluetooth Mesh Bridge Configuration Server Model APIs. + */ +#ifndef ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_SRV_H__ +#define ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_SRV_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup bt_mesh_brg_cfg_srv Bridge Configuration Server Model + * @ingroup bt_mesh + * @{ + * @brief API for the Bluetooth Mesh Bridge Configuration Server model + */ + +/** + * + * @brief Bridge Configuration Server model Composition Data entry. + */ +#define BT_MESH_MODEL_BRG_CFG_SRV \ + BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_SRV, bt_mesh_brg_cfg_srv_op, \ + NULL, NULL, &bt_mesh_brg_cfg_srv_cb) + +/** @cond INTERNAL_HIDDEN */ +extern const struct bt_mesh_model_op bt_mesh_brg_cfg_srv_op[]; +extern const struct bt_mesh_model_cb bt_mesh_brg_cfg_srv_cb; +/** @endcond */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_INCLUDE_BLUETOOTH_MESH_BRG_CFG_SRV_H__ */ diff --git a/subsys/bluetooth/mesh/CMakeLists.txt b/subsys/bluetooth/mesh/CMakeLists.txt index ac69a9234d8e8b2..4d7ce916be51869 100644 --- a/subsys/bluetooth/mesh/CMakeLists.txt +++ b/subsys/bluetooth/mesh/CMakeLists.txt @@ -113,6 +113,10 @@ zephyr_library_sources_ifdef(CONFIG_BT_MESH_SOL_PDU_RPL_CLI sol_pdu_rpl_cli.c) zephyr_library_sources_ifdef(CONFIG_BT_MESH_OD_PRIV_PROXY_SRV sol_pdu_rpl_srv.c) +zephyr_library_sources_ifdef(CONFIG_BT_MESH_BRG_CFG_CLI brg_cfg_cli.c) + +zephyr_library_sources_ifdef(CONFIG_BT_MESH_BRG_CFG_SRV brg_cfg_srv.c) + zephyr_library_sources_ifdef(CONFIG_BT_MESH_SOLICITATION solicitation.c) zephyr_library_sources_ifdef(CONFIG_BT_MESH_STATISTIC statistic.c) diff --git a/subsys/bluetooth/mesh/Kconfig b/subsys/bluetooth/mesh/Kconfig index f89aac2713e1ae4..9102cb36d0e6c42 100644 --- a/subsys/bluetooth/mesh/Kconfig +++ b/subsys/bluetooth/mesh/Kconfig @@ -1267,6 +1267,19 @@ config BT_MESH_SOL_PDU_RPL_CLI_TIMEOUT for a response message to arrive. This value can be changed at runtime using @ref bt_mesh_sol_pdu_rpl_cli_timeout_set. +config BT_MESH_BRG_CFG_SRV + bool "Support for Bridge Configuration Server model" + depends on BT_MESH_MODEL_EXTENSIONS + help + The Bridge Configuration Server model is used to support the configuration + of the subnet bridge functionality of a node. + +config BT_MESH_BRG_CFG_CLI + bool "Support for Bridge Configuration Client model" + help + The Bridge Configuration Client is used to support the functionality of a + node that can configure the subnet bridge functionality of another node. + endmenu # Models menu "Proxy" diff --git a/subsys/bluetooth/mesh/brg_cfg_cli.c b/subsys/bluetooth/mesh/brg_cfg_cli.c new file mode 100644 index 000000000000000..61dede289d4e581 --- /dev/null +++ b/subsys/bluetooth/mesh/brg_cfg_cli.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#define LOG_LEVEL CONFIG_BT_MESH_MODEL_LOG_LEVEL +#include +LOG_MODULE_REGISTER(bt_mesh_brg_cfg_cli); + +const struct bt_mesh_model_op _bt_mesh_brg_cfg_cli_op[] = { + BT_MESH_MODEL_OP_END, +}; + +static int brg_cfg_cli_init(const struct bt_mesh_model *model) +{ + if (!bt_mesh_model_in_primary(model)) { + LOG_ERR("Bridge Configuration Client only allowed in primary element"); + return -EINVAL; + } + + return 0; +} + +const struct bt_mesh_model_cb _bt_mesh_brg_cfg_cli_cb = { + .init = brg_cfg_cli_init, +}; + +int bt_mesh_brg_cfg_cli_subnet_bridge_get(uint16_t net_idx, uint16_t addr, + enum bt_mesh_subnet_bridge_state *status) +{ + return 0; +} + +int bt_mesh_brg_cfg_cli_subnet_bridge_set(uint16_t net_idx, uint16_t addr, + enum bt_mesh_subnet_bridge_state val, + enum bt_mesh_subnet_bridge_state *status) +{ + return 0; +} + +int bt_mesh_brg_cfg_cli_bridging_table_size_get(uint16_t net_idx, uint16_t addr, uint16_t *size) +{ + return 0; +} + +int bt_mesh_brg_cfg_cli_bridging_table_add(uint16_t net_idx, uint16_t addr, uint8_t directions, + uint16_t net_idx1, uint16_t net_idx2, + uint16_t addr1, uint16_t addr2, + struct bt_mesh_bridging_table_status *rsp) +{ + return 0; +} + +int bt_mesh_brg_cfg_cli_bridging_table_remove(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, + uint16_t net_idx2, uint16_t addr1, uint16_t addr2, + struct bt_mesh_bridging_table_status *rsp) +{ + return 0; +} + +int bt_mesh_brg_cfg_cli_bridged_subnets_get(uint16_t net_idx, uint16_t addr, + struct bt_mesh_filter_netkey filter_net_idx, + uint8_t start_idx, + struct bt_mesh_bridged_subnets_list *rsp) +{ + return 0; +} + +int bt_mesh_brg_cfg_cli_bridging_table_get(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, + uint16_t net_idx2, uint16_t start_idx, + struct bt_mesh_bridging_table_list *rsp) +{ + return 0; +} diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c new file mode 100644 index 000000000000000..60aef4bf02c0b78 --- /dev/null +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#define LOG_LEVEL CONFIG_BT_MESH_MODEL_LOG_LEVEL +#include +LOG_MODULE_REGISTER(bt_mesh_brg_cfg_srv); + +const struct bt_mesh_model_op _bt_mesh_brg_cfg_srv_op[] = { + BT_MESH_MODEL_OP_END, +}; + +static int brg_cfg_srv_init(const struct bt_mesh_model *model) +{ + const struct bt_mesh_model *config_srv = + bt_mesh_model_find(bt_mesh_model_elem(model), BT_MESH_MODEL_ID_CFG_SRV); + + if (config_srv == NULL) { + LOG_ERR("Bridge Configuration Server only allowed in primary element"); + return -EINVAL; + } + + + bt_mesh_model_extend(model, config_srv); + + return 0; +} + +const struct bt_mesh_model_cb _bt_mesh_brg_cfg_srv_cb = { + .init = brg_cfg_srv_init, +}; diff --git a/tests/bsim/bluetooth/mesh/prj.conf b/tests/bsim/bluetooth/mesh/prj.conf index 1c343bb512f1307..eb810ef01162bcc 100644 --- a/tests/bsim/bluetooth/mesh/prj.conf +++ b/tests/bsim/bluetooth/mesh/prj.conf @@ -64,6 +64,8 @@ CONFIG_BT_MESH_PRIV_BEACON_SRV=y CONFIG_BT_MESH_PRIV_BEACON_CLI=y CONFIG_BT_MESH_OD_PRIV_PROXY_SRV=y CONFIG_BT_MESH_OD_PRIV_PROXY_CLI=y +CONFIG_BT_MESH_BRG_CFG_SRV=y +CONFIG_BT_MESH_BRG_CFG_CLI=y CONFIG_BT_MESH_COMP_PAGE_1=y CONFIG_BT_MESH_COMP_PAGE_2=y CONFIG_BT_TESTING=y From 092f808ea43bb65de48ebf55dff79aba093ddc5f Mon Sep 17 00:00:00 2001 From: Omkar Kulkarni Date: Tue, 25 Jun 2024 16:45:50 +0200 Subject: [PATCH 114/269] Bluetooth: Mesh: Adds subnet bridge states The `brg_cfg` module implements the states needed for subnet bridge feature. It provides two states - enable state, and bridging table state. APIs are provided to access and modify the states. The module handles responsibility of persistence of the states. Signed-off-by: Omkar Kulkarni --- subsys/bluetooth/Kconfig.logging | 4 + subsys/bluetooth/mesh/CMakeLists.txt | 2 +- subsys/bluetooth/mesh/Kconfig | 12 + subsys/bluetooth/mesh/brg_cfg.c | 307 +++++++++++++++ subsys/bluetooth/mesh/brg_cfg.h | 74 ++++ subsys/bluetooth/mesh/brg_cfg_srv.c | 7 + subsys/bluetooth/mesh/settings.c | 10 +- subsys/bluetooth/mesh/settings.h | 1 + tests/bluetooth/mesh/brg/CMakeLists.txt | 22 ++ tests/bluetooth/mesh/brg/prj.conf | 3 + tests/bluetooth/mesh/brg/src/main.c | 501 ++++++++++++++++++++++++ tests/bluetooth/mesh/brg/testcase.yaml | 10 + 12 files changed, 951 insertions(+), 2 deletions(-) create mode 100644 subsys/bluetooth/mesh/brg_cfg.c create mode 100644 subsys/bluetooth/mesh/brg_cfg.h create mode 100644 tests/bluetooth/mesh/brg/CMakeLists.txt create mode 100644 tests/bluetooth/mesh/brg/prj.conf create mode 100644 tests/bluetooth/mesh/brg/src/main.c create mode 100644 tests/bluetooth/mesh/brg/testcase.yaml diff --git a/subsys/bluetooth/Kconfig.logging b/subsys/bluetooth/Kconfig.logging index 9c2884214e26ed2..d1a20362f7f6c3d 100644 --- a/subsys/bluetooth/Kconfig.logging +++ b/subsys/bluetooth/Kconfig.logging @@ -407,6 +407,10 @@ module = BT_MESH_NET module-str = "Network layer" source "subsys/logging/Kconfig.template.log_config_inherit" +module = BT_MESH_BRG +module-str = "Subnet Bridging layer" +source "subsys/logging/Kconfig.template.log_config_inherit" + module = BT_MESH_RPL module-str = "Replay protection list" source "subsys/logging/Kconfig.template.log_config_inherit" diff --git a/subsys/bluetooth/mesh/CMakeLists.txt b/subsys/bluetooth/mesh/CMakeLists.txt index 4d7ce916be51869..3d5deadc6d92dc6 100644 --- a/subsys/bluetooth/mesh/CMakeLists.txt +++ b/subsys/bluetooth/mesh/CMakeLists.txt @@ -115,7 +115,7 @@ zephyr_library_sources_ifdef(CONFIG_BT_MESH_OD_PRIV_PROXY_SRV sol_pdu_rpl_srv.c) zephyr_library_sources_ifdef(CONFIG_BT_MESH_BRG_CFG_CLI brg_cfg_cli.c) -zephyr_library_sources_ifdef(CONFIG_BT_MESH_BRG_CFG_SRV brg_cfg_srv.c) +zephyr_library_sources_ifdef(CONFIG_BT_MESH_BRG_CFG_SRV brg_cfg_srv.c brg_cfg.c) zephyr_library_sources_ifdef(CONFIG_BT_MESH_SOLICITATION solicitation.c) diff --git a/subsys/bluetooth/mesh/Kconfig b/subsys/bluetooth/mesh/Kconfig index 9102cb36d0e6c42..56f460ff312aaee 100644 --- a/subsys/bluetooth/mesh/Kconfig +++ b/subsys/bluetooth/mesh/Kconfig @@ -1274,6 +1274,18 @@ config BT_MESH_BRG_CFG_SRV The Bridge Configuration Server model is used to support the configuration of the subnet bridge functionality of a node. +menu "Subnet Bridge configuration" + visible if BT_MESH_BRG_CFG_SRV + +config BT_MESH_BRG_TABLE_ITEMS_MAX + int "Maximum number of entries in the bridging table" + default 16 + range 16 255 + help + The maximum number of entries in the bridging table. + +endmenu + config BT_MESH_BRG_CFG_CLI bool "Support for Bridge Configuration Client model" help diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c new file mode 100644 index 000000000000000..8cfa0139512f86a --- /dev/null +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Implementation for states of Subnet Bridge feature in Bluetooth Mesh Protocol v1.1 + * specification + */ +#include +#include + +#include "mesh.h" +#include "net.h" +#include "settings.h" +#include "brg_cfg.h" + +#define LOG_LEVEL CONFIG_BT_MESH_BRG_LOG_LEVEL +#include +LOG_MODULE_REGISTER(bt_mesh_brg_cfg); + +/* Bridging table state and counter */ +static struct bt_mesh_brg_cfg_row brg_tbl[CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX]; +static uint32_t bt_mesh_brg_cfg_row_cnt; +/* Bridging enabled state */ +static bool brg_enabled; + +static void brg_tbl_compact(void) +{ + int j = 0; + + for (int k = 0; k < bt_mesh_brg_cfg_row_cnt; k++) { + if (brg_tbl[k].direction != 0) { + brg_tbl[j] = brg_tbl[k]; + j++; + } + } + memset(&brg_tbl[j], 0, sizeof(brg_tbl[j])); + bt_mesh_brg_cfg_row_cnt--; +} + +#if IS_ENABLED(CONFIG_BT_SETTINGS) +/* Set function for initializing bridging enable state from value stored in settings. */ +static int brg_en_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) +{ + int err; + + if (len_rd == 0) { + brg_enabled = 0; + LOG_DBG("Cleared bridge enable state"); + return 0; + } + + err = bt_mesh_settings_set(read_cb, cb_arg, &brg_enabled, sizeof(brg_enabled)); + if (err) { + LOG_ERR("Failed to set bridge enable state"); + return err; + } + + LOG_DBG("Restored bridge enable state"); + + return 0; +} + +/* Define a setting for storing enable state */ +BT_MESH_SETTINGS_DEFINE(brg_en, "brg_en", brg_en_set); + +/* Set function for initializing bridging table rows from values stored in settings. */ +static int brg_tbl_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) +{ + if (len_rd == 0) { + memset(brg_tbl, 0, sizeof(brg_tbl)); + bt_mesh_brg_cfg_row_cnt = 0; + LOG_DBG("Cleared bridging table entries"); + return 0; + } + + int err = bt_mesh_settings_set(read_cb, cb_arg, brg_tbl, sizeof(brg_tbl)); + + if (err) { + LOG_ERR("Failed to set bridging table entries"); + return err; + } + + LOG_DBG("Restored bridging table"); + + return 0; +} + +/* Define a setting for storing briging table rows */ +BT_MESH_SETTINGS_DEFINE(brg_tbl, "brg_tbl", brg_tbl_set); +#endif + +bool bt_mesh_brg_cfg_enable_get(void) +{ + return brg_enabled; +} + +int bt_mesh_brg_cfg_enable_set(bool enable) +{ + if (brg_enabled == enable) { + return 0; + } + + brg_enabled = enable; +#if IS_ENABLED(CONFIG_BT_SETTINGS) + bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); +#endif + return 0; +} + +void bt_mesh_brg_cfg_pending_store(void) +{ +#if CONFIG_BT_SETTINGS + char *path_en = "bt/mesh/brg_en"; + char *path_tbl = "bt/mesh/brg_tbl"; + int err; + + if (brg_enabled) { + err = settings_save_one(path_en, &brg_enabled, sizeof(brg_enabled)); + } else { + err = settings_delete(path_en); + } + + if (err) { + LOG_ERR("Failed to store %s value", path_en); + } + + + if (bt_mesh_brg_cfg_row_cnt) { + err = settings_save_one(path_tbl, &brg_tbl, + bt_mesh_brg_cfg_row_cnt * sizeof(brg_tbl[0])); + } else { + err = settings_delete(path_tbl); + } + + if (err) { + LOG_ERR("Failed to store %s value", path_tbl); + } +#endif +} + +/* Remove the entry from the bridging table that corresponds with the NetKey Index of the removed + * subnet. + */ +static void brg_tbl_netkey_removed_evt(struct bt_mesh_subnet *sub, enum bt_mesh_key_evt evt) +{ + if (evt != BT_MESH_KEY_DELETED) { + return; + } + + for (int i = 0; i < CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX; i++) { + if (brg_tbl[i].direction && ( + brg_tbl[i].net_idx1 == sub->net_idx || + brg_tbl[i].net_idx2 == sub->net_idx)) { + memset(&brg_tbl[i], 0, sizeof(brg_tbl[i])); + brg_tbl_compact(); + } + } + +#if IS_ENABLED(CONFIG_BT_SETTINGS) + bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); +#endif +} + +/* Add event hook for key deletion event */ +BT_MESH_SUBNET_CB_DEFINE(sbr) = { + .evt_handler = brg_tbl_netkey_removed_evt, +}; + +int bt_mesh_brg_cfg_tbl_reset(void) +{ + int err = 0; + + brg_enabled = false; + bt_mesh_brg_cfg_row_cnt = 0; + memset(brg_tbl, 0, sizeof(brg_tbl)); + +#if CONFIG_BT_SETTINGS + err = settings_delete("bt/mesh/brg_en"); + + if (err) { + return err; + } + + err = settings_delete("bt/mesh/brg_tbl"); +#endif + return err; +} + +int bt_mesh_brg_cfg_tbl_get(const struct bt_mesh_brg_cfg_row **rows) +{ + *rows = brg_tbl; + return bt_mesh_brg_cfg_row_cnt; +} + +int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx1, + uint16_t net_idx2, uint16_t addr1, uint16_t addr2) +{ + /* Sanity checks */ + if (!BT_MESH_ADDR_IS_UNICAST(addr1) || net_idx1 == net_idx2 || addr1 == addr2 || + net_idx1 > 0x03FF || net_idx2 > 0x03FF) { + return -EINVAL; + } + + if (direction != BT_MESH_BRG_CFG_DIR_ONEWAY && direction != BT_MESH_BRG_CFG_DIR_TWOWAY) { + return -EINVAL; + } + + if ((direction == BT_MESH_BRG_CFG_DIR_ONEWAY && + (addr2 == BT_MESH_ADDR_UNASSIGNED || addr2 == BT_MESH_ADDR_ALL_NODES)) || + (direction == BT_MESH_BRG_CFG_DIR_TWOWAY && + !BT_MESH_ADDR_IS_UNICAST(addr2))) { + return -EINVAL; + } + + /* Check if entry already exists, if yes, then, update the direction field and it is a + * success. + * "If a Bridging Table state entry corresponding to the received message exists, the + * element shall set the Directions field in the entry to the value of the Directions field + * in the received message." + */ + for (int i = 0; i < bt_mesh_brg_cfg_row_cnt; i++) { + if (brg_tbl[i].net_idx1 == net_idx1 && + brg_tbl[i].net_idx2 == net_idx2 && brg_tbl[i].addr1 == addr1 && + brg_tbl[i].addr2 == addr2) { + brg_tbl[i].direction = direction; + goto store; + } + } + + /* Empty element, is the current table row counter */ + if (bt_mesh_brg_cfg_row_cnt == CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { + return -ENOMEM; + } + + /* Update the row */ + brg_tbl[bt_mesh_brg_cfg_row_cnt].direction = direction; + brg_tbl[bt_mesh_brg_cfg_row_cnt].net_idx1 = net_idx1; + brg_tbl[bt_mesh_brg_cfg_row_cnt].net_idx2 = net_idx2; + brg_tbl[bt_mesh_brg_cfg_row_cnt].addr1 = addr1; + brg_tbl[bt_mesh_brg_cfg_row_cnt].addr2 = addr2; + bt_mesh_brg_cfg_row_cnt++; + +store: +#if IS_ENABLED(CONFIG_BT_SETTINGS) + bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); +#endif + + return 0; +} + +void bt_mesh_brg_cfg_tbl_foreach_subnet(uint16_t src, uint16_t dst, uint16_t net_idx, + bt_mesh_brg_cfg_cb_t cb, void *user_data) +{ + for (int i = 0; i < bt_mesh_brg_cfg_row_cnt; i++) { + if ((brg_tbl[i].direction == BT_MESH_BRG_CFG_DIR_ONEWAY || + brg_tbl[i].direction == BT_MESH_BRG_CFG_DIR_TWOWAY) && + brg_tbl[i].net_idx1 == net_idx && brg_tbl[i].addr1 == src && + brg_tbl[i].addr2 == dst) { + cb(brg_tbl[i].net_idx2, user_data); + } else if ((brg_tbl[i].direction == BT_MESH_BRG_CFG_DIR_TWOWAY && + brg_tbl[i].net_idx2 == net_idx && brg_tbl[i].addr2 == src && + brg_tbl[i].addr1 == dst)) { + cb(brg_tbl[i].net_idx1, user_data); + } + } +} + +void bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, + uint16_t addr2) +{ +#if IS_ENABLED(CONFIG_BT_SETTINGS) + bool store = false; +#endif + + /* Iterate over items and set matching row to 0, if nothing exist, or nothing matches, then + * it is success (similar to add) + */ + if (bt_mesh_brg_cfg_row_cnt == 0) { + return; + } + + for (int i = 0; i < bt_mesh_brg_cfg_row_cnt; i++) { + /* Match according to remove behavior in Section 4.4.9.2.2 of MshPRT_v1.1 */ + if (brg_tbl[i].direction) { + if (!(brg_tbl[i].net_idx1 == net_idx1 && brg_tbl[i].net_idx2 == net_idx2)) { + continue; + } + + if ((brg_tbl[i].addr1 == addr1 && brg_tbl[i].addr2 == addr2) || + (addr2 == BT_MESH_ADDR_UNASSIGNED && brg_tbl[i].addr1 == addr1) || + (addr1 == BT_MESH_ADDR_UNASSIGNED && brg_tbl[i].addr2 == addr2)) { + memset(&brg_tbl[i], 0, sizeof(brg_tbl[i])); + brg_tbl_compact(); +#if IS_ENABLED(CONFIG_BT_SETTINGS) + store = true; +#endif + } + } + } +#if IS_ENABLED(CONFIG_BT_SETTINGS) + if (store) { + bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); + } +#endif +} diff --git a/subsys/bluetooth/mesh/brg_cfg.h b/subsys/bluetooth/mesh/brg_cfg.h new file mode 100644 index 000000000000000..28364398de38145 --- /dev/null +++ b/subsys/bluetooth/mesh/brg_cfg.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_BLUETOOTH_MESH_BRG_CFG_H_ +#define ZEPHYR_SUBSYS_BLUETOOTH_MESH_BRG_CFG_H_ + +/** These are internal APIs. They do not sanitize input params. */ +enum bt_mesh_brg_cfg_dir { + /* Value is prohibited. */ + BT_MESH_BRG_CFG_DIR_PROHIBITED = 0, + /* Briging from Addr1 to Addr2. */ + BT_MESH_BRG_CFG_DIR_ONEWAY = 1, + /* Briging to/from Addr1 from/to Addr2. */ + BT_MESH_BRG_CFG_DIR_TWOWAY = 2, + /* Values above these are prohibited. */ + BT_MESH_BRG_CFG_DIR_MAX = 3, +}; + +#define BT_MESH_BRG_CFG_NETIDX_NOMATCH 0xFFFF + +/* One row of the bridging table */ +struct bt_mesh_brg_cfg_row { + /* Direction of the entry in the bridging table + * 0 - no entry, + * 1 - bridge messages with src as addr1 and dst as addr2 + * 2 - bridge messages with src as addr1 and dst as addr2 and vice-versa + */ + uint32_t direction:8; + uint32_t net_idx1:12; + uint32_t net_idx2:12; + uint16_t addr1; + uint16_t addr2; +}; + +bool bt_mesh_brg_cfg_enable_get(void); + +int bt_mesh_brg_cfg_enable_set(bool enable); + +void bt_mesh_brg_cfg_pending_store(void); + +int bt_mesh_brg_cfg_tbl_reset(void); + +int bt_mesh_brg_cfg_tbl_get(const struct bt_mesh_brg_cfg_row **rows); + +int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx1, + uint16_t net_idx2, uint16_t addr1, uint16_t addr2); + +void bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, + uint16_t addr2); + +typedef void (*bt_mesh_brg_cfg_cb_t)(uint16_t new_netidx, void *user_data); + +/** + * @brief Iterate over the bridging table to find a matching entry for the given SRC, DST, and + * NetKey Index. + * + * This function iterates over the bridging table and checks if there is a match for the provided + * parameters. If a match is found, the callback function specified by the 'cb' parameter is + * invoked with the NetKey Index of each matching entry (there can be several). Relaying operation + * can then happen inside this callback. + * + * @param src The source address to match. + * @param dst The destination address to match. + * @param net_idx The NetKey Index to match. + * @param cb The callback function to be invoked for each matching entry. + * @param user_data User data to be passed to the callback function. + */ +void bt_mesh_brg_cfg_tbl_foreach_subnet(uint16_t src, uint16_t dst, uint16_t net_idx, + bt_mesh_brg_cfg_cb_t cb, void *user_data); + +#endif /* ZEPHYR_SUBSYS_BLUETOOTH_MESH_BRG_CFG_H_ */ diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c index 60aef4bf02c0b78..bd5ced50abdff2b 100644 --- a/subsys/bluetooth/mesh/brg_cfg_srv.c +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -5,6 +5,7 @@ */ #include +#include "brg_cfg.h" #define LOG_LEVEL CONFIG_BT_MESH_MODEL_LOG_LEVEL #include @@ -30,6 +31,12 @@ static int brg_cfg_srv_init(const struct bt_mesh_model *model) return 0; } +void brg_cfg_srv_reset(const struct bt_mesh_model *model) +{ + bt_mesh_brg_cfg_tbl_reset(); +} + const struct bt_mesh_model_cb _bt_mesh_brg_cfg_srv_cb = { .init = brg_cfg_srv_init, + .reset = brg_cfg_srv_reset, }; diff --git a/subsys/bluetooth/mesh/settings.c b/subsys/bluetooth/mesh/settings.c index 8ec9c66481ac8c5..7997b5e9985af27 100644 --- a/subsys/bluetooth/mesh/settings.c +++ b/subsys/bluetooth/mesh/settings.c @@ -29,6 +29,7 @@ #include "pb_gatt_srv.h" #include "settings.h" #include "cfg.h" +#include "brg_cfg.h" #include "solicitation.h" #include "va.h" @@ -134,7 +135,8 @@ SETTINGS_STATIC_HANDLER_DEFINE(bt_mesh, "bt/mesh", NULL, NULL, mesh_commit, BIT(BT_MESH_SETTINGS_VA_PENDING) | \ BIT(BT_MESH_SETTINGS_SSEQ_PENDING) | \ BIT(BT_MESH_SETTINGS_COMP_PENDING) | \ - BIT(BT_MESH_SETTINGS_DEV_KEY_CAND_PENDING)) + BIT(BT_MESH_SETTINGS_DEV_KEY_CAND_PENDING) | \ + BIT(BT_MESH_SETTINGS_BRG_PENDING)) void bt_mesh_settings_store_schedule(enum bt_mesh_settings_flag flag) { @@ -262,6 +264,12 @@ static void store_pending(struct k_work *work) BT_MESH_SETTINGS_SSEQ_PENDING)) { bt_mesh_sseq_pending_store(); } + + if (IS_ENABLED(CONFIG_BT_MESH_BRG_CFG_SRV) && + atomic_test_and_clear_bit(pending_flags, + BT_MESH_SETTINGS_BRG_PENDING)) { + bt_mesh_brg_cfg_pending_store(); + } } void bt_mesh_settings_init(void) diff --git a/subsys/bluetooth/mesh/settings.h b/subsys/bluetooth/mesh/settings.h index bd6db9c3cdc238f..e50820ae61ce2f7 100644 --- a/subsys/bluetooth/mesh/settings.h +++ b/subsys/bluetooth/mesh/settings.h @@ -21,6 +21,7 @@ enum bt_mesh_settings_flag { BT_MESH_SETTINGS_SSEQ_PENDING, BT_MESH_SETTINGS_COMP_PENDING, BT_MESH_SETTINGS_DEV_KEY_CAND_PENDING, + BT_MESH_SETTINGS_BRG_PENDING, BT_MESH_SETTINGS_FLAG_COUNT, }; diff --git a/tests/bluetooth/mesh/brg/CMakeLists.txt b/tests/bluetooth/mesh/brg/CMakeLists.txt new file mode 100644 index 000000000000000..d878ad04d50fd68 --- /dev/null +++ b/tests/bluetooth/mesh/brg/CMakeLists.txt @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(bluetooth_mesh_brg) + +FILE(GLOB app_sources src/*.c) +target_sources(app + PRIVATE + ${app_sources} + ${ZEPHYR_BASE}/subsys/bluetooth/mesh/brg_cfg.c) + +target_include_directories(app + PRIVATE + ${ZEPHYR_BASE}/subsys/bluetooth/mesh) + +target_compile_options(app + PRIVATE + -DCONFIG_BT_SETTINGS + -DCONFIG_BT_MESH_BRG_CFG_SRV + -DCONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX=16 + -DCONFIG_BT_MESH_USES_TINYCRYPT) diff --git a/tests/bluetooth/mesh/brg/prj.conf b/tests/bluetooth/mesh/brg/prj.conf new file mode 100644 index 000000000000000..1eea5516d41a969 --- /dev/null +++ b/tests/bluetooth/mesh/brg/prj.conf @@ -0,0 +1,3 @@ +CONFIG_ZTEST=y +CONFIG_ZTEST_MOCKING=y +CONFIG_BT_MESH_BRG_CFG_SRV=y diff --git a/tests/bluetooth/mesh/brg/src/main.c b/tests/bluetooth/mesh/brg/src/main.c new file mode 100644 index 000000000000000..8f6fe6d276a419d --- /dev/null +++ b/tests/bluetooth/mesh/brg/src/main.c @@ -0,0 +1,501 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include "settings.h" +#include "brg_cfg.h" + +#define TEST_VECT_SZ (CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX + 1) + +static struct test_brg_cfg_row { + uint8_t direction; + uint16_t net_idx1; + uint16_t net_idx2; + uint16_t addr1; + uint16_t addr2; +} test_vector[TEST_VECT_SZ]; + +#define ADDR1_BASE (1) +#define ADDR2_BASE (100) + +/**** Helper functions ****/ +static void setup(void *f) +{ + /* create test vector */ + for (int i = 0; i < TEST_VECT_SZ; i++) { + test_vector[i].direction = i < (TEST_VECT_SZ / 2) ? 1 : 2; + test_vector[i].net_idx1 = (i/8); + test_vector[i].addr1 = ADDR1_BASE + i; + test_vector[i].net_idx2 = (i/8) + 16; + test_vector[i].addr2 = ADDR2_BASE + i; + } + +} + +/**** Mocked functions ****/ + +void bt_mesh_settings_store_schedule(enum bt_mesh_settings_flag flag) +{ + ztest_check_expected_value(flag); +} + +int settings_save_one(const char *name, const void *value, size_t val_len) +{ + ztest_check_expected_data(name, strlen(name)); + ztest_check_expected_value(val_len); + ztest_check_expected_data(value, val_len); + return 0; +} + +int settings_delete(const char *name) +{ + ztest_check_expected_data(name, strlen(name)); + return 0; +} + +/**** Mocked functions - end ****/ + +static void check_fill_all_bt_entries(void) +{ + int err; + + for (int i = 0; i < TEST_VECT_SZ; i++) { + + if (i < CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { + ztest_expect_value(bt_mesh_settings_store_schedule, flag, + BT_MESH_SETTINGS_BRG_PENDING); + } + + err = bt_mesh_brg_cfg_tbl_add(test_vector[i].direction, test_vector[i].net_idx1, + test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2); + + if (i != CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { + zassert_equal(err, 0); + } else { + zassert_equal(err, -ENOMEM); + } + } +} + +static void check_delete_all_bt_entries(void) +{ + for (int i = 0; i < TEST_VECT_SZ; i++) { + + if (i < CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { + ztest_expect_value(bt_mesh_settings_store_schedule, flag, + BT_MESH_SETTINGS_BRG_PENDING); + } + + bt_mesh_brg_cfg_tbl_remove(test_vector[i].net_idx1, test_vector[i].net_idx2, + test_vector[i].addr1, test_vector[i].addr2); + } +} + + +static void check_bt_mesh_brg_cfg_tbl_reset(void) +{ + int err; + + ztest_expect_data(settings_delete, name, "bt/mesh/brg_en"); + ztest_expect_data(settings_delete, name, "bt/mesh/brg_tbl"); + err = bt_mesh_brg_cfg_tbl_reset(); + zassert_equal(err, 0); +} + +/**** Tests ****/ + +ZTEST_SUITE(bt_mesh_brg_cfg, NULL, NULL, setup, NULL, NULL); + +/* Test if basic functionality (add and remove entries) works correctly. */ +ZTEST(bt_mesh_brg_cfg, test_basic_functionality_storage) +{ + check_bt_mesh_brg_cfg_tbl_reset(); + + /* Test add entries to bridging table. */ + check_fill_all_bt_entries(); + + /* Test remove entries from bridging table, and then fill it again. */ + check_delete_all_bt_entries(); + check_fill_all_bt_entries(); + + /* Test resetting of the table, and then fill it again. */ + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries(); + + /* Test remove entries matching netkey1, and netkey2 */ + uint16_t net_idx1 = test_vector[TEST_VECT_SZ - 1].net_idx1; + uint16_t net_idx2 = test_vector[TEST_VECT_SZ - 1].net_idx2; + uint16_t addr1 = BT_MESH_ADDR_UNASSIGNED; + uint16_t addr2 = BT_MESH_ADDR_UNASSIGNED; + + bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + + const struct bt_mesh_brg_cfg_row *brg_tbl; + int n = bt_mesh_brg_cfg_tbl_get(&brg_tbl); + + zassert_true(n > 0); + + for (int i = 0; i < n; i++) { + zassert_true(brg_tbl[i].net_idx1 != net_idx1); + zassert_true(brg_tbl[i].net_idx2 != net_idx2); + } + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries(); + + /* Test remove entries matching netkey1, and netkey2, and addr1 */ + addr1 = test_vector[TEST_VECT_SZ - 1].addr1; + n = bt_mesh_brg_cfg_tbl_get(&brg_tbl); + + zassert_true(n > 0); + + for (int i = 0; i < n; i++) { + zassert_true(brg_tbl[i].net_idx1 != net_idx1); + zassert_true(brg_tbl[i].net_idx2 != net_idx2); + zassert_true(brg_tbl[i].addr1 != addr1); + } + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries(); + + /* Test remove entries matching netkey1, and netkey2, and addr2 */ + addr1 = BT_MESH_ADDR_UNASSIGNED; + addr2 = test_vector[TEST_VECT_SZ - 1].addr2; + n = bt_mesh_brg_cfg_tbl_get(&brg_tbl); + + zassert_true(n > 0); + + for (int i = 0; i < n; i++) { + zassert_true(brg_tbl[i].net_idx1 != net_idx1); + zassert_true(brg_tbl[i].net_idx2 != net_idx2); + zassert_true(brg_tbl[i].addr2 != addr2); + } +} + +static void pending_store_enable_create_expectations(bool *enable_val, + int n, const struct bt_mesh_brg_cfg_row *tbl_val) +{ + if (*enable_val) { + ztest_expect_data(settings_save_one, name, "bt/mesh/brg_en"); + ztest_expect_value(settings_save_one, val_len, 1); + ztest_expect_data(settings_save_one, value, enable_val); + } else { + ztest_expect_data(settings_delete, name, "bt/mesh/brg_en"); + } + + if (n > 0) { + ztest_expect_data(settings_save_one, name, "bt/mesh/brg_tbl"); + ztest_expect_value(settings_save_one, val_len, + n * sizeof(struct bt_mesh_brg_cfg_row)); + ztest_expect_data(settings_save_one, value, tbl_val); + } else { + ztest_expect_data(settings_delete, name, "bt/mesh/brg_tbl"); + } +} + +/* Test if enable flag is stored correctly. */ +ZTEST(bt_mesh_brg_cfg, test_brg_cfg_en) +{ + int err; + int n; + bool val; + const struct bt_mesh_brg_cfg_row *tbl; + + check_bt_mesh_brg_cfg_tbl_reset(); + val = bt_mesh_brg_cfg_enable_get(); + n = bt_mesh_brg_cfg_tbl_get(&tbl); + zassert_equal(val, false, NULL); + pending_store_enable_create_expectations(&val, n, tbl); + bt_mesh_brg_cfg_pending_store(); + + + ztest_expect_value(bt_mesh_settings_store_schedule, flag, + BT_MESH_SETTINGS_BRG_PENDING); + err = bt_mesh_brg_cfg_enable_set(true); + zassert_equal(err, 0, NULL); + val = bt_mesh_brg_cfg_enable_get(); + n = bt_mesh_brg_cfg_tbl_get(&tbl); + pending_store_enable_create_expectations(&val, n, tbl); + bt_mesh_brg_cfg_pending_store(); + + zassert_equal(bt_mesh_brg_cfg_enable_get(), true, NULL); +} + +/* Test if pending store works correctly by adding one entry to the table. */ +ZTEST(bt_mesh_brg_cfg, test_brg_tbl_pending_store) +{ + int n, err; + bool b_en; + struct bt_mesh_brg_cfg_row test_vec = { + .direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 1, + .net_idx2 = 2, + .addr1 = 3, + .addr2 = 4, + }; + + check_bt_mesh_brg_cfg_tbl_reset(); + ztest_expect_value(bt_mesh_settings_store_schedule, flag, + BT_MESH_SETTINGS_BRG_PENDING); + err = bt_mesh_brg_cfg_tbl_add(test_vec.direction, test_vec.net_idx1, + test_vec.net_idx2, test_vec.addr1, test_vec.addr2); + zassert_equal(err, 0); + + const struct bt_mesh_brg_cfg_row *tbl; + + n = bt_mesh_brg_cfg_tbl_get(&tbl); + b_en = bt_mesh_brg_cfg_enable_get(); + + zassert_equal(n, 1); + zassert_true(tbl); + + pending_store_enable_create_expectations(&b_en, 1, &test_vec); + bt_mesh_brg_cfg_pending_store(); +} + +/* Test if invalid entries are not added to the table. */ +ZTEST(bt_mesh_brg_cfg, test_tbl_add_invalid_ip) +{ + int err; + /* Create test vector array of test_brg_cfg_row iteams with invalid values. + * Each vector has only one invalid field value, rest all are valid values. + */ + const struct test_brg_cfg_row inv_test_vector[] = { + /* Direction has invalid values */ + {.direction = BT_MESH_BRG_CFG_DIR_PROHIBITED, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 2}, + {.direction = BT_MESH_BRG_CFG_DIR_MAX, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 2}, + /* Out of range netidx values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 4096, .net_idx2 = 1, .addr1 = 1, .addr2 = 2}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 4096, .addr1 = 1, .addr2 = 2}, + /* Same netidx values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 0, .addr1 = 1, .addr2 = 2}, + /* Same addr values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 1}, + /* Invalid address1 value */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0, .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0x8000, .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0xC000, .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0xFFFE, .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0xFFFF, .addr2 = 1}, + /* Invalid address2 values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xFFFF}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0x8000}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xC000}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xFFFE}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xFFFF}, + }; + + check_bt_mesh_brg_cfg_tbl_reset(); + + for (int i = 0; i < ARRAY_SIZE(inv_test_vector); i++) { + err = bt_mesh_brg_cfg_tbl_add(inv_test_vector[i].direction, + inv_test_vector[i].net_idx1, inv_test_vector[i].net_idx2, + inv_test_vector[i].addr1, inv_test_vector[i].addr2); + zassert_equal(err, -EINVAL, "Test vector index: %zu", i); + } +} + + +/* Following are helper functions for the test that checks the iteration logic */ +#define NUM_MSGS (10000) + +static void print_brg_tbl(void) +{ + const struct bt_mesh_brg_cfg_row *tbl; + int n = bt_mesh_brg_cfg_tbl_get(&tbl); + + zassert_true(n <= CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX); + + for (int i = 0; i < n; i++) { + printk("entry: %3d # dir: %d, net_idx1: %3d, addr1: %3d, net_idx2: %3d, addr2: %3d\n", + i, tbl[i].direction, tbl[i].net_idx1, tbl[i].addr1, tbl[i].net_idx2, + tbl[i].addr2); + } +} + +static void check_fill_all_bt_entries_reversed(void) +{ + int err; + + for (int i = TEST_VECT_SZ - 2; i >= 0 ; i--) { + ztest_expect_value(bt_mesh_settings_store_schedule, flag, + BT_MESH_SETTINGS_BRG_PENDING); + err = bt_mesh_brg_cfg_tbl_add(test_vector[i].direction, test_vector[i].net_idx1, + test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2); + zassert_equal(err, 0); + } + + int last = TEST_VECT_SZ - 1; + + err = bt_mesh_brg_cfg_tbl_add(test_vector[last].direction, test_vector[last].net_idx1, + test_vector[last].net_idx2, test_vector[last].addr1, test_vector[last].addr2); + zassert_equal(err, -ENOMEM); +} + +static struct test_brg_cfg_row test_vector_copy[TEST_VECT_SZ - 1]; + +static void check_fill_all_bt_entries_randomly(void) +{ + int err; + int copy_cnt = ARRAY_SIZE(test_vector_copy); + + memcpy(test_vector_copy, test_vector, sizeof(test_vector_copy)); + + for (int i = 0; i < copy_cnt; i++) { + int idx = rand() % copy_cnt; + struct test_brg_cfg_row tmp = test_vector_copy[i]; + + test_vector_copy[i] = test_vector_copy[idx]; + test_vector_copy[idx] = tmp; + } + + for (int i = 0; i < copy_cnt; i++) { + ztest_expect_value(bt_mesh_settings_store_schedule, flag, + BT_MESH_SETTINGS_BRG_PENDING); + err = bt_mesh_brg_cfg_tbl_add(test_vector_copy[i].direction, + test_vector_copy[i].net_idx1, test_vector_copy[i].net_idx2, + test_vector_copy[i].addr1, test_vector_copy[i].addr2); + zassert_equal(err, 0); + } + + int last = TEST_VECT_SZ - 1; + + err = bt_mesh_brg_cfg_tbl_add(test_vector[last].direction, test_vector[last].net_idx1, + test_vector[last].net_idx2, test_vector[last].addr1, test_vector[last].addr2); + zassert_equal(err, -ENOMEM); +} + +static void subnet_relay_cb_check(uint16_t new_net_idx, void *user_data) +{ + int idx = *(int *)user_data; + + zassert_equal(new_net_idx, test_vector[idx].net_idx2); +} + +static void subnet_relay_cb_check_rev(uint16_t new_net_idx, void *user_data) +{ + int idx = *(int *)user_data; + + if (test_vector[idx].direction == 2) { + zassert_equal(new_net_idx, test_vector[idx].net_idx1); + } else { + /* Should never assert. Test vector created in setup(). */ + zassert_true(false); + } +} + +static void test_bridging_performance(bool test_one_way) +{ + int idx; + uint32_t tick1; + uint32_t ticks = 0; + + for (int i = 0; i < NUM_MSGS; i++) { + /* randomly pick an entry from the test vector */ + idx = rand() % TEST_VECT_SZ; + + /* check src to dst bridging*/ + const struct bt_mesh_brg_cfg_row *tbl_row = NULL; + + tick1 = k_uptime_ticks(); + bt_mesh_brg_cfg_tbl_foreach_subnet(test_vector[idx].addr1, test_vector[idx].addr2, + test_vector[idx].net_idx1, subnet_relay_cb_check, &idx); + ticks += k_uptime_ticks() - tick1; + + if (test_one_way) { + continue; + } + + /* check dst to src bridging - for the same test vector src-dst pairs + * but now, reverse them and consider packets are arriving on net_idx2 + */ + tbl_row = NULL; + tick1 = k_uptime_ticks(); + bt_mesh_brg_cfg_tbl_foreach_subnet(test_vector[idx].addr2, test_vector[idx].addr1, + test_vector[idx].net_idx2, subnet_relay_cb_check_rev, &idx); + ticks += k_uptime_ticks() - tick1; + } + printk("ticks: %8u us: %u\n", ticks, k_ticks_to_us_floor32(ticks)); +} + +/* Test checks iteration logic and performance when run on real devices. */ +ZTEST(bt_mesh_brg_cfg, test_zcheck_entry_randomly_sorting) +{ + printk("num msgs: %d\n\n", NUM_MSGS); + + /* Test performance when packets are flowing in one directions */ + /* Fill bridging table in sorted order */ + printk("\n\nPackets going only in one direction (from outside towards the subnet)\n"); + printk("\nBridging table is pre-filled in sorted order\n"); + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries(); + print_brg_tbl(); + test_bridging_performance(true); + + /* Fill bridging table in reversed order */ + printk("\nBridging table is pre-filled in reversed order\n"); + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries_reversed(); + print_brg_tbl(); + test_bridging_performance(true); + + /* Fill bridging table in random order */ + printk("\nBridging table is pre-filled in random order\n"); + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries_randomly(); + print_brg_tbl(); + test_bridging_performance(true); + + /* Test performance when packets are flowing in both directions - use same dataset. */ + printk("\n\nPackets going in both directions (same data set, flip src and dst pairs)\n"); + printk("\nBridging table is pre-filled in sorted order\n"); + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries(); + print_brg_tbl(); + test_bridging_performance(false); + + /* Fill bridging table in reversed order */ + printk("\nBridging table is pre-filled in reversed order\n"); + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries_reversed(); + print_brg_tbl(); + test_bridging_performance(false); + + /* Fill bridging table in random order */ + printk("\nBridging table is pre-filled in random order\n"); + + check_bt_mesh_brg_cfg_tbl_reset(); + check_fill_all_bt_entries_randomly(); + print_brg_tbl(); + test_bridging_performance(false); +} diff --git a/tests/bluetooth/mesh/brg/testcase.yaml b/tests/bluetooth/mesh/brg/testcase.yaml new file mode 100644 index 000000000000000..b94a3d445e226e1 --- /dev/null +++ b/tests/bluetooth/mesh/brg/testcase.yaml @@ -0,0 +1,10 @@ +tests: + bluetooth.mesh.brg: + platform_allow: + - native_posix + - native_sim + tags: + - bluetooth + - mesh + integration_platforms: + - native_sim From 6846f6f64c23e730ac8927ff54a07b55b34f7635 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5vard=20Reierstad?= Date: Thu, 18 Jul 2024 10:08:59 +0200 Subject: [PATCH 115/269] Bluetooth: Mesh: Fix subnet bridge table status type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Changes status type to be status codes defined in Mesh Protocol 4.3.14 as defined for the `BRIDGING_TABLE_STATUS` message. Signed-off-by: Håvard Reierstad --- include/zephyr/bluetooth/mesh/brg_cfg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/zephyr/bluetooth/mesh/brg_cfg.h b/include/zephyr/bluetooth/mesh/brg_cfg.h index 51a863e497b274e..bb26370bcf5d4ac 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg.h @@ -45,7 +45,7 @@ struct bridging_table_entry { /** Bridging Table Status response */ struct bt_mesh_bridging_table_status { /** Status Code of the requesting message */ - enum bt_mesh_subnet_bridge_state status; + uint8_t status; /** Requested Bridging Table entry */ struct bridging_table_entry entry; }; From 7c6c5b4965cf74eba9b84fe8308db812a2720755 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5vard=20Reierstad?= Date: Thu, 18 Jul 2024 13:27:43 +0200 Subject: [PATCH 116/269] Bluetooth: Mesh: Change bridge table add params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change the parameters of the bridge table add function to take an entry struct rather than the fields of an entry. Signed-off-by: Håvard Reierstad --- include/zephyr/bluetooth/mesh/brg_cfg.h | 4 ++-- include/zephyr/bluetooth/mesh/brg_cfg_cli.h | 11 +++-------- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/include/zephyr/bluetooth/mesh/brg_cfg.h b/include/zephyr/bluetooth/mesh/brg_cfg.h index bb26370bcf5d4ac..8cdc59ce76d98f5 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg.h @@ -29,7 +29,7 @@ enum bt_mesh_subnet_bridge_state { }; /** Bridging Table state entry corresponding to a entry in the Bridging Table. */ -struct bridging_table_entry { +struct bt_mesh_bridging_table_entry { /** Allowed directions for the bridged traffic (or bridged traffic not allowed) */ uint8_t directions; /** NetKey Index of the first subnet */ @@ -47,7 +47,7 @@ struct bt_mesh_bridging_table_status { /** Status Code of the requesting message */ uint8_t status; /** Requested Bridging Table entry */ - struct bridging_table_entry entry; + struct bt_mesh_bridging_table_entry entry; }; /** Used to filter set of pairs of NetKey Indexes from the Bridging Table */ diff --git a/include/zephyr/bluetooth/mesh/brg_cfg_cli.h b/include/zephyr/bluetooth/mesh/brg_cfg_cli.h index 2c71e133f92baf0..88876497530df4b 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg_cli.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg_cli.h @@ -193,18 +193,13 @@ int bt_mesh_brg_cfg_cli_bridging_table_size_get(uint16_t net_idx, uint16_t addr, * * @param net_idx Network index to encrypt the message with. * @param addr Target node address. - * @param directions Allowed directions for the bridged traffic - * @param net_idx1 NetKey Index of the first subnet - * @param net_idx2 NetKey Index of the second subnet - * @param addr1 Address of the node in the first subnet - * @param addr2 Address of the node in the second subnet + * @param entry Pointer to bridging Table entry to add. * @param rsp Status response parameter * * @return 0 on success, or (negative) error code on failure. */ -int bt_mesh_brg_cfg_cli_bridging_table_add(uint16_t net_idx, uint16_t addr, uint8_t directions, - uint16_t net_idx1, uint16_t net_idx2, - uint16_t addr1, uint16_t addr2, +int bt_mesh_brg_cfg_cli_bridging_table_add(uint16_t net_idx, uint16_t addr, + struct bt_mesh_bridging_table_entry *entry, struct bt_mesh_bridging_table_status *rsp); /** @brief Sends a Bridging Table Remove message to the given destination From d49068e60874e0efc04b9aa07d16e6de287a7aba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5vard=20Reierstad?= Date: Mon, 15 Jul 2024 15:22:58 +0200 Subject: [PATCH 117/269] Bluetooth: Mesh: Implement Bridge Config Client MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implements the Bridge Configuration Client model. Adds opcodes for all Bridge messages to `foundation.h`. Adds client-side support for these messages. Adds a new Kconfig option for the Bridge Configuration Client model to configure the waiting time for respones for acked messages. Signed-off-by: Håvard Reierstad --- .../bluetooth/api/mesh/brg_cfg_cli.rst | 21 ++ .../bluetooth/api/mesh/brg_cfg_srv.rst | 9 + .../bluetooth/api/mesh/models.rst | 2 + include/zephyr/bluetooth/mesh/brg_cfg_cli.h | 14 +- subsys/bluetooth/mesh/Kconfig | 12 + subsys/bluetooth/mesh/brg_cfg_cli.c | 296 +++++++++++++++++- subsys/bluetooth/mesh/foundation.h | 13 + 7 files changed, 356 insertions(+), 11 deletions(-) create mode 100644 doc/connectivity/bluetooth/api/mesh/brg_cfg_cli.rst create mode 100644 doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst diff --git a/doc/connectivity/bluetooth/api/mesh/brg_cfg_cli.rst b/doc/connectivity/bluetooth/api/mesh/brg_cfg_cli.rst new file mode 100644 index 000000000000000..3db407043a6920b --- /dev/null +++ b/doc/connectivity/bluetooth/api/mesh/brg_cfg_cli.rst @@ -0,0 +1,21 @@ +.. _bluetooth_mesh_models_brg_cfg_cli: + +Bridge Configuration Client +########################### + +The Bridge Configuration Client is a foundation model defined by the Bluetooth Mesh +specification. The model is optional, and is enabled through +the :kconfig:option:`CONFIG_BT_MESH_BRG_CFG_CLI` option. + +The Bridge Configuration Client model provides functionality for configuring the +subnet bridge functionality of another Mesh node containing the +:ref:`bluetooth_mesh_models_brg_cfg_srv`. The device key of the node containing +the target Bridge Configuration Server is used for access layer security. + +If present, the Bridge Configuration Client model must only be instantiated on the primary +element. + +API reference +************* + +.. doxygengroup:: bt_mesh_brg_cfg_cli diff --git a/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst b/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst new file mode 100644 index 000000000000000..124cd76ca7e01d0 --- /dev/null +++ b/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst @@ -0,0 +1,9 @@ +.. _bluetooth_mesh_models_brg_cfg_srv: + +Bridge Configuration Server +########################### + +API reference +************* + +.. doxygengroup:: bt_mesh_brg_cfg_srv diff --git a/doc/connectivity/bluetooth/api/mesh/models.rst b/doc/connectivity/bluetooth/api/mesh/models.rst index 94c3914ca53ccff..d5a2f6a8a85d71d 100644 --- a/doc/connectivity/bluetooth/api/mesh/models.rst +++ b/doc/connectivity/bluetooth/api/mesh/models.rst @@ -12,6 +12,8 @@ used by network administrators to configure and diagnose mesh nodes. .. toctree:: :maxdepth: 1 + brg_cfg_cli + brg_cfg_srv cfg_cli cfg_srv health_cli diff --git a/include/zephyr/bluetooth/mesh/brg_cfg_cli.h b/include/zephyr/bluetooth/mesh/brg_cfg_cli.h index 88876497530df4b..c29650a5df97619 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg_cli.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg_cli.h @@ -100,7 +100,7 @@ struct bt_mesh_brg_cfg_cli { const struct bt_mesh_model *model; /** Event handler callbacks */ - const struct bt_mesh_bdg_cfg_cli_cb *cb; + const struct bt_mesh_brg_cfg_cli_cb *cb; /* Internal parameters for tracking message responses. */ struct bt_mesh_msg_ack_ctx ack_ctx; @@ -295,6 +295,18 @@ int bt_mesh_brg_cfg_cli_bridging_table_get(uint16_t net_idx, uint16_t addr, uint uint16_t net_idx2, uint16_t start_idx, struct bt_mesh_bridging_table_list *rsp); +/** @brief Get the current transmission timeout value. + * + * @return The configured transmission timeout in milliseconds. + */ +int32_t bt_mesh_brg_cfg_cli_timeout_get(void); + +/** @brief Set the transmission timeout value. + * + * @param timeout The new transmission timeout. + */ +void bt_mesh_brg_cfg_cli_timeout_set(int32_t timeout); + /** @cond INTERNAL_HIDDEN */ extern const struct bt_mesh_model_op _bt_mesh_brg_cfg_cli_op[]; extern const struct bt_mesh_model_cb _bt_mesh_brg_cfg_cli_cb; diff --git a/subsys/bluetooth/mesh/Kconfig b/subsys/bluetooth/mesh/Kconfig index 56f460ff312aaee..63dbc4abfe02e27 100644 --- a/subsys/bluetooth/mesh/Kconfig +++ b/subsys/bluetooth/mesh/Kconfig @@ -1292,6 +1292,18 @@ config BT_MESH_BRG_CFG_CLI The Bridge Configuration Client is used to support the functionality of a node that can configure the subnet bridge functionality of another node. +if BT_MESH_BRG_CFG_CLI + +config BT_MESH_BRG_CFG_CLI_TIMEOUT + int "Bridge Configuration Client model timeout in milliseconds" + default 5000 + help + This timeout controls how long the bridge configuration client waits for a + response message to arrive. This value can be changed at runtime using + @ref bt_mesh_brg_cfg_cli_timeout_set. + +endif # BT_MESH_BRG_CFG_CLI + endmenu # Models menu "Proxy" diff --git a/subsys/bluetooth/mesh/brg_cfg_cli.c b/subsys/bluetooth/mesh/brg_cfg_cli.c index 61dede289d4e581..3a35885520e732d 100644 --- a/subsys/bluetooth/mesh/brg_cfg_cli.c +++ b/subsys/bluetooth/mesh/brg_cfg_cli.c @@ -5,12 +5,152 @@ */ #include +#include "access.h" +#include "foundation.h" +#include "msg.h" #define LOG_LEVEL CONFIG_BT_MESH_MODEL_LOG_LEVEL #include LOG_MODULE_REGISTER(bt_mesh_brg_cfg_cli); +static int32_t msg_timeout; + +static struct bt_mesh_brg_cfg_cli *cli; + +static int subnet_bridge_status(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + enum bt_mesh_subnet_bridge_state status = + (enum bt_mesh_subnet_bridge_state)net_buf_simple_pull_u8(buf); + enum bt_mesh_subnet_bridge_state *rsp; + + if (bt_mesh_msg_ack_ctx_match(&cli->ack_ctx, OP_SUBNET_BRIDGE_STATUS, ctx->addr, + (void **)&rsp)) { + *rsp = status; + bt_mesh_msg_ack_ctx_rx(&cli->ack_ctx); + } + + if (cli->cb && cli->cb->subnet_bridge_status) { + cli->cb->subnet_bridge_status(cli, ctx->addr, status); + } + return 0; +} + +static int bridging_table_status(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + struct bt_mesh_bridging_table_status table_status; + struct bt_mesh_bridging_table_status *rsp; + + table_status.status = net_buf_simple_pull_u8(buf); + table_status.entry.directions = net_buf_simple_pull_u8(buf); + key_idx_unpack_pair(buf, &table_status.entry.net_idx1, &table_status.entry.net_idx2); + table_status.entry.addr1 = net_buf_simple_pull_le16(buf); + table_status.entry.addr2 = net_buf_simple_pull_le16(buf); + + if (!(table_status.entry.addr1 == BT_MESH_ADDR_UNASSIGNED || + BT_MESH_ADDR_IS_UNICAST(table_status.entry.addr1))) { + LOG_ERR("addr1 shall be a unicast address or unassigned."); + return -EINVAL; + } else if (table_status.entry.addr2 == BT_MESH_ADDR_ALL_NODES) { + LOG_ERR("addr2 shall not be the all-nodes fixed group address."); + return -EINVAL; + } + + if (bt_mesh_msg_ack_ctx_match(&cli->ack_ctx, OP_BRIDGING_TABLE_STATUS, ctx->addr, + (void **)&rsp)) { + *rsp = table_status; + bt_mesh_msg_ack_ctx_rx(&cli->ack_ctx); + } + + if (cli->cb && cli->cb->bridging_table_status) { + cli->cb->bridging_table_status(cli, ctx->addr, &table_status); + } + return 0; +} + +static int bridged_subnets_list(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + struct bt_mesh_bridged_subnets_list subnets_list; + struct bt_mesh_bridged_subnets_list *rsp; + uint16_t net_idx_filter; + + net_idx_filter = net_buf_simple_pull_le16(buf); + subnets_list.net_idx_filter.filter = net_idx_filter & BIT_MASK(2); + subnets_list.net_idx_filter.net_idx = (net_idx_filter >> 4) & BIT_MASK(12); + subnets_list.start_idx = net_buf_simple_pull_u8(buf); + + if (buf->len && !(buf->len % 3)) { + subnets_list.list = buf; + } else { + subnets_list.list = NULL; + } + + if (bt_mesh_msg_ack_ctx_match(&cli->ack_ctx, OP_BRIDGED_SUBNETS_LIST, ctx->addr, + (void **)&rsp)) { + *rsp = subnets_list; + bt_mesh_msg_ack_ctx_rx(&cli->ack_ctx); + } + + if (cli->cb && cli->cb->bridged_subnets_list) { + cli->cb->bridged_subnets_list(cli, ctx->addr, &subnets_list); + } + return 0; +} + +static int bridging_table_list(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + struct bt_mesh_bridging_table_list table_list; + struct bt_mesh_bridging_table_list *rsp; + + table_list.status = net_buf_simple_pull_u8(buf); + key_idx_unpack_pair(buf, &table_list.net_idx1, &table_list.net_idx2); + table_list.start_idx = net_buf_simple_pull_le16(buf); + + if ((table_list.status == STATUS_SUCCESS) && buf->len && !(buf->len % 5)) { + table_list.list = buf; + } else { + table_list.list = NULL; + } + + if (bt_mesh_msg_ack_ctx_match(&cli->ack_ctx, OP_BRIDGING_TABLE_LIST, ctx->addr, + (void **)&rsp)) { + *rsp = table_list; + bt_mesh_msg_ack_ctx_rx(&cli->ack_ctx); + } + + if (cli->cb && cli->cb->bridging_table_list) { + cli->cb->bridging_table_list(cli, ctx->addr, &table_list); + } + return 0; +} + +static int bridging_table_size_status(const struct bt_mesh_model *model, + struct bt_mesh_msg_ctx *ctx, struct net_buf_simple *buf) +{ + uint16_t size = net_buf_simple_pull_le16(buf); + uint16_t *rsp; + + if (bt_mesh_msg_ack_ctx_match(&cli->ack_ctx, OP_BRIDGING_TABLE_SIZE_STATUS, ctx->addr, + (void **)&rsp)) { + *rsp = size; + bt_mesh_msg_ack_ctx_rx(&cli->ack_ctx); + } + + if (cli->cb && cli->cb->bridging_table_size_status) { + cli->cb->bridging_table_size_status(cli, ctx->addr, size); + } + return 0; +} + const struct bt_mesh_model_op _bt_mesh_brg_cfg_cli_op[] = { + { OP_SUBNET_BRIDGE_STATUS, BT_MESH_LEN_EXACT(1), subnet_bridge_status }, + { OP_BRIDGING_TABLE_STATUS, BT_MESH_LEN_EXACT(9), bridging_table_status }, + { OP_BRIDGED_SUBNETS_LIST, BT_MESH_LEN_MIN(3), bridged_subnets_list }, + { OP_BRIDGING_TABLE_LIST, BT_MESH_LEN_MIN(6), bridging_table_list }, + { OP_BRIDGING_TABLE_SIZE_STATUS, BT_MESH_LEN_EXACT(2), bridging_table_size_status }, BT_MESH_MODEL_OP_END, }; @@ -21,6 +161,20 @@ static int brg_cfg_cli_init(const struct bt_mesh_model *model) return -EINVAL; } + if (!model->rt->user_data) { + LOG_ERR("No Bridge Configuration Client context provided"); + return -EINVAL; + } + + cli = model->rt->user_data; + cli->model = model; + msg_timeout = CONFIG_BT_MESH_BRG_CFG_CLI_TIMEOUT; + + model->keys[0] = BT_MESH_KEY_DEV_ANY; + model->rt->flags |= BT_MESH_MOD_DEVKEY_ONLY; + + bt_mesh_msg_ack_ctx_init(&cli->ack_ctx); + return 0; } @@ -31,34 +185,120 @@ const struct bt_mesh_model_cb _bt_mesh_brg_cfg_cli_cb = { int bt_mesh_brg_cfg_cli_subnet_bridge_get(uint16_t net_idx, uint16_t addr, enum bt_mesh_subnet_bridge_state *status) { - return 0; + BT_MESH_MODEL_BUF_DEFINE(msg, OP_SUBNET_BRIDGE_GET, 0); + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); + const struct bt_mesh_msg_rsp_ctx rsp_ctx = { + .ack = &cli->ack_ctx, + .op = OP_SUBNET_BRIDGE_STATUS, + .user_data = status, + .timeout = msg_timeout, + }; + + bt_mesh_model_msg_init(&msg, OP_SUBNET_BRIDGE_GET); + + return bt_mesh_msg_ackd_send(cli->model, &ctx, &msg, !status ? NULL : &rsp_ctx); } int bt_mesh_brg_cfg_cli_subnet_bridge_set(uint16_t net_idx, uint16_t addr, enum bt_mesh_subnet_bridge_state val, enum bt_mesh_subnet_bridge_state *status) { - return 0; + BT_MESH_MODEL_BUF_DEFINE(msg, OP_SUBNET_BRIDGE_SET, 1); + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); + const struct bt_mesh_msg_rsp_ctx rsp_ctx = { + .ack = &cli->ack_ctx, + .op = OP_SUBNET_BRIDGE_STATUS, + .user_data = status, + .timeout = msg_timeout, + }; + + bt_mesh_model_msg_init(&msg, OP_SUBNET_BRIDGE_SET); + net_buf_simple_add_u8(&msg, (uint8_t)val); + + return bt_mesh_msg_ackd_send(cli->model, &ctx, &msg, !status ? NULL : &rsp_ctx); } int bt_mesh_brg_cfg_cli_bridging_table_size_get(uint16_t net_idx, uint16_t addr, uint16_t *size) { - return 0; + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_SIZE_GET, 0); + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); + const struct bt_mesh_msg_rsp_ctx rsp_ctx = { + .ack = &cli->ack_ctx, + .op = OP_BRIDGING_TABLE_SIZE_STATUS, + .user_data = size, + .timeout = msg_timeout, + }; + + bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_SIZE_GET); + + return bt_mesh_msg_ackd_send(cli->model, &ctx, &msg, !size ? NULL : &rsp_ctx); } -int bt_mesh_brg_cfg_cli_bridging_table_add(uint16_t net_idx, uint16_t addr, uint8_t directions, - uint16_t net_idx1, uint16_t net_idx2, - uint16_t addr1, uint16_t addr2, +int bt_mesh_brg_cfg_cli_bridging_table_add(uint16_t net_idx, uint16_t addr, + struct bt_mesh_bridging_table_entry *entry, struct bt_mesh_bridging_table_status *rsp) { - return 0; + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_ADD, 8); + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); + const struct bt_mesh_msg_rsp_ctx rsp_ctx = { + .ack = &cli->ack_ctx, + .op = OP_BRIDGING_TABLE_STATUS, + .user_data = rsp, + .timeout = msg_timeout, + }; + + if (entry->addr1 == entry->addr2) { + LOG_ERR("addr1 and addr2 shall have different values."); + return -EINVAL; + } else if (!BT_MESH_ADDR_IS_UNICAST(entry->addr1)) { + LOG_ERR("addr1 shall be a unicast address."); + return -EINVAL; + } else if (entry->directions == 0x01 && (entry->addr2 == BT_MESH_ADDR_UNASSIGNED || + entry->addr2 == BT_MESH_ADDR_ALL_NODES)) { + LOG_ERR("For direction 0x01: addr2 shall not be unassigned or the all-nodes fixed " + "group address."); + return -EINVAL; + } else if (entry->directions == 0x02 && !BT_MESH_ADDR_IS_UNICAST(entry->addr2)) { + LOG_ERR("For direction 0x02: addr2 shall be a unicast address."); + return -EINVAL; + } + + bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_ADD); + net_buf_simple_add_u8(&msg, entry->directions); + key_idx_pack_pair(&msg, entry->net_idx1, entry->net_idx2); + net_buf_simple_add_le16(&msg, entry->addr1); + net_buf_simple_add_le16(&msg, entry->addr2); + + return bt_mesh_msg_ackd_send(cli->model, &ctx, &msg, !rsp ? NULL : &rsp_ctx); } int bt_mesh_brg_cfg_cli_bridging_table_remove(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2, struct bt_mesh_bridging_table_status *rsp) { - return 0; + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_REMOVE, 7); + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); + const struct bt_mesh_msg_rsp_ctx rsp_ctx = { + .ack = &cli->ack_ctx, + .op = OP_BRIDGING_TABLE_STATUS, + .user_data = rsp, + .timeout = msg_timeout, + }; + + if (!(addr1 == BT_MESH_ADDR_UNASSIGNED || BT_MESH_ADDR_IS_UNICAST(addr1))) { + LOG_ERR("addr1 shall be a unicast address or unassigned."); + return -EINVAL; + } else if (addr2 == BT_MESH_ADDR_ALL_NODES) { + LOG_ERR("addr2 shall not be the all-nodes fixed group address."); + return -EINVAL; + } + + bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_REMOVE); + key_idx_pack_pair(&msg, net_idx1, net_idx2); + net_buf_simple_add_le16(&msg, addr1); + net_buf_simple_add_le16(&msg, addr2); + + return bt_mesh_msg_ackd_send(cli->model, &ctx, &msg, !rsp ? NULL : &rsp_ctx); } int bt_mesh_brg_cfg_cli_bridged_subnets_get(uint16_t net_idx, uint16_t addr, @@ -66,12 +306,48 @@ int bt_mesh_brg_cfg_cli_bridged_subnets_get(uint16_t net_idx, uint16_t addr, uint8_t start_idx, struct bt_mesh_bridged_subnets_list *rsp) { - return 0; + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGED_SUBNETS_GET, 3); + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); + const struct bt_mesh_msg_rsp_ctx rsp_ctx = { + .ack = &cli->ack_ctx, + .op = OP_BRIDGED_SUBNETS_LIST, + .user_data = rsp, + .timeout = msg_timeout, + }; + + bt_mesh_model_msg_init(&msg, OP_BRIDGED_SUBNETS_GET); + net_buf_simple_add_le16(&msg, (filter_net_idx.filter | filter_net_idx.net_idx << 4)); + net_buf_simple_add_u8(&msg, start_idx); + + return bt_mesh_msg_ackd_send(cli->model, &ctx, &msg, !rsp ? NULL : &rsp_ctx); } int bt_mesh_brg_cfg_cli_bridging_table_get(uint16_t net_idx, uint16_t addr, uint16_t net_idx1, uint16_t net_idx2, uint16_t start_idx, struct bt_mesh_bridging_table_list *rsp) { - return 0; + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_GET, 5); + struct bt_mesh_msg_ctx ctx = BT_MESH_MSG_CTX_INIT_DEV(net_idx, addr); + const struct bt_mesh_msg_rsp_ctx rsp_ctx = { + .ack = &cli->ack_ctx, + .op = OP_BRIDGING_TABLE_LIST, + .user_data = rsp, + .timeout = msg_timeout, + }; + + bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_GET); + key_idx_pack_pair(&msg, net_idx1, net_idx2); + net_buf_simple_add_le16(&msg, start_idx); + + return bt_mesh_msg_ackd_send(cli->model, &ctx, &msg, !rsp ? NULL : &rsp_ctx); +} + +int32_t bt_mesh_brg_cfg_cli_timeout_get(void) +{ + return msg_timeout; +} + +void bt_mesh_brg_cfg_cli_timeout_set(int32_t timeout) +{ + msg_timeout = timeout; } diff --git a/subsys/bluetooth/mesh/foundation.h b/subsys/bluetooth/mesh/foundation.h index 8a9beef642e8b3e..a71c1f44700047e 100644 --- a/subsys/bluetooth/mesh/foundation.h +++ b/subsys/bluetooth/mesh/foundation.h @@ -122,6 +122,19 @@ #define OP_SOL_PDU_RPL_ITEM_CLEAR_UNACKED BT_MESH_MODEL_OP_2(0x80, 0x79) #define OP_SOL_PDU_RPL_ITEM_STATUS BT_MESH_MODEL_OP_2(0x80, 0x7a) +#define OP_SUBNET_BRIDGE_GET BT_MESH_MODEL_OP_2(0x80, 0xb1) +#define OP_SUBNET_BRIDGE_SET BT_MESH_MODEL_OP_2(0x80, 0xb2) +#define OP_SUBNET_BRIDGE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xb3) +#define OP_BRIDGING_TABLE_ADD BT_MESH_MODEL_OP_2(0x80, 0xb4) +#define OP_BRIDGING_TABLE_REMOVE BT_MESH_MODEL_OP_2(0x80, 0xb5) +#define OP_BRIDGING_TABLE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xb6) +#define OP_BRIDGED_SUBNETS_GET BT_MESH_MODEL_OP_2(0x80, 0xb7) +#define OP_BRIDGED_SUBNETS_LIST BT_MESH_MODEL_OP_2(0x80, 0xb8) +#define OP_BRIDGING_TABLE_GET BT_MESH_MODEL_OP_2(0x80, 0xb9) +#define OP_BRIDGING_TABLE_LIST BT_MESH_MODEL_OP_2(0x80, 0xba) +#define OP_BRIDGING_TABLE_SIZE_GET BT_MESH_MODEL_OP_2(0x80, 0xbb) +#define OP_BRIDGING_TABLE_SIZE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xbc) + #define STATUS_SUCCESS 0x00 #define STATUS_INVALID_ADDRESS 0x01 #define STATUS_INVALID_MODEL 0x02 From 50a4c2d17a91ed2845004e312a11a669f923de6a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?H=C3=A5vard=20Reierstad?= Date: Tue, 30 Jul 2024 14:58:22 +0200 Subject: [PATCH 118/269] Bluetooth: Mesh: Add brg_cfg_cli commands to shell MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds the Bridge Configuration Client commands to Mesh shell. Unifies documentation for shell Kconfig options. Signed-off-by: Håvard Reierstad --- doc/connectivity/bluetooth/api/mesh/shell.rst | 74 ++++++ subsys/bluetooth/mesh/shell/CMakeLists.txt | 2 + subsys/bluetooth/mesh/shell/Kconfig | 13 +- subsys/bluetooth/mesh/shell/brg_cfg.c | 241 ++++++++++++++++++ tests/bluetooth/mesh_shell/src/main.c | 7 + 5 files changed, 334 insertions(+), 3 deletions(-) create mode 100644 subsys/bluetooth/mesh/shell/brg_cfg.c diff --git a/doc/connectivity/bluetooth/api/mesh/shell.rst b/doc/connectivity/bluetooth/api/mesh/shell.rst index 707f2c8a8ab9323..4ef1b4a0701b6d2 100644 --- a/doc/connectivity/bluetooth/api/mesh/shell.rst +++ b/doc/connectivity/bluetooth/api/mesh/shell.rst @@ -1788,6 +1788,80 @@ a Config Composition Data Status message, and reading the metadata of the model * ``Offset``: Offset within the page. +Bridge Configuration Client +--------------------------- + +The Bridge Configuration Client model is an optional Bluetooth Mesh model that can be enabled through the +:kconfig:option:`CONFIG_BT_MESH_BRG_CFG_CLI` configuration option. The model provides functionality +for configuring the subnet bridge functionality of a mesh node. + +``mesh models brg_cfg bridge-get`` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Get the current Subnet Bridge state. + +``mesh models brg_cfg bridge-set `` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Set the Subnet Bridge state. + + * ``State``: Disable or enable the Subnet Bridge functionality. + +``mesh models brg_cfg table-size-get`` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Get the current size of the Bridging Table. + +``mesh models brg_cfg table-add `` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Add an entry to the Bridging Table. + + * ``Directions``: Allowed directions for the bridged traffic. Valid values are: + + * ``0x01``: Bridging is allowed only for messages with ``Addr1`` as the source address and ``Addr2`` as the destination address. + * ``0x02``: Bridging is allowed in both directions. + + * ``NetIdx1``: NetKey index of the first subnet. + * ``NetIdx2``: NetKey index of the second subnet. + * ``Addr1``: Address of the node in the first subnet. + * ``Addr2``: Address of the node in the second subnet. + +``mesh models brg_cfg table-remove `` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Remove an entry from the Bridging Table. + + * ``NetIdx1``: NetKey index of the first subnet. + * ``NetIdx2``: NetKey index of the second subnet. + * ``Addr1``: Address of the node in the first subnet. + * ``Addr2``: Address of the node in the second subnet. + +``mesh models brg_cfg subnets-get `` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Get a filtered set of NetKey index pairs extracted from the Bridging Table. + + * ``Filter``: Filter to be applied when reporting pairs of NetKey indexes extracted from the Bridging Table. Allowed values: + + * ``0x00``: Report all pairs. + * ``0x01``: Report pairs in which the NetKey index of the first subnet matches ``NetIdx``. + * ``0x02``: Report pairs in which the NetKey index of the second subnet matches ``NetIdx``. + * ``0x03``: Report pairs in which one of the NetKey indexes matches ``NetIdx``. + + * ``NetIdx``: NetKey index of any of the subnets. + * ``StartIdx``: Start offset in units of pairs of NetKey indexes to read. + +``mesh models brg_cfg table-get `` +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + + Get a list of addresses and allowed traffic directions of the Bridging Table entries. + + * ``NetIdx1``: NetKey index of the first subnet. + * ``NetIdx2``: NetKey index of the second subnet. + * ``StartIdx``: Start offset to read in units of Bridging Table state entries. + + Configuration database ====================== diff --git a/subsys/bluetooth/mesh/shell/CMakeLists.txt b/subsys/bluetooth/mesh/shell/CMakeLists.txt index b751c3d212a237b..e90e554284693e6 100644 --- a/subsys/bluetooth/mesh/shell/CMakeLists.txt +++ b/subsys/bluetooth/mesh/shell/CMakeLists.txt @@ -34,3 +34,5 @@ zephyr_library_sources_ifdef(CONFIG_BT_MESH_SHELL_DFD_SRV dfd.c) zephyr_library_sources_ifdef(CONFIG_BT_MESH_OD_PRIV_PROXY_CLI od_priv_proxy.c) zephyr_library_sources_ifdef(CONFIG_BT_MESH_SOL_PDU_RPL_CLI sol_pdu_rpl.c) + +zephyr_library_sources_ifdef(CONFIG_BT_MESH_SHELL_BRG_CFG_CLI brg_cfg.c) diff --git a/subsys/bluetooth/mesh/shell/Kconfig b/subsys/bluetooth/mesh/shell/Kconfig index 46671c3bfaa50a2..cda2219324371fd 100644 --- a/subsys/bluetooth/mesh/shell/Kconfig +++ b/subsys/bluetooth/mesh/shell/Kconfig @@ -50,7 +50,7 @@ config BT_MESH_SHELL_TEST This option enables support for test mesh shell commands. config BT_MESH_SHELL_HEALTH_SRV_INSTANCE - bool "Support for shell Health Server model instance" + bool "Support for shell Health Server instance" depends on BT_MESH_SHELL_TEST help This option enables Health Server model instance in the @@ -67,14 +67,21 @@ config BT_MESH_SHELL_GATT_PROXY This option enables support for GATT Proxy shell commands. config BT_MESH_SHELL_HEALTH_CLI - bool "Support for Health Client Model shell commands" + bool "Support for Health Client shell commands" depends on BT_MESH_HEALTH_CLI default y help This option enables support of Health Client shell commands. +config BT_MESH_SHELL_BRG_CFG_CLI + bool "Support for Bridge Configuration Client shell commands" + depends on BT_MESH_BRG_CFG_CLI + default y + help + This option enables support of Bridge Configuration Client shell commands. + config BT_MESH_SHELL_CFG_CLI - bool "Support for Configuration Client Model shell commands" + bool "Support for Configuration Client shell commands" depends on BT_MESH_CFG_CLI default y help diff --git a/subsys/bluetooth/mesh/shell/brg_cfg.c b/subsys/bluetooth/mesh/shell/brg_cfg.c new file mode 100644 index 000000000000000..41fb503b9f61b7e --- /dev/null +++ b/subsys/bluetooth/mesh/shell/brg_cfg.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include "mesh/foundation.h" +#include "utils.h" + +static int cmd_subnet_bridge_get(const struct shell *sh, size_t argc, char *argv[]) +{ + enum bt_mesh_subnet_bridge_state rsp; + int err; + + err = bt_mesh_brg_cfg_cli_subnet_bridge_get(bt_mesh_shell_target_ctx.net_idx, + bt_mesh_shell_target_ctx.dst, &rsp); + if (err) { + shell_error(sh, "Failed to send Subnet Bridge Get (err %d)", err); + return -ENOEXEC; + } + + shell_print(sh, "Subnet Bridge State: %s", + (rsp == BT_MESH_SUBNET_BRIDGE_ENABLED) ? "Enabled" : "Disabled"); + return 0; +} + +static int cmd_subnet_bridge_set(const struct shell *sh, size_t argc, char *argv[]) +{ + enum bt_mesh_subnet_bridge_state set, rsp; + int err = 0; + + set = shell_strtobool(argv[1], 0, &err) ? BT_MESH_SUBNET_BRIDGE_ENABLED : + BT_MESH_SUBNET_BRIDGE_DISABLED; + + if (err) { + shell_warn(sh, "Unable to parse input string argument"); + return err; + } + + err = bt_mesh_brg_cfg_cli_subnet_bridge_set(bt_mesh_shell_target_ctx.net_idx, + bt_mesh_shell_target_ctx.dst, set, &rsp); + if (err) { + shell_error(sh, "Failed to send Subnet Bridge Set (err %d)", err); + return -ENOEXEC; + } + + shell_print(sh, "Subnet Bridge State: %s", + (rsp == BT_MESH_SUBNET_BRIDGE_ENABLED) ? "Enabled" : "Disabled"); + return 0; +} + +static int cmd_bridging_table_size_get(const struct shell *sh, size_t argc, char *argv[]) +{ + uint16_t rsp; + int err; + + err = bt_mesh_brg_cfg_cli_bridging_table_size_get(bt_mesh_shell_target_ctx.net_idx, + bt_mesh_shell_target_ctx.dst, &rsp); + if (err) { + shell_error(sh, "Failed to send Bridging Table Size Get (err %d)", err); + return -ENOEXEC; + } + + shell_print(sh, "Bridging Table Size: %u", rsp); + return 0; +} + +static int cmd_bridging_table_add(const struct shell *sh, size_t argc, char *argv[]) +{ + struct bt_mesh_bridging_table_entry entry; + struct bt_mesh_bridging_table_status rsp; + int err = 0; + + entry.directions = shell_strtoul(argv[1], 0, &err); + entry.net_idx1 = shell_strtoul(argv[2], 0, &err); + entry.net_idx2 = shell_strtoul(argv[3], 0, &err); + entry.addr1 = shell_strtoul(argv[4], 0, &err); + entry.addr2 = shell_strtoul(argv[5], 0, &err); + if (err) { + shell_warn(sh, "Unable to parse input string argument"); + return err; + } + + err = bt_mesh_brg_cfg_cli_bridging_table_add(bt_mesh_shell_target_ctx.net_idx, + bt_mesh_shell_target_ctx.dst, &entry, &rsp); + if (err) { + shell_error(sh, "Failed to send Bridging Table Add (err %d)", err); + return -ENOEXEC; + } + + if (rsp.status) { + shell_print(sh, "Bridging Table Add failed with status 0x%02x", rsp.status); + } else { + shell_print(sh, "Bridging Table Add was successful."); + } + return 0; +} + +static int cmd_bridging_table_remove(const struct shell *sh, size_t argc, char *argv[]) +{ + uint16_t net_idx1, net_idx2, addr1, addr2; + struct bt_mesh_bridging_table_status rsp; + int err = 0; + + net_idx1 = shell_strtoul(argv[1], 0, &err); + net_idx2 = shell_strtoul(argv[2], 0, &err); + addr1 = shell_strtoul(argv[3], 0, &err); + addr2 = shell_strtoul(argv[4], 0, &err); + if (err) { + shell_warn(sh, "Unable to parse input string argument"); + return err; + } + + err = bt_mesh_brg_cfg_cli_bridging_table_remove(bt_mesh_shell_target_ctx.net_idx, + bt_mesh_shell_target_ctx.dst, net_idx1, + net_idx2, addr1, addr2, &rsp); + if (err) { + shell_error(sh, "Failed to send Bridging Table Remove (err %d)", err); + return -ENOEXEC; + } + + if (rsp.status) { + shell_print(sh, "Bridging Table Remove failed with status 0x%02x", rsp.status); + } else { + shell_print(sh, "Bridging Table Remove was successful."); + } + return 0; +} + +static int cmd_bridged_subnets_get(const struct shell *sh, size_t argc, char *argv[]) +{ + struct bt_mesh_filter_netkey filter_net_idx; + uint8_t start_idx; + struct bt_mesh_bridged_subnets_list rsp; + int err = 0; + + filter_net_idx.filter = shell_strtoul(argv[1], 0, &err); + filter_net_idx.net_idx = shell_strtoul(argv[2], 0, &err); + start_idx = shell_strtoul(argv[3], 0, &err); + if (err) { + shell_warn(sh, "Unable to parse input string argument"); + return err; + } + + err = bt_mesh_brg_cfg_cli_bridged_subnets_get(bt_mesh_shell_target_ctx.net_idx, + bt_mesh_shell_target_ctx.dst, filter_net_idx, + start_idx, &rsp); + if (err) { + shell_error(sh, "Failed to send Bridged Subnets Get (err %d)", err); + return -ENOEXEC; + } + + shell_print(sh, "Bridged Subnets List:"); + shell_print(sh, "\tfilter: %02x", rsp.net_idx_filter.filter); + shell_print(sh, "\tnet_idx: %04x", rsp.net_idx_filter.net_idx); + shell_print(sh, "\tstart_idx: %u", rsp.start_idx); + if (rsp.list) { + uint16_t net_idx1, net_idx2; + int i = 0; + + while (rsp.list->len) { + key_idx_unpack_pair(rsp.list, &net_idx1, &net_idx2); + shell_print(sh, "\tEntry %d:", i++); + shell_print(sh, "\t\tnet_idx1: 0x%04x, net_idx2: 0x%04x", net_idx1, + net_idx2); + } + } + return 0; +} + +static int cmd_bridging_table_get(const struct shell *sh, size_t argc, char *argv[]) +{ + uint16_t net_idx1, net_idx2, start_idx; + struct bt_mesh_bridging_table_list rsp; + int err = 0; + + net_idx1 = shell_strtoul(argv[1], 0, &err); + net_idx2 = shell_strtoul(argv[2], 0, &err); + start_idx = shell_strtoul(argv[3], 0, &err); + if (err) { + shell_warn(sh, "Unable to parse input string argument"); + return err; + } + + err = bt_mesh_brg_cfg_cli_bridging_table_get(bt_mesh_shell_target_ctx.net_idx, + bt_mesh_shell_target_ctx.dst, net_idx1, + net_idx2, start_idx, &rsp); + if (err) { + shell_error(sh, "Failed to send Bridging Table Get (err %d)", err); + return -ENOEXEC; + } + + if (rsp.status) { + shell_print(sh, "Bridging Table Get failed with status 0x%02x", rsp.status); + } else { + shell_print(sh, "Bridging Table List:"); + shell_print(sh, "\tstatus: %02x", rsp.status); + shell_print(sh, "\tnet_idx1: %04x", rsp.net_idx1); + shell_print(sh, "\tnet_idx2: %04x", rsp.net_idx2); + shell_print(sh, "\tstart_idx: %u", rsp.start_idx); + if (rsp.list) { + uint16_t addr1, addr2; + uint8_t directions; + int i = 0; + + while (rsp.list->len) { + addr1 = net_buf_simple_pull_le16(rsp.list); + addr2 = net_buf_simple_pull_le16(rsp.list); + directions = net_buf_simple_pull_u8(rsp.list); + shell_print(sh, "\tEntry %d:", i++); + shell_print(sh, + "\t\taddr1: 0x%04x, addr2: 0x%04x, directions: 0x%02x", + addr1, addr2, directions); + } + } + } + return 0; +} + +SHELL_STATIC_SUBCMD_SET_CREATE( + brg_cfg_cmds, + SHELL_CMD_ARG(bridge-get, NULL, NULL, cmd_subnet_bridge_get, 1, 0), + SHELL_CMD_ARG(bridge-set, NULL, "", cmd_subnet_bridge_set, 2, 0), + SHELL_CMD_ARG(table-size-get, NULL, NULL, cmd_bridging_table_size_get, 1, 0), + SHELL_CMD_ARG(table-add, NULL, " ", + cmd_bridging_table_add, 6, 0), + SHELL_CMD_ARG(table-remove, NULL, " ", + cmd_bridging_table_remove, 5, 0), + SHELL_CMD_ARG(subnets-get, NULL, " ", cmd_bridged_subnets_get, + 4, 0), + SHELL_CMD_ARG(table-get, NULL, " ", cmd_bridging_table_get, + 4, 0), + SHELL_SUBCMD_SET_END); + +SHELL_SUBCMD_ADD((mesh, models), brg, &brg_cfg_cmds, "Bridge Configuration Cli commands", + bt_mesh_shell_mdl_cmds_help, 1, 1); diff --git a/tests/bluetooth/mesh_shell/src/main.c b/tests/bluetooth/mesh_shell/src/main.c index 2428b38a19f6252..e2afbd183c114d0 100644 --- a/tests/bluetooth/mesh_shell/src/main.c +++ b/tests/bluetooth/mesh_shell/src/main.c @@ -41,6 +41,10 @@ static struct bt_mesh_od_priv_proxy_cli od_priv_proxy_cli; struct bt_mesh_large_comp_data_cli large_comp_data_cli; #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) +static struct bt_mesh_brg_cfg_cli brg_cfg_cli; +#endif + BT_MESH_SHELL_HEALTH_PUB_DEFINE(health_pub); static const struct bt_mesh_model root_models[] = { @@ -106,6 +110,9 @@ static const struct bt_mesh_model root_models[] = { #if defined(CONFIG_BT_MESH_OD_PRIV_PROXY_SRV) BT_MESH_MODEL_OD_PRIV_PROXY_SRV, #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) + BT_MESH_MODEL_BRG_CFG_CLI(&brg_cfg_cli), +#endif }; static const struct bt_mesh_elem elements[] = { From 8210d2da1b550f291fa9f95b397f5e5ac75d5402 Mon Sep 17 00:00:00 2001 From: Omkar Kulkarni Date: Tue, 30 Jul 2024 17:48:35 +0200 Subject: [PATCH 119/269] Bluetooth: Mesh: Populate Bridge Config Server Adds implementation for the Bridge Configuration Server model. Updates `brg_cfg` module to add sanity check for bt_mesh_brg_cfg_tbl_remove() API. Also, updates the unit test accordingly. Adds documentation for the Bridge Configuration Server model Signed-off-by: Omkar Kulkarni --- .../bluetooth/api/mesh/brg_cfg_srv.rst | 29 ++ subsys/bluetooth/mesh/brg_cfg.c | 19 +- subsys/bluetooth/mesh/brg_cfg.h | 7 +- subsys/bluetooth/mesh/brg_cfg_srv.c | 285 +++++++++++++++++- tests/bluetooth/mesh/brg/src/main.c | 36 ++- 5 files changed, 365 insertions(+), 11 deletions(-) diff --git a/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst b/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst index 124cd76ca7e01d0..68aa43a15e30806 100644 --- a/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst +++ b/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst @@ -3,6 +3,35 @@ Bridge Configuration Server ########################### +The Bridge Configuration Server model is a foundation model defined by the Bluetooth Mesh +specification. It is an optional model, enabled with the +:kconfig:option:`CONFIG_BT_MESH_BRG_CFG_SRV` configuration option. This model extends +the :ref:`bluetooth_mesh_models_cfg_srv` model. + +The Bridge Configuration Server model was introduced in the Bluetooth Mesh Protocol Specification +version 1.1, and is used for supporting and configuring the Subnet Bridge feature. + +The Bridge Configuration Server model relies on a :ref:`bluetooth_mesh_models_brg_cfg_cli` to +configure it. The Bridge Configuration Server model only accepts messages encrypted with the node’s +device key. + +If present, the Bridge Configuration Server model must be instantiated on the primary element. + +The Bridge Configuration Server model provides access to the following three states: + +* **Subnet Bridge state**: This state enables or disables the Subnet Bridge feature on a node. When + the Subnet Bridge feature is enabled on a node, the node can transfer received messages from one + subnet to another as specified by the Bridging Table state. + +* **Bridging Table state**: This state holds the bridging table. This table is used to check if + incoming messages can be bridged from one subnet to another. The maximum number of rows supported + by the Bridging Table state can be configured using the + :kconfig:option:`CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX` configuration option. + +* **Bridging Table Size state**: This state reports the maximum number of rows supported by the + Bridging Table state. This is a read-only state. + + API reference ************* diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c index 8cfa0139512f86a..5771962a015bfba 100644 --- a/subsys/bluetooth/mesh/brg_cfg.c +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -199,7 +199,7 @@ int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx { /* Sanity checks */ if (!BT_MESH_ADDR_IS_UNICAST(addr1) || net_idx1 == net_idx2 || addr1 == addr2 || - net_idx1 > 0x03FF || net_idx2 > 0x03FF) { + net_idx1 > BT_MESH_BRG_CFG_KEY_INDEX_MAX || net_idx2 > BT_MESH_BRG_CFG_KEY_INDEX_MAX) { return -EINVAL; } @@ -267,18 +267,29 @@ void bt_mesh_brg_cfg_tbl_foreach_subnet(uint16_t src, uint16_t dst, uint16_t net } } -void bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, +int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2) { #if IS_ENABLED(CONFIG_BT_SETTINGS) bool store = false; #endif + /* Sanity checks */ + if ((!BT_MESH_ADDR_IS_UNICAST(addr1) && addr1 != BT_MESH_ADDR_UNASSIGNED) || + addr2 == BT_MESH_ADDR_ALL_NODES) { + return -EINVAL; + } + + if (net_idx1 == net_idx2 || net_idx1 > BT_MESH_BRG_CFG_KEY_INDEX_MAX || + net_idx2 > BT_MESH_BRG_CFG_KEY_INDEX_MAX) { + return -EINVAL; + } + /* Iterate over items and set matching row to 0, if nothing exist, or nothing matches, then * it is success (similar to add) */ if (bt_mesh_brg_cfg_row_cnt == 0) { - return; + return 0; } for (int i = 0; i < bt_mesh_brg_cfg_row_cnt; i++) { @@ -304,4 +315,6 @@ void bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t a bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); } #endif + + return 0; } diff --git a/subsys/bluetooth/mesh/brg_cfg.h b/subsys/bluetooth/mesh/brg_cfg.h index 28364398de38145..033572e9496774f 100644 --- a/subsys/bluetooth/mesh/brg_cfg.h +++ b/subsys/bluetooth/mesh/brg_cfg.h @@ -8,6 +8,11 @@ #define ZEPHYR_SUBSYS_BLUETOOTH_MESH_BRG_CFG_H_ /** These are internal APIs. They do not sanitize input params. */ + +#define BT_MESH_BRG_CFG_KEY_INDEX_MAX 0x0FFF + +#define BT_MESH_BRG_CFG_NKEY_PRHB_FLT_MASK 0x000C + enum bt_mesh_brg_cfg_dir { /* Value is prohibited. */ BT_MESH_BRG_CFG_DIR_PROHIBITED = 0, @@ -48,7 +53,7 @@ int bt_mesh_brg_cfg_tbl_get(const struct bt_mesh_brg_cfg_row **rows); int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2); -void bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, +int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2); typedef void (*bt_mesh_brg_cfg_cb_t)(uint16_t new_netidx, void *user_data); diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c index bd5ced50abdff2b..e2a501d3bbbc4ee 100644 --- a/subsys/bluetooth/mesh/brg_cfg_srv.c +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -5,13 +5,295 @@ */ #include +#include #include "brg_cfg.h" +#include "foundation.h" +#include "subnet.h" #define LOG_LEVEL CONFIG_BT_MESH_MODEL_LOG_LEVEL #include LOG_MODULE_REGISTER(bt_mesh_brg_cfg_srv); +static void bridge_status_send(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx) +{ + BT_MESH_MODEL_BUF_DEFINE(msg, OP_SUBNET_BRIDGE_STATUS, 1); + + bt_mesh_model_msg_init(&msg, OP_SUBNET_BRIDGE_STATUS); + net_buf_simple_add_u8(&msg, bt_mesh_brg_cfg_enable_get() ? 1 : 0); + + if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { + LOG_ERR("Brg Status send failed"); + } +} + +static int subnet_bridge_get(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + bridge_status_send(model, ctx); + + return 0; +} + +static int subnet_bridge_set(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + uint8_t enable = net_buf_simple_pull_u8(buf); + + if (enable > BT_MESH_SUBNET_BRIDGE_ENABLED) { + return -EINVAL; + } + + bt_mesh_brg_cfg_enable_set(enable); + bridge_status_send(model, ctx); + + return 0; +} + +static void bridging_table_status_send(const struct bt_mesh_model *model, + struct bt_mesh_msg_ctx *ctx, uint8_t status, + struct bt_mesh_bridging_table_entry *entry) +{ + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_STATUS, 9); + + bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_STATUS); + net_buf_simple_add_u8(&msg, status); + net_buf_simple_add_u8(&msg, entry->directions); + key_idx_pack_pair(&msg, entry->net_idx1, entry->net_idx2); + net_buf_simple_add_le16(&msg, entry->addr1); + net_buf_simple_add_le16(&msg, entry->addr2); + + if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { + LOG_ERR("Brg Tbl Status send failed"); + } +} + +static bool netkey_check(uint16_t net_idx1, uint16_t net_idx2) +{ + return bt_mesh_subnet_get(net_idx1) && bt_mesh_subnet_get(net_idx2); +} + +static int bridging_table_add(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + struct bt_mesh_bridging_table_entry entry; + uint8_t status = STATUS_SUCCESS; + + entry.directions = net_buf_simple_pull_u8(buf); + key_idx_unpack_pair(buf, &entry.net_idx1, &entry.net_idx2); + entry.addr1 = net_buf_simple_pull_le16(buf); + entry.addr2 = net_buf_simple_pull_le16(buf); + + if (!netkey_check(entry.net_idx1, entry.net_idx2)) { + status = STATUS_INVALID_NETKEY; + goto add_respond; + } + + int err = bt_mesh_brg_cfg_tbl_add(entry.directions, entry.net_idx1, entry.net_idx2, + entry.addr1, entry.addr2); + if (err == -ENOMEM) { + status = STATUS_INSUFF_RESOURCES; + } else if (err) { + /* Per spec, do not respond if parameters values are invalid. */ + return err; + } + +add_respond: + + bridging_table_status_send(model, ctx, status, &entry); + + return 0; +} + +static int bridging_table_remove(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + struct bt_mesh_bridging_table_entry entry; + uint8_t status = STATUS_SUCCESS; + + key_idx_unpack_pair(buf, &entry.net_idx1, &entry.net_idx2); + entry.addr1 = net_buf_simple_pull_le16(buf); + entry.addr2 = net_buf_simple_pull_le16(buf); + + if (!netkey_check(entry.net_idx1, entry.net_idx2)) { + entry.directions = 0; + status = STATUS_INVALID_NETKEY; + goto rmv_respond; + } + + int err = bt_mesh_brg_cfg_tbl_remove(entry.net_idx1, entry.net_idx2, entry.addr1, + entry.addr2); + + /* Per spec, do not respond if parameters values are invalid. */ + if (err) { + return err; + } + +rmv_respond: + + bridging_table_status_send(model, ctx, status, &entry); + + return 0; +} + +static int bridged_subnets_get(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGED_SUBNETS_LIST, + BT_MESH_TX_SDU_MAX - BT_MESH_MODEL_OP_LEN(OP_BRIDGED_SUBNETS_LIST)); + bt_mesh_model_msg_init(&msg, OP_BRIDGED_SUBNETS_LIST); + + const struct bt_mesh_brg_cfg_row *brg_tbl; + int rows = bt_mesh_brg_cfg_tbl_get(&brg_tbl); + int16_t net_idx_filter = net_buf_simple_pull_le16(buf); + + if (net_idx_filter & BT_MESH_BRG_CFG_NKEY_PRHB_FLT_MASK) { + return -EINVAL; + } + + struct bt_mesh_filter_netkey filter_net_idx; + + filter_net_idx.filter = net_idx_filter & BIT_MASK(2); + filter_net_idx.net_idx = (net_idx_filter >> 4) & BIT_MASK(12); + + uint8_t start_id = net_buf_simple_pull_u8(buf); + + net_buf_simple_add_le16(&msg, net_idx_filter); + net_buf_simple_add_u8(&msg, start_id); + + uint8_t cnt = 0; + uint16_t net_idx1, net_idx2; + + for (int i = 0; i < rows; i++) { + net_idx1 = brg_tbl[i].net_idx1; + net_idx2 = brg_tbl[i].net_idx2; + + switch (filter_net_idx.filter) { + /* Report pair of NetKeys from the table, starting from start_id. */ + case 0: + if (i >= start_id) { + key_idx_pack_pair(&msg, net_idx1, net_idx2); + } + break; + + /* Report pair of NetKeys in which (NetKeyIndex1) matches the net_idx */ + case 1: + if (net_idx1 == filter_net_idx.net_idx) { + if (cnt >= start_id) { + key_idx_pack_pair(&msg, net_idx1, net_idx2); + } + cnt++; + } + break; + + /* Report pair of NetKeys in which (NetKeyIndex2) matches the net_idx */ + case 2: + if (net_idx2 == filter_net_idx.net_idx) { + if (cnt >= start_id) { + key_idx_pack_pair(&msg, net_idx1, net_idx2); + } + cnt++; + } + break; + + /* Report pair of NetKeys in which (NetKeyIndex1 or NetKeyIndex2) matches the + * net_idx + */ + case 3: + if (net_idx1 == filter_net_idx.net_idx || + net_idx2 == filter_net_idx.net_idx) { + if (cnt >= start_id) { + key_idx_pack_pair(&msg, net_idx1, net_idx2); + } + cnt++; + } + break; + + default: + CODE_UNREACHABLE; + } + } + + if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { + LOG_ERR("Brg Subnet List send failed"); + } + + return 0; +} + +static int bridging_table_get(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_LIST, + BT_MESH_TX_SDU_MAX - BT_MESH_MODEL_OP_LEN(OP_BRIDGING_TABLE_LIST)); + uint8_t status = STATUS_SUCCESS; + uint16_t net_idx1, net_idx2; + + bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_LIST); + + key_idx_unpack_pair(buf, &net_idx1, &net_idx2); + + uint16_t start_id = net_buf_simple_pull_le16(buf); + + if (!netkey_check(net_idx1, net_idx2)) { + status = STATUS_INVALID_NETKEY; + } + + net_buf_simple_add_u8(&msg, status); + key_idx_pack_pair(&msg, net_idx1, net_idx2); + net_buf_simple_add_le16(&msg, start_id); + + if (status != STATUS_SUCCESS) { + goto tbl_get_respond; + } + + int cnt = 0; + const struct bt_mesh_brg_cfg_row *brg_tbl; + int rows = bt_mesh_brg_cfg_tbl_get(&brg_tbl); + + for (int i = 0; i < rows; i++) { + if (brg_tbl[i].net_idx1 == net_idx1 && brg_tbl[i].net_idx2 == net_idx2) { + if (cnt >= start_id) { + net_buf_simple_add_le16(&msg, brg_tbl[i].addr1); + net_buf_simple_add_le16(&msg, brg_tbl[i].addr2); + net_buf_simple_add_u8(&msg, brg_tbl[i].direction); + } + cnt++; + } + + } + +tbl_get_respond: + if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { + LOG_ERR("Brg Tbl List send failed"); + } + + return 0; +} + +static int bridging_table_size_get(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, + struct net_buf_simple *buf) +{ + BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_SIZE_STATUS, 2); + bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_SIZE_STATUS); + + net_buf_simple_add_le16(&msg, CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX); + + if (bt_mesh_model_send(model, ctx, &msg, NULL, NULL)) { + LOG_ERR("Brg Tbl Size Status send failed"); + } + + return 0; +} + + const struct bt_mesh_model_op _bt_mesh_brg_cfg_srv_op[] = { + { OP_SUBNET_BRIDGE_GET, BT_MESH_LEN_EXACT(0), subnet_bridge_get }, + { OP_SUBNET_BRIDGE_SET, BT_MESH_LEN_EXACT(1), subnet_bridge_set }, + { OP_BRIDGING_TABLE_ADD, BT_MESH_LEN_EXACT(8), bridging_table_add }, + { OP_BRIDGING_TABLE_REMOVE, BT_MESH_LEN_EXACT(7), bridging_table_remove }, + { OP_BRIDGED_SUBNETS_GET, BT_MESH_LEN_EXACT(3), bridged_subnets_get }, + { OP_BRIDGING_TABLE_GET, BT_MESH_LEN_EXACT(5), bridging_table_get }, + { OP_BRIDGING_TABLE_SIZE_GET, BT_MESH_LEN_EXACT(0), bridging_table_size_get }, BT_MESH_MODEL_OP_END, }; @@ -21,11 +303,10 @@ static int brg_cfg_srv_init(const struct bt_mesh_model *model) bt_mesh_model_find(bt_mesh_model_elem(model), BT_MESH_MODEL_ID_CFG_SRV); if (config_srv == NULL) { - LOG_ERR("Bridge Configuration Server only allowed in primary element"); + LOG_ERR("Not on primary element"); return -EINVAL; } - bt_mesh_model_extend(model, config_srv); return 0; diff --git a/tests/bluetooth/mesh/brg/src/main.c b/tests/bluetooth/mesh/brg/src/main.c index 8f6fe6d276a419d..30b848503d9ca8c 100644 --- a/tests/bluetooth/mesh/brg/src/main.c +++ b/tests/bluetooth/mesh/brg/src/main.c @@ -93,8 +93,11 @@ static void check_delete_all_bt_entries(void) BT_MESH_SETTINGS_BRG_PENDING); } - bt_mesh_brg_cfg_tbl_remove(test_vector[i].net_idx1, test_vector[i].net_idx2, - test_vector[i].addr1, test_vector[i].addr2); + int err = bt_mesh_brg_cfg_tbl_remove(test_vector[i].net_idx1, + test_vector[i].net_idx2, test_vector[i].addr1, + test_vector[i].addr2); + + zassert_equal(err, 0); } } @@ -129,13 +132,36 @@ ZTEST(bt_mesh_brg_cfg, test_basic_functionality_storage) check_bt_mesh_brg_cfg_tbl_reset(); check_fill_all_bt_entries(); - /* Test remove entries matching netkey1, and netkey2 */ + int err; uint16_t net_idx1 = test_vector[TEST_VECT_SZ - 1].net_idx1; uint16_t net_idx2 = test_vector[TEST_VECT_SZ - 1].net_idx2; uint16_t addr1 = BT_MESH_ADDR_UNASSIGNED; - uint16_t addr2 = BT_MESH_ADDR_UNASSIGNED; - bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + /* Try removing entries with invalid params */ + uint16_t addr2 = BT_MESH_ADDR_ALL_NODES; + + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + zassert_equal(err, -EINVAL); + + addr2 = BT_MESH_ADDR_UNASSIGNED; + addr1 = BT_MESH_ADDR_RELAYS; + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + zassert_equal(err, -EINVAL); + + addr1 = BT_MESH_ADDR_UNASSIGNED; + net_idx1 = 4096; + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + zassert_equal(err, -EINVAL); + + net_idx1 = test_vector[TEST_VECT_SZ - 1].net_idx1; + net_idx2 = 4096; + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + zassert_equal(err, -EINVAL); + + /* Test remove entries matching netkey1, and netkey2 */ + net_idx2 = test_vector[TEST_VECT_SZ - 1].net_idx2; + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + zassert_equal(err, 0); const struct bt_mesh_brg_cfg_row *brg_tbl; int n = bt_mesh_brg_cfg_tbl_get(&brg_tbl); From fc4576ce3f0bd380c7010359a39e159418de7ebb Mon Sep 17 00:00:00 2001 From: Omkar Kulkarni Date: Mon, 12 Aug 2024 21:27:05 +0200 Subject: [PATCH 120/269] Bluetooth: Mesh: Add bridging functionality Adds subnet bridging functionality to the network layer. Also fixes brg_cfg_srv for minor issues to get it working. Signed-off-by: Omkar Kulkarni --- include/zephyr/bluetooth/mesh/brg_cfg_srv.h | 4 +- subsys/bluetooth/mesh/Kconfig | 12 +++++- subsys/bluetooth/mesh/brg_cfg_srv.c | 8 ++++ subsys/bluetooth/mesh/net.c | 43 +++++++++++++++++++++ 4 files changed, 63 insertions(+), 4 deletions(-) diff --git a/include/zephyr/bluetooth/mesh/brg_cfg_srv.h b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h index b642cc78b42a0f1..d1ba71e250f6231 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg_srv.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h @@ -32,8 +32,8 @@ extern "C" { NULL, NULL, &bt_mesh_brg_cfg_srv_cb) /** @cond INTERNAL_HIDDEN */ -extern const struct bt_mesh_model_op bt_mesh_brg_cfg_srv_op[]; -extern const struct bt_mesh_model_cb bt_mesh_brg_cfg_srv_cb; +extern const struct bt_mesh_model_op _bt_mesh_brg_cfg_srv_op[]; +extern const struct bt_mesh_model_cb _bt_mesh_brg_cfg_srv_cb; /** @endcond */ /** diff --git a/subsys/bluetooth/mesh/Kconfig b/subsys/bluetooth/mesh/Kconfig index 63dbc4abfe02e27..384033f79083e84 100644 --- a/subsys/bluetooth/mesh/Kconfig +++ b/subsys/bluetooth/mesh/Kconfig @@ -664,12 +664,20 @@ menu "Replay Protection List" config BT_MESH_CRPL int "Maximum capacity of the replay protection list" + default 26 if BT_MESH_BRG_CFG_SRV default 10 range 2 $(UINT16_MAX) help - This options specifies the maximum capacity of the replay + This option specifies the maximum capacity of the replay protection list. This option is similar to the network message - cache size, but has a different purpose. + cache size, but has a purpose of preventing replay attacks. + + Note that: To ensure sufficient space in CRPL for normal node + operations and as specified by other Bluetooth specification + requirements, when subnet bridge functionality is enabled on a node, + you should increase the CRPL capacity in your project configuration + file with the number of bridging table entries + (BT_MESH_BRG_TABLE_ITEMS_MAX) specified for the project as a minimum. choice BT_MESH_RPL_STORAGE_MODE prompt "Replay protection list storage mode" diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c index e2a501d3bbbc4ee..94ca0dcfa9fd488 100644 --- a/subsys/bluetooth/mesh/brg_cfg_srv.c +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -6,6 +6,7 @@ #include #include +#include "access.h" #include "brg_cfg.h" #include "foundation.h" #include "subnet.h" @@ -307,6 +308,13 @@ static int brg_cfg_srv_init(const struct bt_mesh_model *model) return -EINVAL; } + /* + * Bridge Configuration Server model security is device key based and only the local + * device key is allowed to access this model. + */ + model->keys[0] = BT_MESH_KEY_DEV_LOCAL; + model->rt->flags |= BT_MESH_MOD_DEVKEY_ONLY; + bt_mesh_model_extend(model, config_srv); return 0; diff --git a/subsys/bluetooth/mesh/net.c b/subsys/bluetooth/mesh/net.c index d69ecf99edfa26c..a73e9fce4dd3a16 100644 --- a/subsys/bluetooth/mesh/net.c +++ b/subsys/bluetooth/mesh/net.c @@ -36,6 +36,7 @@ #include "cfg.h" #include "statistic.h" #include "sar_cfg_internal.h" +#include "brg_cfg.h" #define LOG_LEVEL CONFIG_BT_MESH_NET_LOG_LEVEL #include @@ -54,6 +55,13 @@ LOG_MODULE_REGISTER(bt_mesh_net); #define SRC(pdu) (sys_get_be16(&(pdu)[5])) #define DST(pdu) (sys_get_be16(&(pdu)[7])) +/* Information needed for bridging the network PDUs */ +struct pdu_ctx { + struct net_buf_simple *sbuf; + struct net_buf_simple_state *state; + struct bt_mesh_net_rx *rx; +}; + /* Mesh network information for persistent storage. */ struct net_val { uint16_t primary_addr; @@ -756,6 +764,19 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, bt_mesh_adv_unref(adv); } +#if IS_ENABLED(CONFIG_BT_MESH_BRG_CFG_SRV) +static void bt_mesh_sbr_check_cb(uint16_t new_net_idx, void *user_data) +{ + struct pdu_ctx *ctx = (struct pdu_ctx *)user_data; + + if (new_net_idx < BT_MESH_BRG_CFG_NETIDX_NOMATCH) { + ctx->rx->ctx.net_idx = new_net_idx; + net_buf_simple_restore(ctx->sbuf, ctx->state); + bt_mesh_net_relay(ctx->sbuf, ctx->rx); + } +} +#endif + void bt_mesh_net_header_parse(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx) { @@ -893,6 +914,28 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, net_buf_simple_restore(&buf, &state); bt_mesh_net_relay(&buf, &rx); } + +#if IS_ENABLED(CONFIG_BT_MESH_BRG_CFG_SRV) + struct pdu_ctx tx_ctx = { + .sbuf = &buf, + .state = &state, + .rx = &rx, + }; + + /* Bridge the traffic if enabled */ + if (!bt_mesh_brg_cfg_enable_get()) { + return; + } + + struct bt_mesh_rpl *rpl = NULL; + + if (bt_mesh_rpl_check(&rx, &rpl)) { + return; + } + + bt_mesh_brg_cfg_tbl_foreach_subnet(rx.ctx.addr, rx.ctx.recv_dst, rx.ctx.net_idx, + bt_mesh_sbr_check_cb, &tx_ctx); +#endif } static void ivu_refresh(struct k_work *work) From 21fa5c81d280f3977e57ffacf3bff1a2969b763b Mon Sep 17 00:00:00 2001 From: Ingar Kulbrandstad Date: Fri, 16 Aug 2024 15:11:09 +0200 Subject: [PATCH 121/269] Bluetooth: Tester: Mesh: Added support for Bridge client/server Added support for the Bridge Configuration client and server to the tester application. Signed-off-by: Ingar Kulbrandstad --- .../ICS_Zephyr_Bluetooth_Host.pts | 8 + tests/bluetooth/tester/overlay-mesh.conf | 2 + tests/bluetooth/tester/src/btp/btp_mesh.h | 51 +++++ tests/bluetooth/tester/src/btp_mesh.c | 208 ++++++++++++++++++ 4 files changed, 269 insertions(+) diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts index cded5003f6e58f1..613ae9734e6b942 100644 --- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts +++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts @@ -2545,6 +2545,14 @@ 11
6 + + 11
+ 7 + + + 11
+ 8 + 11
19 diff --git a/tests/bluetooth/tester/overlay-mesh.conf b/tests/bluetooth/tester/overlay-mesh.conf index 1609177c5334f57..a9e96686da8aa4c 100644 --- a/tests/bluetooth/tester/overlay-mesh.conf +++ b/tests/bluetooth/tester/overlay-mesh.conf @@ -49,4 +49,6 @@ CONFIG_BT_MESH_OD_PRIV_PROXY_SRV=y CONFIG_BT_MESH_MODEL_EXTENSIONS=y CONFIG_BT_MESH_COMP_PAGE_1=y CONFIG_BT_MESH_COMP_PAGE_2=y +CONFIG_BT_MESH_BRG_CFG_SRV=y +CONFIG_BT_MESH_BRG_CFG_CLI=y CONFIG_SETTINGS=y diff --git a/tests/bluetooth/tester/src/btp/btp_mesh.h b/tests/bluetooth/tester/src/btp/btp_mesh.h index ad1ef1a1f4f75ae..8ad82323d541a21 100644 --- a/tests/bluetooth/tester/src/btp/btp_mesh.h +++ b/tests/bluetooth/tester/src/btp/btp_mesh.h @@ -904,6 +904,57 @@ struct btp_rpr_reprov_remote_cmd { bool comp_change; } __packed; +#define BTP_MESH_SUBNET_BRIDGE_GET 0x62 +struct btp_mesh_subnet_bridge_get_cmd { + uint16_t addr; +} __packed; + +#define BTP_MESH_SUBNET_BRIDGE_SET 0x63 +struct btp_mesh_subnet_bridge_set_cmd { + uint16_t addr; + uint8_t val; +} __packed; + +#define BTP_MESH_BRIDGING_TABLE_ADD 0x64 +struct btp_mesh_bridging_table_add_cmd { + uint16_t addr; + uint8_t directions; + uint16_t net_idx1; + uint16_t net_idx2; + uint16_t addr1; + uint16_t addr2; +} __packed; + +#define BTP_MESH_BRIDGING_TABLE_REMOVE 0x65 +struct btp_mesh_bridging_table_remove_cmd { + uint16_t addr; + uint16_t net_idx1; + uint16_t net_idx2; + uint16_t addr1; + uint16_t addr2; +} __packed; + +#define BTP_MESH_BRIDGED_SUBNETS_GET 0x66 +struct btp_mesh_bridged_subnets_get_cmd { + uint16_t addr; + uint8_t filter; + uint16_t net_idx; + uint8_t start_idx; +} __packed; + +#define BTP_MESH_BRIDGING_TABLE_GET 0x67 +struct btp_mesh_bridging_table_get_cmd { + uint16_t addr; + uint16_t net_idx1; + uint16_t net_idx2; + uint16_t start_idx; +} __packed; + +#define BTP_MESH_BRIDGING_TABLE_SIZE_GET 0x68 +struct btp_mesh_bridging_table_size_get_cmd { + uint16_t addr; +} __packed; + #define BTP_MMDL_DFU_INFO_GET 0x5f struct btp_mmdl_dfu_info_get_cmd { uint8_t limit; diff --git a/tests/bluetooth/tester/src/btp_mesh.c b/tests/bluetooth/tester/src/btp_mesh.c index b036e3b0c241ad8..8041394c215b6ef 100644 --- a/tests/bluetooth/tester/src/btp_mesh.c +++ b/tests/bluetooth/tester/src/btp_mesh.c @@ -1019,6 +1019,10 @@ static uint8_t proxy_solicit(const void *cmd, uint16_t cmd_len, } #endif /* CONFIG_BT_MESH_PROXY_SOLICITATION */ +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) +static struct bt_mesh_brg_cfg_cli brg_cfg_cli; +#endif /* CONFIG_BT_MESH_BRG_CFG_CLI */ + static const struct bt_mesh_model root_models[] = { BT_MESH_MODEL_CFG_SRV, BT_MESH_MODEL_CFG_CLI(&cfg_cli), @@ -1072,6 +1076,12 @@ static const struct bt_mesh_model root_models[] = { #if defined(CONFIG_BT_MESH_OD_PRIV_PROXY_SRV) BT_MESH_MODEL_OD_PRIV_PROXY_SRV, #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_SRV) + BT_MESH_MODEL_BRG_CFG_SRV, +#endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) + BT_MESH_MODEL_BRG_CFG_CLI(&brg_cfg_cli), +#endif }; @@ -1128,6 +1138,12 @@ static const struct bt_mesh_model root_models_alt[] = { #if defined(CONFIG_BT_MESH_OD_PRIV_PROXY_SRV) BT_MESH_MODEL_OD_PRIV_PROXY_SRV, #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_SRV) + BT_MESH_MODEL_BRG_CFG_SRV, +#endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) + BT_MESH_MODEL_BRG_CFG_CLI(&brg_cfg_cli), +#endif }; struct model_data *lookup_model_bound(uint16_t id) @@ -2066,6 +2082,161 @@ static uint8_t models_metadata_get(const void *cmd, uint16_t cmd_len, } #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) +static uint8_t subnet_bridge_get(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_mesh_subnet_bridge_get_cmd *cp = cmd; + enum bt_mesh_subnet_bridge_state state; + int err; + + err = bt_mesh_brg_cfg_cli_subnet_bridge_get(net.net_idx, sys_le16_to_cpu(cp->addr), + &state); + if (err) { + LOG_ERR("err=%d", err); + return BTP_STATUS_FAILED; + } + + LOG_DBG("Subnet Bridge state: %u", state); + + return BTP_STATUS_SUCCESS; +} + +static uint8_t subnet_bridge_set(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_mesh_subnet_bridge_set_cmd *cp = cmd; + enum bt_mesh_subnet_bridge_state state; + int err; + + state = cp->val; + + err = bt_mesh_brg_cfg_cli_subnet_bridge_set(net.net_idx, sys_le16_to_cpu(cp->addr), + state, &state); + if (err) { + LOG_ERR("err=%d", err); + return BTP_STATUS_FAILED; + } + + LOG_DBG("Subnet Bridge state: %u", state); + + return BTP_STATUS_SUCCESS; +} + +static uint8_t bridging_table_add(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_mesh_bridging_table_add_cmd *cp = cmd; + struct bt_mesh_bridging_table_entry entry; + struct bt_mesh_bridging_table_status rp; + int err; + + LOG_DBG(""); + + entry.directions = cp->directions; + entry.net_idx1 = sys_le16_to_cpu(cp->net_idx1); + entry.net_idx2 = sys_le16_to_cpu(cp->net_idx2); + entry.addr1 = sys_le16_to_cpu(cp->addr1); + entry.addr2 = sys_le16_to_cpu(cp->addr2); + + err = bt_mesh_brg_cfg_cli_bridging_table_add(net_key_idx, sys_le16_to_cpu(cp->addr), + &entry, &rp); + if (err) { + LOG_ERR("err=%d", err); + return BTP_STATUS_FAILED; + } + + return BTP_STATUS_SUCCESS; +} + +static uint8_t bridging_table_remove(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_mesh_bridging_table_remove_cmd *cp = cmd; + struct bt_mesh_bridging_table_status rp; + int err; + + LOG_DBG(""); + + err = bt_mesh_brg_cfg_cli_bridging_table_remove(net_key_idx, sys_le16_to_cpu(cp->addr), + sys_le16_to_cpu(cp->net_idx1), + sys_le16_to_cpu(cp->net_idx2), + sys_le16_to_cpu(cp->addr1), + sys_le16_to_cpu(cp->addr2), &rp); + + if (err) { + LOG_ERR("err=%d", err); + return BTP_STATUS_FAILED; + } + + return BTP_STATUS_SUCCESS; +} + +static uint8_t bridged_subnets_get(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_mesh_bridged_subnets_get_cmd *cp = cmd; + struct bt_mesh_filter_netkey filter_net_idx; + struct bt_mesh_bridged_subnets_list rp; + int err; + + LOG_DBG(""); + + filter_net_idx.filter = cp->filter; + filter_net_idx.net_idx = sys_le16_to_cpu(cp->net_idx); + + err = bt_mesh_brg_cfg_cli_bridged_subnets_get(net_key_idx, sys_le16_to_cpu(cp->addr), + filter_net_idx, cp->start_idx, &rp); + if (err) { + LOG_ERR("err=%d", err); + return BTP_STATUS_FAILED; + } + + return BTP_STATUS_SUCCESS; +} + +static uint8_t bridging_table_get(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_mesh_bridging_table_get_cmd *cp = cmd; + struct bt_mesh_bridging_table_list rp; + int err; + + LOG_DBG(""); + + err = bt_mesh_brg_cfg_cli_bridging_table_get(net_key_idx, sys_le16_to_cpu(cp->addr), + sys_le16_to_cpu(cp->net_idx1), + sys_le16_to_cpu(cp->net_idx2), + sys_le16_to_cpu(cp->start_idx), &rp); + if (err) { + LOG_ERR("err=%d", err); + return BTP_STATUS_FAILED; + } + + return BTP_STATUS_SUCCESS; +} + +static uint8_t bridging_table_size_get(const void *cmd, uint16_t cmd_len, + void *rsp, uint16_t *rsp_len) +{ + const struct btp_mesh_bridging_table_size_get_cmd *cp = cmd; + uint16_t size; + int err; + + LOG_DBG(""); + + err = bt_mesh_brg_cfg_cli_bridging_table_size_get(net_key_idx, sys_le16_to_cpu(cp->addr), + &size); + if (err) { + LOG_ERR("err=%d", err); + return BTP_STATUS_FAILED; + } + + return BTP_STATUS_SUCCESS; +} + +#endif + static uint8_t composition_data_get(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { @@ -5142,6 +5313,43 @@ static const struct btp_handler handlers[] = { .func = srpl_clear }, #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) + { + .opcode = BTP_MESH_SUBNET_BRIDGE_GET, + .expect_len = sizeof(struct btp_mesh_subnet_bridge_get_cmd), + .func = subnet_bridge_get + }, + { + .opcode = BTP_MESH_SUBNET_BRIDGE_SET, + .expect_len = sizeof(struct btp_mesh_subnet_bridge_set_cmd), + .func = subnet_bridge_set + }, + { + .opcode = BTP_MESH_BRIDGING_TABLE_ADD, + .expect_len = sizeof(struct btp_mesh_bridging_table_add_cmd), + .func = bridging_table_add + }, + { + .opcode = BTP_MESH_BRIDGING_TABLE_REMOVE, + .expect_len = sizeof(struct btp_mesh_bridging_table_remove_cmd), + .func = bridging_table_remove + }, + { + .opcode = BTP_MESH_BRIDGED_SUBNETS_GET, + .expect_len = sizeof(struct btp_mesh_bridged_subnets_get_cmd), + .func = bridged_subnets_get + }, + { + .opcode = BTP_MESH_BRIDGING_TABLE_GET, + .expect_len = sizeof(struct btp_mesh_bridging_table_get_cmd), + .func = bridging_table_get + }, + { + .opcode = BTP_MESH_BRIDGING_TABLE_SIZE_GET, + .expect_len = sizeof(struct btp_mesh_bridging_table_size_get_cmd), + .func = bridging_table_size_get + }, +#endif #if defined(CONFIG_BT_MESH_PROXY_SOLICITATION) { .opcode = BTP_MESH_PROXY_SOLICIT, From 0e2f8b21cf79f461f632cd68890fd3d5b7e9bc1d Mon Sep 17 00:00:00 2001 From: Ingar Kulbrandstad Date: Tue, 27 Aug 2024 11:48:52 +0200 Subject: [PATCH 122/269] Bluetooth: Mesh: Fixed bugs found in PTS testing Fixed bugs found while running PTS test. Signed-off-by: Ingar Kulbrandstad --- include/zephyr/bluetooth/mesh/brg_cfg_srv.h | 4 ++-- subsys/bluetooth/mesh/brg_cfg.c | 5 ++++- subsys/bluetooth/mesh/brg_cfg_srv.c | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/include/zephyr/bluetooth/mesh/brg_cfg_srv.h b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h index d1ba71e250f6231..271dd37c5f6898e 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg_srv.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h @@ -28,8 +28,8 @@ extern "C" { * @brief Bridge Configuration Server model Composition Data entry. */ #define BT_MESH_MODEL_BRG_CFG_SRV \ - BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_SRV, bt_mesh_brg_cfg_srv_op, \ - NULL, NULL, &bt_mesh_brg_cfg_srv_cb) + BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_SRV, _bt_mesh_brg_cfg_srv_op, \ + NULL, NULL, &_bt_mesh_brg_cfg_srv_cb) /** @cond INTERNAL_HIDDEN */ extern const struct bt_mesh_model_op _bt_mesh_brg_cfg_srv_op[]; diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c index 5771962a015bfba..7d6d487ab03492c 100644 --- a/subsys/bluetooth/mesh/brg_cfg.c +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -303,13 +303,16 @@ int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t ad (addr2 == BT_MESH_ADDR_UNASSIGNED && brg_tbl[i].addr1 == addr1) || (addr1 == BT_MESH_ADDR_UNASSIGNED && brg_tbl[i].addr2 == addr2)) { memset(&brg_tbl[i], 0, sizeof(brg_tbl[i])); - brg_tbl_compact(); #if IS_ENABLED(CONFIG_BT_SETTINGS) store = true; #endif } } } + + /* Compact when all rows have been deleted. */ + brg_tbl_compact(); + #if IS_ENABLED(CONFIG_BT_SETTINGS) if (store) { bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c index 94ca0dcfa9fd488..68a85db0fd71d9e 100644 --- a/subsys/bluetooth/mesh/brg_cfg_srv.c +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -111,12 +111,12 @@ static int bridging_table_remove(const struct bt_mesh_model *model, struct bt_me struct bt_mesh_bridging_table_entry entry; uint8_t status = STATUS_SUCCESS; + entry.directions = 0; key_idx_unpack_pair(buf, &entry.net_idx1, &entry.net_idx2); entry.addr1 = net_buf_simple_pull_le16(buf); entry.addr2 = net_buf_simple_pull_le16(buf); if (!netkey_check(entry.net_idx1, entry.net_idx2)) { - entry.directions = 0; status = STATUS_INVALID_NETKEY; goto rmv_respond; } From e1232a45e21f17eb7e30d20ef571a17b614f82d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stine=20=C3=85kredalen?= Date: Wed, 4 Sep 2024 19:12:06 +0200 Subject: [PATCH 123/269] docs: Bluetooth: Mesh: add Subnet Bridge doc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added high-level documentation for Subnet Bridge, connecting models together and explaining usage. Signed-off-by: Stine Åkredalen --- doc/connectivity/bluetooth/api/mesh.rst | 1 + .../bluetooth/api/mesh/brg_cfg.rst | 160 ++++++++++++++++++ .../bluetooth/api/mesh/brg_cfg_srv.rst | 15 +- 3 files changed, 165 insertions(+), 11 deletions(-) create mode 100644 doc/connectivity/bluetooth/api/mesh/brg_cfg.rst diff --git a/doc/connectivity/bluetooth/api/mesh.rst b/doc/connectivity/bluetooth/api/mesh.rst index 358ba3dc62e1032..404e86018c7a698 100644 --- a/doc/connectivity/bluetooth/api/mesh.rst +++ b/doc/connectivity/bluetooth/api/mesh.rst @@ -24,3 +24,4 @@ Read more about Bluetooth Mesh on the mesh/cfg.rst mesh/statistic.rst mesh/shell.rst + mesh/brg_cfg.rst diff --git a/doc/connectivity/bluetooth/api/mesh/brg_cfg.rst b/doc/connectivity/bluetooth/api/mesh/brg_cfg.rst new file mode 100644 index 000000000000000..b118116f620d82f --- /dev/null +++ b/doc/connectivity/bluetooth/api/mesh/brg_cfg.rst @@ -0,0 +1,160 @@ +.. _bluetooth_mesh_brg_cfg: + +Subnet Bridge +############# + +With Bluetooth Mesh Protocol Specification version 1.1, the Bluetooth Mesh Subnet Bridge feature was +introduced. +This feature allows mesh networks to use subnets for area isolation, but to also allow communication +between specific devices in different, adjacent subnets without compromising security. + +The Bluetooth Mesh Subnet Bridge feature makes it possible for selected nodes in the network to act +as Subnet Bridges, allowing controlled communication by relaying messages between nodes in adjacent +subnets. + +The Subnet Bridge feature includes two models: + +- :ref:`bluetooth_mesh_models_brg_cfg_srv` +- :ref:`bluetooth_mesh_models_brg_cfg_cli` + +The Bridge Configuration Server model is mandatory for supporting the Subnet Bridge feature. +The Bridge Configuration Client model is optional and allows nodes to configure the Subnet Bridge on +other nodes. +These models define the necessary states, messages, and behaviors for configuring and managing the +Subnet Bridge feature. + +The configuration and management of the Subnet Bridge feature are handled using the Bridge +Configuration Server and Client models. +A node implementing the Bridge Configuration Client model can act as a *Configuration Manager* for +the Subnet Bridge feature. + +Concepts +******** + +To get a better understanding of the Subnet Bridge feature and its capabilities, an overview of a +few concepts is needed. + +Subnet +====== + +A subnet is a group of nodes within a mesh network that share a common network key, enabling them to +communicate securely at the network layer. +Each subnet operates independently, with nodes exchanging messages exclusively within that group. +A node may belong to multiple subnets at the same time. + +Subnet Bridge node +================== + +A Subnet Bridge node is a node in a Bluetooth Mesh network that belongs to multiple subnets and has +a Subnet Bridge functionality enabled. Subnet bridging can be performed only by such a node. The +Subnet Bridge node connects the subnets, and allows communication between them by relaying +messages across the subnet groups. + +The Subnet Bridge node has a primary subnet, based on the primary NetKey, which handles the +IV Update procedure and propagates updates to other subnets. +The secondary subnets, on which messages are relayed, are referred to as *bridged subnets*. + +Bridging Table +============== + +The Bridging Table contains the entries for the subnets that are bridged by the node, and is managed +by the Bridge Configuration Server model. + +The maximum number of entries in the bridging table is defined by the +:kconfig:option:`CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX` option, which defaults to the minimum value of +16, with a maximum possible size of 255. + +Enabling or disabling the Subnet Bridge feature +*********************************************** + +The Bridge Configuration Client (or Configuration Manager) can enable or disable the Subnet Bridge +feature on a node by sending a **Subnet Bridge Set** message to the Bridge Configuration +Server model on the target node, using the :c:func:`bt_mesh_brg_cfg_cli_subnet_bridge_set` function. + +Adding or removing subnets +************************** + +The Bridge Configuration Client can add or remove an entry from the Bridging Table by sending a +**Bridging Table Add** or **Bridging Table Remove** message to the Bridge Configuration +Server model on the target node, calling the :c:func:`bt_mesh_brg_cfg_cli_bridging_table_add` or +:c:func:`bt_mesh_brg_cfg_cli_bridging_table_remove` functions. + +.. _bluetooth_mesh_brg_cfg_states: + +Subnet Bridge states +******************** + +The Subnet Bridge has the following states: + +- *Subnet Bridge*: This state indicates whether the Subnet Bridge feature is enabled or disabled on + the node. + The Bridge Configuration Client can retrieve this information by sending a **Subnet Bridge Get** + message to the Bridge Configuration Server using the + :c:func:`bt_mesh_brg_cfg_cli_subnet_bridge_get` function. + +- *Bridging Table*: This state holds the bridging table. The Client can request a list of + entries from a Bridging Table by sending a **Bridging Table Get** message to the target node using + the :c:func:`bt_mesh_brg_cfg_cli_bridging_table_get` function. + + The Client can get a list of subnets currently bridged by a Subnet Bridge by sending a + **Bridged Subnets Get** message to the target Server by calling the + :c:func:`bt_mesh_brg_cfg_cli_bridged_subnets_get` function. + +- *Bridging Table Size*: This state reports the maximum number of entries the Bridging Table can + store. The Client can retrieve this information by sending a **Bridging Table Size Get** message + using the :c:func:`bt_mesh_brg_cfg_cli_bridging_table_size_get` function. + This is a read-only state. + +Subnet bridging and replay protection +************************************* + +The Subnet Bridge feature enables message relaying between subnets and requires effective replay +protection to ensure network security. Key considerations to take into account are described below. + +Relay buffer considerations +=========================== + +When a message is relayed between subnets by a Subnet Bridge, it is allocated from the relay buffer. +To ensure that messages can be retransmitted to all subnetworks, +the :kconfig:option:`CONFIG_BT_MESH_RELAY_BUF_COUNT` option should be increased accordingly. + +However, if the :kconfig:option:`CONFIG_BT_MESH_RELAY` feature is disabled, the messages will be +allocated from the advertising buffer instead. In this case, increase the +:kconfig:option:`CONFIG_BT_MESH_ADV_BUF_COUNT` option to allow for sufficient buffer space. + +Replay protection and Bridging Table +==================================== + +A Subnet Bridge node must implement replay protection for all Access and Transport Control messages +sent to bridged subnets. + +The Replay Protection List (RPL) works with the Bridging Table to ensure security: + +- The Subnet Bridge stores the latest IVISeq for each source address authorized to send messages to + bridged subnets. + +- Messages with an IVISeq less than or equal to the stored value are discarded, while valid messages + update the stored IVISeq before being relayed. + +To ensure proper operation, it is important that the RPL and Bridging Table are synchronized, +as every bridged message must pass through the replay protection mechanism before being relayed. + +.. note:: + + The RPL size should scale with the Bridging Table. As the number of bridged subnets grows, + more source addresses and IVISeq values must be tracked, requiring a larger RPL to maintain + effective replay protection. + +Subnet Bridge and Directed Forwarding +************************************* + +Bluetooth Mesh Directed Forwarding (MDF) enables efficient routing between nodes across subnets by +optimizing relay paths. While MDF can enhance Subnet Bridging by handling path discovery and +forwarding, the current implementation does not support this feature. + +API reference +************* + +This section contains types and defines common to the Bridge Configuration models. + +.. doxygengroup:: bt_mesh_brg_cfg diff --git a/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst b/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst index 68aa43a15e30806..4edae789f4f6c21 100644 --- a/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst +++ b/doc/connectivity/bluetooth/api/mesh/brg_cfg_srv.rst @@ -19,18 +19,11 @@ If present, the Bridge Configuration Server model must be instantiated on the pr The Bridge Configuration Server model provides access to the following three states: -* **Subnet Bridge state**: This state enables or disables the Subnet Bridge feature on a node. When - the Subnet Bridge feature is enabled on a node, the node can transfer received messages from one - subnet to another as specified by the Bridging Table state. - -* **Bridging Table state**: This state holds the bridging table. This table is used to check if - incoming messages can be bridged from one subnet to another. The maximum number of rows supported - by the Bridging Table state can be configured using the - :kconfig:option:`CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX` configuration option. - -* **Bridging Table Size state**: This state reports the maximum number of rows supported by the - Bridging Table state. This is a read-only state. +* Subnet Bridge +* Bridging Table +* Bridging Table Size +For more information about the states, see :ref:`bluetooth_mesh_brg_cfg_states`. API reference ************* From ceba348ca4f6e97622e2340a393ee34ef9cb5852 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Mon, 2 Sep 2024 13:06:15 +0200 Subject: [PATCH 124/269] bluetooth: mesh: brg_cfg: fix restoring bridging table We store only filled up entries, but want to restore the entire table. `bt_mesh_setting_set` fails if the restored length didn't match the provided length. This commit fixes the restoring of the bridging table by allowing to restore any size as long as the stored size is less than the allocated one and it is a multiple of the size of a single entry. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/brg_cfg.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c index 7d6d487ab03492c..3f476d55be907f3 100644 --- a/subsys/bluetooth/mesh/brg_cfg.c +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -68,6 +68,8 @@ BT_MESH_SETTINGS_DEFINE(brg_en, "brg_en", brg_en_set); /* Set function for initializing bridging table rows from values stored in settings. */ static int brg_tbl_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) { + ssize_t len; + if (len_rd == 0) { memset(brg_tbl, 0, sizeof(brg_tbl)); bt_mesh_brg_cfg_row_cnt = 0; @@ -75,14 +77,24 @@ static int brg_tbl_set(const char *name, size_t len_rd, settings_read_cb read_cb return 0; } - int err = bt_mesh_settings_set(read_cb, cb_arg, brg_tbl, sizeof(brg_tbl)); + if (len_rd % sizeof(brg_tbl[0])) { + LOG_ERR("Invalid data size"); + return -EINVAL; + } - if (err) { - LOG_ERR("Failed to set bridging table entries"); - return err; + if (len_rd > sizeof(brg_tbl)) { + LOG_ERR("Too many entries to fit in bridging table"); + return -ENOMEM; + } + + len = read_cb(cb_arg, brg_tbl, sizeof(brg_tbl)); + if (len < 0 || len % sizeof(brg_tbl[0])) { + LOG_ERR("Failed to read bridging table entries (err %zd)", len); + return len < 0 ? len : -EINVAL; } - LOG_DBG("Restored bridging table"); + bt_mesh_brg_cfg_row_cnt = len / sizeof(brg_tbl[0]); + LOG_DBG("Restored %d entries in bridging table", bt_mesh_brg_cfg_row_cnt); return 0; } From f06f69a8b89b18baed2422ade4eb1a880de055b6 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Mon, 2 Sep 2024 13:32:53 +0200 Subject: [PATCH 125/269] bluetooth: mesh: brg_cfg: store tbl when changed only Though nvs backend checks whether the data passed to it is identical to the stored one, this isn't guaranteed by other the settings api. We can also avoid going into the settings subsystem since we know what was actually changed. This commit adds 2 flags that allow to control whether Subnet Bridge or Bridging Table states were changed and skips storing if the certain state was not changed. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/brg_cfg.c | 49 +++++++++++++++++++---------- tests/bluetooth/mesh/brg/src/main.c | 20 +++++------- 2 files changed, 41 insertions(+), 28 deletions(-) diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c index 3f476d55be907f3..c45bb8780ff84d5 100644 --- a/subsys/bluetooth/mesh/brg_cfg.c +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -25,6 +25,15 @@ static uint32_t bt_mesh_brg_cfg_row_cnt; /* Bridging enabled state */ static bool brg_enabled; +enum { + STATE_UPDATED, + TABLE_UPDATED, + BRG_CFG_FLAGS_COUNT, +}; +#if defined(CONFIG_BT_SETTINGS) +static ATOMIC_DEFINE(brg_cfg_flags, BRG_CFG_FLAGS_COUNT); +#endif + static void brg_tbl_compact(void) { int j = 0; @@ -116,6 +125,7 @@ int bt_mesh_brg_cfg_enable_set(bool enable) brg_enabled = enable; #if IS_ENABLED(CONFIG_BT_SETTINGS) + atomic_set_bit(brg_cfg_flags, STATE_UPDATED); bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); #endif return 0; @@ -128,26 +138,29 @@ void bt_mesh_brg_cfg_pending_store(void) char *path_tbl = "bt/mesh/brg_tbl"; int err; - if (brg_enabled) { - err = settings_save_one(path_en, &brg_enabled, sizeof(brg_enabled)); - } else { - err = settings_delete(path_en); - } + if (atomic_test_and_clear_bit(brg_cfg_flags, STATE_UPDATED)) { + if (brg_enabled) { + err = settings_save_one(path_en, &brg_enabled, sizeof(brg_enabled)); + } else { + err = settings_delete(path_en); + } - if (err) { - LOG_ERR("Failed to store %s value", path_en); + if (err) { + LOG_ERR("Failed to store %s value", path_en); + } } + if (atomic_test_and_clear_bit(brg_cfg_flags, TABLE_UPDATED)) { + if (bt_mesh_brg_cfg_row_cnt) { + err = settings_save_one(path_tbl, &brg_tbl, + bt_mesh_brg_cfg_row_cnt * sizeof(brg_tbl[0])); + } else { + err = settings_delete(path_tbl); + } - if (bt_mesh_brg_cfg_row_cnt) { - err = settings_save_one(path_tbl, &brg_tbl, - bt_mesh_brg_cfg_row_cnt * sizeof(brg_tbl[0])); - } else { - err = settings_delete(path_tbl); - } - - if (err) { - LOG_ERR("Failed to store %s value", path_tbl); + if (err) { + LOG_ERR("Failed to store %s value", path_tbl); + } } #endif } @@ -171,6 +184,7 @@ static void brg_tbl_netkey_removed_evt(struct bt_mesh_subnet *sub, enum bt_mesh_ } #if IS_ENABLED(CONFIG_BT_SETTINGS) + atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); #endif } @@ -187,6 +201,7 @@ int bt_mesh_brg_cfg_tbl_reset(void) brg_enabled = false; bt_mesh_brg_cfg_row_cnt = 0; memset(brg_tbl, 0, sizeof(brg_tbl)); + atomic_clear(brg_cfg_flags); #if CONFIG_BT_SETTINGS err = settings_delete("bt/mesh/brg_en"); @@ -256,6 +271,7 @@ int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx store: #if IS_ENABLED(CONFIG_BT_SETTINGS) + atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); #endif @@ -327,6 +343,7 @@ int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t ad #if IS_ENABLED(CONFIG_BT_SETTINGS) if (store) { + atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); } #endif diff --git a/tests/bluetooth/mesh/brg/src/main.c b/tests/bluetooth/mesh/brg/src/main.c index 30b848503d9ca8c..68103c9f14ce29b 100644 --- a/tests/bluetooth/mesh/brg/src/main.c +++ b/tests/bluetooth/mesh/brg/src/main.c @@ -205,8 +205,7 @@ ZTEST(bt_mesh_brg_cfg, test_basic_functionality_storage) } } -static void pending_store_enable_create_expectations(bool *enable_val, - int n, const struct bt_mesh_brg_cfg_row *tbl_val) +static void pending_store_enable_create_expectations(bool *enable_val) { if (*enable_val) { ztest_expect_data(settings_save_one, name, "bt/mesh/brg_en"); @@ -215,7 +214,11 @@ static void pending_store_enable_create_expectations(bool *enable_val, } else { ztest_expect_data(settings_delete, name, "bt/mesh/brg_en"); } +} +static void pending_store_tbl_create_expectations(int n, + const struct bt_mesh_brg_cfg_row *tbl_val) +{ if (n > 0) { ztest_expect_data(settings_save_one, name, "bt/mesh/brg_tbl"); ztest_expect_value(settings_save_one, val_len, @@ -230,16 +233,12 @@ static void pending_store_enable_create_expectations(bool *enable_val, ZTEST(bt_mesh_brg_cfg, test_brg_cfg_en) { int err; - int n; bool val; - const struct bt_mesh_brg_cfg_row *tbl; check_bt_mesh_brg_cfg_tbl_reset(); val = bt_mesh_brg_cfg_enable_get(); - n = bt_mesh_brg_cfg_tbl_get(&tbl); zassert_equal(val, false, NULL); - pending_store_enable_create_expectations(&val, n, tbl); - bt_mesh_brg_cfg_pending_store(); + /* No changed to the states, nothing to check. */ ztest_expect_value(bt_mesh_settings_store_schedule, flag, @@ -247,8 +246,7 @@ ZTEST(bt_mesh_brg_cfg, test_brg_cfg_en) err = bt_mesh_brg_cfg_enable_set(true); zassert_equal(err, 0, NULL); val = bt_mesh_brg_cfg_enable_get(); - n = bt_mesh_brg_cfg_tbl_get(&tbl); - pending_store_enable_create_expectations(&val, n, tbl); + pending_store_enable_create_expectations(&val); bt_mesh_brg_cfg_pending_store(); zassert_equal(bt_mesh_brg_cfg_enable_get(), true, NULL); @@ -258,7 +256,6 @@ ZTEST(bt_mesh_brg_cfg, test_brg_cfg_en) ZTEST(bt_mesh_brg_cfg, test_brg_tbl_pending_store) { int n, err; - bool b_en; struct bt_mesh_brg_cfg_row test_vec = { .direction = BT_MESH_BRG_CFG_DIR_ONEWAY, .net_idx1 = 1, @@ -277,12 +274,11 @@ ZTEST(bt_mesh_brg_cfg, test_brg_tbl_pending_store) const struct bt_mesh_brg_cfg_row *tbl; n = bt_mesh_brg_cfg_tbl_get(&tbl); - b_en = bt_mesh_brg_cfg_enable_get(); zassert_equal(n, 1); zassert_true(tbl); - pending_store_enable_create_expectations(&b_en, 1, &test_vec); + pending_store_tbl_create_expectations(1, &test_vec); bt_mesh_brg_cfg_pending_store(); } From abf02719c458b3e83b3abed571e767fd7fffd655 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Mon, 2 Sep 2024 15:49:04 +0200 Subject: [PATCH 126/269] bluetooth: mesh: rpl: fix rpl for subnet bridge The initial implementation of RPL check for Subnet Bridge wasn't fully correct. It decides whether to relay or not a PDU based on RPL of only received messages. However, the spec section 3.9.8 says: ``` In addition, a Subnet Bridge node shall implement replay protection for all Access and Transport Control messages that are sent to bridged subnets. A Subnet Bridge node shall maintain the most recent IVISeq value for each source address authorized to send messages to bridged subnets. Messages received by the Subnet Bridge node with the IVISeq value less than or equal to the last stored value from that source address shall be discarded immediately upon reception. When a message is retransmitted to a bridged subnet, the stored IVISeq value shall be updated. In this way, bridged subnets are protected against replay attacks from other subnets. ``` This was noticed with MESH/NODE/SBR/NET/BV-02-C test. It passes when PTS misses the message at step 3 and 4, and fails when PTS manages to receive the message. This commit fixes the wrong behavior by removing argument for `bt_mesh_rpl_check` function making store a new message and bypassing `local_match` check in case of Subnet Bridge node. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/net.c | 4 +--- subsys/bluetooth/mesh/proxy_srv.c | 2 +- subsys/bluetooth/mesh/rpl.c | 6 +++--- subsys/bluetooth/mesh/rpl.h | 3 +-- subsys/bluetooth/mesh/transport.c | 4 ++-- tests/bluetooth/mesh/rpl/src/main.c | 16 ++++++++-------- 6 files changed, 16 insertions(+), 19 deletions(-) diff --git a/subsys/bluetooth/mesh/net.c b/subsys/bluetooth/mesh/net.c index a73e9fce4dd3a16..fe7898bbba4b52a 100644 --- a/subsys/bluetooth/mesh/net.c +++ b/subsys/bluetooth/mesh/net.c @@ -927,9 +927,7 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, return; } - struct bt_mesh_rpl *rpl = NULL; - - if (bt_mesh_rpl_check(&rx, &rpl)) { + if (bt_mesh_rpl_check(&rx, NULL, true)) { return; } diff --git a/subsys/bluetooth/mesh/proxy_srv.c b/subsys/bluetooth/mesh/proxy_srv.c index ddd0f35faf734d6..c3b33035a3f5075 100644 --- a/subsys/bluetooth/mesh/proxy_srv.c +++ b/subsys/bluetooth/mesh/proxy_srv.c @@ -277,7 +277,7 @@ static void proxy_cfg(struct bt_mesh_proxy_role *role) rx.local_match = 1U; - if (bt_mesh_rpl_check(&rx, NULL)) { + if (bt_mesh_rpl_check(&rx, NULL, false)) { LOG_WRN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", rx.ctx.addr, rx.ctx.recv_dst, rx.seq); return; diff --git a/subsys/bluetooth/mesh/rpl.c b/subsys/bluetooth/mesh/rpl.c index 1a158df046942c8..213ed7d44794a65 100644 --- a/subsys/bluetooth/mesh/rpl.c +++ b/subsys/bluetooth/mesh/rpl.c @@ -107,7 +107,7 @@ void bt_mesh_rpl_update(struct bt_mesh_rpl *rpl, * by upper logic (access, transport commands) and for receiving the segmented messages. * If a NULL match is given the RPL is immediately updated (used for proxy configuration). */ -bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match) +bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match, bool bridge) { struct bt_mesh_rpl *rpl; int i; @@ -117,8 +117,8 @@ bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match) return false; } - /* The RPL is used only for the local node */ - if (!rx->local_match) { + /* The RPL is used only for the local node or Subnet Bridge. */ + if (!rx->local_match && !bridge) { return false; } diff --git a/subsys/bluetooth/mesh/rpl.h b/subsys/bluetooth/mesh/rpl.h index ceb0d7149e6b21f..39395bb25d13f98 100644 --- a/subsys/bluetooth/mesh/rpl.h +++ b/subsys/bluetooth/mesh/rpl.h @@ -22,8 +22,7 @@ typedef void (*bt_mesh_rpl_func_t)(struct bt_mesh_rpl *rpl, void *user_data); void bt_mesh_rpl_reset(void); -bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, - struct bt_mesh_rpl **match); +bool bt_mesh_rpl_check(struct bt_mesh_net_rx *rx, struct bt_mesh_rpl **match, bool bridge); void bt_mesh_rpl_clear(void); void bt_mesh_rpl_update(struct bt_mesh_rpl *rpl, struct bt_mesh_net_rx *rx); diff --git a/subsys/bluetooth/mesh/transport.c b/subsys/bluetooth/mesh/transport.c index b9c0babd4ea3d35..122fe42dc3006ed 100644 --- a/subsys/bluetooth/mesh/transport.c +++ b/subsys/bluetooth/mesh/transport.c @@ -1035,7 +1035,7 @@ static int trans_unseg(struct net_buf_simple *buf, struct bt_mesh_net_rx *rx, return -EBADMSG; } - if (bt_mesh_rpl_check(rx, &rpl)) { + if (bt_mesh_rpl_check(rx, &rpl, false)) { LOG_WRN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", rx->ctx.addr, rx->ctx.recv_dst, rx->seq); return -EINVAL; @@ -1349,7 +1349,7 @@ static int trans_seg(struct net_buf_simple *buf, struct bt_mesh_net_rx *net_rx, return -EBADMSG; } - if (bt_mesh_rpl_check(net_rx, &rpl)) { + if (bt_mesh_rpl_check(net_rx, &rpl, false)) { LOG_WRN("Replay: src 0x%04x dst 0x%04x seq 0x%06x", net_rx->ctx.addr, net_rx->ctx.recv_dst, net_rx->seq); return -EINVAL; diff --git a/tests/bluetooth/mesh/rpl/src/main.c b/tests/bluetooth/mesh/rpl/src/main.c index bd3980d172ccc09..d7a6d11c0a9c1f5 100644 --- a/tests/bluetooth/mesh/rpl/src/main.c +++ b/tests/bluetooth/mesh/rpl/src/main.c @@ -59,7 +59,7 @@ static void prepare_rpl_and_start_reset(void) ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_RPL_PENDING); - zassert_false(bt_mesh_rpl_check(&msg, NULL)); + zassert_false(bt_mesh_rpl_check(&msg, NULL, false)); } /* settings_save_one() will be triggered for all new entries when @@ -79,7 +79,7 @@ static void prepare_rpl_and_start_reset(void) .seq = test_vector[i].seq, }; - zassert_true(bt_mesh_rpl_check(&msg, NULL)); + zassert_true(bt_mesh_rpl_check(&msg, NULL, false)); } /* Simulate IVI Update. This should only flip flags. The actual storing will happen @@ -108,9 +108,9 @@ static void check_entries_from_test_vector(void) if (test_vector[i].old_iv) { ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_RPL_PENDING); - zassert_false(bt_mesh_rpl_check(&msg, NULL)); + zassert_false(bt_mesh_rpl_check(&msg, NULL, false)); } else { - zassert_true(bt_mesh_rpl_check(&msg, NULL)); + zassert_true(bt_mesh_rpl_check(&msg, NULL, false)); } } } @@ -128,7 +128,7 @@ static void check_empty_entries(int cnt) ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_RPL_PENDING); - zassert_false(bt_mesh_rpl_check(&msg, NULL)); + zassert_false(bt_mesh_rpl_check(&msg, NULL, false)); } /* Check that there are no more empty entries in RPL. */ @@ -138,7 +138,7 @@ static void check_empty_entries(int cnt) .old_iv = false, .seq = 1024, }; - zassert_true(bt_mesh_rpl_check(&msg, NULL)); + zassert_true(bt_mesh_rpl_check(&msg, NULL, false)); } static void check_op(int op) @@ -149,7 +149,7 @@ static void check_op(int op) } else { ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_RPL_PENDING); - zassert_false(bt_mesh_rpl_check(&recv_msg, NULL)); + zassert_false(bt_mesh_rpl_check(&recv_msg, NULL, false)); settings_func_cnt--; settings_func = 0; @@ -466,6 +466,6 @@ ZTEST(bt_mesh_rpl_reset, test_rpl_check_on_save_new_entry) .old_iv = entry.old_iv, .seq = entry.seq }; - zassert_true(bt_mesh_rpl_check(&msg, NULL)); + zassert_true(bt_mesh_rpl_check(&msg, NULL, false)); check_empty_entries(EMPTY_ENTRIES_CNT - 1); } From 96cb386f39add12fd88cc608c2c2b1737532fc74 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Tue, 3 Sep 2024 15:42:46 +0200 Subject: [PATCH 127/269] bluetooth: mesh: brg_cfg: add constants for directions Add constants for directions so that they can be used in the subnet bridge client api. Signed-off-by: Pavel Vasilyev --- include/zephyr/bluetooth/mesh/brg_cfg.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/zephyr/bluetooth/mesh/brg_cfg.h b/include/zephyr/bluetooth/mesh/brg_cfg.h index 8cdc59ce76d98f5..470625609ac697c 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg.h @@ -28,6 +28,11 @@ enum bt_mesh_subnet_bridge_state { BT_MESH_SUBNET_BRIDGE_ENABLED, }; +/* Briding from Addr1 to Addr2. */ +#define BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY 1 +/* Bidirectional briging between Addr1 and Addr2. */ +#define BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY 2 + /** Bridging Table state entry corresponding to a entry in the Bridging Table. */ struct bt_mesh_bridging_table_entry { /** Allowed directions for the bridged traffic (or bridged traffic not allowed) */ From 957bb4754a461b3ad9b5fe21879cb68fd8e0afdb Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Tue, 3 Sep 2024 15:49:42 +0200 Subject: [PATCH 128/269] bluetooth: mesh: net: use subnet credentials when relaying When relaying a Network PDU to another subnet, we need to update sub field of rx structure so that correct credentials are used. We also need to update NID field of the Network PDU. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/net.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/subsys/bluetooth/mesh/net.c b/subsys/bluetooth/mesh/net.c index fe7898bbba4b52a..2ae7c96603f12ce 100644 --- a/subsys/bluetooth/mesh/net.c +++ b/subsys/bluetooth/mesh/net.c @@ -683,7 +683,7 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if) } static void bt_mesh_net_relay(struct net_buf_simple *sbuf, - struct bt_mesh_net_rx *rx) + struct bt_mesh_net_rx *rx, bool update_nid) { const struct bt_mesh_net_cred *cred; struct bt_mesh_adv *adv; @@ -730,8 +730,8 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, LOG_DBG("Relaying packet. TTL is now %u", TTL(adv->b.data)); - /* Update NID if RX or RX was with friend credentials */ - if (rx->friend_cred) { + /* Update NID if RX, RX was with friend credentials or when bridging the message */ + if (rx->friend_cred || update_nid) { adv->b.data[0] &= 0x80; /* Clear everything except IVI */ adv->b.data[0] |= cred->nid; } @@ -765,14 +765,30 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, } #if IS_ENABLED(CONFIG_BT_MESH_BRG_CFG_SRV) +static bool find_subnet_cb(struct bt_mesh_subnet *sub, void *cb_data) +{ + uint16_t *net_idx = cb_data; + + return sub->net_idx == *net_idx; +} + static void bt_mesh_sbr_check_cb(uint16_t new_net_idx, void *user_data) { struct pdu_ctx *ctx = (struct pdu_ctx *)user_data; if (new_net_idx < BT_MESH_BRG_CFG_NETIDX_NOMATCH) { + struct bt_mesh_subnet *subnet = bt_mesh_subnet_find(find_subnet_cb, &new_net_idx); + + if (!subnet) { + LOG_ERR("Failed to find subnet 0x%04x", new_net_idx); + return; + } + + ctx->rx->sub = subnet; ctx->rx->ctx.net_idx = new_net_idx; + net_buf_simple_restore(ctx->sbuf, ctx->state); - bt_mesh_net_relay(ctx->sbuf, ctx->rx); + bt_mesh_net_relay(ctx->sbuf, ctx->rx, true); } } #endif @@ -912,7 +928,7 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, if (!BT_MESH_ADDR_IS_UNICAST(rx.ctx.recv_dst) || (!rx.local_match && !rx.friend_match)) { net_buf_simple_restore(&buf, &state); - bt_mesh_net_relay(&buf, &rx); + bt_mesh_net_relay(&buf, &rx, false); } #if IS_ENABLED(CONFIG_BT_MESH_BRG_CFG_SRV) From 6c94d3bec6308d3e534e1072b2563974ff2f3fcb Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Wed, 4 Sep 2024 12:56:23 +0200 Subject: [PATCH 129/269] bluetooth: mesh: net: bridge traffic regardless of relay state The Subnet Bridge node must bridge traffic regardless of the Relay state. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/net.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/subsys/bluetooth/mesh/net.c b/subsys/bluetooth/mesh/net.c index 2ae7c96603f12ce..16ccdfe0e0a27ca 100644 --- a/subsys/bluetooth/mesh/net.c +++ b/subsys/bluetooth/mesh/net.c @@ -683,7 +683,7 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if) } static void bt_mesh_net_relay(struct net_buf_simple *sbuf, - struct bt_mesh_net_rx *rx, bool update_nid) + struct bt_mesh_net_rx *rx, bool bridge) { const struct bt_mesh_net_cred *cred; struct bt_mesh_adv *adv; @@ -695,6 +695,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, if (rx->net_if == BT_MESH_NET_IF_ADV && !rx->friend_cred && + !bridge && bt_mesh_relay_get() != BT_MESH_RELAY_ENABLED && bt_mesh_gatt_proxy_get() != BT_MESH_GATT_PROXY_ENABLED && bt_mesh_priv_gatt_proxy_get() != BT_MESH_PRIV_GATT_PROXY_ENABLED) { @@ -731,7 +732,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, LOG_DBG("Relaying packet. TTL is now %u", TTL(adv->b.data)); /* Update NID if RX, RX was with friend credentials or when bridging the message */ - if (rx->friend_cred || update_nid) { + if (rx->friend_cred || bridge) { adv->b.data[0] &= 0x80; /* Clear everything except IVI */ adv->b.data[0] |= cred->nid; } @@ -756,7 +757,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, bt_mesh_proxy_relay(adv, rx->ctx.recv_dst); } - if (relay_to_adv(rx->net_if) || rx->friend_cred) { + if (relay_to_adv(rx->net_if) || rx->friend_cred || bridge) { bt_mesh_adv_send(adv, NULL, NULL); } From 76f015b61f69007bb28a2a99cf5bb2d5e96e4e2a Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Thu, 5 Sep 2024 15:41:23 +0200 Subject: [PATCH 130/269] bluetooth: mesh: brg_cfg_cli: copy buf in synchronous api When a synchronous API is used, the content of `buf` will not be valid by the time the thread that called the synchronous API is woken up again. Therefore, the simplest way to solve this is when a user allocates the buffer which will be filled up with the content of the buffer passed to the model callback. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/brg_cfg_cli.c | 24 ++++++++++++++++++++++-- subsys/bluetooth/mesh/shell/brg_cfg.c | 12 ++++++++++-- tests/bluetooth/tester/src/btp_mesh.c | 10 ++++++++++ 3 files changed, 42 insertions(+), 4 deletions(-) diff --git a/subsys/bluetooth/mesh/brg_cfg_cli.c b/subsys/bluetooth/mesh/brg_cfg_cli.c index 3a35885520e732d..54cafd552629a8e 100644 --- a/subsys/bluetooth/mesh/brg_cfg_cli.c +++ b/subsys/bluetooth/mesh/brg_cfg_cli.c @@ -89,7 +89,16 @@ static int bridged_subnets_list(const struct bt_mesh_model *model, struct bt_mes if (bt_mesh_msg_ack_ctx_match(&cli->ack_ctx, OP_BRIDGED_SUBNETS_LIST, ctx->addr, (void **)&rsp)) { - *rsp = subnets_list; + rsp->net_idx_filter = subnets_list.net_idx_filter; + rsp->start_idx = subnets_list.start_idx; + + if (rsp->list) { + size_t to_copy; + + to_copy = MIN(net_buf_simple_tailroom(rsp->list), buf->len); + net_buf_simple_add_mem(rsp->list, buf->data, to_copy); + } + bt_mesh_msg_ack_ctx_rx(&cli->ack_ctx); } @@ -117,7 +126,18 @@ static int bridging_table_list(const struct bt_mesh_model *model, struct bt_mesh if (bt_mesh_msg_ack_ctx_match(&cli->ack_ctx, OP_BRIDGING_TABLE_LIST, ctx->addr, (void **)&rsp)) { - *rsp = table_list; + rsp->status = table_list.status; + rsp->net_idx1 = table_list.net_idx1; + rsp->net_idx2 = table_list.net_idx2; + rsp->start_idx = table_list.start_idx; + + if (rsp->list) { + size_t to_copy; + + to_copy = MIN(net_buf_simple_tailroom(rsp->list), (buf->len / 5) * 5); + net_buf_simple_add_mem(rsp->list, buf->data, to_copy); + } + bt_mesh_msg_ack_ctx_rx(&cli->ack_ctx); } diff --git a/subsys/bluetooth/mesh/shell/brg_cfg.c b/subsys/bluetooth/mesh/shell/brg_cfg.c index 41fb503b9f61b7e..81a218788a2a212 100644 --- a/subsys/bluetooth/mesh/shell/brg_cfg.c +++ b/subsys/bluetooth/mesh/shell/brg_cfg.c @@ -136,9 +136,13 @@ static int cmd_bridged_subnets_get(const struct shell *sh, size_t argc, char *ar { struct bt_mesh_filter_netkey filter_net_idx; uint8_t start_idx; - struct bt_mesh_bridged_subnets_list rsp; + struct bt_mesh_bridged_subnets_list rsp = { + .list = NET_BUF_SIMPLE(CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX * 3), + }; int err = 0; + net_buf_simple_init(rsp.list, 0); + filter_net_idx.filter = shell_strtoul(argv[1], 0, &err); filter_net_idx.net_idx = shell_strtoul(argv[2], 0, &err); start_idx = shell_strtoul(argv[3], 0, &err); @@ -176,9 +180,13 @@ static int cmd_bridged_subnets_get(const struct shell *sh, size_t argc, char *ar static int cmd_bridging_table_get(const struct shell *sh, size_t argc, char *argv[]) { uint16_t net_idx1, net_idx2, start_idx; - struct bt_mesh_bridging_table_list rsp; + struct bt_mesh_bridging_table_list rsp = { + .list = NET_BUF_SIMPLE(CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX * 5), + }; int err = 0; + net_buf_simple_init(rsp.list, 0); + net_idx1 = shell_strtoul(argv[1], 0, &err); net_idx2 = shell_strtoul(argv[2], 0, &err); start_idx = shell_strtoul(argv[3], 0, &err); diff --git a/tests/bluetooth/tester/src/btp_mesh.c b/tests/bluetooth/tester/src/btp_mesh.c index 8041394c215b6ef..f913efdebb6507f 100644 --- a/tests/bluetooth/tester/src/btp_mesh.c +++ b/tests/bluetooth/tester/src/btp_mesh.c @@ -2182,6 +2182,11 @@ static uint8_t bridged_subnets_get(const void *cmd, uint16_t cmd_len, LOG_DBG(""); + /* Initialize list ptr to NULL to prevent the client copying response to whatever was + * on the stack where `rp` was allocated. + */ + rp.list = NULL; + filter_net_idx.filter = cp->filter; filter_net_idx.net_idx = sys_le16_to_cpu(cp->net_idx); @@ -2204,6 +2209,11 @@ static uint8_t bridging_table_get(const void *cmd, uint16_t cmd_len, LOG_DBG(""); + /* Initialize list ptr to NULL to prevent the client copying response to whatever was + * on the stack where `rp` was allocated. + */ + rp.list = NULL; + err = bt_mesh_brg_cfg_cli_bridging_table_get(net_key_idx, sys_le16_to_cpu(cp->addr), sys_le16_to_cpu(cp->net_idx1), sys_le16_to_cpu(cp->net_idx2), From f44ee3c50c898144853297dccd0b996d728c1a7d Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Thu, 5 Sep 2024 14:57:11 +0200 Subject: [PATCH 131/269] bluetooth: mesh: adv_ext: resched main adv set if relay doesn't have own If relay feature doesn't have own adv set, it should use the main adv set to send messages. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/adv_ext.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/subsys/bluetooth/mesh/adv_ext.c b/subsys/bluetooth/mesh/adv_ext.c index 2e78f14e426200b..b437e6d91eff998 100644 --- a/subsys/bluetooth/mesh/adv_ext.c +++ b/subsys/bluetooth/mesh/adv_ext.c @@ -360,8 +360,9 @@ void bt_mesh_adv_relay_ready(void) } } - /* Attempt to use the main adv set for the sending of relay messages. */ - if (IS_ENABLED(CONFIG_BT_MESH_ADV_EXT_RELAY_USING_MAIN_ADV_SET)) { + /* Use the main adv set for the sending of relay messages. */ + if (IS_ENABLED(CONFIG_BT_MESH_ADV_EXT_RELAY_USING_MAIN_ADV_SET) || + CONFIG_BT_MESH_RELAY_ADV_SETS == 0) { (void)schedule_send(advs); } } From 945e320e751e46c314fa0105400420a1b245d432 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Thu, 5 Sep 2024 15:42:04 +0200 Subject: [PATCH 132/269] bluetooth: mesh: brg_cfg_srv: check buf tailroom before packing data We must tcheck if buf has enough tailroom to fit another pair of keys or pair addresses with direction. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/brg_cfg_srv.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c index 68a85db0fd71d9e..adfe5de535a51c8 100644 --- a/subsys/bluetooth/mesh/brg_cfg_srv.c +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -168,6 +168,10 @@ static int bridged_subnets_get(const struct bt_mesh_model *model, struct bt_mesh net_idx1 = brg_tbl[i].net_idx1; net_idx2 = brg_tbl[i].net_idx2; + if (net_buf_simple_tailroom(&msg) < 3 + BT_MESH_MIC_SHORT) { + break; + } + switch (filter_net_idx.filter) { /* Report pair of NetKeys from the table, starting from start_id. */ case 0: @@ -254,6 +258,11 @@ static int bridging_table_get(const struct bt_mesh_model *model, struct bt_mesh_ for (int i = 0; i < rows; i++) { if (brg_tbl[i].net_idx1 == net_idx1 && brg_tbl[i].net_idx2 == net_idx2) { if (cnt >= start_id) { + if (net_buf_simple_tailroom(&msg) < 5 + BT_MESH_MIC_SHORT) { + LOG_WRN("Bridging Table List message too large"); + break; + } + net_buf_simple_add_le16(&msg, brg_tbl[i].addr1); net_buf_simple_add_le16(&msg, brg_tbl[i].addr2); net_buf_simple_add_u8(&msg, brg_tbl[i].direction); From dd7b6757f41e29fc642b03d73cff258416aa1d43 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Tue, 10 Sep 2024 13:59:55 +0200 Subject: [PATCH 133/269] bluetooth: mesh: brg_cfg: use IS_ENABLED macro optimally If use `IS_ENABLED` macro inside if statements but not as preprocessor directives, we can always compile the code for settings even if settings are not used. This allows to reduce amount of firmwares we need to build in CI to ensure that code compiles. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/brg_cfg.c | 47 ++++++++++++++------------------- 1 file changed, 20 insertions(+), 27 deletions(-) diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c index c45bb8780ff84d5..c6974b9ede1a4e2 100644 --- a/subsys/bluetooth/mesh/brg_cfg.c +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -30,9 +30,7 @@ enum { TABLE_UPDATED, BRG_CFG_FLAGS_COUNT, }; -#if defined(CONFIG_BT_SETTINGS) static ATOMIC_DEFINE(brg_cfg_flags, BRG_CFG_FLAGS_COUNT); -#endif static void brg_tbl_compact(void) { @@ -48,7 +46,6 @@ static void brg_tbl_compact(void) bt_mesh_brg_cfg_row_cnt--; } -#if IS_ENABLED(CONFIG_BT_SETTINGS) /* Set function for initializing bridging enable state from value stored in settings. */ static int brg_en_set(const char *name, size_t len_rd, settings_read_cb read_cb, void *cb_arg) { @@ -110,7 +107,6 @@ static int brg_tbl_set(const char *name, size_t len_rd, settings_read_cb read_cb /* Define a setting for storing briging table rows */ BT_MESH_SETTINGS_DEFINE(brg_tbl, "brg_tbl", brg_tbl_set); -#endif bool bt_mesh_brg_cfg_enable_get(void) { @@ -124,16 +120,17 @@ int bt_mesh_brg_cfg_enable_set(bool enable) } brg_enabled = enable; -#if IS_ENABLED(CONFIG_BT_SETTINGS) - atomic_set_bit(brg_cfg_flags, STATE_UPDATED); - bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); -#endif + + if (IS_ENABLED(CONFIG_BT_SETTINGS)) { + atomic_set_bit(brg_cfg_flags, STATE_UPDATED); + bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); + } + return 0; } void bt_mesh_brg_cfg_pending_store(void) { -#if CONFIG_BT_SETTINGS char *path_en = "bt/mesh/brg_en"; char *path_tbl = "bt/mesh/brg_tbl"; int err; @@ -162,7 +159,6 @@ void bt_mesh_brg_cfg_pending_store(void) LOG_ERR("Failed to store %s value", path_tbl); } } -#endif } /* Remove the entry from the bridging table that corresponds with the NetKey Index of the removed @@ -183,10 +179,10 @@ static void brg_tbl_netkey_removed_evt(struct bt_mesh_subnet *sub, enum bt_mesh_ } } -#if IS_ENABLED(CONFIG_BT_SETTINGS) - atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); - bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); -#endif + if (IS_ENABLED(CONFIG_BT_SETTINGS)) { + atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); + bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); + } } /* Add event hook for key deletion event */ @@ -203,7 +199,10 @@ int bt_mesh_brg_cfg_tbl_reset(void) memset(brg_tbl, 0, sizeof(brg_tbl)); atomic_clear(brg_cfg_flags); -#if CONFIG_BT_SETTINGS + if (!IS_ENABLED(CONFIG_BT_SETTINGS)) { + return 0; + } + err = settings_delete("bt/mesh/brg_en"); if (err) { @@ -211,7 +210,6 @@ int bt_mesh_brg_cfg_tbl_reset(void) } err = settings_delete("bt/mesh/brg_tbl"); -#endif return err; } @@ -270,10 +268,10 @@ int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx bt_mesh_brg_cfg_row_cnt++; store: -#if IS_ENABLED(CONFIG_BT_SETTINGS) - atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); - bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); -#endif + if (IS_ENABLED(CONFIG_BT_SETTINGS)) { + atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); + bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); + } return 0; } @@ -298,9 +296,8 @@ void bt_mesh_brg_cfg_tbl_foreach_subnet(uint16_t src, uint16_t dst, uint16_t net int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2) { -#if IS_ENABLED(CONFIG_BT_SETTINGS) bool store = false; -#endif + /* Sanity checks */ if ((!BT_MESH_ADDR_IS_UNICAST(addr1) && addr1 != BT_MESH_ADDR_UNASSIGNED) || addr2 == BT_MESH_ADDR_ALL_NODES) { @@ -331,9 +328,7 @@ int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t ad (addr2 == BT_MESH_ADDR_UNASSIGNED && brg_tbl[i].addr1 == addr1) || (addr1 == BT_MESH_ADDR_UNASSIGNED && brg_tbl[i].addr2 == addr2)) { memset(&brg_tbl[i], 0, sizeof(brg_tbl[i])); -#if IS_ENABLED(CONFIG_BT_SETTINGS) store = true; -#endif } } } @@ -341,12 +336,10 @@ int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t ad /* Compact when all rows have been deleted. */ brg_tbl_compact(); -#if IS_ENABLED(CONFIG_BT_SETTINGS) - if (store) { + if (IS_ENABLED(CONFIG_BT_SETTINGS) && store) { atomic_set_bit(brg_cfg_flags, TABLE_UPDATED); bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); } -#endif return 0; } From b267da33d61970eaacbe19ab3ef16fa77370da00 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Mon, 2 Sep 2024 13:13:13 +0200 Subject: [PATCH 134/269] tests: bluetooth: mesh_shell: add brg_cfg_srv instance This commit adds Bridge Configuration Server to the mesh_shell sample. Signed-off-by: Pavel Vasilyev --- tests/bluetooth/mesh_shell/src/main.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/bluetooth/mesh_shell/src/main.c b/tests/bluetooth/mesh_shell/src/main.c index e2afbd183c114d0..cba985c49c880d9 100644 --- a/tests/bluetooth/mesh_shell/src/main.c +++ b/tests/bluetooth/mesh_shell/src/main.c @@ -110,6 +110,9 @@ static const struct bt_mesh_model root_models[] = { #if defined(CONFIG_BT_MESH_OD_PRIV_PROXY_SRV) BT_MESH_MODEL_OD_PRIV_PROXY_SRV, #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_SRV) + BT_MESH_MODEL_BRG_CFG_SRV, +#endif #if defined(CONFIG_BT_MESH_BRG_CFG_CLI) BT_MESH_MODEL_BRG_CFG_CLI(&brg_cfg_cli), #endif From ed051cddb9b5dbedbbe5709609b23eb753ca92b8 Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Tue, 10 Sep 2024 11:32:02 +0200 Subject: [PATCH 135/269] tests: bluetooth: mesh: add subnet bridge bsim tests This commit adds the following tests: - Simple test for bridging table - Test bridging table state changes - Test persistence storage of subnet bridge - Test IV Index update with subnet bridge - Test network key removal for subnet bridge Signed-off-by: Pavel Vasilyev --- tests/bsim/bluetooth/mesh/CMakeLists.txt | 2 + tests/bsim/bluetooth/mesh/overlay_pst.conf | 3 - tests/bsim/bluetooth/mesh/prj.conf | 1 + tests/bsim/bluetooth/mesh/src/main.c | 4 + tests/bsim/bluetooth/mesh/src/mesh_test.c | 12 +- tests/bsim/bluetooth/mesh/src/test_brg.c | 978 ++++++++++++++++++ .../bluetooth/mesh/src/test_replay_cache.c | 12 +- .../mesh/tests_scripts/bridge/brg_ivu.sh | 22 + .../bridge/brg_net_key_update.sh | 25 + .../bridge/brg_persistent_storage.sh | 30 + .../mesh/tests_scripts/bridge/brg_simple.sh | 45 + .../bridge/brg_table_state_change.sh | 32 + 12 files changed, 1156 insertions(+), 10 deletions(-) create mode 100644 tests/bsim/bluetooth/mesh/src/test_brg.c create mode 100755 tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh create mode 100755 tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh create mode 100755 tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh create mode 100755 tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh create mode 100755 tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh diff --git a/tests/bsim/bluetooth/mesh/CMakeLists.txt b/tests/bsim/bluetooth/mesh/CMakeLists.txt index a3e32b97fb4ab9c..c907e8c036be883 100644 --- a/tests/bsim/bluetooth/mesh/CMakeLists.txt +++ b/tests/bsim/bluetooth/mesh/CMakeLists.txt @@ -23,6 +23,7 @@ if(CONFIG_SETTINGS) src/test_blob.c src/test_sar.c src/test_lcd.c + src/test_brg.c ) if(CONFIG_BT_MESH_USES_MBEDTLS_PSA) @@ -72,6 +73,7 @@ else() src/test_op_agg.c src/test_sar.c src/test_cdp1.c + src/test_brg.c ) endif() diff --git a/tests/bsim/bluetooth/mesh/overlay_pst.conf b/tests/bsim/bluetooth/mesh/overlay_pst.conf index 42c1d0d26cef817..37b9f2b9969271f 100644 --- a/tests/bsim/bluetooth/mesh/overlay_pst.conf +++ b/tests/bsim/bluetooth/mesh/overlay_pst.conf @@ -11,9 +11,6 @@ CONFIG_BT_MESH_PB_GATT=y CONFIG_BT_MESH_GATT_PROXY_ENABLED=n CONFIG_BT_MESH_MODEL_GROUP_COUNT=4 -CONFIG_BT_MESH_CDB_NODE_COUNT=3 -CONFIG_BT_MESH_CDB_SUBNET_COUNT=2 -CONFIG_BT_MESH_SUBNET_COUNT=2 CONFIG_BT_MESH_SEQ_STORE_RATE=1 CONFIG_BT_MESH_RPL_STORE_TIMEOUT=1 CONFIG_BT_MESH_STORE_TIMEOUT=1 diff --git a/tests/bsim/bluetooth/mesh/prj.conf b/tests/bsim/bluetooth/mesh/prj.conf index eb810ef01162bcc..156b12496758f7a 100644 --- a/tests/bsim/bluetooth/mesh/prj.conf +++ b/tests/bsim/bluetooth/mesh/prj.conf @@ -43,6 +43,7 @@ CONFIG_BT_MESH_CDB=y CONFIG_BT_MESH_CDB_NODE_COUNT=4 CONFIG_BT_MESH_PROV_OOB_PUBLIC_KEY=y CONFIG_BT_MESH_MODEL_EXTENSIONS=y +CONFIG_BT_MESH_CDB_SUBNET_COUNT=3 CONFIG_BT_MESH_SUBNET_COUNT=5 CONFIG_BT_MESH_SAR_CFG_CLI=y CONFIG_BT_MESH_SAR_CFG_SRV=y diff --git a/tests/bsim/bluetooth/mesh/src/main.c b/tests/bsim/bluetooth/mesh/src/main.c index 45e10c9a412ff5b..f83b0717e49ab56 100644 --- a/tests/bsim/bluetooth/mesh/src/main.c +++ b/tests/bsim/bluetooth/mesh/src/main.c @@ -15,6 +15,7 @@ extern struct bst_test_list *test_dfu_install(struct bst_test_list *test); extern struct bst_test_list *test_blob_pst_install(struct bst_test_list *test); extern struct bst_test_list *test_lcd_install(struct bst_test_list *test); extern struct bst_test_list *test_sar_pst_install(struct bst_test_list *test); +extern struct bst_test_list *test_brg_install(struct bst_test_list *test); #if (CONFIG_BT_MESH_GATT_PROXY && CONFIG_BT_MESH_PROXY_SOLICITATION) extern struct bst_test_list *test_proxy_sol_install(struct bst_test_list *test); #endif @@ -42,6 +43,7 @@ extern struct bst_test_list *test_blob_install(struct bst_test_list *test); extern struct bst_test_list *test_op_agg_install(struct bst_test_list *test); extern struct bst_test_list *test_sar_install(struct bst_test_list *test); extern struct bst_test_list *test_cdp1_install(struct bst_test_list *test); +extern struct bst_test_list *test_brg_install(struct bst_test_list *test); #endif bst_test_install_t test_installers[] = { @@ -53,6 +55,7 @@ bst_test_install_t test_installers[] = { test_blob_pst_install, test_lcd_install, test_sar_pst_install, + test_brg_install, #if (CONFIG_BT_MESH_GATT_PROXY && CONFIG_BT_MESH_PROXY_SOLICITATION) test_proxy_sol_install, #endif @@ -80,6 +83,7 @@ bst_test_install_t test_installers[] = { test_op_agg_install, test_sar_install, test_cdp1_install, + test_brg_install, #endif NULL }; diff --git a/tests/bsim/bluetooth/mesh/src/mesh_test.c b/tests/bsim/bluetooth/mesh/src/mesh_test.c index 1edafd657c342db..c092c9135b179cc 100644 --- a/tests/bsim/bluetooth/mesh/src/mesh_test.c +++ b/tests/bsim/bluetooth/mesh/src/mesh_test.c @@ -88,7 +88,7 @@ static int ra_rx(const struct bt_mesh_model *mod, struct bt_mesh_msg_ctx *ctx, LOG_INF("\trssi: %d", ctx->recv_rssi); if (ra_cb) { - ra_cb(net_buf_simple_pull_mem(buf, buf->len), buf->len); + ra_cb(buf->data, buf->len); } return 0; @@ -186,6 +186,10 @@ static struct bt_mesh_priv_beacon_cli priv_beacon_cli; static struct bt_mesh_od_priv_proxy_cli priv_proxy_cli; #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) +static struct bt_mesh_brg_cfg_cli brg_cfg_cli; +#endif + static const struct bt_mesh_model models[] = { BT_MESH_MODEL_CFG_SRV, BT_MESH_MODEL_CFG_CLI(&cfg_cli), @@ -205,6 +209,12 @@ static const struct bt_mesh_model models[] = { #if defined(CONFIG_BT_MESH_OD_PRIV_PROXY_CLI) BT_MESH_MODEL_OD_PRIV_PROXY_CLI(&priv_proxy_cli), #endif +#if defined(CONFIG_BT_MESH_BRG_CFG_SRV) + BT_MESH_MODEL_BRG_CFG_SRV, +#endif +#if defined(CONFIG_BT_MESH_BRG_CFG_CLI) + BT_MESH_MODEL_BRG_CFG_CLI(&brg_cfg_cli), +#endif }; const struct bt_mesh_model *test_model = &models[2]; diff --git a/tests/bsim/bluetooth/mesh/src/test_brg.c b/tests/bsim/bluetooth/mesh/src/test_brg.c new file mode 100644 index 000000000000000..448ff10ea848f29 --- /dev/null +++ b/tests/bsim/bluetooth/mesh/src/test_brg.c @@ -0,0 +1,978 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + * + * Subnet bridge test + */ + +#include "mesh_test.h" +#include +#include "mesh/net.h" +#include "mesh/keys.h" +#include "bsim_args_runner.h" +#include "common/bt_str.h" + +#include +LOG_MODULE_REGISTER(test_brg, LOG_LEVEL_INF); + +#define WAIT_TIME 32 /*seconds*/ +#define WAIT_TIME_IVU_TEST 240 /* seconds */ +#define BEACON_INTERVAL 10 /*seconds */ + +#define PROV_ADDR 0x0001 +/* Bridge address must be less than DEVICE_ADDR_START */ +#define BRIDGE_ADDR 0x0002 +#define DEVICE_ADDR_START 0x0003 + +#define REMOTE_NODES 2 + +static const uint8_t prov_dev_key[16] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, + 0xcd, 0xef, 0x01, 0x23, 0x45, 0x67, + 0x89, 0xab, 0xcd, 0xef }; + +static const uint8_t subnet_keys[][16] = { + { 0xaa, 0xbb, 0xcc }, + { 0xdd, 0xee, 0xff }, + { 0x11, 0x22, 0x33 }, +}; + +static uint8_t prov_uuid[16] = { 0x6c, 0x69, 0x6e, 0x67, 0x61, 0xaa }; +static uint8_t bridge_uuid[16] = { 0x6c, 0x69, 0x6e, 0x67, 0x61, 0xbb }; +static uint8_t dev_uuid[16] = { 0x6c, 0x69, 0x6e, 0x67, 0x61, 0xcc }; + +static int test_ividx = 0x123456; + +extern const struct bt_mesh_comp comp; +static bool tester_ready; + +enum { + MSG_TYPE_DATA = 0, + MSG_TYPE_GET = 1, + MSG_TYPE_STATUS = 2, +}; + +static uint8_t recvd_msgs[10]; +static uint8_t recvd_msgs_cnt; + +BUILD_ASSERT((2 /* opcode */ + 1 /* type */ + 1 /* msgs cnt */ + sizeof(recvd_msgs) + + BT_MESH_MIC_SHORT) <= BT_MESH_RX_SDU_MAX, + "Status message does not fit into the maximum incoming SDU size."); +BUILD_ASSERT((2 /* opcode */ + 1 /* type */ + 1 /* msgs cnt */ + sizeof(recvd_msgs) + + BT_MESH_MIC_SHORT) <= BT_MESH_TX_SDU_MAX, + "Status message does not fit into the maximum outgoing SDU size."); + +static K_SEM_DEFINE(status_msg_recvd_sem, 0, 1); +static K_SEM_DEFINE(prov_sem, 0, 1); + +static void test_tester_init(void) +{ + /* Stub */ +} + +static void test_bridge_init(void) +{ + /* Bridge device must always be the second device. */ + ASSERT_EQUAL(1, get_device_nbr()); +} + +static void test_device_init(void) +{ + ASSERT_TRUE_MSG(get_device_nbr() >= 2, "Regular devices must be initialized after " + "tester and Bridge devices."); + + /* Regular devices addresses starts from address 0x0003.*/ + dev_uuid[6] = get_device_nbr() + 1; + + /* Regular devices are provisioned into subnets starting with idx 1. */ + dev_uuid[8] = get_device_nbr() - 1; +} + +static void unprovisioned_beacon(uint8_t uuid[16], bt_mesh_prov_oob_info_t oob_info, + uint32_t *uri_hash) +{ + int err; + + /* Subnet may not be ready yet when tester receives a beacon. */ + if (!tester_ready) { + LOG_INF("tester is not ready yet"); + return; + } + + LOG_INF("Received unprovisioned beacon, uuid %s", bt_hex(uuid, 16)); + + if (!memcmp(uuid, bridge_uuid, 16)) { + err = bt_mesh_provision_adv(uuid, 0, BRIDGE_ADDR, 0); + if (!err) { + LOG_INF("Provisioning bridge at address 0x%04x", BRIDGE_ADDR); + } + + return; + } + + /* UUID[6] - address to be used for provisioning. + * UUID[8] - subnet to be used for provisioning. + */ + uint16_t addr = uuid[6]; + int subnet_idx = uuid[8]; + + err = bt_mesh_provision_adv(uuid, subnet_idx, addr, 0); + if (!err) { + LOG_INF("Provisioning device at address 0x%04x with NetKeyIdx 0x%04x", addr, + subnet_idx); + } +} + +static void prov_node_added(uint16_t net_idx, uint8_t uuid[16], uint16_t addr, uint8_t num_elem) +{ + LOG_INF("Device 0x%04x provisioned, NetKeyIdx 0x%04x", addr, net_idx); + k_sem_give(&prov_sem); +} + +static struct bt_mesh_prov tester_prov = { + .uuid = prov_uuid, + .unprovisioned_beacon = unprovisioned_beacon, + .node_added = prov_node_added +}; + +static void prov_complete(uint16_t net_idx, uint16_t addr) +{ + LOG_INF("Device 0x%04x provisioning is complete, NetKeyIdx 0x%04x", addr, net_idx); + k_sem_give(&prov_sem); +} + +static struct bt_mesh_prov device_prov = { + .uuid = dev_uuid, + .complete = prov_complete, +}; + +static struct bt_mesh_prov bridge_prov = { + .uuid = bridge_uuid, + .complete = prov_complete, +}; + +static void tester_setup(void) +{ + uint8_t status; + int err; + + ASSERT_OK(bt_mesh_cdb_create(test_net_key)); + ASSERT_OK(bt_mesh_provision(test_net_key, 0, 0, test_ividx, PROV_ADDR, prov_dev_key)); + + err = bt_mesh_cfg_cli_app_key_add(0, PROV_ADDR, 0, 0, test_app_key, &status); + if (err || status) { + FAIL("AppKey add failed (err %d, status %u)", err, status); + return; + } + + err = bt_mesh_cfg_cli_mod_app_bind(0, PROV_ADDR, PROV_ADDR, 0, TEST_MOD_ID, &status); + if (err || status) { + FAIL("Mod app bind failed (err %d, status %u)", err, status); + return; + } + + for (int i = 0; i < REMOTE_NODES; i++) { + LOG_INF("Creating subnet idx %d", i); + + ASSERT_OK(bt_mesh_cfg_cli_net_key_add(0, PROV_ADDR, i + 1, subnet_keys[i], + &status)); + if (status) { + FAIL("NetKey add failed (status %u)", status); + return; + } + + struct bt_mesh_cdb_subnet *subnet = bt_mesh_cdb_subnet_alloc(i + 1); + + ASSERT_TRUE(subnet != NULL); + + ASSERT_OK(bt_mesh_cdb_subnet_key_import(subnet, 0, subnet_keys[i])); + + bt_mesh_cdb_subnet_store(subnet); + } + + uint8_t transmit; + + ASSERT_OK(bt_mesh_cfg_cli_relay_set(0, PROV_ADDR, BT_MESH_RELAY_DISABLED, + BT_MESH_TRANSMIT(2, 20), &status, &transmit)); + if (status) { + FAIL("Relay set failed (status %u)", status); + return; + } + + tester_ready = true; +} + +static void bridge_entry_add(uint16_t src, uint16_t dst, uint16_t net_idx1, uint16_t net_idx2, + uint8_t dir) +{ + struct bt_mesh_bridging_table_entry entry; + struct bt_mesh_bridging_table_status rsp; + int err; + + entry.directions = dir; + entry.net_idx1 = net_idx1; + entry.net_idx2 = net_idx2; + entry.addr1 = src; + entry.addr2 = dst; + + err = bt_mesh_brg_cfg_cli_bridging_table_add(0, BRIDGE_ADDR, &entry, &rsp); + if (err || rsp.status || + rsp.entry.directions != dir || + rsp.entry.net_idx1 != net_idx1 || rsp.entry.net_idx2 != net_idx2 || + rsp.entry.addr1 != src || rsp.entry.addr2 != dst) { + FAIL("Bridging table add failed (err %d) (status %u)", err, rsp.status); + return; + } +} + +static void bridge_entry_remove(uint16_t src, uint16_t dst, uint16_t net_idx1, uint16_t net_idx2) +{ + struct bt_mesh_bridging_table_status rsp; + + ASSERT_OK(bt_mesh_brg_cfg_cli_bridging_table_remove(0, BRIDGE_ADDR, net_idx1, net_idx2, + src, dst, &rsp)); + if (rsp.status) { + FAIL("Bridging table remove failed (status %u)", rsp.status); + return; + } +} + +static void tester_bridge_configure(int subnets) +{ + uint8_t status; + int err; + + LOG_INF("Configuring bridge..."); + + for (int i = 0; i < subnets; i++) { + err = bt_mesh_cfg_cli_net_key_add(0, BRIDGE_ADDR, i + 1, subnet_keys[i], &status); + if (err || status) { + FAIL("NetKey add failed (err %d, status %u)", err, status); + return; + } + } + + ASSERT_OK(bt_mesh_brg_cfg_cli_subnet_bridge_set(0, BRIDGE_ADDR, + BT_MESH_SUBNET_BRIDGE_ENABLED, &status)); + if (status != BT_MESH_SUBNET_BRIDGE_ENABLED) { + FAIL("Subnet bridge set failed (status %u)", status); + return; + } + + /* Disable Relay feature to avoid interference in the test. */ + uint8_t transmit; + + ASSERT_OK(bt_mesh_cfg_cli_relay_set(0, BRIDGE_ADDR, BT_MESH_RELAY_DISABLED, + BT_MESH_TRANSMIT(2, 20), &status, &transmit)); + if (status) { + FAIL("Relay set failed (status %u)", status); + return; + } + + LOG_INF("Bridge configured"); +} + +static void tester_device_configure(uint16_t net_key_idx, uint16_t addr) +{ + int err; + uint8_t status; + + err = bt_mesh_cfg_cli_app_key_add(net_key_idx, addr, net_key_idx, 0, test_app_key, &status); + if (err || status) { + FAIL("AppKey add failed (err %d, status %u)", err, status); + return; + } + + err = bt_mesh_cfg_cli_mod_app_bind(net_key_idx, addr, addr, 0, TEST_MOD_ID, &status); + if (err || status) { + FAIL("Mod app bind failed (err %d, status %u)", err, status); + return; + } + + /* Disable SNB on devices to let Subnet Bridge propagate new IV index value. */ + err = bt_mesh_cfg_cli_beacon_set(net_key_idx, addr, BT_MESH_BEACON_DISABLED, &status); + if (err || status) { + FAIL("Beacon set failed (err %d, status %u)", err, status); + return; + } + + LOG_INF("Device 0x%04x configured", addr); +} + +static void tester_ra_cb(uint8_t *data, size_t length) +{ + uint8_t type = data[0]; + + LOG_HEXDUMP_DBG(data, length, "tester received message"); + + ASSERT_TRUE_MSG(length > 1, "Too short message"); + ASSERT_EQUAL(type, MSG_TYPE_STATUS); + + recvd_msgs_cnt = data[1]; + ASSERT_EQUAL(recvd_msgs_cnt * sizeof(recvd_msgs[0]), length - 2); + memcpy(recvd_msgs, &data[2], recvd_msgs_cnt * sizeof(recvd_msgs[0])); + + k_sem_give(&status_msg_recvd_sem); +} + +static int send_data(uint16_t dst, uint8_t payload) +{ + uint8_t data[2] = {MSG_TYPE_DATA, payload}; + + return bt_mesh_test_send_ra(dst, data, sizeof(data), NULL, NULL); +} + +static int send_get(uint16_t dst) +{ + uint8_t data[1] = {MSG_TYPE_GET}; + + return bt_mesh_test_send_ra(dst, data, sizeof(data), NULL, NULL); +} + +struct bridged_addresses_entry { + uint16_t addr1; + uint16_t addr2; + uint8_t dir; +}; + +static void bridge_table_verify(uint16_t net_idx1, uint16_t net_idx2, uint16_t start_idx, + struct bridged_addresses_entry *list, size_t list_len) +{ + struct bt_mesh_bridging_table_list rsp = { + .list = NET_BUF_SIMPLE(BT_MESH_RX_SDU_MAX), + }; + + net_buf_simple_init(rsp.list, 0); + + ASSERT_OK(bt_mesh_brg_cfg_cli_bridging_table_get(0, BRIDGE_ADDR, net_idx1, + net_idx2, start_idx, + &rsp)); + ASSERT_EQUAL(rsp.status, 0); + ASSERT_EQUAL(rsp.net_idx1, net_idx1); + ASSERT_EQUAL(rsp.net_idx2, net_idx2); + ASSERT_EQUAL(rsp.start_idx, start_idx); + + LOG_HEXDUMP_DBG(rsp.list->data, rsp.list->len, "Received table"); + + ASSERT_EQUAL(rsp.list->len / 5, list_len); + ASSERT_EQUAL(rsp.list->len % 5, 0); + + for (int i = 0; i < list_len; i++) { + struct bridged_addresses_entry entry; + + entry.addr1 = net_buf_simple_pull_le16(rsp.list); + entry.addr2 = net_buf_simple_pull_le16(rsp.list); + entry.dir = net_buf_simple_pull_u8(rsp.list); + + ASSERT_EQUAL(entry.addr1, list[i].addr1); + ASSERT_EQUAL(entry.addr2, list[i].addr2); + ASSERT_EQUAL(entry.dir, list[i].dir); + } +} + +static void device_ra_cb(uint8_t *data, size_t length) +{ + uint8_t type = data[0]; + + LOG_HEXDUMP_DBG(data, length, "Device received message"); + + switch (type) { + case MSG_TYPE_DATA: + ASSERT_EQUAL(2, length); + ASSERT_TRUE_MSG(recvd_msgs_cnt < ARRAY_SIZE(recvd_msgs), "Too many messages"); + + recvd_msgs[recvd_msgs_cnt] = data[1]; + recvd_msgs_cnt++; + + break; + + case MSG_TYPE_GET: { + uint8_t test_data[1 /*type */ + 1 /* msgs cnt */ + sizeof(recvd_msgs)] = { + MSG_TYPE_STATUS, + recvd_msgs_cnt + }; + + memcpy(&test_data[2], recvd_msgs, recvd_msgs_cnt * sizeof(recvd_msgs[0])); + + ASSERT_OK(bt_mesh_test_send_ra(PROV_ADDR, test_data, + 2 + recvd_msgs_cnt * sizeof(recvd_msgs[0]), NULL, + NULL)); + + memset(recvd_msgs, 0, sizeof(recvd_msgs)); + recvd_msgs_cnt = 0; + + break; + } + + case MSG_TYPE_STATUS: + ASSERT_TRUE_MSG(false, "Unexpected message"); + break; + } +} + +/** + * This is a workaround that removes secondary subnets from the tester to avoid message cache + * hit when the devices send STATUS message encrypted with the subnet key known by the tester, + * but with different app key pair (app key is the same, but net key <-> app key pair is different). + */ +static void tester_workaround(void) +{ + uint8_t status; + int err; + + LOG_INF("Applying subnet's workaround for tester..."); + + for (int i = 0; i < REMOTE_NODES; i++) { + err = bt_mesh_cfg_cli_net_key_del(0, PROV_ADDR, i + 1, &status); + if (err || status) { + FAIL("NetKey del failed (err %d, status %u)", err, status); + return; + } + } +} + +static void send_and_receive(void) +{ + const int msgs_cnt = 3; + + LOG_INF("Sending data..."); + + for (int i = 0; i < REMOTE_NODES; i++) { + uint8_t payload = i | i << 4; + + for (int j = 0; j < msgs_cnt; j++) { + ASSERT_OK(send_data(DEVICE_ADDR_START + i, payload + j)); + } + } + + LOG_INF("Checking data..."); + + for (int i = 0; i < REMOTE_NODES; i++) { + uint8_t payload = i | i << 4; + + ASSERT_OK(send_get(DEVICE_ADDR_START + i)); + ASSERT_OK(k_sem_take(&status_msg_recvd_sem, K_SECONDS(5))); + + ASSERT_EQUAL(recvd_msgs_cnt, msgs_cnt); + for (int j = 0; j < recvd_msgs_cnt; j++) { + ASSERT_EQUAL(recvd_msgs[j], payload + j); + } + } +} + +static void test_tester_simple(void) +{ + uint8_t status; + int err; + + bt_mesh_test_cfg_set(NULL, WAIT_TIME); + bt_mesh_device_setup(&tester_prov, &comp); + + tester_setup(); + + for (int i = 0; i < 1 /* bridge */ + REMOTE_NODES; i++) { + LOG_INF("Waiting for a device to provision..."); + ASSERT_OK(k_sem_take(&prov_sem, K_SECONDS(40))); + } + + tester_bridge_configure(REMOTE_NODES); + + /* Adding devices to bridge table */ + for (int i = 0; i < REMOTE_NODES; i++) { + bridge_entry_add(PROV_ADDR, DEVICE_ADDR_START + i, 0, i + 1, + BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY); + } + + for (int i = 0; i < REMOTE_NODES; i++) { + tester_device_configure(i + 1, DEVICE_ADDR_START + i); + } + + tester_workaround(); + + bt_mesh_test_ra_cb_setup(tester_ra_cb); + + LOG_INF("Step 1: Checking bridging table..."); + + send_and_receive(); + + LOG_INF("Step 2: Disabling bridging..."); + + err = bt_mesh_brg_cfg_cli_subnet_bridge_set(0, BRIDGE_ADDR, BT_MESH_SUBNET_BRIDGE_DISABLED, + &status); + if (err || status != BT_MESH_SUBNET_BRIDGE_DISABLED) { + FAIL("Subnet bridge set failed (err %d) (status %u)", err, status); + return; + } + + LOG_INF("Sending data..."); + for (int i = 0; i < REMOTE_NODES; i++) { + uint8_t payload = i | i << 4; + + for (int j = 0; j < 3; j++) { + ASSERT_OK(send_data(DEVICE_ADDR_START + i, payload + j)); + } + } + + LOG_INF("Step3: Enabling bridging..."); + err = bt_mesh_brg_cfg_cli_subnet_bridge_set(0, BRIDGE_ADDR, BT_MESH_SUBNET_BRIDGE_ENABLED, + &status); + if (err || status != BT_MESH_SUBNET_BRIDGE_ENABLED) { + FAIL("Subnet bridge set failed (err %d) (status %u)", err, status); + return; + } + + LOG_INF("Checking data..."); + for (int i = 0; i < REMOTE_NODES; i++) { + ASSERT_OK(send_get(DEVICE_ADDR_START + i)); + ASSERT_OK(k_sem_take(&status_msg_recvd_sem, K_SECONDS(5))); + + ASSERT_EQUAL(recvd_msgs_cnt, 0); + } + + PASS(); +} + +static void test_tester_table_state_change(void) +{ + int err; + + bt_mesh_test_cfg_set(NULL, WAIT_TIME); + bt_mesh_device_setup(&tester_prov, &comp); + + tester_setup(); + + for (int i = 0; i < 1 /* bridge */ + REMOTE_NODES; i++) { + LOG_INF("Waiting for a device to provision..."); + ASSERT_OK(k_sem_take(&prov_sem, K_SECONDS(40))); + } + + tester_bridge_configure(REMOTE_NODES); + + for (int i = 0; i < REMOTE_NODES; i++) { + tester_device_configure(i + 1, DEVICE_ADDR_START + i); + } + + tester_workaround(); + + bt_mesh_test_ra_cb_setup(tester_ra_cb); + + /* Bridge Table is empty, will not get any message back. */ + ASSERT_OK(send_get(DEVICE_ADDR_START)); + err = k_sem_take(&status_msg_recvd_sem, K_SECONDS(5)); + ASSERT_EQUAL(err, -EAGAIN); + + /* DATA and GET messages should reach Device 1, but STATUS message won't be received. */ + bridge_entry_add(PROV_ADDR, DEVICE_ADDR_START, 0, 1, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY); + + ASSERT_OK(send_data(DEVICE_ADDR_START, 0xAA)); + + ASSERT_OK(send_get(DEVICE_ADDR_START)); + err = k_sem_take(&status_msg_recvd_sem, K_SECONDS(5)); + ASSERT_EQUAL(err, -EAGAIN); + + /* Sending DATA message again before adding a new entry as the previous GET message resets + * received messages counter on Devices + */ + ASSERT_OK(send_data(DEVICE_ADDR_START, 0xAA)); + /* Adding a reverse entry. This should be added to the bridge table as a separate entry as + * the addresses and net keys indexs are provided in the opposite order. + */ + bridge_entry_add(DEVICE_ADDR_START, PROV_ADDR, 1, 0, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY); + bridge_table_verify(0, 1, 0, (struct bridged_addresses_entry[]) { + { PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, + }, 1); + bridge_table_verify(1, 0, 0, (struct bridged_addresses_entry[]) { + { DEVICE_ADDR_START, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, + }, 1); + + k_sleep(K_SECONDS(1)); + + /* Now we should receive STATUS message. */ + ASSERT_OK(send_get(DEVICE_ADDR_START)); + ASSERT_OK(k_sem_take(&status_msg_recvd_sem, K_SECONDS(5))); + + ASSERT_EQUAL(recvd_msgs_cnt, 1); + ASSERT_EQUAL(recvd_msgs[0], 0xAA); + + /* Removing the reverse entry and changing direction on the first entry. + * tester should still receive STATUS message. + */ + bridge_entry_remove(DEVICE_ADDR_START, PROV_ADDR, 1, 0); + bridge_entry_add(PROV_ADDR, DEVICE_ADDR_START, 0, 1, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY); + bridge_table_verify(0, 1, 0, (struct bridged_addresses_entry[]) { + { PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, + }, 1); + bridge_table_verify(1, 0, 0, NULL, 0); + + ASSERT_OK(send_get(DEVICE_ADDR_START)); + ASSERT_OK(k_sem_take(&status_msg_recvd_sem, K_SECONDS(5))); + ASSERT_EQUAL(recvd_msgs_cnt, 0); + + PASS(); +} + +static void net_key_remove(uint16_t dst, uint16_t net_idx, uint16_t net_idx_to_remove) +{ + uint8_t status; + int err; + + err = bt_mesh_cfg_cli_net_key_del(net_idx, dst, net_idx_to_remove, &status); + if (err || status) { + FAIL("NetKey del failed (err %d, status %u)", err, status); + return; + } +} + +static void test_tester_net_key_remove(void) +{ + int err; + + bt_mesh_test_cfg_set(NULL, WAIT_TIME); + bt_mesh_device_setup(&tester_prov, &comp); + + tester_setup(); + + for (int i = 0; i < 1 /* bridge */ + REMOTE_NODES; i++) { + LOG_INF("Waiting for a device to provision..."); + ASSERT_OK(k_sem_take(&prov_sem, K_SECONDS(40))); + } + + tester_bridge_configure(REMOTE_NODES); + + for (int i = 0; i < REMOTE_NODES; i++) { + tester_device_configure(i + 1, DEVICE_ADDR_START + i); + } + + tester_workaround(); + + bt_mesh_test_ra_cb_setup(tester_ra_cb); + + /* Adding devices to bridge table */ + for (int i = 0; i < REMOTE_NODES; i++) { + bridge_entry_add(PROV_ADDR, DEVICE_ADDR_START + i, 0, i + 1, + BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY); + } + + ASSERT_OK(send_data(DEVICE_ADDR_START, 0xAA)); + ASSERT_OK(send_get(DEVICE_ADDR_START)); + ASSERT_OK(k_sem_take(&status_msg_recvd_sem, K_SECONDS(5))); + ASSERT_EQUAL(recvd_msgs_cnt, 1); + ASSERT_EQUAL(recvd_msgs[0], 0xAA); + + /* Removing subnet 1 from Subnet Bridge. */ + net_key_remove(BRIDGE_ADDR, 0, 1); + + ASSERT_OK(send_get(DEVICE_ADDR_START)); + err = k_sem_take(&status_msg_recvd_sem, K_SECONDS(5)); + ASSERT_EQUAL(err, -EAGAIN); + + bridge_table_verify(0, 2, 0, (struct bridged_addresses_entry[]) { + { PROV_ADDR, DEVICE_ADDR_START + 1, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, + }, 1); + + /* Bridging Table Get message will return Invalid NetKey Index error because Subnet 1 is + * removed. + */ + struct bt_mesh_bridging_table_list rsp = { + .list = NULL, + }; + + ASSERT_OK(bt_mesh_brg_cfg_cli_bridging_table_get(0, BRIDGE_ADDR, 0, 1, 0, &rsp)); + ASSERT_EQUAL(rsp.status, 4); + + PASS(); +} + +#if CONFIG_BT_SETTINGS +static void test_tester_persistence(void) +{ + bt_mesh_test_cfg_set(NULL, WAIT_TIME); + + bt_mesh_device_setup(&tester_prov, &comp); + + if (bt_mesh_is_provisioned()) { + uint8_t status; + + LOG_INF("Already provisioned, skipping provisioning"); + + ASSERT_OK(bt_mesh_brg_cfg_cli_subnet_bridge_get(0, BRIDGE_ADDR, &status)); + if (status != BT_MESH_SUBNET_BRIDGE_ENABLED) { + FAIL("Subnet bridge set failed (status %u)", status); + return; + } + + bridge_table_verify(0, 1, 0, (struct bridged_addresses_entry[]) { + { PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, + }, 1); + + bridge_table_verify(0, 2, 0, (struct bridged_addresses_entry[]) { + { PROV_ADDR, DEVICE_ADDR_START + 1, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, + }, 1); + + bridge_table_verify(1, 0, 0, (struct bridged_addresses_entry[]) { + { DEVICE_ADDR_START, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, + }, 1); + + bridge_table_verify(2, 0, 0, (struct bridged_addresses_entry[]) { + { DEVICE_ADDR_START + 1, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, + }, 1); + } else { + tester_setup(); + + LOG_INF("Waiting for a bridge to provision..."); + ASSERT_OK(k_sem_take(&prov_sem, K_SECONDS(40))); + + LOG_INF("Configuring bridge..."); + tester_bridge_configure(REMOTE_NODES); + + /* Adding devices to bridge table */ + for (int i = 0; i < REMOTE_NODES; i++) { + bridge_entry_add(PROV_ADDR, DEVICE_ADDR_START + i, 0, i + 1, + BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY); + bridge_entry_add(DEVICE_ADDR_START + i, PROV_ADDR, i + 1, 0, + BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY); + } + + k_sleep(K_SECONDS(CONFIG_BT_MESH_STORE_TIMEOUT)); + } + + PASS(); +} +#endif + +/* When testing IV Index update, after the IV Index incremented devices starts sending messages + * with SEQ number 0 that is lower than the SEQ number of the last message received before IV Index. + * The Network Message Cache is not cleared and thus will drop these messages. + * + * The workaround is to send GET message to each device to bump SEQ number and overflow the cache so + * that after IV Index update there is no message with SEQ 0 in the cache. + */ +static void msg_cache_workaround(void) +{ + LOG_INF("Applying Msg Cache workaround..."); + + for (int i = 0; i < REMOTE_NODES; i++) { + for (int j = 0; j < CONFIG_BT_MESH_MSG_CACHE_SIZE; j++) { + ASSERT_OK(send_get(DEVICE_ADDR_START + i)); + /* k_sem_take is needed to not overflow network buffer pool. The result + * of the semaphor is not important as we just need to bump sequence number + * enough to bypass message cache. + */ + (void) k_sem_take(&status_msg_recvd_sem, K_SECONDS(1)); + } + } + + LOG_INF("Msg Cache workaround applied"); + k_sleep(K_SECONDS(10)); +} + +static int beacon_set(uint16_t dst, uint8_t val) +{ + uint8_t status; + int err; + + err = bt_mesh_cfg_cli_beacon_set(0, dst, val, &status); + if (err || status != val) { + FAIL("Beacon set failed (err %d, status %u)", err, status); + return -EINVAL; + } + + return 0; +} + +/* This function guarantees that IV Update procedure state is propagated to all nodes by togging off + * Beacon features on Subnet Bridge and Tester nodes. When Beacon feature is disabled on Subnet + * Bridge, Tester will be able to send beacon with new IVI flag and vice versa. + * + * Beacon feature is disabled on other nodes at the setup. + */ +static void propagate_ivi_update_state(void) +{ + /* Disable Beacon feature on subnet bridge to let tester send beacon first. */ + ASSERT_OK(beacon_set(BRIDGE_ADDR, BT_MESH_BEACON_DISABLED)); + + LOG_INF("Waiting for IV Update state to propagate to Subnet Bridge"); + k_sleep(K_SECONDS(BEACON_INTERVAL * 2)); + + /* Disable Beacon feature on tester and enable it on subnet bridge to let it send beacon. */ + ASSERT_OK(beacon_set(PROV_ADDR, BT_MESH_BEACON_DISABLED)); + ASSERT_OK(beacon_set(BRIDGE_ADDR, BT_MESH_BEACON_ENABLED)); + + LOG_INF("Waiting for IV Update state to propagate to other nodes"); + k_sleep(K_SECONDS(BEACON_INTERVAL * 2)); + + /* Restore Beacon feature on tester. */ + ASSERT_OK(beacon_set(PROV_ADDR, BT_MESH_BEACON_ENABLED)); +} + +static void test_tester_ivu(void) +{ + bt_mesh_test_cfg_set(NULL, WAIT_TIME_IVU_TEST); + bt_mesh_device_setup(&tester_prov, &comp); + bt_mesh_iv_update_test(true); + + tester_setup(); + + for (int i = 0; i < 1 /* bridge */ + REMOTE_NODES; i++) { + LOG_INF("Waiting for a device to provision..."); + ASSERT_OK(k_sem_take(&prov_sem, K_SECONDS(40))); + } + + tester_bridge_configure(REMOTE_NODES); + + /* Adding devices to bridge table */ + for (int i = 0; i < REMOTE_NODES; i++) { + bridge_entry_add(PROV_ADDR, DEVICE_ADDR_START + i, 0, i + 1, + BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY); + } + + for (int i = 0; i < REMOTE_NODES; i++) { + tester_device_configure(i + 1, DEVICE_ADDR_START + i); + } + + tester_workaround(); + + bt_mesh_test_ra_cb_setup(tester_ra_cb); + + ASSERT_TRUE(!atomic_test_bit(bt_mesh.flags, BT_MESH_IVU_IN_PROGRESS)); + ASSERT_TRUE(bt_mesh.iv_index == test_ividx); + + LOG_INF("IV Update procedure state: Normal"); + + k_sleep(K_SECONDS(BEACON_INTERVAL)); + + send_and_receive(); + + for (int i = 0; i < 2; i++) { + uint32_t iv_index = bt_mesh.iv_index; + + LOG_INF("Round: %d", i); + + msg_cache_workaround(); + + LOG_INF("Starting IV Update procedure, IVI %d -> %d", bt_mesh.iv_index, + bt_mesh.iv_index + 1); + + iv_index = bt_mesh.iv_index; + + ASSERT_TRUE(bt_mesh_iv_update()); + ASSERT_TRUE(atomic_test_bit(bt_mesh.flags, BT_MESH_IVU_IN_PROGRESS)); + ASSERT_TRUE(bt_mesh.iv_index == iv_index + 1); + + send_and_receive(); + + propagate_ivi_update_state(); + + LOG_INF("Finishing IV Update procedure"); + + ASSERT_TRUE(!bt_mesh_iv_update()); + ASSERT_TRUE(!atomic_test_bit(bt_mesh.flags, BT_MESH_IVU_IN_PROGRESS)); + ASSERT_TRUE(bt_mesh.iv_index == iv_index + 1); + + propagate_ivi_update_state(); + + send_and_receive(); + } + + PASS(); +} + +static void bridge_setup(void) +{ + bt_mesh_device_setup(&bridge_prov, &comp); + + if (IS_ENABLED(CONFIG_BT_SETTINGS) && bt_mesh_is_provisioned()) { + LOG_INF("Already provisioned, skipping provisioning"); + } else { + ASSERT_OK(bt_mesh_prov_enable(BT_MESH_PROV_ADV)); + LOG_INF("Waiting for being provisioned..."); + ASSERT_OK(k_sem_take(&prov_sem, K_SECONDS(40))); + LOG_INF("Bridge is provisioned"); + } +} + +static void test_bridge_simple(void) +{ + bt_mesh_test_cfg_set(NULL, WAIT_TIME); + + bridge_setup(); + + PASS(); +} + +static void test_bridge_simple_iv_test_mode(void) +{ + bt_mesh_test_cfg_set(NULL, WAIT_TIME_IVU_TEST); + bt_mesh_iv_update_test(true); + + bridge_setup(); + + PASS(); +} + +static void device_setup(void) +{ + bt_mesh_device_setup(&device_prov, &comp); + + ASSERT_OK(bt_mesh_prov_enable(BT_MESH_PROV_ADV)); + + LOG_INF("Waiting for being provisioned..."); + ASSERT_OK(k_sem_take(&prov_sem, K_SECONDS(40))); + LOG_INF("Node is provisioned"); + + bt_mesh_test_ra_cb_setup(device_ra_cb); +} + +static void test_device_simple(void) +{ + bt_mesh_test_cfg_set(NULL, WAIT_TIME); + + device_setup(); + + PASS(); +} + +static void test_device_simple_iv_test_mode(void) +{ + bt_mesh_test_cfg_set(NULL, WAIT_TIME_IVU_TEST); + bt_mesh_iv_update_test(true); + + device_setup(); + + PASS(); +} + +#define TEST_CASE(role, name, description) \ + { \ + .test_id = "brg_" #role "_" #name, \ + .test_post_init_f = test_##role##_init, \ + .test_descr = description, \ + .test_tick_f = bt_mesh_test_timeout, \ + .test_main_f = test_##role##_##name, \ + } + +static const struct bst_test_instance test_brg[] = { + TEST_CASE(tester, simple, "Tester node: provisions network, exchanges messages with " + "mesh nodes"), + TEST_CASE(tester, table_state_change, "Tester node: tests changing bridging table " + "state"), + TEST_CASE(tester, net_key_remove, "Tester node: tests removing net key from Subnet " + "Bridge"), +#if CONFIG_BT_SETTINGS + TEST_CASE(tester, persistence, "Tester node: test persistence of subnet bridge states"), +#endif + TEST_CASE(tester, ivu, "Tester node: tests subnet bridge with IV Update procedure"), + TEST_CASE(bridge, simple, "Subnet Bridge node"), + TEST_CASE(device, simple, "A mesh node"), + + TEST_CASE(bridge, simple_iv_test_mode, "Subnet Bridge node with IV test mode enabled"), + TEST_CASE(device, simple_iv_test_mode, "A mesh node with IV test mode enabled"), + + BSTEST_END_MARKER +}; + +struct bst_test_list *test_brg_install(struct bst_test_list *tests) +{ + tests = bst_add_tests(tests, test_brg); + return tests; +} diff --git a/tests/bsim/bluetooth/mesh/src/test_replay_cache.c b/tests/bsim/bluetooth/mesh/src/test_replay_cache.c index 57d605fb97a50df..636e112715a1ed6 100644 --- a/tests/bsim/bluetooth/mesh/src/test_replay_cache.c +++ b/tests/bsim/bluetooth/mesh/src/test_replay_cache.c @@ -381,11 +381,11 @@ static void test_rx_rpl_frag(void) .ctx.addr = 100, .local_match = 1, }; - ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl)); + ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl, false)); rx.ctx.addr = 101; - ASSERT_FALSE(bt_mesh_rpl_check(&rx, &rpl)); + ASSERT_FALSE(bt_mesh_rpl_check(&rx, &rpl, false)); rx.ctx.addr = 102; - ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl)); + ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl, false)); /* Let the settings store RPL. */ k_sleep(K_SECONDS(CONFIG_BT_MESH_RPL_STORE_TIMEOUT)); @@ -455,11 +455,11 @@ static void test_rx_reboot_after_defrag(void) .ctx.addr = 100, .local_match = 1, }; - ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl)); + ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl, false)); rx.ctx.addr = 101; - ASSERT_FALSE(bt_mesh_rpl_check(&rx, &rpl)); + ASSERT_FALSE(bt_mesh_rpl_check(&rx, &rpl, false)); rx.ctx.addr = 102; - ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl)); + ASSERT_TRUE(bt_mesh_rpl_check(&rx, &rpl, false)); PASS(); } diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh new file mode 100755 index 000000000000000..1a6ad2b27749a11 --- /dev/null +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh @@ -0,0 +1,22 @@ +#!/usr/bin/env bash +# Copyright 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh + +# Test that correct Net Keys are used when bridged subnets in a different IVU phase. +# +# Test Procedure: +# 1. All nodes have IV Update test mode enabled. +# 2. Provisioner configures itself and creates subnets equal to number of non-bridge devices. +# 3. Provisioner provisions and configures Subnet Bridge node to bridge the subnets. +# 4. Provisioner provisions and configures non-bridge devices for each subnet. + +RunTest mesh_brg_ivu \ + brg_tester_ivu brg_bridge_simple_iv_test_mode brg_device_simple_iv_test_mode \ + brg_device_simple_iv_test_mode + +overlay=overlay_psa_conf +RunTest mesh_brg_ivu \ + brg_tester_ivu brg_bridge_simple_iv_test_mode brg_device_simple_iv_test_mode \ + brg_device_simple_iv_test_mode diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh new file mode 100755 index 000000000000000..17ca0ea2b4bbad8 --- /dev/null +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh @@ -0,0 +1,25 @@ +#!/usr/bin/env bash +# Copyright 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh + +# Test verifies that an entry is removed from the bridging table when the NetKey is removed +# +# Test procedure: +# 1. Tester configures itself and creates subnets equal to number of non-bridge nodes. +# 2. Tester provisions and configures Subnet Bridge node. +# 3. Tester provisions and configures non-bridge nodes for each subnet. +# 4. Tester sends DATA and GET messages to the device 1 encrypted with primary key and verifies that +# device 1 sends a STATUS message with the content of the DATA message. +# 5. Tester removes the NetKey from Subnet Bridge node. +# 6. Tester sends a GET message and verifies that no response is received. +# 7. Tester retrieves entries from the bridging table and verifies that the entry with NetKeyIndex2 +# set to the removed NetKey is removed. + +RunTest mesh_brg_net_key_remove \ + brg_tester_net_key_remove brg_bridge_simple brg_device_simple brg_device_simple + +overlay=overlay_psa_conf +RunTest mesh_brg_net_key_remove \ + brg_tester_net_key_remove brg_bridge_simple brg_device_simple brg_device_simple diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh new file mode 100755 index 000000000000000..989f01abb23e79d --- /dev/null +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh @@ -0,0 +1,30 @@ +#!/usr/bin/env bash +# Copyright 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh + +# Test verifies that subnet bridge states are restored correctly after reboot +# +# Test procedure: +# 1. Tester configures itself and creates subnets equal to number of non-bridge nodes. +# 2. Tester provisions and configures Subnet Bridge node to bridge the subnets. +# 3. Devices reboot +# 4. Tester retrieves and verifies configuration of the Subnet Bridge node + +overlay=overlay_pst_conf +RunTestFlash mesh_brg_persistence \ + brg_tester_persistence -flash_erase brg_bridge_simple -flash_erase + +overlay=overlay_pst_conf +RunTestFlash mesh_brg_persistence \ + brg_tester_persistence brg_bridge_simple + +# The same test but with PSA crypto +overlay="overlay_pst_conf_overlay_psa_conf" +RunTestFlash mesh_brg_persistence \ + brg_tester_persistence -flash_erase brg_bridge_simple -flash_erase + +overlay="overlay_pst_conf_overlay_psa_conf" +RunTestFlash mesh_brg_persistence \ + brg_tester_persistence brg_bridge_simple diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh new file mode 100755 index 000000000000000..16aa96ac1a2cd85 --- /dev/null +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh @@ -0,0 +1,45 @@ +#!/usr/bin/env bash +# Copyright 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh + +# This test verifies that Subnet Bridge stops bridging messages when the Subnet Bridge state is +# disabled. +# +# 3 roles are used in this test: Tester (Tester), Subnet Bridge node, and Mesh node. +# +# Subnets topology*: +# Tester +# | +# (subnet 0) +# | +# Subnet Bridge (bridges subnets 0 <-> 1, 0 <-> 2) +# / \ +# (subnet 1) (subnet 2) +# | | +# Node Node +# +# (*) - All nodes are in the tester's range +# +# Test procedure: +# 1. Tester configures itself and creates subnets equal to number of non-bridge nodes. +# 2. Tester provisions and configures Subnet Bridge node to bridge the subnets. +# 3. Tester provisions and configures non-bridge nodes for each subnet. +# 4. Tester sends a DATA message to each node encrypted with primary key. +# 5. Nodes store the received messages. +# 6. Tester sends a GET message to each node encrypted with primary key. +# 7. Nodes send the stored messages back to the tester through a STATUS message encrypted +# with the key of the subnets they are provisioned to. +# 8. Tester verifies that each node received messages. +# 9. Tester disables Subnet Bridge state. +# 10. Tester sends a DATA message to each node encrypted with primary key. +# 11. Tester sends a GET message to each node encrypted with primary key. +# 12. Tester verifies that each node didn't receive DATA messages. + +RunTest mesh_brg_simple \ + brg_tester_simple brg_bridge_simple brg_device_simple brg_device_simple + +overlay=overlay_psa_conf +RunTest mesh_brg_simple \ + brg_tester_simple brg_bridge_simple brg_device_simple brg_device_simple diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh new file mode 100755 index 000000000000000..ffaa6104530324a --- /dev/null +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh @@ -0,0 +1,32 @@ +#!/usr/bin/env bash +# Copyright 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh + +# Test verifies that bridging table works correctly +# +# Test procedure: +# 1. Tester configures itself and creates subnets equal to number of non-bridge nodes. +# 2. Tester provisions and configures Subnet Bridge node. +# 3. Tester provisions and configures non-bridge nodes for each subnet. +# 4. While bridging table is empty, Tester sends a GET message to each node encrypted with primary +# key and verifies that no response is received. +# 5. Tester adds an entry to the bridging table to bridge traffic in one direction from tester to +# device 1 +# 6. Tester sends a DATA and GET messages to device 1 encrypted with primary key and verifies that +# no response is received. +# 9. Tester adds a reverse entry to the bridging table to bridge traffic in the other direction from +# device 1 to tester. +# 10. Tester sends a GET message to device 1 encrypted with primary key and verifies that a STATUS +# message is received with the content of the previously sent DATA message. +# 11. Tester removes the reverse entry from the bridging table and updates direction of the first +# entry to bridge traffic in the both directions between tester and device 1. +# 12. Tester sends a GET message to device 1 encrypted with primary key and verifies that a STATUS +# message is received with the empty content. +RunTest mesh_brg_table_state_change \ + brg_tester_table_state_change brg_bridge_simple brg_device_simple brg_device_simple + +overlay=overlay_psa_conf +RunTest mesh_brg_table_state_change \ + brg_tester_table_state_change brg_bridge_simple brg_device_simple brg_device_simple From e0f5f3acf4f08e1fc5b226fd2d9edbd0960e8cde Mon Sep 17 00:00:00 2001 From: Pavel Vasilyev Date: Tue, 10 Sep 2024 21:52:32 +0200 Subject: [PATCH 136/269] bluetooth: mesh: brg_cfg_srv: ignore message with invalid parameters When a message with invalid parameters is received, we must ignore it. In this commit we check invalid parameters first. Signed-off-by: Pavel Vasilyev --- subsys/bluetooth/mesh/brg_cfg.c | 38 ++++++++++++++---- subsys/bluetooth/mesh/brg_cfg.h | 4 +- subsys/bluetooth/mesh/brg_cfg_srv.c | 31 ++++----------- tests/bluetooth/mesh/brg/src/main.c | 62 ++++++++++++++++++++--------- 4 files changed, 83 insertions(+), 52 deletions(-) diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c index c6974b9ede1a4e2..d13e1a582a9a8ac 100644 --- a/subsys/bluetooth/mesh/brg_cfg.c +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -14,6 +14,7 @@ #include "net.h" #include "settings.h" #include "brg_cfg.h" +#include "foundation.h" #define LOG_LEVEL CONFIG_BT_MESH_BRG_LOG_LEVEL #include @@ -219,26 +220,38 @@ int bt_mesh_brg_cfg_tbl_get(const struct bt_mesh_brg_cfg_row **rows) return bt_mesh_brg_cfg_row_cnt; } +static bool netkey_check(uint16_t net_idx1, uint16_t net_idx2) +{ + return bt_mesh_subnet_get(net_idx1) && bt_mesh_subnet_get(net_idx2); +} + int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx1, - uint16_t net_idx2, uint16_t addr1, uint16_t addr2) + uint16_t net_idx2, uint16_t addr1, uint16_t addr2, uint8_t *status) { /* Sanity checks */ - if (!BT_MESH_ADDR_IS_UNICAST(addr1) || net_idx1 == net_idx2 || addr1 == addr2 || - net_idx1 > BT_MESH_BRG_CFG_KEY_INDEX_MAX || net_idx2 > BT_MESH_BRG_CFG_KEY_INDEX_MAX) { + if (!BT_MESH_ADDR_IS_UNICAST(addr1) || net_idx1 == net_idx2 || + addr1 == addr2 || net_idx1 > BT_MESH_BRG_CFG_KEY_INDEX_MAX || + net_idx2 > BT_MESH_BRG_CFG_KEY_INDEX_MAX) { return -EINVAL; } - if (direction != BT_MESH_BRG_CFG_DIR_ONEWAY && direction != BT_MESH_BRG_CFG_DIR_TWOWAY) { + if (direction != BT_MESH_BRG_CFG_DIR_ONEWAY && + direction != BT_MESH_BRG_CFG_DIR_TWOWAY) { return -EINVAL; } if ((direction == BT_MESH_BRG_CFG_DIR_ONEWAY && - (addr2 == BT_MESH_ADDR_UNASSIGNED || addr2 == BT_MESH_ADDR_ALL_NODES)) || + (addr2 == BT_MESH_ADDR_UNASSIGNED || addr2 == BT_MESH_ADDR_ALL_NODES)) || (direction == BT_MESH_BRG_CFG_DIR_TWOWAY && - !BT_MESH_ADDR_IS_UNICAST(addr2))) { + !BT_MESH_ADDR_IS_UNICAST(addr2))) { return -EINVAL; } + if (!netkey_check(net_idx1, net_idx2)) { + *status = STATUS_INVALID_NETKEY; + return 0; + } + /* Check if entry already exists, if yes, then, update the direction field and it is a * success. * "If a Bridging Table state entry corresponding to the received message exists, the @@ -256,7 +269,8 @@ int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx /* Empty element, is the current table row counter */ if (bt_mesh_brg_cfg_row_cnt == CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { - return -ENOMEM; + *status = STATUS_INSUFF_RESOURCES; + return 0; } /* Update the row */ @@ -273,6 +287,7 @@ int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); } + *status = STATUS_SUCCESS; return 0; } @@ -294,12 +309,13 @@ void bt_mesh_brg_cfg_tbl_foreach_subnet(uint16_t src, uint16_t dst, uint16_t net } int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, - uint16_t addr2) + uint16_t addr2, uint8_t *status) { bool store = false; /* Sanity checks */ if ((!BT_MESH_ADDR_IS_UNICAST(addr1) && addr1 != BT_MESH_ADDR_UNASSIGNED) || + (BT_MESH_ADDR_IS_UNICAST(addr1) && addr1 == addr2) || addr2 == BT_MESH_ADDR_ALL_NODES) { return -EINVAL; } @@ -309,11 +325,16 @@ int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t ad return -EINVAL; } + if (!netkey_check(net_idx1, net_idx2)) { + *status = STATUS_INVALID_NETKEY; + return 0; + } /* Iterate over items and set matching row to 0, if nothing exist, or nothing matches, then * it is success (similar to add) */ if (bt_mesh_brg_cfg_row_cnt == 0) { + *status = STATUS_SUCCESS; return 0; } @@ -341,5 +362,6 @@ int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t ad bt_mesh_settings_store_schedule(BT_MESH_SETTINGS_BRG_PENDING); } + *status = STATUS_SUCCESS; return 0; } diff --git a/subsys/bluetooth/mesh/brg_cfg.h b/subsys/bluetooth/mesh/brg_cfg.h index 033572e9496774f..95455c4e02a2c21 100644 --- a/subsys/bluetooth/mesh/brg_cfg.h +++ b/subsys/bluetooth/mesh/brg_cfg.h @@ -51,10 +51,10 @@ int bt_mesh_brg_cfg_tbl_reset(void); int bt_mesh_brg_cfg_tbl_get(const struct bt_mesh_brg_cfg_row **rows); int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx1, - uint16_t net_idx2, uint16_t addr1, uint16_t addr2); + uint16_t net_idx2, uint16_t addr1, uint16_t addr2, uint8_t *status); int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, - uint16_t addr2); + uint16_t addr2, uint8_t *status); typedef void (*bt_mesh_brg_cfg_cb_t)(uint16_t new_netidx, void *user_data); diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c index adfe5de535a51c8..581dd980111ed06 100644 --- a/subsys/bluetooth/mesh/brg_cfg_srv.c +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -78,28 +78,19 @@ static int bridging_table_add(const struct bt_mesh_model *model, struct bt_mesh_ { struct bt_mesh_bridging_table_entry entry; uint8_t status = STATUS_SUCCESS; + int err; entry.directions = net_buf_simple_pull_u8(buf); key_idx_unpack_pair(buf, &entry.net_idx1, &entry.net_idx2); entry.addr1 = net_buf_simple_pull_le16(buf); entry.addr2 = net_buf_simple_pull_le16(buf); - if (!netkey_check(entry.net_idx1, entry.net_idx2)) { - status = STATUS_INVALID_NETKEY; - goto add_respond; - } - - int err = bt_mesh_brg_cfg_tbl_add(entry.directions, entry.net_idx1, entry.net_idx2, - entry.addr1, entry.addr2); - if (err == -ENOMEM) { - status = STATUS_INSUFF_RESOURCES; - } else if (err) { - /* Per spec, do not respond if parameters values are invalid. */ + err = bt_mesh_brg_cfg_tbl_add(entry.directions, entry.net_idx1, entry.net_idx2, entry.addr1, + entry.addr2, &status); + if (err) { return err; } -add_respond: - bridging_table_status_send(model, ctx, status, &entry); return 0; @@ -110,27 +101,19 @@ static int bridging_table_remove(const struct bt_mesh_model *model, struct bt_me { struct bt_mesh_bridging_table_entry entry; uint8_t status = STATUS_SUCCESS; + int err; entry.directions = 0; key_idx_unpack_pair(buf, &entry.net_idx1, &entry.net_idx2); entry.addr1 = net_buf_simple_pull_le16(buf); entry.addr2 = net_buf_simple_pull_le16(buf); - if (!netkey_check(entry.net_idx1, entry.net_idx2)) { - status = STATUS_INVALID_NETKEY; - goto rmv_respond; - } - - int err = bt_mesh_brg_cfg_tbl_remove(entry.net_idx1, entry.net_idx2, entry.addr1, - entry.addr2); - - /* Per spec, do not respond if parameters values are invalid. */ + err = bt_mesh_brg_cfg_tbl_remove(entry.net_idx1, entry.net_idx2, entry.addr1, entry.addr2, + &status); if (err) { return err; } -rmv_respond: - bridging_table_status_send(model, ctx, status, &entry); return 0; diff --git a/tests/bluetooth/mesh/brg/src/main.c b/tests/bluetooth/mesh/brg/src/main.c index 68103c9f14ce29b..15d964fadcb2bc3 100644 --- a/tests/bluetooth/mesh/brg/src/main.c +++ b/tests/bluetooth/mesh/brg/src/main.c @@ -11,6 +11,7 @@ #include "settings.h" #include "brg_cfg.h" +#include "foundation.h" #define TEST_VECT_SZ (CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX + 1) @@ -36,7 +37,6 @@ static void setup(void *f) test_vector[i].net_idx2 = (i/8) + 16; test_vector[i].addr2 = ADDR2_BASE + i; } - } /**** Mocked functions ****/ @@ -60,10 +60,17 @@ int settings_delete(const char *name) return 0; } +struct bt_mesh_subnet *bt_mesh_subnet_get(uint16_t net_idx) +{ + /* Return anything non-zero. */ + return (struct bt_mesh_subnet *) 1; +} + /**** Mocked functions - end ****/ static void check_fill_all_bt_entries(void) { + uint8_t status; int err; for (int i = 0; i < TEST_VECT_SZ; i++) { @@ -74,18 +81,23 @@ static void check_fill_all_bt_entries(void) } err = bt_mesh_brg_cfg_tbl_add(test_vector[i].direction, test_vector[i].net_idx1, - test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2); + test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2, + &status); + + zassert_equal(err, 0); if (i != CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { - zassert_equal(err, 0); + zassert_equal(status, STATUS_SUCCESS); } else { - zassert_equal(err, -ENOMEM); + zassert_equal(status, STATUS_INSUFF_RESOURCES); } } } static void check_delete_all_bt_entries(void) { + uint8_t status; + for (int i = 0; i < TEST_VECT_SZ; i++) { if (i < CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { @@ -95,9 +107,10 @@ static void check_delete_all_bt_entries(void) int err = bt_mesh_brg_cfg_tbl_remove(test_vector[i].net_idx1, test_vector[i].net_idx2, test_vector[i].addr1, - test_vector[i].addr2); + test_vector[i].addr2, &status); zassert_equal(err, 0); + zassert_equal(status, STATUS_SUCCESS); } } @@ -132,6 +145,7 @@ ZTEST(bt_mesh_brg_cfg, test_basic_functionality_storage) check_bt_mesh_brg_cfg_tbl_reset(); check_fill_all_bt_entries(); + uint8_t status; int err; uint16_t net_idx1 = test_vector[TEST_VECT_SZ - 1].net_idx1; uint16_t net_idx2 = test_vector[TEST_VECT_SZ - 1].net_idx2; @@ -140,27 +154,27 @@ ZTEST(bt_mesh_brg_cfg, test_basic_functionality_storage) /* Try removing entries with invalid params */ uint16_t addr2 = BT_MESH_ADDR_ALL_NODES; - err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2, &status); zassert_equal(err, -EINVAL); addr2 = BT_MESH_ADDR_UNASSIGNED; addr1 = BT_MESH_ADDR_RELAYS; - err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2, &status); zassert_equal(err, -EINVAL); addr1 = BT_MESH_ADDR_UNASSIGNED; net_idx1 = 4096; - err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2, &status); zassert_equal(err, -EINVAL); net_idx1 = test_vector[TEST_VECT_SZ - 1].net_idx1; net_idx2 = 4096; - err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2, &status); zassert_equal(err, -EINVAL); /* Test remove entries matching netkey1, and netkey2 */ net_idx2 = test_vector[TEST_VECT_SZ - 1].net_idx2; - err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2); + err = bt_mesh_brg_cfg_tbl_remove(net_idx1, net_idx2, addr1, addr2, &status); zassert_equal(err, 0); const struct bt_mesh_brg_cfg_row *brg_tbl; @@ -255,6 +269,7 @@ ZTEST(bt_mesh_brg_cfg, test_brg_cfg_en) /* Test if pending store works correctly by adding one entry to the table. */ ZTEST(bt_mesh_brg_cfg, test_brg_tbl_pending_store) { + uint8_t status; int n, err; struct bt_mesh_brg_cfg_row test_vec = { .direction = BT_MESH_BRG_CFG_DIR_ONEWAY, @@ -268,8 +283,9 @@ ZTEST(bt_mesh_brg_cfg, test_brg_tbl_pending_store) ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_BRG_PENDING); err = bt_mesh_brg_cfg_tbl_add(test_vec.direction, test_vec.net_idx1, - test_vec.net_idx2, test_vec.addr1, test_vec.addr2); + test_vec.net_idx2, test_vec.addr1, test_vec.addr2, &status); zassert_equal(err, 0); + zassert_equal(status, STATUS_SUCCESS); const struct bt_mesh_brg_cfg_row *tbl; @@ -285,6 +301,7 @@ ZTEST(bt_mesh_brg_cfg, test_brg_tbl_pending_store) /* Test if invalid entries are not added to the table. */ ZTEST(bt_mesh_brg_cfg, test_tbl_add_invalid_ip) { + uint8_t status; int err; /* Create test vector array of test_brg_cfg_row iteams with invalid values. * Each vector has only one invalid field value, rest all are valid values. @@ -337,7 +354,8 @@ ZTEST(bt_mesh_brg_cfg, test_tbl_add_invalid_ip) for (int i = 0; i < ARRAY_SIZE(inv_test_vector); i++) { err = bt_mesh_brg_cfg_tbl_add(inv_test_vector[i].direction, inv_test_vector[i].net_idx1, inv_test_vector[i].net_idx2, - inv_test_vector[i].addr1, inv_test_vector[i].addr2); + inv_test_vector[i].addr1, inv_test_vector[i].addr2, + &status); zassert_equal(err, -EINVAL, "Test vector index: %zu", i); } } @@ -362,27 +380,32 @@ static void print_brg_tbl(void) static void check_fill_all_bt_entries_reversed(void) { + uint8_t status; int err; for (int i = TEST_VECT_SZ - 2; i >= 0 ; i--) { ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_BRG_PENDING); err = bt_mesh_brg_cfg_tbl_add(test_vector[i].direction, test_vector[i].net_idx1, - test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2); + test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2, + &status); zassert_equal(err, 0); } int last = TEST_VECT_SZ - 1; err = bt_mesh_brg_cfg_tbl_add(test_vector[last].direction, test_vector[last].net_idx1, - test_vector[last].net_idx2, test_vector[last].addr1, test_vector[last].addr2); - zassert_equal(err, -ENOMEM); + test_vector[last].net_idx2, test_vector[last].addr1, + test_vector[last].addr2, &status); + zassert_equal(err, 0); + zassert_equal(status, STATUS_INSUFF_RESOURCES); } static struct test_brg_cfg_row test_vector_copy[TEST_VECT_SZ - 1]; static void check_fill_all_bt_entries_randomly(void) { + uint8_t status; int err; int copy_cnt = ARRAY_SIZE(test_vector_copy); @@ -401,15 +424,18 @@ static void check_fill_all_bt_entries_randomly(void) BT_MESH_SETTINGS_BRG_PENDING); err = bt_mesh_brg_cfg_tbl_add(test_vector_copy[i].direction, test_vector_copy[i].net_idx1, test_vector_copy[i].net_idx2, - test_vector_copy[i].addr1, test_vector_copy[i].addr2); + test_vector_copy[i].addr1, test_vector_copy[i].addr2, &status); zassert_equal(err, 0); + zassert_equal(status, STATUS_SUCCESS); } int last = TEST_VECT_SZ - 1; err = bt_mesh_brg_cfg_tbl_add(test_vector[last].direction, test_vector[last].net_idx1, - test_vector[last].net_idx2, test_vector[last].addr1, test_vector[last].addr2); - zassert_equal(err, -ENOMEM); + test_vector[last].net_idx2, test_vector[last].addr1, test_vector[last].addr2, + &status); + zassert_equal(err, 0); + zassert_equal(status, STATUS_INSUFF_RESOURCES); } static void subnet_relay_cb_check(uint16_t new_net_idx, void *user_data) From d41e834bbe2f4090fdead7478781b22fee912fd3 Mon Sep 17 00:00:00 2001 From: Ingar Kulbrandstad Date: Fri, 13 Sep 2024 16:11:13 +0200 Subject: [PATCH 137/269] tests: bluetooth: mesh: Removed native_posix and renamed sim_ids Removed deprecated native_posix as test platform. Added unique sim_ids for tests with the psa as a overlay. Fixed clang-format issues. Signed-off-by: Ingar Kulbrandstad --- include/zephyr/bluetooth/mesh/brg_cfg.h | 6 +- include/zephyr/bluetooth/mesh/brg_cfg_srv.h | 6 +- subsys/bluetooth/mesh/brg_cfg.c | 38 +- subsys/bluetooth/mesh/brg_cfg.h | 10 +- subsys/bluetooth/mesh/brg_cfg_cli.c | 16 +- subsys/bluetooth/mesh/brg_cfg_srv.c | 29 +- subsys/bluetooth/mesh/foundation.h | 24 +- subsys/bluetooth/mesh/net.c | 9 +- subsys/bluetooth/mesh/settings.c | 19 +- subsys/bluetooth/mesh/shell/brg_cfg.c | 19 +- tests/bluetooth/mesh/brg/prj.conf | 1 - tests/bluetooth/mesh/brg/src/main.c | 209 ++++++---- tests/bluetooth/mesh/brg/testcase.yaml | 1 - tests/bluetooth/mesh_shell/src/main.c | 3 +- tests/bluetooth/tester/src/btp/btp_mesh.h | 14 +- tests/bluetooth/tester/src/btp_mesh.c | 374 +++++++----------- tests/bsim/bluetooth/mesh/src/main.c | 12 +- tests/bsim/bluetooth/mesh/src/test_brg.c | 164 ++++---- .../mesh/tests_scripts/bridge/brg_ivu.sh | 2 +- .../bridge/brg_net_key_update.sh | 2 +- .../bridge/brg_persistent_storage.sh | 4 +- .../mesh/tests_scripts/bridge/brg_simple.sh | 2 +- .../bridge/brg_table_state_change.sh | 2 +- 23 files changed, 454 insertions(+), 512 deletions(-) diff --git a/include/zephyr/bluetooth/mesh/brg_cfg.h b/include/zephyr/bluetooth/mesh/brg_cfg.h index 470625609ac697c..906a2e0bb381f65 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg.h @@ -57,9 +57,9 @@ struct bt_mesh_bridging_table_status { /** Used to filter set of pairs of NetKey Indexes from the Bridging Table */ struct bt_mesh_filter_netkey { - uint16_t filter:2, /* Filter applied to the set of pairs of NetKey Indexes */ - prohibited:2, /* Prohibited */ - net_idx:12; /* NetKey Index used for filtering or ignored */ + uint16_t filter: 2, /* Filter applied to the set of pairs of NetKey Indexes */ + prohibited: 2, /* Prohibited */ + net_idx: 12; /* NetKey Index used for filtering or ignored */ }; /** Bridged Subnets List response */ diff --git a/include/zephyr/bluetooth/mesh/brg_cfg_srv.h b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h index 271dd37c5f6898e..0440be6fdaa0e30 100644 --- a/include/zephyr/bluetooth/mesh/brg_cfg_srv.h +++ b/include/zephyr/bluetooth/mesh/brg_cfg_srv.h @@ -27,9 +27,9 @@ extern "C" { * * @brief Bridge Configuration Server model Composition Data entry. */ -#define BT_MESH_MODEL_BRG_CFG_SRV \ - BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_SRV, _bt_mesh_brg_cfg_srv_op, \ - NULL, NULL, &_bt_mesh_brg_cfg_srv_cb) +#define BT_MESH_MODEL_BRG_CFG_SRV \ + BT_MESH_MODEL_CB(BT_MESH_MODEL_ID_BRG_CFG_SRV, _bt_mesh_brg_cfg_srv_op, NULL, NULL, \ + &_bt_mesh_brg_cfg_srv_cb) /** @cond INTERNAL_HIDDEN */ extern const struct bt_mesh_model_op _bt_mesh_brg_cfg_srv_op[]; diff --git a/subsys/bluetooth/mesh/brg_cfg.c b/subsys/bluetooth/mesh/brg_cfg.c index d13e1a582a9a8ac..9c90773faef30d7 100644 --- a/subsys/bluetooth/mesh/brg_cfg.c +++ b/subsys/bluetooth/mesh/brg_cfg.c @@ -172,9 +172,8 @@ static void brg_tbl_netkey_removed_evt(struct bt_mesh_subnet *sub, enum bt_mesh_ } for (int i = 0; i < CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX; i++) { - if (brg_tbl[i].direction && ( - brg_tbl[i].net_idx1 == sub->net_idx || - brg_tbl[i].net_idx2 == sub->net_idx)) { + if (brg_tbl[i].direction && + (brg_tbl[i].net_idx1 == sub->net_idx || brg_tbl[i].net_idx2 == sub->net_idx)) { memset(&brg_tbl[i], 0, sizeof(brg_tbl[i])); brg_tbl_compact(); } @@ -229,21 +228,18 @@ int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx uint16_t net_idx2, uint16_t addr1, uint16_t addr2, uint8_t *status) { /* Sanity checks */ - if (!BT_MESH_ADDR_IS_UNICAST(addr1) || net_idx1 == net_idx2 || - addr1 == addr2 || net_idx1 > BT_MESH_BRG_CFG_KEY_INDEX_MAX || - net_idx2 > BT_MESH_BRG_CFG_KEY_INDEX_MAX) { + if (!BT_MESH_ADDR_IS_UNICAST(addr1) || net_idx1 == net_idx2 || addr1 == addr2 || + net_idx1 > BT_MESH_BRG_CFG_KEY_INDEX_MAX || net_idx2 > BT_MESH_BRG_CFG_KEY_INDEX_MAX) { return -EINVAL; } - if (direction != BT_MESH_BRG_CFG_DIR_ONEWAY && - direction != BT_MESH_BRG_CFG_DIR_TWOWAY) { + if (direction != BT_MESH_BRG_CFG_DIR_ONEWAY && direction != BT_MESH_BRG_CFG_DIR_TWOWAY) { return -EINVAL; } if ((direction == BT_MESH_BRG_CFG_DIR_ONEWAY && (addr2 == BT_MESH_ADDR_UNASSIGNED || addr2 == BT_MESH_ADDR_ALL_NODES)) || - (direction == BT_MESH_BRG_CFG_DIR_TWOWAY && - !BT_MESH_ADDR_IS_UNICAST(addr2))) { + (direction == BT_MESH_BRG_CFG_DIR_TWOWAY && !BT_MESH_ADDR_IS_UNICAST(addr2))) { return -EINVAL; } @@ -259,9 +255,8 @@ int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx * in the received message." */ for (int i = 0; i < bt_mesh_brg_cfg_row_cnt; i++) { - if (brg_tbl[i].net_idx1 == net_idx1 && - brg_tbl[i].net_idx2 == net_idx2 && brg_tbl[i].addr1 == addr1 && - brg_tbl[i].addr2 == addr2) { + if (brg_tbl[i].net_idx1 == net_idx1 && brg_tbl[i].net_idx2 == net_idx2 && + brg_tbl[i].addr1 == addr1 && brg_tbl[i].addr2 == addr2) { brg_tbl[i].direction = direction; goto store; } @@ -295,28 +290,27 @@ void bt_mesh_brg_cfg_tbl_foreach_subnet(uint16_t src, uint16_t dst, uint16_t net bt_mesh_brg_cfg_cb_t cb, void *user_data) { for (int i = 0; i < bt_mesh_brg_cfg_row_cnt; i++) { - if ((brg_tbl[i].direction == BT_MESH_BRG_CFG_DIR_ONEWAY || + if ((brg_tbl[i].direction == BT_MESH_BRG_CFG_DIR_ONEWAY || brg_tbl[i].direction == BT_MESH_BRG_CFG_DIR_TWOWAY) && - brg_tbl[i].net_idx1 == net_idx && brg_tbl[i].addr1 == src && - brg_tbl[i].addr2 == dst) { + brg_tbl[i].net_idx1 == net_idx && brg_tbl[i].addr1 == src && + brg_tbl[i].addr2 == dst) { cb(brg_tbl[i].net_idx2, user_data); } else if ((brg_tbl[i].direction == BT_MESH_BRG_CFG_DIR_TWOWAY && - brg_tbl[i].net_idx2 == net_idx && brg_tbl[i].addr2 == src && - brg_tbl[i].addr1 == dst)) { + brg_tbl[i].net_idx2 == net_idx && brg_tbl[i].addr2 == src && + brg_tbl[i].addr1 == dst)) { cb(brg_tbl[i].net_idx1, user_data); } } } -int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, - uint16_t addr2, uint8_t *status) +int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2, + uint8_t *status) { bool store = false; /* Sanity checks */ if ((!BT_MESH_ADDR_IS_UNICAST(addr1) && addr1 != BT_MESH_ADDR_UNASSIGNED) || - (BT_MESH_ADDR_IS_UNICAST(addr1) && addr1 == addr2) || - addr2 == BT_MESH_ADDR_ALL_NODES) { + (BT_MESH_ADDR_IS_UNICAST(addr1) && addr1 == addr2) || addr2 == BT_MESH_ADDR_ALL_NODES) { return -EINVAL; } diff --git a/subsys/bluetooth/mesh/brg_cfg.h b/subsys/bluetooth/mesh/brg_cfg.h index 95455c4e02a2c21..af8cc5adc0f1ff4 100644 --- a/subsys/bluetooth/mesh/brg_cfg.h +++ b/subsys/bluetooth/mesh/brg_cfg.h @@ -33,9 +33,9 @@ struct bt_mesh_brg_cfg_row { * 1 - bridge messages with src as addr1 and dst as addr2 * 2 - bridge messages with src as addr1 and dst as addr2 and vice-versa */ - uint32_t direction:8; - uint32_t net_idx1:12; - uint32_t net_idx2:12; + uint32_t direction: 8; + uint32_t net_idx1: 12; + uint32_t net_idx2: 12; uint16_t addr1; uint16_t addr2; }; @@ -53,8 +53,8 @@ int bt_mesh_brg_cfg_tbl_get(const struct bt_mesh_brg_cfg_row **rows); int bt_mesh_brg_cfg_tbl_add(enum bt_mesh_brg_cfg_dir direction, uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2, uint8_t *status); -int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, - uint16_t addr2, uint8_t *status); +int bt_mesh_brg_cfg_tbl_remove(uint16_t net_idx1, uint16_t net_idx2, uint16_t addr1, uint16_t addr2, + uint8_t *status); typedef void (*bt_mesh_brg_cfg_cb_t)(uint16_t new_netidx, void *user_data); diff --git a/subsys/bluetooth/mesh/brg_cfg_cli.c b/subsys/bluetooth/mesh/brg_cfg_cli.c index 54cafd552629a8e..229b0b6f89227a5 100644 --- a/subsys/bluetooth/mesh/brg_cfg_cli.c +++ b/subsys/bluetooth/mesh/brg_cfg_cli.c @@ -37,7 +37,7 @@ static int subnet_bridge_status(const struct bt_mesh_model *model, struct bt_mes } static int bridging_table_status(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, - struct net_buf_simple *buf) + struct net_buf_simple *buf) { struct bt_mesh_bridging_table_status table_status; struct bt_mesh_bridging_table_status *rsp; @@ -49,7 +49,7 @@ static int bridging_table_status(const struct bt_mesh_model *model, struct bt_me table_status.entry.addr2 = net_buf_simple_pull_le16(buf); if (!(table_status.entry.addr1 == BT_MESH_ADDR_UNASSIGNED || - BT_MESH_ADDR_IS_UNICAST(table_status.entry.addr1))) { + BT_MESH_ADDR_IS_UNICAST(table_status.entry.addr1))) { LOG_ERR("addr1 shall be a unicast address or unassigned."); return -EINVAL; } else if (table_status.entry.addr2 == BT_MESH_ADDR_ALL_NODES) { @@ -109,7 +109,7 @@ static int bridged_subnets_list(const struct bt_mesh_model *model, struct bt_mes } static int bridging_table_list(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, - struct net_buf_simple *buf) + struct net_buf_simple *buf) { struct bt_mesh_bridging_table_list table_list; struct bt_mesh_bridging_table_list *rsp; @@ -166,11 +166,11 @@ static int bridging_table_size_status(const struct bt_mesh_model *model, } const struct bt_mesh_model_op _bt_mesh_brg_cfg_cli_op[] = { - { OP_SUBNET_BRIDGE_STATUS, BT_MESH_LEN_EXACT(1), subnet_bridge_status }, - { OP_BRIDGING_TABLE_STATUS, BT_MESH_LEN_EXACT(9), bridging_table_status }, - { OP_BRIDGED_SUBNETS_LIST, BT_MESH_LEN_MIN(3), bridged_subnets_list }, - { OP_BRIDGING_TABLE_LIST, BT_MESH_LEN_MIN(6), bridging_table_list }, - { OP_BRIDGING_TABLE_SIZE_STATUS, BT_MESH_LEN_EXACT(2), bridging_table_size_status }, + {OP_SUBNET_BRIDGE_STATUS, BT_MESH_LEN_EXACT(1), subnet_bridge_status}, + {OP_BRIDGING_TABLE_STATUS, BT_MESH_LEN_EXACT(9), bridging_table_status}, + {OP_BRIDGED_SUBNETS_LIST, BT_MESH_LEN_MIN(3), bridged_subnets_list}, + {OP_BRIDGING_TABLE_LIST, BT_MESH_LEN_MIN(6), bridging_table_list}, + {OP_BRIDGING_TABLE_SIZE_STATUS, BT_MESH_LEN_EXACT(2), bridging_table_size_status}, BT_MESH_MODEL_OP_END, }; diff --git a/subsys/bluetooth/mesh/brg_cfg_srv.c b/subsys/bluetooth/mesh/brg_cfg_srv.c index 581dd980111ed06..7492caf3771cf24 100644 --- a/subsys/bluetooth/mesh/brg_cfg_srv.c +++ b/subsys/bluetooth/mesh/brg_cfg_srv.c @@ -51,8 +51,8 @@ static int subnet_bridge_set(const struct bt_mesh_model *model, struct bt_mesh_m } static void bridging_table_status_send(const struct bt_mesh_model *model, - struct bt_mesh_msg_ctx *ctx, uint8_t status, - struct bt_mesh_bridging_table_entry *entry) + struct bt_mesh_msg_ctx *ctx, uint8_t status, + struct bt_mesh_bridging_table_entry *entry) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_STATUS, 9); @@ -123,7 +123,8 @@ static int bridged_subnets_get(const struct bt_mesh_model *model, struct bt_mesh struct net_buf_simple *buf) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGED_SUBNETS_LIST, - BT_MESH_TX_SDU_MAX - BT_MESH_MODEL_OP_LEN(OP_BRIDGED_SUBNETS_LIST)); + BT_MESH_TX_SDU_MAX - + BT_MESH_MODEL_OP_LEN(OP_BRIDGED_SUBNETS_LIST)); bt_mesh_model_msg_init(&msg, OP_BRIDGED_SUBNETS_LIST); const struct bt_mesh_brg_cfg_row *brg_tbl; @@ -209,10 +210,10 @@ static int bridged_subnets_get(const struct bt_mesh_model *model, struct bt_mesh } static int bridging_table_get(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, - struct net_buf_simple *buf) + struct net_buf_simple *buf) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_LIST, - BT_MESH_TX_SDU_MAX - BT_MESH_MODEL_OP_LEN(OP_BRIDGING_TABLE_LIST)); + BT_MESH_TX_SDU_MAX - BT_MESH_MODEL_OP_LEN(OP_BRIDGING_TABLE_LIST)); uint8_t status = STATUS_SUCCESS; uint16_t net_idx1, net_idx2; @@ -252,7 +253,6 @@ static int bridging_table_get(const struct bt_mesh_model *model, struct bt_mesh_ } cnt++; } - } tbl_get_respond: @@ -264,7 +264,7 @@ static int bridging_table_get(const struct bt_mesh_model *model, struct bt_mesh_ } static int bridging_table_size_get(const struct bt_mesh_model *model, struct bt_mesh_msg_ctx *ctx, - struct net_buf_simple *buf) + struct net_buf_simple *buf) { BT_MESH_MODEL_BUF_DEFINE(msg, OP_BRIDGING_TABLE_SIZE_STATUS, 2); bt_mesh_model_msg_init(&msg, OP_BRIDGING_TABLE_SIZE_STATUS); @@ -278,15 +278,14 @@ static int bridging_table_size_get(const struct bt_mesh_model *model, struct bt_ return 0; } - const struct bt_mesh_model_op _bt_mesh_brg_cfg_srv_op[] = { - { OP_SUBNET_BRIDGE_GET, BT_MESH_LEN_EXACT(0), subnet_bridge_get }, - { OP_SUBNET_BRIDGE_SET, BT_MESH_LEN_EXACT(1), subnet_bridge_set }, - { OP_BRIDGING_TABLE_ADD, BT_MESH_LEN_EXACT(8), bridging_table_add }, - { OP_BRIDGING_TABLE_REMOVE, BT_MESH_LEN_EXACT(7), bridging_table_remove }, - { OP_BRIDGED_SUBNETS_GET, BT_MESH_LEN_EXACT(3), bridged_subnets_get }, - { OP_BRIDGING_TABLE_GET, BT_MESH_LEN_EXACT(5), bridging_table_get }, - { OP_BRIDGING_TABLE_SIZE_GET, BT_MESH_LEN_EXACT(0), bridging_table_size_get }, + {OP_SUBNET_BRIDGE_GET, BT_MESH_LEN_EXACT(0), subnet_bridge_get}, + {OP_SUBNET_BRIDGE_SET, BT_MESH_LEN_EXACT(1), subnet_bridge_set}, + {OP_BRIDGING_TABLE_ADD, BT_MESH_LEN_EXACT(8), bridging_table_add}, + {OP_BRIDGING_TABLE_REMOVE, BT_MESH_LEN_EXACT(7), bridging_table_remove}, + {OP_BRIDGED_SUBNETS_GET, BT_MESH_LEN_EXACT(3), bridged_subnets_get}, + {OP_BRIDGING_TABLE_GET, BT_MESH_LEN_EXACT(5), bridging_table_get}, + {OP_BRIDGING_TABLE_SIZE_GET, BT_MESH_LEN_EXACT(0), bridging_table_size_get}, BT_MESH_MODEL_OP_END, }; diff --git a/subsys/bluetooth/mesh/foundation.h b/subsys/bluetooth/mesh/foundation.h index a71c1f44700047e..c073e5cb5872ece 100644 --- a/subsys/bluetooth/mesh/foundation.h +++ b/subsys/bluetooth/mesh/foundation.h @@ -122,18 +122,18 @@ #define OP_SOL_PDU_RPL_ITEM_CLEAR_UNACKED BT_MESH_MODEL_OP_2(0x80, 0x79) #define OP_SOL_PDU_RPL_ITEM_STATUS BT_MESH_MODEL_OP_2(0x80, 0x7a) -#define OP_SUBNET_BRIDGE_GET BT_MESH_MODEL_OP_2(0x80, 0xb1) -#define OP_SUBNET_BRIDGE_SET BT_MESH_MODEL_OP_2(0x80, 0xb2) -#define OP_SUBNET_BRIDGE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xb3) -#define OP_BRIDGING_TABLE_ADD BT_MESH_MODEL_OP_2(0x80, 0xb4) -#define OP_BRIDGING_TABLE_REMOVE BT_MESH_MODEL_OP_2(0x80, 0xb5) -#define OP_BRIDGING_TABLE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xb6) -#define OP_BRIDGED_SUBNETS_GET BT_MESH_MODEL_OP_2(0x80, 0xb7) -#define OP_BRIDGED_SUBNETS_LIST BT_MESH_MODEL_OP_2(0x80, 0xb8) -#define OP_BRIDGING_TABLE_GET BT_MESH_MODEL_OP_2(0x80, 0xb9) -#define OP_BRIDGING_TABLE_LIST BT_MESH_MODEL_OP_2(0x80, 0xba) -#define OP_BRIDGING_TABLE_SIZE_GET BT_MESH_MODEL_OP_2(0x80, 0xbb) -#define OP_BRIDGING_TABLE_SIZE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xbc) +#define OP_SUBNET_BRIDGE_GET BT_MESH_MODEL_OP_2(0x80, 0xb1) +#define OP_SUBNET_BRIDGE_SET BT_MESH_MODEL_OP_2(0x80, 0xb2) +#define OP_SUBNET_BRIDGE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xb3) +#define OP_BRIDGING_TABLE_ADD BT_MESH_MODEL_OP_2(0x80, 0xb4) +#define OP_BRIDGING_TABLE_REMOVE BT_MESH_MODEL_OP_2(0x80, 0xb5) +#define OP_BRIDGING_TABLE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xb6) +#define OP_BRIDGED_SUBNETS_GET BT_MESH_MODEL_OP_2(0x80, 0xb7) +#define OP_BRIDGED_SUBNETS_LIST BT_MESH_MODEL_OP_2(0x80, 0xb8) +#define OP_BRIDGING_TABLE_GET BT_MESH_MODEL_OP_2(0x80, 0xb9) +#define OP_BRIDGING_TABLE_LIST BT_MESH_MODEL_OP_2(0x80, 0xba) +#define OP_BRIDGING_TABLE_SIZE_GET BT_MESH_MODEL_OP_2(0x80, 0xbb) +#define OP_BRIDGING_TABLE_SIZE_STATUS BT_MESH_MODEL_OP_2(0x80, 0xbc) #define STATUS_SUCCESS 0x00 #define STATUS_INVALID_ADDRESS 0x01 diff --git a/subsys/bluetooth/mesh/net.c b/subsys/bluetooth/mesh/net.c index 16ccdfe0e0a27ca..25d0551a2ee276b 100644 --- a/subsys/bluetooth/mesh/net.c +++ b/subsys/bluetooth/mesh/net.c @@ -682,8 +682,7 @@ static bool relay_to_adv(enum bt_mesh_net_if net_if) } } -static void bt_mesh_net_relay(struct net_buf_simple *sbuf, - struct bt_mesh_net_rx *rx, bool bridge) +static void bt_mesh_net_relay(struct net_buf_simple *sbuf, struct bt_mesh_net_rx *rx, bool bridge) { const struct bt_mesh_net_cred *cred; struct bt_mesh_adv *adv; @@ -693,9 +692,7 @@ static void bt_mesh_net_relay(struct net_buf_simple *sbuf, return; } - if (rx->net_if == BT_MESH_NET_IF_ADV && - !rx->friend_cred && - !bridge && + if (rx->net_if == BT_MESH_NET_IF_ADV && !rx->friend_cred && !bridge && bt_mesh_relay_get() != BT_MESH_RELAY_ENABLED && bt_mesh_gatt_proxy_get() != BT_MESH_GATT_PROXY_ENABLED && bt_mesh_priv_gatt_proxy_get() != BT_MESH_PRIV_GATT_PROXY_ENABLED) { @@ -949,7 +946,7 @@ void bt_mesh_net_recv(struct net_buf_simple *data, int8_t rssi, } bt_mesh_brg_cfg_tbl_foreach_subnet(rx.ctx.addr, rx.ctx.recv_dst, rx.ctx.net_idx, - bt_mesh_sbr_check_cb, &tx_ctx); + bt_mesh_sbr_check_cb, &tx_ctx); #endif } diff --git a/subsys/bluetooth/mesh/settings.c b/subsys/bluetooth/mesh/settings.c index 7997b5e9985af27..5c9e03693bc7ea2 100644 --- a/subsys/bluetooth/mesh/settings.c +++ b/subsys/bluetooth/mesh/settings.c @@ -127,16 +127,12 @@ SETTINGS_STATIC_HANDLER_DEFINE(bt_mesh, "bt/mesh", NULL, NULL, mesh_commit, BIT(BT_MESH_SETTINGS_CDB_PENDING)) /* Pending flags that use CONFIG_BT_MESH_STORE_TIMEOUT */ -#define GENERIC_PENDING_BITS (BIT(BT_MESH_SETTINGS_NET_KEYS_PENDING) | \ - BIT(BT_MESH_SETTINGS_APP_KEYS_PENDING) | \ - BIT(BT_MESH_SETTINGS_HB_PUB_PENDING) | \ - BIT(BT_MESH_SETTINGS_CFG_PENDING) | \ - BIT(BT_MESH_SETTINGS_MOD_PENDING) | \ - BIT(BT_MESH_SETTINGS_VA_PENDING) | \ - BIT(BT_MESH_SETTINGS_SSEQ_PENDING) | \ - BIT(BT_MESH_SETTINGS_COMP_PENDING) | \ - BIT(BT_MESH_SETTINGS_DEV_KEY_CAND_PENDING) | \ - BIT(BT_MESH_SETTINGS_BRG_PENDING)) +#define GENERIC_PENDING_BITS \ + (BIT(BT_MESH_SETTINGS_NET_KEYS_PENDING) | BIT(BT_MESH_SETTINGS_APP_KEYS_PENDING) | \ + BIT(BT_MESH_SETTINGS_HB_PUB_PENDING) | BIT(BT_MESH_SETTINGS_CFG_PENDING) | \ + BIT(BT_MESH_SETTINGS_MOD_PENDING) | BIT(BT_MESH_SETTINGS_VA_PENDING) | \ + BIT(BT_MESH_SETTINGS_SSEQ_PENDING) | BIT(BT_MESH_SETTINGS_COMP_PENDING) | \ + BIT(BT_MESH_SETTINGS_DEV_KEY_CAND_PENDING) | BIT(BT_MESH_SETTINGS_BRG_PENDING)) void bt_mesh_settings_store_schedule(enum bt_mesh_settings_flag flag) { @@ -266,8 +262,7 @@ static void store_pending(struct k_work *work) } if (IS_ENABLED(CONFIG_BT_MESH_BRG_CFG_SRV) && - atomic_test_and_clear_bit(pending_flags, - BT_MESH_SETTINGS_BRG_PENDING)) { + atomic_test_and_clear_bit(pending_flags, BT_MESH_SETTINGS_BRG_PENDING)) { bt_mesh_brg_cfg_pending_store(); } } diff --git a/subsys/bluetooth/mesh/shell/brg_cfg.c b/subsys/bluetooth/mesh/shell/brg_cfg.c index 81a218788a2a212..43ab3e0b1576592 100644 --- a/subsys/bluetooth/mesh/shell/brg_cfg.c +++ b/subsys/bluetooth/mesh/shell/brg_cfg.c @@ -34,8 +34,8 @@ static int cmd_subnet_bridge_set(const struct shell *sh, size_t argc, char *argv enum bt_mesh_subnet_bridge_state set, rsp; int err = 0; - set = shell_strtobool(argv[1], 0, &err) ? BT_MESH_SUBNET_BRIDGE_ENABLED : - BT_MESH_SUBNET_BRIDGE_DISABLED; + set = shell_strtobool(argv[1], 0, &err) ? BT_MESH_SUBNET_BRIDGE_ENABLED + : BT_MESH_SUBNET_BRIDGE_DISABLED; if (err) { shell_warn(sh, "Unable to parse input string argument"); @@ -231,17 +231,16 @@ static int cmd_bridging_table_get(const struct shell *sh, size_t argc, char *arg } SHELL_STATIC_SUBCMD_SET_CREATE( - brg_cfg_cmds, - SHELL_CMD_ARG(bridge-get, NULL, NULL, cmd_subnet_bridge_get, 1, 0), - SHELL_CMD_ARG(bridge-set, NULL, "", cmd_subnet_bridge_set, 2, 0), - SHELL_CMD_ARG(table-size-get, NULL, NULL, cmd_bridging_table_size_get, 1, 0), - SHELL_CMD_ARG(table-add, NULL, " ", + brg_cfg_cmds, SHELL_CMD_ARG(bridge - get, NULL, NULL, cmd_subnet_bridge_get, 1, 0), + SHELL_CMD_ARG(bridge - set, NULL, "", cmd_subnet_bridge_set, 2, 0), + SHELL_CMD_ARG(table - size - get, NULL, NULL, cmd_bridging_table_size_get, 1, 0), + SHELL_CMD_ARG(table - add, NULL, " ", cmd_bridging_table_add, 6, 0), - SHELL_CMD_ARG(table-remove, NULL, " ", + SHELL_CMD_ARG(table - remove, NULL, " ", cmd_bridging_table_remove, 5, 0), - SHELL_CMD_ARG(subnets-get, NULL, " ", cmd_bridged_subnets_get, + SHELL_CMD_ARG(subnets - get, NULL, " ", cmd_bridged_subnets_get, 4, 0), - SHELL_CMD_ARG(table-get, NULL, " ", cmd_bridging_table_get, + SHELL_CMD_ARG(table - get, NULL, " ", cmd_bridging_table_get, 4, 0), SHELL_SUBCMD_SET_END); diff --git a/tests/bluetooth/mesh/brg/prj.conf b/tests/bluetooth/mesh/brg/prj.conf index 1eea5516d41a969..31c31ebcd123444 100644 --- a/tests/bluetooth/mesh/brg/prj.conf +++ b/tests/bluetooth/mesh/brg/prj.conf @@ -1,3 +1,2 @@ CONFIG_ZTEST=y CONFIG_ZTEST_MOCKING=y -CONFIG_BT_MESH_BRG_CFG_SRV=y diff --git a/tests/bluetooth/mesh/brg/src/main.c b/tests/bluetooth/mesh/brg/src/main.c index 15d964fadcb2bc3..65cf5424012dbf0 100644 --- a/tests/bluetooth/mesh/brg/src/main.c +++ b/tests/bluetooth/mesh/brg/src/main.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include @@ -32,9 +32,9 @@ static void setup(void *f) /* create test vector */ for (int i = 0; i < TEST_VECT_SZ; i++) { test_vector[i].direction = i < (TEST_VECT_SZ / 2) ? 1 : 2; - test_vector[i].net_idx1 = (i/8); + test_vector[i].net_idx1 = (i / 8); test_vector[i].addr1 = ADDR1_BASE + i; - test_vector[i].net_idx2 = (i/8) + 16; + test_vector[i].net_idx2 = (i / 8) + 16; test_vector[i].addr2 = ADDR2_BASE + i; } } @@ -63,7 +63,7 @@ int settings_delete(const char *name) struct bt_mesh_subnet *bt_mesh_subnet_get(uint16_t net_idx) { /* Return anything non-zero. */ - return (struct bt_mesh_subnet *) 1; + return (struct bt_mesh_subnet *)1; } /**** Mocked functions - end ****/ @@ -77,12 +77,12 @@ static void check_fill_all_bt_entries(void) if (i < CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { ztest_expect_value(bt_mesh_settings_store_schedule, flag, - BT_MESH_SETTINGS_BRG_PENDING); + BT_MESH_SETTINGS_BRG_PENDING); } err = bt_mesh_brg_cfg_tbl_add(test_vector[i].direction, test_vector[i].net_idx1, - test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2, - &status); + test_vector[i].net_idx2, test_vector[i].addr1, + test_vector[i].addr2, &status); zassert_equal(err, 0); @@ -102,19 +102,18 @@ static void check_delete_all_bt_entries(void) if (i < CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX) { ztest_expect_value(bt_mesh_settings_store_schedule, flag, - BT_MESH_SETTINGS_BRG_PENDING); + BT_MESH_SETTINGS_BRG_PENDING); } int err = bt_mesh_brg_cfg_tbl_remove(test_vector[i].net_idx1, - test_vector[i].net_idx2, test_vector[i].addr1, - test_vector[i].addr2, &status); + test_vector[i].net_idx2, test_vector[i].addr1, + test_vector[i].addr2, &status); zassert_equal(err, 0); zassert_equal(status, STATUS_SUCCESS); } } - static void check_bt_mesh_brg_cfg_tbl_reset(void) { int err; @@ -230,13 +229,12 @@ static void pending_store_enable_create_expectations(bool *enable_val) } } -static void pending_store_tbl_create_expectations(int n, - const struct bt_mesh_brg_cfg_row *tbl_val) +static void pending_store_tbl_create_expectations(int n, const struct bt_mesh_brg_cfg_row *tbl_val) { if (n > 0) { ztest_expect_data(settings_save_one, name, "bt/mesh/brg_tbl"); ztest_expect_value(settings_save_one, val_len, - n * sizeof(struct bt_mesh_brg_cfg_row)); + n * sizeof(struct bt_mesh_brg_cfg_row)); ztest_expect_data(settings_save_one, value, tbl_val); } else { ztest_expect_data(settings_delete, name, "bt/mesh/brg_tbl"); @@ -254,9 +252,7 @@ ZTEST(bt_mesh_brg_cfg, test_brg_cfg_en) zassert_equal(val, false, NULL); /* No changed to the states, nothing to check. */ - - ztest_expect_value(bt_mesh_settings_store_schedule, flag, - BT_MESH_SETTINGS_BRG_PENDING); + ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_BRG_PENDING); err = bt_mesh_brg_cfg_enable_set(true); zassert_equal(err, 0, NULL); val = bt_mesh_brg_cfg_enable_get(); @@ -280,10 +276,9 @@ ZTEST(bt_mesh_brg_cfg, test_brg_tbl_pending_store) }; check_bt_mesh_brg_cfg_tbl_reset(); - ztest_expect_value(bt_mesh_settings_store_schedule, flag, - BT_MESH_SETTINGS_BRG_PENDING); - err = bt_mesh_brg_cfg_tbl_add(test_vec.direction, test_vec.net_idx1, - test_vec.net_idx2, test_vec.addr1, test_vec.addr2, &status); + ztest_expect_value(bt_mesh_settings_store_schedule, flag, BT_MESH_SETTINGS_BRG_PENDING); + err = bt_mesh_brg_cfg_tbl_add(test_vec.direction, test_vec.net_idx1, test_vec.net_idx2, + test_vec.addr1, test_vec.addr2, &status); zassert_equal(err, 0); zassert_equal(status, STATUS_SUCCESS); @@ -307,60 +302,110 @@ ZTEST(bt_mesh_brg_cfg, test_tbl_add_invalid_ip) * Each vector has only one invalid field value, rest all are valid values. */ const struct test_brg_cfg_row inv_test_vector[] = { - /* Direction has invalid values */ - {.direction = BT_MESH_BRG_CFG_DIR_PROHIBITED, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 2}, - {.direction = BT_MESH_BRG_CFG_DIR_MAX, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 2}, - /* Out of range netidx values */ - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 4096, .net_idx2 = 1, .addr1 = 1, .addr2 = 2}, - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 4096, .addr1 = 1, .addr2 = 2}, - /* Same netidx values */ - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 0, .addr1 = 1, .addr2 = 2}, - /* Same addr values */ - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 1}, - /* Invalid address1 value */ - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0, .addr2 = 1}, - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0x8000, .addr2 = 1}, - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0xC000, .addr2 = 1}, - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0xFFFE, .addr2 = 1}, - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 0xFFFF, .addr2 = 1}, - /* Invalid address2 values */ - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0}, - {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xFFFF}, - {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0x8000}, - {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xC000}, - {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xFFFE}, - {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, - .net_idx1 = 0, .net_idx2 = 1, .addr1 = 1, .addr2 = 0xFFFF}, + /* Direction has invalid values */ + {.direction = BT_MESH_BRG_CFG_DIR_PROHIBITED, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 2}, + {.direction = BT_MESH_BRG_CFG_DIR_MAX, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 2}, + /* Out of range netidx values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 4096, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 2}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 4096, + .addr1 = 1, + .addr2 = 2}, + /* Same netidx values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 0, + .addr1 = 1, + .addr2 = 2}, + /* Same addr values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 1}, + /* Invalid address1 value */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 0, + .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 0x8000, + .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 0xC000, + .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 0xFFFE, + .addr2 = 1}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 0xFFFF, + .addr2 = 1}, + /* Invalid address2 values */ + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 0}, + {.direction = BT_MESH_BRG_CFG_DIR_ONEWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 0xFFFF}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 0x8000}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 0xC000}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 0xFFFE}, + {.direction = BT_MESH_BRG_CFG_DIR_TWOWAY, + .net_idx1 = 0, + .net_idx2 = 1, + .addr1 = 1, + .addr2 = 0xFFFF}, }; check_bt_mesh_brg_cfg_tbl_reset(); for (int i = 0; i < ARRAY_SIZE(inv_test_vector); i++) { err = bt_mesh_brg_cfg_tbl_add(inv_test_vector[i].direction, - inv_test_vector[i].net_idx1, inv_test_vector[i].net_idx2, - inv_test_vector[i].addr1, inv_test_vector[i].addr2, - &status); + inv_test_vector[i].net_idx1, + inv_test_vector[i].net_idx2, inv_test_vector[i].addr1, + inv_test_vector[i].addr2, &status); zassert_equal(err, -EINVAL, "Test vector index: %zu", i); } } - /* Following are helper functions for the test that checks the iteration logic */ #define NUM_MSGS (10000) @@ -372,9 +417,10 @@ static void print_brg_tbl(void) zassert_true(n <= CONFIG_BT_MESH_BRG_TABLE_ITEMS_MAX); for (int i = 0; i < n; i++) { - printk("entry: %3d # dir: %d, net_idx1: %3d, addr1: %3d, net_idx2: %3d, addr2: %3d\n", - i, tbl[i].direction, tbl[i].net_idx1, tbl[i].addr1, tbl[i].net_idx2, - tbl[i].addr2); + printk("entry: %3d # dir: %d, net_idx1: %3d, addr1: %3d, net_idx2: %3d, addr2: " + "%3d\n", + i, tbl[i].direction, tbl[i].net_idx1, tbl[i].addr1, tbl[i].net_idx2, + tbl[i].addr2); } } @@ -383,12 +429,12 @@ static void check_fill_all_bt_entries_reversed(void) uint8_t status; int err; - for (int i = TEST_VECT_SZ - 2; i >= 0 ; i--) { + for (int i = TEST_VECT_SZ - 2; i >= 0; i--) { ztest_expect_value(bt_mesh_settings_store_schedule, flag, - BT_MESH_SETTINGS_BRG_PENDING); + BT_MESH_SETTINGS_BRG_PENDING); err = bt_mesh_brg_cfg_tbl_add(test_vector[i].direction, test_vector[i].net_idx1, - test_vector[i].net_idx2, test_vector[i].addr1, test_vector[i].addr2, - &status); + test_vector[i].net_idx2, test_vector[i].addr1, + test_vector[i].addr2, &status); zassert_equal(err, 0); } @@ -421,10 +467,11 @@ static void check_fill_all_bt_entries_randomly(void) for (int i = 0; i < copy_cnt; i++) { ztest_expect_value(bt_mesh_settings_store_schedule, flag, - BT_MESH_SETTINGS_BRG_PENDING); - err = bt_mesh_brg_cfg_tbl_add(test_vector_copy[i].direction, - test_vector_copy[i].net_idx1, test_vector_copy[i].net_idx2, - test_vector_copy[i].addr1, test_vector_copy[i].addr2, &status); + BT_MESH_SETTINGS_BRG_PENDING); + err = bt_mesh_brg_cfg_tbl_add( + test_vector_copy[i].direction, test_vector_copy[i].net_idx1, + test_vector_copy[i].net_idx2, test_vector_copy[i].addr1, + test_vector_copy[i].addr2, &status); zassert_equal(err, 0); zassert_equal(status, STATUS_SUCCESS); } @@ -432,8 +479,8 @@ static void check_fill_all_bt_entries_randomly(void) int last = TEST_VECT_SZ - 1; err = bt_mesh_brg_cfg_tbl_add(test_vector[last].direction, test_vector[last].net_idx1, - test_vector[last].net_idx2, test_vector[last].addr1, test_vector[last].addr2, - &status); + test_vector[last].net_idx2, test_vector[last].addr1, + test_vector[last].addr2, &status); zassert_equal(err, 0); zassert_equal(status, STATUS_INSUFF_RESOURCES); } @@ -472,7 +519,8 @@ static void test_bridging_performance(bool test_one_way) tick1 = k_uptime_ticks(); bt_mesh_brg_cfg_tbl_foreach_subnet(test_vector[idx].addr1, test_vector[idx].addr2, - test_vector[idx].net_idx1, subnet_relay_cb_check, &idx); + test_vector[idx].net_idx1, subnet_relay_cb_check, + &idx); ticks += k_uptime_ticks() - tick1; if (test_one_way) { @@ -485,7 +533,8 @@ static void test_bridging_performance(bool test_one_way) tbl_row = NULL; tick1 = k_uptime_ticks(); bt_mesh_brg_cfg_tbl_foreach_subnet(test_vector[idx].addr2, test_vector[idx].addr1, - test_vector[idx].net_idx2, subnet_relay_cb_check_rev, &idx); + test_vector[idx].net_idx2, + subnet_relay_cb_check_rev, &idx); ticks += k_uptime_ticks() - tick1; } printk("ticks: %8u us: %u\n", ticks, k_ticks_to_us_floor32(ticks)); diff --git a/tests/bluetooth/mesh/brg/testcase.yaml b/tests/bluetooth/mesh/brg/testcase.yaml index b94a3d445e226e1..41cba4632d3a58e 100644 --- a/tests/bluetooth/mesh/brg/testcase.yaml +++ b/tests/bluetooth/mesh/brg/testcase.yaml @@ -1,7 +1,6 @@ tests: bluetooth.mesh.brg: platform_allow: - - native_posix - native_sim tags: - bluetooth diff --git a/tests/bluetooth/mesh_shell/src/main.c b/tests/bluetooth/mesh_shell/src/main.c index cba985c49c880d9..1c9dcb003502bba 100644 --- a/tests/bluetooth/mesh_shell/src/main.c +++ b/tests/bluetooth/mesh_shell/src/main.c @@ -50,8 +50,7 @@ BT_MESH_SHELL_HEALTH_PUB_DEFINE(health_pub); static const struct bt_mesh_model root_models[] = { BT_MESH_MODEL_CFG_SRV, BT_MESH_MODEL_CFG_CLI(&cfg_cli), - BT_MESH_MODEL_HEALTH_SRV(&bt_mesh_shell_health_srv, &health_pub, - health_srv_meta), + BT_MESH_MODEL_HEALTH_SRV(&bt_mesh_shell_health_srv, &health_pub, health_srv_meta), BT_MESH_MODEL_HEALTH_CLI(&bt_mesh_shell_health_cli), #if defined(CONFIG_BT_MESH_DFD_SRV) BT_MESH_MODEL_DFD_SRV(&dfd_srv), diff --git a/tests/bluetooth/tester/src/btp/btp_mesh.h b/tests/bluetooth/tester/src/btp/btp_mesh.h index 8ad82323d541a21..17f49e4927ed047 100644 --- a/tests/bluetooth/tester/src/btp/btp_mesh.h +++ b/tests/bluetooth/tester/src/btp/btp_mesh.h @@ -904,18 +904,18 @@ struct btp_rpr_reprov_remote_cmd { bool comp_change; } __packed; -#define BTP_MESH_SUBNET_BRIDGE_GET 0x62 +#define BTP_MESH_SUBNET_BRIDGE_GET 0x62 struct btp_mesh_subnet_bridge_get_cmd { uint16_t addr; } __packed; -#define BTP_MESH_SUBNET_BRIDGE_SET 0x63 +#define BTP_MESH_SUBNET_BRIDGE_SET 0x63 struct btp_mesh_subnet_bridge_set_cmd { uint16_t addr; uint8_t val; } __packed; -#define BTP_MESH_BRIDGING_TABLE_ADD 0x64 +#define BTP_MESH_BRIDGING_TABLE_ADD 0x64 struct btp_mesh_bridging_table_add_cmd { uint16_t addr; uint8_t directions; @@ -925,7 +925,7 @@ struct btp_mesh_bridging_table_add_cmd { uint16_t addr2; } __packed; -#define BTP_MESH_BRIDGING_TABLE_REMOVE 0x65 +#define BTP_MESH_BRIDGING_TABLE_REMOVE 0x65 struct btp_mesh_bridging_table_remove_cmd { uint16_t addr; uint16_t net_idx1; @@ -934,7 +934,7 @@ struct btp_mesh_bridging_table_remove_cmd { uint16_t addr2; } __packed; -#define BTP_MESH_BRIDGED_SUBNETS_GET 0x66 +#define BTP_MESH_BRIDGED_SUBNETS_GET 0x66 struct btp_mesh_bridged_subnets_get_cmd { uint16_t addr; uint8_t filter; @@ -942,7 +942,7 @@ struct btp_mesh_bridged_subnets_get_cmd { uint8_t start_idx; } __packed; -#define BTP_MESH_BRIDGING_TABLE_GET 0x67 +#define BTP_MESH_BRIDGING_TABLE_GET 0x67 struct btp_mesh_bridging_table_get_cmd { uint16_t addr; uint16_t net_idx1; @@ -950,7 +950,7 @@ struct btp_mesh_bridging_table_get_cmd { uint16_t start_idx; } __packed; -#define BTP_MESH_BRIDGING_TABLE_SIZE_GET 0x68 +#define BTP_MESH_BRIDGING_TABLE_SIZE_GET 0x68 struct btp_mesh_bridging_table_size_get_cmd { uint16_t addr; } __packed; diff --git a/tests/bluetooth/tester/src/btp_mesh.c b/tests/bluetooth/tester/src/btp_mesh.c index f913efdebb6507f..efd1d4c35848f16 100644 --- a/tests/bluetooth/tester/src/btp_mesh.c +++ b/tests/bluetooth/tester/src/btp_mesh.c @@ -2083,15 +2083,13 @@ static uint8_t models_metadata_get(const void *cmd, uint16_t cmd_len, #endif #if defined(CONFIG_BT_MESH_BRG_CFG_CLI) -static uint8_t subnet_bridge_get(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t subnet_bridge_get(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { const struct btp_mesh_subnet_bridge_get_cmd *cp = cmd; enum bt_mesh_subnet_bridge_state state; int err; - err = bt_mesh_brg_cfg_cli_subnet_bridge_get(net.net_idx, sys_le16_to_cpu(cp->addr), - &state); + err = bt_mesh_brg_cfg_cli_subnet_bridge_get(net.net_idx, sys_le16_to_cpu(cp->addr), &state); if (err) { LOG_ERR("err=%d", err); return BTP_STATUS_FAILED; @@ -2102,8 +2100,7 @@ static uint8_t subnet_bridge_get(const void *cmd, uint16_t cmd_len, return BTP_STATUS_SUCCESS; } -static uint8_t subnet_bridge_set(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t subnet_bridge_set(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { const struct btp_mesh_subnet_bridge_set_cmd *cp = cmd; enum bt_mesh_subnet_bridge_state state; @@ -2111,8 +2108,8 @@ static uint8_t subnet_bridge_set(const void *cmd, uint16_t cmd_len, state = cp->val; - err = bt_mesh_brg_cfg_cli_subnet_bridge_set(net.net_idx, sys_le16_to_cpu(cp->addr), - state, &state); + err = bt_mesh_brg_cfg_cli_subnet_bridge_set(net.net_idx, sys_le16_to_cpu(cp->addr), state, + &state); if (err) { LOG_ERR("err=%d", err); return BTP_STATUS_FAILED; @@ -2123,8 +2120,7 @@ static uint8_t subnet_bridge_set(const void *cmd, uint16_t cmd_len, return BTP_STATUS_SUCCESS; } -static uint8_t bridging_table_add(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t bridging_table_add(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { const struct btp_mesh_bridging_table_add_cmd *cp = cmd; struct bt_mesh_bridging_table_entry entry; @@ -2139,8 +2135,8 @@ static uint8_t bridging_table_add(const void *cmd, uint16_t cmd_len, entry.addr1 = sys_le16_to_cpu(cp->addr1); entry.addr2 = sys_le16_to_cpu(cp->addr2); - err = bt_mesh_brg_cfg_cli_bridging_table_add(net_key_idx, sys_le16_to_cpu(cp->addr), - &entry, &rp); + err = bt_mesh_brg_cfg_cli_bridging_table_add(net_key_idx, sys_le16_to_cpu(cp->addr), &entry, + &rp); if (err) { LOG_ERR("err=%d", err); return BTP_STATUS_FAILED; @@ -2149,8 +2145,8 @@ static uint8_t bridging_table_add(const void *cmd, uint16_t cmd_len, return BTP_STATUS_SUCCESS; } -static uint8_t bridging_table_remove(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t bridging_table_remove(const void *cmd, uint16_t cmd_len, void *rsp, + uint16_t *rsp_len) { const struct btp_mesh_bridging_table_remove_cmd *cp = cmd; struct bt_mesh_bridging_table_status rp; @@ -2158,11 +2154,10 @@ static uint8_t bridging_table_remove(const void *cmd, uint16_t cmd_len, LOG_DBG(""); - err = bt_mesh_brg_cfg_cli_bridging_table_remove(net_key_idx, sys_le16_to_cpu(cp->addr), - sys_le16_to_cpu(cp->net_idx1), - sys_le16_to_cpu(cp->net_idx2), - sys_le16_to_cpu(cp->addr1), - sys_le16_to_cpu(cp->addr2), &rp); + err = bt_mesh_brg_cfg_cli_bridging_table_remove( + net_key_idx, sys_le16_to_cpu(cp->addr), sys_le16_to_cpu(cp->net_idx1), + sys_le16_to_cpu(cp->net_idx2), sys_le16_to_cpu(cp->addr1), + sys_le16_to_cpu(cp->addr2), &rp); if (err) { LOG_ERR("err=%d", err); @@ -2172,8 +2167,7 @@ static uint8_t bridging_table_remove(const void *cmd, uint16_t cmd_len, return BTP_STATUS_SUCCESS; } -static uint8_t bridged_subnets_get(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t bridged_subnets_get(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { const struct btp_mesh_bridged_subnets_get_cmd *cp = cmd; struct bt_mesh_filter_netkey filter_net_idx; @@ -2200,8 +2194,7 @@ static uint8_t bridged_subnets_get(const void *cmd, uint16_t cmd_len, return BTP_STATUS_SUCCESS; } -static uint8_t bridging_table_get(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t bridging_table_get(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { const struct btp_mesh_bridging_table_get_cmd *cp = cmd; struct bt_mesh_bridging_table_list rp; @@ -2214,10 +2207,9 @@ static uint8_t bridging_table_get(const void *cmd, uint16_t cmd_len, */ rp.list = NULL; - err = bt_mesh_brg_cfg_cli_bridging_table_get(net_key_idx, sys_le16_to_cpu(cp->addr), - sys_le16_to_cpu(cp->net_idx1), - sys_le16_to_cpu(cp->net_idx2), - sys_le16_to_cpu(cp->start_idx), &rp); + err = bt_mesh_brg_cfg_cli_bridging_table_get( + net_key_idx, sys_le16_to_cpu(cp->addr), sys_le16_to_cpu(cp->net_idx1), + sys_le16_to_cpu(cp->net_idx2), sys_le16_to_cpu(cp->start_idx), &rp); if (err) { LOG_ERR("err=%d", err); return BTP_STATUS_FAILED; @@ -2226,8 +2218,8 @@ static uint8_t bridging_table_get(const void *cmd, uint16_t cmd_len, return BTP_STATUS_SUCCESS; } -static uint8_t bridging_table_size_get(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t bridging_table_size_get(const void *cmd, uint16_t cmd_len, void *rsp, + uint16_t *rsp_len) { const struct btp_mesh_bridging_table_size_get_cmd *cp = cmd; uint16_t size; @@ -2247,8 +2239,7 @@ static uint8_t bridging_table_size_get(const void *cmd, uint16_t cmd_len, #endif -static uint8_t composition_data_get(const void *cmd, uint16_t cmd_len, - void *rsp, uint16_t *rsp_len) +static uint8_t composition_data_get(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len) { const struct btp_mesh_comp_data_get_cmd *cp = cmd; struct btp_mesh_comp_data_get_rp *rp = rsp; @@ -5163,218 +5154,137 @@ static const struct btp_handler handlers[] = { .func = proxy_identity_enable, }, #if defined(CONFIG_BT_MESH_PROXY_CLIENT) - { - .opcode = BTP_MESH_PROXY_CONNECT, - .expect_len = sizeof(struct btp_proxy_connect_cmd), - .func = proxy_connect - }, + {.opcode = BTP_MESH_PROXY_CONNECT, + .expect_len = sizeof(struct btp_proxy_connect_cmd), + .func = proxy_connect}, #endif #if defined(CONFIG_BT_MESH_SAR_CFG_CLI) - { - .opcode = BTP_MESH_SAR_TRANSMITTER_GET, - .expect_len = sizeof(struct btp_mesh_sar_transmitter_get_cmd), - .func = sar_transmitter_get - }, - { - .opcode = BTP_MESH_SAR_TRANSMITTER_SET, - .expect_len = sizeof(struct btp_mesh_sar_transmitter_set_cmd), - .func = sar_transmitter_set - }, - { - .opcode = BTP_MESH_SAR_RECEIVER_GET, - .expect_len = sizeof(struct btp_mesh_sar_receiver_get_cmd), - .func = sar_receiver_get - }, - { - .opcode = BTP_MESH_SAR_RECEIVER_SET, - .expect_len = sizeof(struct btp_mesh_sar_receiver_set_cmd), - .func = sar_receiver_set - }, + {.opcode = BTP_MESH_SAR_TRANSMITTER_GET, + .expect_len = sizeof(struct btp_mesh_sar_transmitter_get_cmd), + .func = sar_transmitter_get}, + {.opcode = BTP_MESH_SAR_TRANSMITTER_SET, + .expect_len = sizeof(struct btp_mesh_sar_transmitter_set_cmd), + .func = sar_transmitter_set}, + {.opcode = BTP_MESH_SAR_RECEIVER_GET, + .expect_len = sizeof(struct btp_mesh_sar_receiver_get_cmd), + .func = sar_receiver_get}, + {.opcode = BTP_MESH_SAR_RECEIVER_SET, + .expect_len = sizeof(struct btp_mesh_sar_receiver_set_cmd), + .func = sar_receiver_set}, #endif #if defined(CONFIG_BT_MESH_LARGE_COMP_DATA_CLI) - { - .opcode = BTP_MESH_LARGE_COMP_DATA_GET, - .expect_len = sizeof(struct btp_mesh_large_comp_data_get_cmd), - .func = large_comp_data_get - }, - { - .opcode = BTP_MESH_MODELS_METADATA_GET, - .expect_len = sizeof(struct btp_mesh_models_metadata_get_cmd), - .func = models_metadata_get - }, + {.opcode = BTP_MESH_LARGE_COMP_DATA_GET, + .expect_len = sizeof(struct btp_mesh_large_comp_data_get_cmd), + .func = large_comp_data_get}, + {.opcode = BTP_MESH_MODELS_METADATA_GET, + .expect_len = sizeof(struct btp_mesh_models_metadata_get_cmd), + .func = models_metadata_get}, #endif #if defined(CONFIG_BT_MESH_OP_AGG_CLI) - { - .opcode = BTP_MESH_OPCODES_AGGREGATOR_INIT, - .expect_len = sizeof(struct btp_mesh_opcodes_aggregator_init_cmd), - .func = opcodes_aggregator_init - }, - { - .opcode = BTP_MESH_OPCODES_AGGREGATOR_SEND, - .expect_len = 0, - .func = opcodes_aggregator_send - }, + {.opcode = BTP_MESH_OPCODES_AGGREGATOR_INIT, + .expect_len = sizeof(struct btp_mesh_opcodes_aggregator_init_cmd), + .func = opcodes_aggregator_init}, + {.opcode = BTP_MESH_OPCODES_AGGREGATOR_SEND, + .expect_len = 0, + .func = opcodes_aggregator_send}, #endif - { - .opcode = BTP_MESH_COMP_CHANGE_PREPARE, - .expect_len = 0, - .func = change_prepare - }, + {.opcode = BTP_MESH_COMP_CHANGE_PREPARE, .expect_len = 0, .func = change_prepare}, #if defined(CONFIG_BT_MESH_RPR_CLI) - { - .opcode = BTP_MESH_RPR_SCAN_START, - .expect_len = sizeof(struct btp_rpr_scan_start_cmd), - .func = rpr_scan_start - }, - { - .opcode = BTP_MESH_RPR_EXT_SCAN_START, - .expect_len = BTP_HANDLER_LENGTH_VARIABLE, - .func = rpr_ext_scan_start - }, - { - .opcode = BTP_MESH_RPR_SCAN_CAPS_GET, - .expect_len = sizeof(struct btp_rpr_scan_caps_get_cmd), - .func = rpr_scan_caps_get - }, - { - .opcode = BTP_MESH_RPR_SCAN_GET, - .expect_len = sizeof(struct btp_rpr_scan_get_cmd), - .func = rpr_scan_get - }, - { - .opcode = BTP_MESH_RPR_SCAN_STOP, - .expect_len = sizeof(struct btp_rpr_scan_stop_cmd), - .func = rpr_scan_stop - }, - { - .opcode = BTP_MESH_RPR_LINK_GET, - .expect_len = sizeof(struct btp_rpr_link_get_cmd), - .func = rpr_link_get - }, - { - .opcode = BTP_MESH_RPR_LINK_CLOSE, - .expect_len = sizeof(struct btp_rpr_link_close_cmd), - .func = rpr_link_close - }, - { - .opcode = BTP_MESH_RPR_PROV_REMOTE, - .expect_len = sizeof(struct btp_rpr_prov_remote_cmd), - .func = rpr_prov_remote - }, - { - .opcode = BTP_MESH_RPR_REPROV_REMOTE, - .expect_len = sizeof(struct btp_rpr_reprov_remote_cmd), - .func = rpr_reprov_remote - }, + {.opcode = BTP_MESH_RPR_SCAN_START, + .expect_len = sizeof(struct btp_rpr_scan_start_cmd), + .func = rpr_scan_start}, + {.opcode = BTP_MESH_RPR_EXT_SCAN_START, + .expect_len = BTP_HANDLER_LENGTH_VARIABLE, + .func = rpr_ext_scan_start}, + {.opcode = BTP_MESH_RPR_SCAN_CAPS_GET, + .expect_len = sizeof(struct btp_rpr_scan_caps_get_cmd), + .func = rpr_scan_caps_get}, + {.opcode = BTP_MESH_RPR_SCAN_GET, + .expect_len = sizeof(struct btp_rpr_scan_get_cmd), + .func = rpr_scan_get}, + {.opcode = BTP_MESH_RPR_SCAN_STOP, + .expect_len = sizeof(struct btp_rpr_scan_stop_cmd), + .func = rpr_scan_stop}, + {.opcode = BTP_MESH_RPR_LINK_GET, + .expect_len = sizeof(struct btp_rpr_link_get_cmd), + .func = rpr_link_get}, + {.opcode = BTP_MESH_RPR_LINK_CLOSE, + .expect_len = sizeof(struct btp_rpr_link_close_cmd), + .func = rpr_link_close}, + {.opcode = BTP_MESH_RPR_PROV_REMOTE, + .expect_len = sizeof(struct btp_rpr_prov_remote_cmd), + .func = rpr_prov_remote}, + {.opcode = BTP_MESH_RPR_REPROV_REMOTE, + .expect_len = sizeof(struct btp_rpr_reprov_remote_cmd), + .func = rpr_reprov_remote}, #endif #if defined(CONFIG_BT_MESH_PRIV_BEACON_CLI) - { - .opcode = BTP_MESH_PRIV_BEACON_GET, - .expect_len = sizeof(struct btp_priv_beacon_get_cmd), - .func = priv_beacon_get - }, - { - .opcode = BTP_MESH_PRIV_BEACON_SET, - .expect_len = sizeof(struct btp_priv_beacon_set_cmd), - .func = priv_beacon_set - }, - { - .opcode = BTP_MESH_PRIV_GATT_PROXY_GET, - .expect_len = sizeof(struct btp_priv_gatt_proxy_get_cmd), - .func = priv_gatt_proxy_get - }, - { - .opcode = BTP_MESH_PRIV_GATT_PROXY_SET, - .expect_len = sizeof(struct btp_priv_gatt_proxy_set_cmd), - .func = priv_gatt_proxy_set - }, - { - .opcode = BTP_MESH_PRIV_NODE_ID_GET, - .expect_len = sizeof(struct btp_priv_node_id_get_cmd), - .func = priv_node_id_get - }, - { - .opcode = BTP_MESH_PRIV_NODE_ID_SET, - .expect_len = sizeof(struct btp_priv_node_id_set_cmd), - .func = priv_node_id_set - }, - { - .opcode = BTP_MESH_PROXY_PRIVATE_IDENTITY, - .expect_len = 0, - .func = proxy_private_identity_enable - }, + {.opcode = BTP_MESH_PRIV_BEACON_GET, + .expect_len = sizeof(struct btp_priv_beacon_get_cmd), + .func = priv_beacon_get}, + {.opcode = BTP_MESH_PRIV_BEACON_SET, + .expect_len = sizeof(struct btp_priv_beacon_set_cmd), + .func = priv_beacon_set}, + {.opcode = BTP_MESH_PRIV_GATT_PROXY_GET, + .expect_len = sizeof(struct btp_priv_gatt_proxy_get_cmd), + .func = priv_gatt_proxy_get}, + {.opcode = BTP_MESH_PRIV_GATT_PROXY_SET, + .expect_len = sizeof(struct btp_priv_gatt_proxy_set_cmd), + .func = priv_gatt_proxy_set}, + {.opcode = BTP_MESH_PRIV_NODE_ID_GET, + .expect_len = sizeof(struct btp_priv_node_id_get_cmd), + .func = priv_node_id_get}, + {.opcode = BTP_MESH_PRIV_NODE_ID_SET, + .expect_len = sizeof(struct btp_priv_node_id_set_cmd), + .func = priv_node_id_set}, + {.opcode = BTP_MESH_PROXY_PRIVATE_IDENTITY, + .expect_len = 0, + .func = proxy_private_identity_enable}, #endif #if defined(CONFIG_BT_MESH_OD_PRIV_PROXY_CLI) - { - .opcode = BTP_MESH_OD_PRIV_PROXY_GET, - .expect_len = sizeof(struct btp_od_priv_proxy_get_cmd), - .func = od_priv_proxy_get - }, - { - .opcode = BTP_MESH_OD_PRIV_PROXY_SET, - .expect_len = sizeof(struct btp_od_priv_proxy_set_cmd), - .func = od_priv_proxy_set - }, + {.opcode = BTP_MESH_OD_PRIV_PROXY_GET, + .expect_len = sizeof(struct btp_od_priv_proxy_get_cmd), + .func = od_priv_proxy_get}, + {.opcode = BTP_MESH_OD_PRIV_PROXY_SET, + .expect_len = sizeof(struct btp_od_priv_proxy_set_cmd), + .func = od_priv_proxy_set}, #endif #if defined(CONFIG_BT_MESH_SOL_PDU_RPL_CLI) - { - .opcode = BTP_MESH_SRPL_CLEAR, - .expect_len = sizeof(struct btp_srpl_clear_cmd), - .func = srpl_clear - }, + {.opcode = BTP_MESH_SRPL_CLEAR, + .expect_len = sizeof(struct btp_srpl_clear_cmd), + .func = srpl_clear}, #endif #if defined(CONFIG_BT_MESH_BRG_CFG_CLI) - { - .opcode = BTP_MESH_SUBNET_BRIDGE_GET, - .expect_len = sizeof(struct btp_mesh_subnet_bridge_get_cmd), - .func = subnet_bridge_get - }, - { - .opcode = BTP_MESH_SUBNET_BRIDGE_SET, - .expect_len = sizeof(struct btp_mesh_subnet_bridge_set_cmd), - .func = subnet_bridge_set - }, - { - .opcode = BTP_MESH_BRIDGING_TABLE_ADD, - .expect_len = sizeof(struct btp_mesh_bridging_table_add_cmd), - .func = bridging_table_add - }, - { - .opcode = BTP_MESH_BRIDGING_TABLE_REMOVE, - .expect_len = sizeof(struct btp_mesh_bridging_table_remove_cmd), - .func = bridging_table_remove - }, - { - .opcode = BTP_MESH_BRIDGED_SUBNETS_GET, - .expect_len = sizeof(struct btp_mesh_bridged_subnets_get_cmd), - .func = bridged_subnets_get - }, - { - .opcode = BTP_MESH_BRIDGING_TABLE_GET, - .expect_len = sizeof(struct btp_mesh_bridging_table_get_cmd), - .func = bridging_table_get - }, - { - .opcode = BTP_MESH_BRIDGING_TABLE_SIZE_GET, - .expect_len = sizeof(struct btp_mesh_bridging_table_size_get_cmd), - .func = bridging_table_size_get - }, + {.opcode = BTP_MESH_SUBNET_BRIDGE_GET, + .expect_len = sizeof(struct btp_mesh_subnet_bridge_get_cmd), + .func = subnet_bridge_get}, + {.opcode = BTP_MESH_SUBNET_BRIDGE_SET, + .expect_len = sizeof(struct btp_mesh_subnet_bridge_set_cmd), + .func = subnet_bridge_set}, + {.opcode = BTP_MESH_BRIDGING_TABLE_ADD, + .expect_len = sizeof(struct btp_mesh_bridging_table_add_cmd), + .func = bridging_table_add}, + {.opcode = BTP_MESH_BRIDGING_TABLE_REMOVE, + .expect_len = sizeof(struct btp_mesh_bridging_table_remove_cmd), + .func = bridging_table_remove}, + {.opcode = BTP_MESH_BRIDGED_SUBNETS_GET, + .expect_len = sizeof(struct btp_mesh_bridged_subnets_get_cmd), + .func = bridged_subnets_get}, + {.opcode = BTP_MESH_BRIDGING_TABLE_GET, + .expect_len = sizeof(struct btp_mesh_bridging_table_get_cmd), + .func = bridging_table_get}, + {.opcode = BTP_MESH_BRIDGING_TABLE_SIZE_GET, + .expect_len = sizeof(struct btp_mesh_bridging_table_size_get_cmd), + .func = bridging_table_size_get}, #endif #if defined(CONFIG_BT_MESH_PROXY_SOLICITATION) - { - .opcode = BTP_MESH_PROXY_SOLICIT, - .expect_len = sizeof(struct btp_proxy_solicit_cmd), - .func = proxy_solicit - }, + {.opcode = BTP_MESH_PROXY_SOLICIT, + .expect_len = sizeof(struct btp_proxy_solicit_cmd), + .func = proxy_solicit}, #endif - { - .opcode = BTP_MESH_START, - .expect_len = 0, - .func = start - }, + {.opcode = BTP_MESH_START, .expect_len = 0, .func = start}, }; - static const struct btp_handler mdl_handlers[] = { #if defined(CONFIG_BT_MESH_DFD_SRV) { @@ -5431,23 +5341,13 @@ static const struct btp_handler mdl_handlers[] = { }, #endif #if defined(CONFIG_BT_MESH_BLOB_SRV) - { - .opcode = BTP_MMDL_BLOB_SRV_RECV, - .expect_len = sizeof(struct btp_mmdl_blob_srv_recv_cmd), - .func = blob_srv_recv - }, - { - .opcode = BTP_MMDL_BLOB_SRV_CANCEL, - .expect_len = 0, - .func = blob_srv_cancel - }, + {.opcode = BTP_MMDL_BLOB_SRV_RECV, + .expect_len = sizeof(struct btp_mmdl_blob_srv_recv_cmd), + .func = blob_srv_recv}, + {.opcode = BTP_MMDL_BLOB_SRV_CANCEL, .expect_len = 0, .func = blob_srv_cancel}, #endif #if defined(CONFIG_BT_MESH_DFU_SRV) - { - .opcode = BTP_MMDL_DFU_SRV_APPLY, - .expect_len = 0, - .func = dfu_srv_apply - }, + {.opcode = BTP_MMDL_DFU_SRV_APPLY, .expect_len = 0, .func = dfu_srv_apply}, #endif }; diff --git a/tests/bsim/bluetooth/mesh/src/main.c b/tests/bsim/bluetooth/mesh/src/main.c index f83b0717e49ab56..bae3146fb210b4a 100644 --- a/tests/bsim/bluetooth/mesh/src/main.c +++ b/tests/bsim/bluetooth/mesh/src/main.c @@ -60,14 +60,9 @@ bst_test_install_t test_installers[] = { test_proxy_sol_install, #endif #elif defined(CONFIG_BT_MESH_GATT_PROXY) - test_adv_install, - test_suspend_install, - test_beacon_install, + test_adv_install, test_suspend_install, test_beacon_install, #elif defined(CONFIG_BT_CTLR_LOW_LAT) - test_transport_install, - test_friendship_install, - test_suspend_install, - test_adv_install, + test_transport_install, test_friendship_install, test_suspend_install, test_adv_install, #else test_transport_install, test_friendship_install, @@ -85,8 +80,7 @@ bst_test_install_t test_installers[] = { test_cdp1_install, test_brg_install, #endif - NULL -}; + NULL}; static struct k_thread bsim_mesh_thread; static K_KERNEL_STACK_DEFINE(bsim_mesh_thread_stack, 4096); diff --git a/tests/bsim/bluetooth/mesh/src/test_brg.c b/tests/bsim/bluetooth/mesh/src/test_brg.c index 448ff10ea848f29..279bed1767bfe45 100644 --- a/tests/bsim/bluetooth/mesh/src/test_brg.c +++ b/tests/bsim/bluetooth/mesh/src/test_brg.c @@ -16,30 +16,29 @@ #include LOG_MODULE_REGISTER(test_brg, LOG_LEVEL_INF); -#define WAIT_TIME 32 /*seconds*/ +#define WAIT_TIME 32 /*seconds*/ #define WAIT_TIME_IVU_TEST 240 /* seconds */ -#define BEACON_INTERVAL 10 /*seconds */ +#define BEACON_INTERVAL 10 /*seconds */ -#define PROV_ADDR 0x0001 +#define PROV_ADDR 0x0001 /* Bridge address must be less than DEVICE_ADDR_START */ -#define BRIDGE_ADDR 0x0002 +#define BRIDGE_ADDR 0x0002 #define DEVICE_ADDR_START 0x0003 #define REMOTE_NODES 2 -static const uint8_t prov_dev_key[16] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, - 0xcd, 0xef, 0x01, 0x23, 0x45, 0x67, - 0x89, 0xab, 0xcd, 0xef }; +static const uint8_t prov_dev_key[16] = {0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef}; static const uint8_t subnet_keys[][16] = { - { 0xaa, 0xbb, 0xcc }, - { 0xdd, 0xee, 0xff }, - { 0x11, 0x22, 0x33 }, + {0xaa, 0xbb, 0xcc}, + {0xdd, 0xee, 0xff}, + {0x11, 0x22, 0x33}, }; -static uint8_t prov_uuid[16] = { 0x6c, 0x69, 0x6e, 0x67, 0x61, 0xaa }; -static uint8_t bridge_uuid[16] = { 0x6c, 0x69, 0x6e, 0x67, 0x61, 0xbb }; -static uint8_t dev_uuid[16] = { 0x6c, 0x69, 0x6e, 0x67, 0x61, 0xcc }; +static uint8_t prov_uuid[16] = {0x6c, 0x69, 0x6e, 0x67, 0x61, 0xaa}; +static uint8_t bridge_uuid[16] = {0x6c, 0x69, 0x6e, 0x67, 0x61, 0xbb}; +static uint8_t dev_uuid[16] = {0x6c, 0x69, 0x6e, 0x67, 0x61, 0xcc}; static int test_ividx = 0x123456; @@ -79,7 +78,7 @@ static void test_bridge_init(void) static void test_device_init(void) { ASSERT_TRUE_MSG(get_device_nbr() >= 2, "Regular devices must be initialized after " - "tester and Bridge devices."); + "tester and Bridge devices."); /* Regular devices addresses starts from address 0x0003.*/ dev_uuid[6] = get_device_nbr() + 1; @@ -129,11 +128,9 @@ static void prov_node_added(uint16_t net_idx, uint8_t uuid[16], uint16_t addr, u k_sem_give(&prov_sem); } -static struct bt_mesh_prov tester_prov = { - .uuid = prov_uuid, - .unprovisioned_beacon = unprovisioned_beacon, - .node_added = prov_node_added -}; +static struct bt_mesh_prov tester_prov = {.uuid = prov_uuid, + .unprovisioned_beacon = unprovisioned_beacon, + .node_added = prov_node_added}; static void prov_complete(uint16_t net_idx, uint16_t addr) { @@ -174,8 +171,8 @@ static void tester_setup(void) for (int i = 0; i < REMOTE_NODES; i++) { LOG_INF("Creating subnet idx %d", i); - ASSERT_OK(bt_mesh_cfg_cli_net_key_add(0, PROV_ADDR, i + 1, subnet_keys[i], - &status)); + ASSERT_OK( + bt_mesh_cfg_cli_net_key_add(0, PROV_ADDR, i + 1, subnet_keys[i], &status)); if (status) { FAIL("NetKey add failed (status %u)", status); return; @@ -216,10 +213,8 @@ static void bridge_entry_add(uint16_t src, uint16_t dst, uint16_t net_idx1, uint entry.addr2 = dst; err = bt_mesh_brg_cfg_cli_bridging_table_add(0, BRIDGE_ADDR, &entry, &rsp); - if (err || rsp.status || - rsp.entry.directions != dir || - rsp.entry.net_idx1 != net_idx1 || rsp.entry.net_idx2 != net_idx2 || - rsp.entry.addr1 != src || rsp.entry.addr2 != dst) { + if (err || rsp.status || rsp.entry.directions != dir || rsp.entry.net_idx1 != net_idx1 || + rsp.entry.net_idx2 != net_idx2 || rsp.entry.addr1 != src || rsp.entry.addr2 != dst) { FAIL("Bridging table add failed (err %d) (status %u)", err, rsp.status); return; } @@ -229,8 +224,8 @@ static void bridge_entry_remove(uint16_t src, uint16_t dst, uint16_t net_idx1, u { struct bt_mesh_bridging_table_status rsp; - ASSERT_OK(bt_mesh_brg_cfg_cli_bridging_table_remove(0, BRIDGE_ADDR, net_idx1, net_idx2, - src, dst, &rsp)); + ASSERT_OK(bt_mesh_brg_cfg_cli_bridging_table_remove(0, BRIDGE_ADDR, net_idx1, net_idx2, src, + dst, &rsp)); if (rsp.status) { FAIL("Bridging table remove failed (status %u)", rsp.status); return; @@ -344,9 +339,8 @@ static void bridge_table_verify(uint16_t net_idx1, uint16_t net_idx2, uint16_t s net_buf_simple_init(rsp.list, 0); - ASSERT_OK(bt_mesh_brg_cfg_cli_bridging_table_get(0, BRIDGE_ADDR, net_idx1, - net_idx2, start_idx, - &rsp)); + ASSERT_OK(bt_mesh_brg_cfg_cli_bridging_table_get(0, BRIDGE_ADDR, net_idx1, net_idx2, + start_idx, &rsp)); ASSERT_EQUAL(rsp.status, 0); ASSERT_EQUAL(rsp.net_idx1, net_idx1); ASSERT_EQUAL(rsp.net_idx2, net_idx2); @@ -388,9 +382,7 @@ static void device_ra_cb(uint8_t *data, size_t length) case MSG_TYPE_GET: { uint8_t test_data[1 /*type */ + 1 /* msgs cnt */ + sizeof(recvd_msgs)] = { - MSG_TYPE_STATUS, - recvd_msgs_cnt - }; + MSG_TYPE_STATUS, recvd_msgs_cnt}; memcpy(&test_data[2], recvd_msgs, recvd_msgs_cnt * sizeof(recvd_msgs[0])); @@ -578,12 +570,18 @@ static void test_tester_table_state_change(void) * the addresses and net keys indexs are provided in the opposite order. */ bridge_entry_add(DEVICE_ADDR_START, PROV_ADDR, 1, 0, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY); - bridge_table_verify(0, 1, 0, (struct bridged_addresses_entry[]) { - { PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, - }, 1); - bridge_table_verify(1, 0, 0, (struct bridged_addresses_entry[]) { - { DEVICE_ADDR_START, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, - }, 1); + bridge_table_verify( + 0, 1, 0, + (struct bridged_addresses_entry[]){ + {PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY}, + }, + 1); + bridge_table_verify( + 1, 0, 0, + (struct bridged_addresses_entry[]){ + {DEVICE_ADDR_START, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY}, + }, + 1); k_sleep(K_SECONDS(1)); @@ -599,9 +597,12 @@ static void test_tester_table_state_change(void) */ bridge_entry_remove(DEVICE_ADDR_START, PROV_ADDR, 1, 0); bridge_entry_add(PROV_ADDR, DEVICE_ADDR_START, 0, 1, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY); - bridge_table_verify(0, 1, 0, (struct bridged_addresses_entry[]) { - { PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, - }, 1); + bridge_table_verify( + 0, 1, 0, + (struct bridged_addresses_entry[]){ + {PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY}, + }, + 1); bridge_table_verify(1, 0, 0, NULL, 0); ASSERT_OK(send_get(DEVICE_ADDR_START)); @@ -666,9 +667,12 @@ static void test_tester_net_key_remove(void) err = k_sem_take(&status_msg_recvd_sem, K_SECONDS(5)); ASSERT_EQUAL(err, -EAGAIN); - bridge_table_verify(0, 2, 0, (struct bridged_addresses_entry[]) { - { PROV_ADDR, DEVICE_ADDR_START + 1, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, - }, 1); + bridge_table_verify( + 0, 2, 0, + (struct bridged_addresses_entry[]){ + {PROV_ADDR, DEVICE_ADDR_START + 1, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY}, + }, + 1); /* Bridging Table Get message will return Invalid NetKey Index error because Subnet 1 is * removed. @@ -701,21 +705,33 @@ static void test_tester_persistence(void) return; } - bridge_table_verify(0, 1, 0, (struct bridged_addresses_entry[]) { - { PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, - }, 1); - - bridge_table_verify(0, 2, 0, (struct bridged_addresses_entry[]) { - { PROV_ADDR, DEVICE_ADDR_START + 1, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY }, - }, 1); - - bridge_table_verify(1, 0, 0, (struct bridged_addresses_entry[]) { - { DEVICE_ADDR_START, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, - }, 1); - - bridge_table_verify(2, 0, 0, (struct bridged_addresses_entry[]) { - { DEVICE_ADDR_START + 1, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY }, - }, 1); + bridge_table_verify( + 0, 1, 0, + (struct bridged_addresses_entry[]){ + {PROV_ADDR, DEVICE_ADDR_START, BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY}, + }, + 1); + + bridge_table_verify(0, 2, 0, + (struct bridged_addresses_entry[]){ + {PROV_ADDR, DEVICE_ADDR_START + 1, + BT_MESH_SUBNET_BRIDGE_DIR_TWOWAY}, + }, + 1); + + bridge_table_verify( + 1, 0, 0, + (struct bridged_addresses_entry[]){ + {DEVICE_ADDR_START, PROV_ADDR, BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY}, + }, + 1); + + bridge_table_verify(2, 0, 0, + (struct bridged_addresses_entry[]){ + {DEVICE_ADDR_START + 1, PROV_ADDR, + BT_MESH_SUBNET_BRIDGE_DIR_ONEWAY}, + }, + 1); } else { tester_setup(); @@ -758,7 +774,7 @@ static void msg_cache_workaround(void) * of the semaphor is not important as we just need to bump sequence number * enough to bypass message cache. */ - (void) k_sem_take(&status_msg_recvd_sem, K_SECONDS(1)); + (void)k_sem_take(&status_msg_recvd_sem, K_SECONDS(1)); } } @@ -942,21 +958,24 @@ static void test_device_simple_iv_test_mode(void) PASS(); } -#define TEST_CASE(role, name, description) \ - { \ - .test_id = "brg_" #role "_" #name, \ - .test_post_init_f = test_##role##_init, \ - .test_descr = description, \ - .test_tick_f = bt_mesh_test_timeout, \ - .test_main_f = test_##role##_##name, \ +#define TEST_CASE(role, name, description) \ + { \ + .test_id = "brg_" #role "_" #name, \ + .test_post_init_f = test_##role##_init, \ + .test_descr = description, \ + .test_tick_f = bt_mesh_test_timeout, \ + .test_main_f = test_##role##_##name, \ } static const struct bst_test_instance test_brg[] = { - TEST_CASE(tester, simple, "Tester node: provisions network, exchanges messages with " + TEST_CASE(tester, simple, + "Tester node: provisions network, exchanges messages with " "mesh nodes"), - TEST_CASE(tester, table_state_change, "Tester node: tests changing bridging table " + TEST_CASE(tester, table_state_change, + "Tester node: tests changing bridging table " "state"), - TEST_CASE(tester, net_key_remove, "Tester node: tests removing net key from Subnet " + TEST_CASE(tester, net_key_remove, + "Tester node: tests removing net key from Subnet " "Bridge"), #if CONFIG_BT_SETTINGS TEST_CASE(tester, persistence, "Tester node: test persistence of subnet bridge states"), @@ -968,8 +987,7 @@ static const struct bst_test_instance test_brg[] = { TEST_CASE(bridge, simple_iv_test_mode, "Subnet Bridge node with IV test mode enabled"), TEST_CASE(device, simple_iv_test_mode, "A mesh node with IV test mode enabled"), - BSTEST_END_MARKER -}; + BSTEST_END_MARKER}; struct bst_test_list *test_brg_install(struct bst_test_list *tests) { diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh index 1a6ad2b27749a11..5e056a113b76e30 100755 --- a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_ivu.sh @@ -17,6 +17,6 @@ RunTest mesh_brg_ivu \ brg_device_simple_iv_test_mode overlay=overlay_psa_conf -RunTest mesh_brg_ivu \ +RunTest mesh_brg_ivu_psa \ brg_tester_ivu brg_bridge_simple_iv_test_mode brg_device_simple_iv_test_mode \ brg_device_simple_iv_test_mode diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh index 17ca0ea2b4bbad8..349bb91540b815c 100755 --- a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_net_key_update.sh @@ -21,5 +21,5 @@ RunTest mesh_brg_net_key_remove \ brg_tester_net_key_remove brg_bridge_simple brg_device_simple brg_device_simple overlay=overlay_psa_conf -RunTest mesh_brg_net_key_remove \ +RunTest mesh_brg_net_key_remove_psa \ brg_tester_net_key_remove brg_bridge_simple brg_device_simple brg_device_simple diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh index 989f01abb23e79d..7e22f42589b4bdd 100755 --- a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh @@ -22,9 +22,9 @@ RunTestFlash mesh_brg_persistence \ # The same test but with PSA crypto overlay="overlay_pst_conf_overlay_psa_conf" -RunTestFlash mesh_brg_persistence \ +RunTestFlash mesh_brg_persistence_psa \ brg_tester_persistence -flash_erase brg_bridge_simple -flash_erase overlay="overlay_pst_conf_overlay_psa_conf" -RunTestFlash mesh_brg_persistence \ +RunTestFlash mesh_brg_persistence_psa \ brg_tester_persistence brg_bridge_simple diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh index 16aa96ac1a2cd85..d134502440ddb2f 100755 --- a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_simple.sh @@ -41,5 +41,5 @@ RunTest mesh_brg_simple \ brg_tester_simple brg_bridge_simple brg_device_simple brg_device_simple overlay=overlay_psa_conf -RunTest mesh_brg_simple \ +RunTest mesh_brg_simple_psa \ brg_tester_simple brg_bridge_simple brg_device_simple brg_device_simple diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh index ffaa6104530324a..f424b73d5f7e8d4 100755 --- a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh +++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_table_state_change.sh @@ -28,5 +28,5 @@ RunTest mesh_brg_table_state_change \ brg_tester_table_state_change brg_bridge_simple brg_device_simple brg_device_simple overlay=overlay_psa_conf -RunTest mesh_brg_table_state_change \ +RunTest mesh_brg_table_state_change_psa \ brg_tester_table_state_change brg_bridge_simple brg_device_simple brg_device_simple From 9acf53e412669af762441f3bbc8b79a6f6c236cb Mon Sep 17 00:00:00 2001 From: Jukka Rissanen Date: Fri, 13 Sep 2024 11:48:35 +0300 Subject: [PATCH 138/269] net: context: Set IPv4 address properly for sendmsg() When using sendmsg() and if CONFIG_NET_IPV4_MAPPING_TO_IPV6 is enabled, then the addr4 variable was set too late which was causing null pointer access. Signed-off-by: Jukka Rissanen --- subsys/net/ip/net_context.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/subsys/net/ip/net_context.c b/subsys/net/ip/net_context.c index 26937bd0b99974a..af434e950f17a5f 100644 --- a/subsys/net/ip/net_context.c +++ b/subsys/net/ip/net_context.c @@ -2026,19 +2026,6 @@ static int context_sendto(struct net_context *context, const struct sockaddr_in *addr4 = (const struct sockaddr_in *)dst_addr; struct sockaddr_in mapped; - /* Get the destination address from the mapped IPv6 address */ - if (IS_ENABLED(CONFIG_NET_IPV4_MAPPING_TO_IPV6) && - addr4->sin_family == AF_INET6 && - net_ipv6_addr_is_v4_mapped(&net_sin6(dst_addr)->sin6_addr)) { - struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)dst_addr; - - mapped.sin_port = addr6->sin6_port; - mapped.sin_family = AF_INET; - net_ipaddr_copy(&mapped.sin_addr, - (struct in_addr *)(&addr6->sin6_addr.s6_addr32[3])); - addr4 = &mapped; - } - if (msghdr) { addr4 = msghdr->msg_name; addrlen = msghdr->msg_namelen; @@ -2053,6 +2040,19 @@ static int context_sendto(struct net_context *context, dst_addr = (const struct sockaddr *)addr4; } + /* Get the destination address from the mapped IPv6 address */ + if (IS_ENABLED(CONFIG_NET_IPV4_MAPPING_TO_IPV6) && + addr4->sin_family == AF_INET6 && + net_ipv6_addr_is_v4_mapped(&net_sin6(dst_addr)->sin6_addr)) { + struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)dst_addr; + + mapped.sin_port = addr6->sin6_port; + mapped.sin_family = AF_INET; + net_ipaddr_copy(&mapped.sin_addr, + (struct in_addr *)(&addr6->sin6_addr.s6_addr32[3])); + addr4 = &mapped; + } + if (addrlen < sizeof(struct sockaddr_in)) { return -EINVAL; } From 66bce34af21bef3a399b76c14626f3ea940adabd Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Fri, 13 Sep 2024 12:05:46 +0700 Subject: [PATCH 139/269] drivers: i3c: shell: fix compilation error in `cmd_i3c_ccc_getmxds` Resolved a compilation error where `maxwr`, `maxrd`, and `max_read_turnaround` were incorrectly referenced. The code was updated to correctly access these fields from the `data_speed` structure. Signed-off-by: Pisit Sawangvonganan --- drivers/i3c/i3c_shell.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index 9d39e951b5b9e30..335b63154df580e 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -1714,9 +1714,9 @@ static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char mxds.fmt3.wrrdturn[0], mxds.fmt3.wrrdturn[1], sys_get_le24(&mxds.fmt3.wrrdturn[2])); /* Update values in descriptor */ - desc->maxwr = mxds.fmt3.wrrdturn[0]; - desc->maxrd = mxds.fmt3.wrrdturn[1]; - desc->max_read_turnaround = sys_get_le24(&mxds.fmt3.wrrdturn[2]); + desc->data_speed.maxwr = mxds.fmt3.wrrdturn[0]; + desc->data_speed.maxrd = mxds.fmt3.wrrdturn[1]; + desc->data_speed.max_read_turnaround = sys_get_le24(&mxds.fmt3.wrrdturn[2]); } else if (defbyte == GETMXDS_FORMAT_3_CRHDLY) { shell_print(shell_ctx, "CRHDLY1: 0x%02x", mxds.fmt3.crhdly1); } @@ -1724,9 +1724,9 @@ static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char shell_print(shell_ctx, "GETMXDS: maxwr 0x%02x; maxrd 0x%02x; maxrdturn 0x%06x", mxds.fmt2.maxwr, mxds.fmt2.maxrd, sys_get_le24(mxds.fmt2.maxrdturn)); /* Update values in descriptor */ - desc->maxwr = mxds.fmt2.maxwr; - desc->maxrd = mxds.fmt2.maxrd; - desc->max_read_turnaround = sys_get_le24(mxds.fmt2.maxrdturn); + desc->data_speed.maxwr = mxds.fmt2.maxwr; + desc->data_speed.maxrd = mxds.fmt2.maxrd; + desc->data_speed.max_read_turnaround = sys_get_le24(mxds.fmt2.maxrdturn); } return ret; From fdaaf3624c4b8c5309f53ef2aaf7f28c675e70f0 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Fri, 13 Sep 2024 12:19:00 +0700 Subject: [PATCH 140/269] drivers: i3c: shell: fix unhandled `` argument parsing The `` argument was included in `cmd_i3c_ccc_getvendor`, `cmd_i3c_ccc_setvendor`, and `cmd_i3c_ccc_setvendor_bc` but was not processed. Utilized `shell_strtoul` for proper parsing of the `` argument in these functions. Signed-off-by: Pisit Sawangvonganan --- drivers/i3c/i3c_shell.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index 335b63154df580e..cdc543e112e9e88 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -1548,6 +1548,7 @@ static int cmd_i3c_ccc_getvendor(const struct shell *shell_ctx, size_t argc, cha uint8_t defbyte; size_t num_xfer; uint8_t id; + int err = 0; int ret; dev = device_get_binding(argv[ARGV_DEV]); @@ -1555,6 +1556,7 @@ static int cmd_i3c_ccc_getvendor(const struct shell *shell_ctx, size_t argc, cha shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } + tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); @@ -1566,8 +1568,14 @@ static int cmd_i3c_ccc_getvendor(const struct shell *shell_ctx, size_t argc, cha return -ENODEV; } - if (argc > 3) { - defbyte = strtol(argv[3], NULL, 16); + id = (uint8_t)shell_strtoul(argv[3], 0, &err); + if (err != 0) { + shell_error(sh, "I3C: Invalid ID."); + return -EINVAL; + } + + if (argc > 4) { + defbyte = strtol(argv[4], NULL, 16); ret = i3c_ccc_do_getvendor_defbyte(desc, id, defbyte, buf, MAX_I3C_BYTES, &num_xfer); } else { @@ -1593,6 +1601,7 @@ static int cmd_i3c_ccc_setvendor(const struct shell *shell_ctx, size_t argc, cha uint8_t buf[MAX_I3C_BYTES] = {0}; uint8_t data_length; uint8_t id; + int err = 0; int ret; int i; @@ -1601,6 +1610,7 @@ static int cmd_i3c_ccc_setvendor(const struct shell *shell_ctx, size_t argc, cha shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } + tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); @@ -1613,6 +1623,12 @@ static int cmd_i3c_ccc_setvendor(const struct shell *shell_ctx, size_t argc, cha } data = (struct i3c_driver_data *)dev->data; + id = (uint8_t)shell_strtoul(argv[3], 0, &err); + if (err != 0) { + shell_error(sh, "I3C: Invalid ID."); + return -EINVAL; + } + data_length = argc - 4; for (i = 0; i < data_length; i++) { buf[i] = (uint8_t)strtol(argv[4 + i], NULL, 16); @@ -1634,6 +1650,7 @@ static int cmd_i3c_ccc_setvendor_bc(const struct shell *shell_ctx, size_t argc, uint8_t buf[MAX_I3C_BYTES] = {0}; uint8_t data_length; uint8_t id; + int err = 0; int ret; int i; @@ -1643,6 +1660,12 @@ static int cmd_i3c_ccc_setvendor_bc(const struct shell *shell_ctx, size_t argc, return -ENODEV; } + id = (uint8_t)shell_strtoul(argv[2], 0, &err); + if (err != 0) { + shell_error(sh, "I3C: Invalid ID."); + return -EINVAL; + } + data_length = argc - 3; for (i = 0; i < data_length; i++) { buf[i] = (uint8_t)strtol(argv[3 + i], NULL, 16); From d539257a8721de7c02b542881149125006bba6ec Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Fri, 13 Sep 2024 13:31:11 +0700 Subject: [PATCH 141/269] drivers: i3c: shell: align `struct shell *` argument name to `sh` Aligned the `struct shell *` argument name from `shell_ctx` to `sh` for consistency with other drivers' usage of `sh`, and to match the `shell_cmd_handler` argument name. Signed-off-by: Pisit Sawangvonganan --- drivers/i3c/i3c_shell.c | 494 ++++++++++++++++++++-------------------- 1 file changed, 247 insertions(+), 247 deletions(-) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index cdc543e112e9e88..593fa1dd6174c85 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -172,7 +172,7 @@ static struct i3c_device_desc *get_i3c_attached_desc_from_dev_name(const struct } /* i3c info [] */ -static int cmd_i3c_info(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_info(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_driver_data *data; @@ -182,7 +182,7 @@ static int cmd_i3c_info(const struct shell *shell_ctx, size_t argc, char **argv) dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; @@ -191,7 +191,7 @@ static int cmd_i3c_info(const struct shell *shell_ctx, size_t argc, char **argv) /* TODO: is this needed? */ tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Target Device driver %s not found.", + shell_error(sh, "I3C: Target Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } @@ -202,7 +202,7 @@ static int cmd_i3c_info(const struct shell *shell_ctx, size_t argc, char **argv) CONTAINER_OF(node, struct i3c_device_desc, node); /* only look for a device with the same name */ if (strcmp(desc->dev->name, tdev->name) == 0) { - shell_print(shell_ctx, + shell_print(sh, "name: %s\n" "\tpid: 0x%012llx\n" "\tstatic_addr: 0x%02x\n" @@ -236,21 +236,21 @@ static int cmd_i3c_info(const struct shell *shell_ctx, size_t argc, char **argv) } } } else { - shell_print(shell_ctx, "I3C: No devices found."); + shell_print(sh, "I3C: No devices found."); return -ENODEV; } if (found == false) { - shell_error(shell_ctx, "I3C: Target device not found."); + shell_error(sh, "I3C: Target device not found."); return -ENODEV; } } else if (argc == 2) { /* This gets all "currently attached" I3C and I2C devices */ if (!sys_slist_is_empty(&data->attached_dev.devices.i3c)) { - shell_print(shell_ctx, "I3C: Devices found:"); + shell_print(sh, "I3C: Devices found:"); SYS_SLIST_FOR_EACH_NODE(&data->attached_dev.devices.i3c, node) { struct i3c_device_desc *desc = CONTAINER_OF(node, struct i3c_device_desc, node); - shell_print(shell_ctx, + shell_print(sh, "name: %s\n" "\tpid: 0x%012llx\n" "\tstatic_addr: 0x%02x\n" @@ -281,50 +281,50 @@ static int cmd_i3c_info(const struct shell *shell_ctx, size_t argc, char **argv) desc->getcaps.getcap4); } } else { - shell_print(shell_ctx, "I3C: No devices found."); + shell_print(sh, "I3C: No devices found."); } if (!sys_slist_is_empty(&data->attached_dev.devices.i2c)) { - shell_print(shell_ctx, "I2C: Devices found:"); + shell_print(sh, "I2C: Devices found:"); SYS_SLIST_FOR_EACH_NODE(&data->attached_dev.devices.i2c, node) { struct i3c_i2c_device_desc *desc = CONTAINER_OF(node, struct i3c_i2c_device_desc, node); - shell_print(shell_ctx, + shell_print(sh, "addr: 0x%02x\n" "\tlvr: 0x%02x", desc->addr, desc->lvr); } } else { - shell_print(shell_ctx, "I2C: No devices found."); + shell_print(sh, "I2C: No devices found."); } } else { - shell_error(shell_ctx, "Invalid number of arguments."); + shell_error(sh, "Invalid number of arguments."); } return 0; } /* i3c recover */ -static int cmd_i3c_recover(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_recover(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; int err; dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[1]); + shell_error(sh, "I3C: Device driver %s not found.", argv[1]); return -ENODEV; } err = i3c_recover_bus(dev); if (err) { - shell_error(shell_ctx, "I3C: Bus recovery failed (err %d)", err); + shell_error(sh, "I3C: Bus recovery failed (err %d)", err); return err; } return 0; } -static int i3c_write_from_buffer(const struct shell *shell_ctx, char *s_dev_name, char *s_tdev_name, +static int i3c_write_from_buffer(const struct shell *sh, char *s_dev_name, char *s_tdev_name, char *s_reg_addr, char **data, uint8_t data_length) { /* This buffer must preserve 4 bytes for register address, as it is @@ -341,17 +341,17 @@ static int i3c_write_from_buffer(const struct shell *shell_ctx, char *s_dev_name dev = device_get_binding(s_dev_name); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", s_dev_name); + shell_error(sh, "I3C: Device driver %s not found.", s_dev_name); return -ENODEV; } tdev = device_get_binding(s_tdev_name); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", s_tdev_name); + shell_error(sh, "I3C: Device driver %s not found.", s_tdev_name); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -362,7 +362,7 @@ static int i3c_write_from_buffer(const struct shell *shell_ctx, char *s_dev_name if (data_length + reg_addr_bytes > MAX_I3C_BYTES) { data_length = MAX_I3C_BYTES - reg_addr_bytes; - shell_info(shell_ctx, "Too many bytes provided, limit is %d", + shell_info(sh, "Too many bytes provided, limit is %d", MAX_I3C_BYTES - reg_addr_bytes); } @@ -373,7 +373,7 @@ static int i3c_write_from_buffer(const struct shell *shell_ctx, char *s_dev_name ret = i3c_write(desc, buf + MAX_BYTES_FOR_REGISTER_INDEX - reg_addr_bytes, reg_addr_bytes + data_length); if (ret < 0) { - shell_error(shell_ctx, "Failed to write to device: %s", tdev->name); + shell_error(sh, "Failed to write to device: %s", tdev->name); return -EIO; } @@ -381,20 +381,20 @@ static int i3c_write_from_buffer(const struct shell *shell_ctx, char *s_dev_name } /* i3c write [, ...] */ -static int cmd_i3c_write(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_write(const struct shell *sh, size_t argc, char **argv) { - return i3c_write_from_buffer(shell_ctx, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], + return i3c_write_from_buffer(sh, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], &argv[4], argc - 4); } /* i3c write_byte */ -static int cmd_i3c_write_byte(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_write_byte(const struct shell *sh, size_t argc, char **argv) { - return i3c_write_from_buffer(shell_ctx, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], + return i3c_write_from_buffer(sh, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], &argv[4], 1); } -static int i3c_read_to_buffer(const struct shell *shell_ctx, char *s_dev_name, char *s_tdev_name, +static int i3c_read_to_buffer(const struct shell *sh, char *s_dev_name, char *s_tdev_name, char *s_reg_addr, uint8_t *buf, uint8_t buf_length) { const struct device *dev, *tdev; @@ -406,17 +406,17 @@ static int i3c_read_to_buffer(const struct shell *shell_ctx, char *s_dev_name, c dev = device_get_binding(s_dev_name); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", s_dev_name); + shell_error(sh, "I3C: Device driver %s not found.", s_dev_name); return -ENODEV; } tdev = device_get_binding(s_tdev_name); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", s_dev_name); + shell_error(sh, "I3C: Device driver %s not found.", s_dev_name); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -428,7 +428,7 @@ static int i3c_read_to_buffer(const struct shell *shell_ctx, char *s_dev_name, c ret = i3c_write_read(desc, reg_addr_buf + MAX_BYTES_FOR_REGISTER_INDEX - reg_addr_bytes, reg_addr_bytes, buf, buf_length); if (ret < 0) { - shell_error(shell_ctx, "Failed to read from device: %s", tdev->name); + shell_error(sh, "Failed to read from device: %s", tdev->name); return -EIO; } @@ -436,22 +436,22 @@ static int i3c_read_to_buffer(const struct shell *shell_ctx, char *s_dev_name, c } /* i3c read_byte */ -static int cmd_i3c_read_byte(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_read_byte(const struct shell *sh, size_t argc, char **argv) { uint8_t out; int ret; - ret = i3c_read_to_buffer(shell_ctx, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], &out, + ret = i3c_read_to_buffer(sh, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], &out, 1); if (ret == 0) { - shell_print(shell_ctx, "Output: 0x%x", out); + shell_print(sh, "Output: 0x%x", out); } return ret; } /* i3c read [] */ -static int cmd_i3c_read(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_read(const struct shell *sh, size_t argc, char **argv) { uint8_t buf[MAX_I3C_BYTES]; int num_bytes; @@ -466,17 +466,17 @@ static int cmd_i3c_read(const struct shell *shell_ctx, size_t argc, char **argv) num_bytes = MAX_I3C_BYTES; } - ret = i3c_read_to_buffer(shell_ctx, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], buf, + ret = i3c_read_to_buffer(sh, argv[ARGV_DEV], argv[ARGV_TDEV], argv[ARGV_REG], buf, num_bytes); if (ret == 0) { - shell_hexdump(shell_ctx, buf, num_bytes); + shell_hexdump(sh, buf, num_bytes); } return ret; } /* i3c ccc rstdaa */ -static int cmd_i3c_ccc_rstdaa(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_rstdaa(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -485,14 +485,14 @@ static int cmd_i3c_ccc_rstdaa(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; ret = i3c_ccc_do_rstdaa_all(dev); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC RSTDAA."); + shell_error(sh, "I3C: unable to send CCC RSTDAA."); return ret; } @@ -502,7 +502,7 @@ static int cmd_i3c_ccc_rstdaa(const struct shell *shell_ctx, size_t argc, char * struct i3c_device_desc *desc = CONTAINER_OF(node, struct i3c_device_desc, node); desc->dynamic_addr = 0; - shell_print(shell_ctx, "Reset dynamic address for device %s", + shell_print(sh, "Reset dynamic address for device %s", desc->dev->name); } } @@ -511,13 +511,13 @@ static int cmd_i3c_ccc_rstdaa(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc entdaa */ -static int cmd_i3c_ccc_entdaa(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entdaa(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } @@ -525,7 +525,7 @@ static int cmd_i3c_ccc_entdaa(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc setaasa */ -static int cmd_i3c_ccc_setaasa(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setaasa(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -534,14 +534,14 @@ static int cmd_i3c_ccc_setaasa(const struct shell *shell_ctx, size_t argc, char dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; ret = i3c_ccc_do_setaasa_all(dev); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC SETAASA."); + shell_error(sh, "I3C: unable to send CCC SETAASA."); return ret; } @@ -561,7 +561,7 @@ static int cmd_i3c_ccc_setaasa(const struct shell *shell_ctx, size_t argc, char } /* i3c ccc setdasa */ -static int cmd_i3c_ccc_setdasa(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setdasa(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -569,23 +569,23 @@ static int cmd_i3c_ccc_setdasa(const struct shell *shell_ctx, size_t argc, char dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_setdasa(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC SETDASA."); + shell_error(sh, "I3C: unable to send CCC SETDASA."); return ret; } @@ -594,7 +594,7 @@ static int cmd_i3c_ccc_setdasa(const struct shell *shell_ctx, size_t argc, char if (desc->dynamic_addr != desc->static_addr) { ret = i3c_reattach_i3c_device(desc, desc->static_addr); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to reattach device"); + shell_error(sh, "I3C: unable to reattach device"); return ret; } } @@ -603,7 +603,7 @@ static int cmd_i3c_ccc_setdasa(const struct shell *shell_ctx, size_t argc, char } /* i3c ccc setnewda */ -static int cmd_i3c_ccc_setnewda(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setnewda(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -614,17 +614,17 @@ static int cmd_i3c_ccc_setnewda(const struct shell *shell_ctx, size_t argc, char dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -632,13 +632,13 @@ static int cmd_i3c_ccc_setnewda(const struct shell *shell_ctx, size_t argc, char new_da.addr = strtol(argv[3], NULL, 16); /* check if the addressed is free */ if (!i3c_addr_slots_is_free(&data->attached_dev.addr_slots, new_da.addr)) { - shell_error(shell_ctx, "I3C: Address 0x%02x is already in use.", new_da.addr); + shell_error(sh, "I3C: Address 0x%02x is already in use.", new_da.addr); return -EINVAL; } ret = i3c_ccc_do_setnewda(desc, new_da); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC SETDASA."); + shell_error(sh, "I3C: unable to send CCC SETDASA."); return ret; } @@ -647,7 +647,7 @@ static int cmd_i3c_ccc_setnewda(const struct shell *shell_ctx, size_t argc, char desc->dynamic_addr = new_da.addr; ret = i3c_reattach_i3c_device(desc, old_da); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to reattach device"); + shell_error(sh, "I3C: unable to reattach device"); return ret; } @@ -655,7 +655,7 @@ static int cmd_i3c_ccc_setnewda(const struct shell *shell_ctx, size_t argc, char } /* i3c ccc getbcr */ -static int cmd_i3c_ccc_getbcr(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getbcr(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -664,34 +664,34 @@ static int cmd_i3c_ccc_getbcr(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_getbcr(desc, &bcr); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETBCR."); + shell_error(sh, "I3C: unable to send CCC GETBCR."); return ret; } - shell_print(shell_ctx, "BCR: 0x%02x", bcr.bcr); + shell_print(sh, "BCR: 0x%02x", bcr.bcr); desc->bcr = bcr.bcr; return ret; } /* i3c ccc getdcr */ -static int cmd_i3c_ccc_getdcr(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getdcr(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -700,34 +700,34 @@ static int cmd_i3c_ccc_getdcr(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_getdcr(desc, &dcr); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETDCR."); + shell_error(sh, "I3C: unable to send CCC GETDCR."); return ret; } - shell_print(shell_ctx, "DCR: 0x%02x", dcr.dcr); + shell_print(sh, "DCR: 0x%02x", dcr.dcr); desc->dcr = dcr.dcr; return ret; } /* i3c ccc getpid */ -static int cmd_i3c_ccc_getpid(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getpid(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -736,33 +736,33 @@ static int cmd_i3c_ccc_getpid(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_getpid(desc, &pid); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETPID."); + shell_error(sh, "I3C: unable to send CCC GETPID."); return ret; } - shell_print(shell_ctx, "PID: 0x%012llx", sys_get_be48(pid.pid)); + shell_print(sh, "PID: 0x%012llx", sys_get_be48(pid.pid)); return ret; } /* i3c ccc getmrl */ -static int cmd_i3c_ccc_getmrl(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getmrl(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -771,32 +771,32 @@ static int cmd_i3c_ccc_getmrl(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_getmrl(desc, &mrl); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETMRL."); + shell_error(sh, "I3C: unable to send CCC GETMRL."); return ret; } desc->data_length.mrl = mrl.len; if (desc->bcr & I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE) { - shell_print(shell_ctx, "MRL: 0x%04x; IBI Length:0x%02x", mrl.len, mrl.ibi_len); + shell_print(sh, "MRL: 0x%04x; IBI Length:0x%02x", mrl.len, mrl.ibi_len); desc->data_length.max_ibi = mrl.ibi_len; } else { - shell_print(shell_ctx, "MRL: 0x%04x", mrl.len); + shell_print(sh, "MRL: 0x%04x", mrl.len); desc->data_length.max_ibi = 0; } @@ -804,7 +804,7 @@ static int cmd_i3c_ccc_getmrl(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc getmwl */ -static int cmd_i3c_ccc_getmwl(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getmwl(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -813,34 +813,34 @@ static int cmd_i3c_ccc_getmwl(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_getmwl(desc, &mwl); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETMWL."); + shell_error(sh, "I3C: unable to send CCC GETMWL."); return ret; } - shell_print(shell_ctx, "MWL: 0x%04x", mwl.len); + shell_print(sh, "MWL: 0x%04x", mwl.len); desc->data_length.mwl = mwl.len; return ret; } /* i3c ccc setmrl [] */ -static int cmd_i3c_ccc_setmrl(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setmrl(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -849,23 +849,23 @@ static int cmd_i3c_ccc_setmrl(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } /* IBI length is required if the ibi payload bit is set */ if ((desc->bcr & I3C_BCR_IBI_PAYLOAD_HAS_DATA_BYTE) && (argc < 4)) { - shell_error(shell_ctx, "I3C: Missing IBI length."); + shell_error(sh, "I3C: Missing IBI length."); return -EINVAL; } @@ -876,7 +876,7 @@ static int cmd_i3c_ccc_setmrl(const struct shell *shell_ctx, size_t argc, char * ret = i3c_ccc_do_setmrl(desc, &mrl); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC SETMRL."); + shell_error(sh, "I3C: unable to send CCC SETMRL."); return ret; } @@ -889,7 +889,7 @@ static int cmd_i3c_ccc_setmrl(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc setmwl */ -static int cmd_i3c_ccc_setmwl(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setmwl(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -898,17 +898,17 @@ static int cmd_i3c_ccc_setmwl(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -916,7 +916,7 @@ static int cmd_i3c_ccc_setmwl(const struct shell *shell_ctx, size_t argc, char * ret = i3c_ccc_do_setmwl(desc, &mwl); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC SETMWL."); + shell_error(sh, "I3C: unable to send CCC SETMWL."); return ret; } @@ -926,7 +926,7 @@ static int cmd_i3c_ccc_setmwl(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc setmrl_bc [] */ -static int cmd_i3c_ccc_setmrl_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setmrl_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -936,7 +936,7 @@ static int cmd_i3c_ccc_setmrl_bc(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; @@ -948,7 +948,7 @@ static int cmd_i3c_ccc_setmrl_bc(const struct shell *shell_ctx, size_t argc, cha ret = i3c_ccc_do_setmrl_all(dev, &mrl, argc > 3); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC SETMRL BC."); + shell_error(sh, "I3C: unable to send CCC SETMRL BC."); return ret; } @@ -967,7 +967,7 @@ static int cmd_i3c_ccc_setmrl_bc(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc setmwl_bc */ -static int cmd_i3c_ccc_setmwl_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setmwl_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -977,7 +977,7 @@ static int cmd_i3c_ccc_setmwl_bc(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; @@ -986,7 +986,7 @@ static int cmd_i3c_ccc_setmwl_bc(const struct shell *shell_ctx, size_t argc, cha ret = i3c_ccc_do_setmwl_all(dev, &mwl); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC SETMWL BC."); + shell_error(sh, "I3C: unable to send CCC SETMWL BC."); return ret; } @@ -1002,25 +1002,25 @@ static int cmd_i3c_ccc_setmwl_bc(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc deftgts */ -static int cmd_i3c_ccc_deftgts(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_deftgts(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; int ret; dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } if (!i3c_bus_has_sec_controller(dev)) { - shell_error(shell_ctx, "I3C: No secondary controller on the bus"); + shell_error(sh, "I3C: No secondary controller on the bus"); return -ENXIO; } ret = i3c_bus_deftgts(dev); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC DEFTGTS."); + shell_error(sh, "I3C: unable to send CCC DEFTGTS."); return ret; } @@ -1028,7 +1028,7 @@ static int cmd_i3c_ccc_deftgts(const struct shell *shell_ctx, size_t argc, char } /* i3c ccc enttm */ -static int cmd_i3c_ccc_enttm(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_enttm(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; enum i3c_ccc_enttm_defbyte defbyte; @@ -1036,7 +1036,7 @@ static int cmd_i3c_ccc_enttm(const struct shell *shell_ctx, size_t argc, char ** dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } @@ -1044,7 +1044,7 @@ static int cmd_i3c_ccc_enttm(const struct shell *shell_ctx, size_t argc, char ** ret = i3c_ccc_do_enttm(dev, defbyte); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTTM."); + shell_error(sh, "I3C: unable to send CCC ENTTM."); return ret; } @@ -1052,7 +1052,7 @@ static int cmd_i3c_ccc_enttm(const struct shell *shell_ctx, size_t argc, char ** } /* i3c ccc rstact_bc */ -static int cmd_i3c_ccc_rstact_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_rstact_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; enum i3c_ccc_rstact_defining_byte action; @@ -1060,7 +1060,7 @@ static int cmd_i3c_ccc_rstact_bc(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } @@ -1068,7 +1068,7 @@ static int cmd_i3c_ccc_rstact_bc(const struct shell *shell_ctx, size_t argc, cha ret = i3c_ccc_do_rstact_all(dev, action); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC RSTACT BC."); + shell_error(sh, "I3C: unable to send CCC RSTACT BC."); return ret; } @@ -1076,7 +1076,7 @@ static int cmd_i3c_ccc_rstact_bc(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc enec_bc */ -static int cmd_i3c_ccc_enec_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_enec_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_ccc_events events; @@ -1084,7 +1084,7 @@ static int cmd_i3c_ccc_enec_bc(const struct shell *shell_ctx, size_t argc, char dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } @@ -1092,7 +1092,7 @@ static int cmd_i3c_ccc_enec_bc(const struct shell *shell_ctx, size_t argc, char ret = i3c_ccc_do_events_all_set(dev, true, &events); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENEC BC."); + shell_error(sh, "I3C: unable to send CCC ENEC BC."); return ret; } @@ -1100,7 +1100,7 @@ static int cmd_i3c_ccc_enec_bc(const struct shell *shell_ctx, size_t argc, char } /* i3c ccc disec_bc */ -static int cmd_i3c_ccc_disec_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_disec_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_ccc_events events; @@ -1108,7 +1108,7 @@ static int cmd_i3c_ccc_disec_bc(const struct shell *shell_ctx, size_t argc, char dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } @@ -1116,7 +1116,7 @@ static int cmd_i3c_ccc_disec_bc(const struct shell *shell_ctx, size_t argc, char ret = i3c_ccc_do_events_all_set(dev, false, &events); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENEC BC."); + shell_error(sh, "I3C: unable to send CCC ENEC BC."); return ret; } @@ -1124,7 +1124,7 @@ static int cmd_i3c_ccc_disec_bc(const struct shell *shell_ctx, size_t argc, char } /* i3c ccc enec */ -static int cmd_i3c_ccc_enec(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_enec(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1133,17 +1133,17 @@ static int cmd_i3c_ccc_enec(const struct shell *shell_ctx, size_t argc, char **a dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -1151,7 +1151,7 @@ static int cmd_i3c_ccc_enec(const struct shell *shell_ctx, size_t argc, char **a ret = i3c_ccc_do_events_set(desc, true, &events); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENEC BC."); + shell_error(sh, "I3C: unable to send CCC ENEC BC."); return ret; } @@ -1159,7 +1159,7 @@ static int cmd_i3c_ccc_enec(const struct shell *shell_ctx, size_t argc, char **a } /* i3c ccc disec */ -static int cmd_i3c_ccc_disec(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_disec(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1168,17 +1168,17 @@ static int cmd_i3c_ccc_disec(const struct shell *shell_ctx, size_t argc, char ** dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -1186,7 +1186,7 @@ static int cmd_i3c_ccc_disec(const struct shell *shell_ctx, size_t argc, char ** ret = i3c_ccc_do_events_set(desc, false, &events); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENEC BC."); + shell_error(sh, "I3C: unable to send CCC ENEC BC."); return ret; } @@ -1194,7 +1194,7 @@ static int cmd_i3c_ccc_disec(const struct shell *shell_ctx, size_t argc, char ** } /* i3c ccc entas0_bc */ -static int cmd_i3c_ccc_entas0_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas0_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -1202,14 +1202,14 @@ static int cmd_i3c_ccc_entas0_bc(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; ret = i3c_ccc_do_entas0_all(dev); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS0 BC."); + shell_error(sh, "I3C: unable to send CCC ENTAS0 BC."); return ret; } @@ -1217,7 +1217,7 @@ static int cmd_i3c_ccc_entas0_bc(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc entas1_bc */ -static int cmd_i3c_ccc_entas1_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas1_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -1225,14 +1225,14 @@ static int cmd_i3c_ccc_entas1_bc(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; ret = i3c_ccc_do_entas1_all(dev); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS1 BC."); + shell_error(sh, "I3C: unable to send CCC ENTAS1 BC."); return ret; } @@ -1240,7 +1240,7 @@ static int cmd_i3c_ccc_entas1_bc(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc entas2_bc */ -static int cmd_i3c_ccc_entas2_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas2_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -1248,14 +1248,14 @@ static int cmd_i3c_ccc_entas2_bc(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; ret = i3c_ccc_do_entas2_all(dev); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS2 BC."); + shell_error(sh, "I3C: unable to send CCC ENTAS2 BC."); return ret; } @@ -1263,7 +1263,7 @@ static int cmd_i3c_ccc_entas2_bc(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc entas3_bc */ -static int cmd_i3c_ccc_entas3_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas3_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -1271,14 +1271,14 @@ static int cmd_i3c_ccc_entas3_bc(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; ret = i3c_ccc_do_entas3_all(dev); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS3 BC."); + shell_error(sh, "I3C: unable to send CCC ENTAS3 BC."); return ret; } @@ -1286,7 +1286,7 @@ static int cmd_i3c_ccc_entas3_bc(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc entas0 */ -static int cmd_i3c_ccc_entas0(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas0(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1294,23 +1294,23 @@ static int cmd_i3c_ccc_entas0(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_entas0(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS0."); + shell_error(sh, "I3C: unable to send CCC ENTAS0."); return ret; } @@ -1318,7 +1318,7 @@ static int cmd_i3c_ccc_entas0(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc entas1 */ -static int cmd_i3c_ccc_entas1(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas1(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1326,23 +1326,23 @@ static int cmd_i3c_ccc_entas1(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_entas1(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS1."); + shell_error(sh, "I3C: unable to send CCC ENTAS1."); return ret; } @@ -1350,7 +1350,7 @@ static int cmd_i3c_ccc_entas1(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc entas2 */ -static int cmd_i3c_ccc_entas2(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas2(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1358,23 +1358,23 @@ static int cmd_i3c_ccc_entas2(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_entas2(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS2."); + shell_error(sh, "I3C: unable to send CCC ENTAS2."); return ret; } @@ -1382,7 +1382,7 @@ static int cmd_i3c_ccc_entas2(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc entas3 */ -static int cmd_i3c_ccc_entas3(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_entas3(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1390,23 +1390,23 @@ static int cmd_i3c_ccc_entas3(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_ccc_do_entas3(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC ENTAS3."); + shell_error(sh, "I3C: unable to send CCC ENTAS3."); return ret; } @@ -1414,7 +1414,7 @@ static int cmd_i3c_ccc_entas3(const struct shell *shell_ctx, size_t argc, char * } /* i3c ccc getstatus [] */ -static int cmd_i3c_ccc_getstatus(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getstatus(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1425,17 +1425,17 @@ static int cmd_i3c_ccc_getstatus(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -1444,7 +1444,7 @@ static int cmd_i3c_ccc_getstatus(const struct shell *shell_ctx, size_t argc, cha fmt = GETSTATUS_FORMAT_2; defbyte = strtol(argv[3], NULL, 16); if (defbyte != GETSTATUS_FORMAT_2_TGTSTAT || defbyte != GETSTATUS_FORMAT_2_PRECR) { - shell_error(shell_ctx, "Invalid defining byte."); + shell_error(sh, "Invalid defining byte."); return -EINVAL; } } else { @@ -1453,25 +1453,25 @@ static int cmd_i3c_ccc_getstatus(const struct shell *shell_ctx, size_t argc, cha ret = i3c_ccc_do_getstatus(desc, &status, fmt, defbyte); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETSTATUS."); + shell_error(sh, "I3C: unable to send CCC GETSTATUS."); return ret; } if (fmt == GETSTATUS_FORMAT_2) { if (defbyte == GETSTATUS_FORMAT_2_TGTSTAT) { - shell_print(shell_ctx, "TGTSTAT: 0x%04x", status.fmt2.tgtstat); + shell_print(sh, "TGTSTAT: 0x%04x", status.fmt2.tgtstat); } else if (defbyte == GETSTATUS_FORMAT_2_PRECR) { - shell_print(shell_ctx, "PRECR: 0x%04x", status.fmt2.precr); + shell_print(sh, "PRECR: 0x%04x", status.fmt2.precr); } } else { - shell_print(shell_ctx, "Status: 0x%04x", status.fmt1.status); + shell_print(sh, "Status: 0x%04x", status.fmt1.status); } return ret; } /* i3c ccc getcaps [] */ -static int cmd_i3c_ccc_getcaps(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getcaps(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1482,17 +1482,17 @@ static int cmd_i3c_ccc_getcaps(const struct shell *shell_ctx, size_t argc, char dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -1503,7 +1503,7 @@ static int cmd_i3c_ccc_getcaps(const struct shell *shell_ctx, size_t argc, char if (defbyte != GETCAPS_FORMAT_2_TGTCAPS || defbyte != GETCAPS_FORMAT_2_TESTPAT || defbyte != GETCAPS_FORMAT_2_CRCAPS || defbyte != GETCAPS_FORMAT_2_VTCAPS || defbyte != GETCAPS_FORMAT_2_DBGCAPS) { - shell_error(shell_ctx, "Invalid defining byte."); + shell_error(sh, "Invalid defining byte."); return -EINVAL; } } else { @@ -1512,26 +1512,26 @@ static int cmd_i3c_ccc_getcaps(const struct shell *shell_ctx, size_t argc, char ret = i3c_ccc_do_getcaps(desc, &caps, fmt, defbyte); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETCAPS."); + shell_error(sh, "I3C: unable to send CCC GETCAPS."); return ret; } if (fmt == GETCAPS_FORMAT_2) { if (defbyte == GETCAPS_FORMAT_2_TGTCAPS) { - shell_print(shell_ctx, "TGTCAPS: 0x%02x; 0x%02x; 0x%02x; 0x%02x", + shell_print(sh, "TGTCAPS: 0x%02x; 0x%02x; 0x%02x; 0x%02x", caps.fmt2.tgtcaps[0], caps.fmt2.tgtcaps[1], caps.fmt2.tgtcaps[2], caps.fmt2.tgtcaps[3]); } else if (defbyte == GETCAPS_FORMAT_2_TESTPAT) { - shell_print(shell_ctx, "TESTPAT: 0x%08x", caps.fmt2.testpat); + shell_print(sh, "TESTPAT: 0x%08x", caps.fmt2.testpat); } else if (defbyte == GETCAPS_FORMAT_2_CRCAPS) { - shell_print(shell_ctx, "CRCAPS: 0x%02x; 0x%02x", caps.fmt2.crcaps[0], + shell_print(sh, "CRCAPS: 0x%02x; 0x%02x", caps.fmt2.crcaps[0], caps.fmt2.crcaps[1]); } else if (defbyte == GETCAPS_FORMAT_2_VTCAPS) { - shell_print(shell_ctx, "VTCAPS: 0x%02x; 0x%02x", caps.fmt2.vtcaps[0], + shell_print(sh, "VTCAPS: 0x%02x; 0x%02x", caps.fmt2.vtcaps[0], caps.fmt2.vtcaps[1]); } } else { - shell_print(shell_ctx, "GETCAPS: 0x%02x; 0x%02x; 0x%02x; 0x%02x", + shell_print(sh, "GETCAPS: 0x%02x; 0x%02x; 0x%02x; 0x%02x", caps.fmt1.getcaps[0], caps.fmt1.getcaps[1], caps.fmt1.getcaps[2], caps.fmt1.getcaps[3]); } @@ -1540,7 +1540,7 @@ static int cmd_i3c_ccc_getcaps(const struct shell *shell_ctx, size_t argc, char } /* i3c ccc getvendor [] */ -static int cmd_i3c_ccc_getvendor(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getvendor(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1553,18 +1553,18 @@ static int cmd_i3c_ccc_getvendor(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -1583,17 +1583,17 @@ static int cmd_i3c_ccc_getvendor(const struct shell *shell_ctx, size_t argc, cha } if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC VENDOR."); + shell_error(sh, "I3C: unable to send CCC VENDOR."); return ret; } - shell_hexdump(shell_ctx, buf, num_xfer); + shell_hexdump(sh, buf, num_xfer); return ret; } /* i3c ccc setvendor [] */ -static int cmd_i3c_ccc_setvendor(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setvendor(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1607,18 +1607,18 @@ static int cmd_i3c_ccc_setvendor(const struct shell *shell_ctx, size_t argc, cha dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; @@ -1636,7 +1636,7 @@ static int cmd_i3c_ccc_setvendor(const struct shell *shell_ctx, size_t argc, cha ret = i3c_ccc_do_setvendor(desc, id, buf, data_length); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC VENDOR."); + shell_error(sh, "I3C: unable to send CCC VENDOR."); return ret; } @@ -1644,7 +1644,7 @@ static int cmd_i3c_ccc_setvendor(const struct shell *shell_ctx, size_t argc, cha } /* i3c ccc setvendor_bc [] */ -static int cmd_i3c_ccc_setvendor_bc(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_setvendor_bc(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; uint8_t buf[MAX_I3C_BYTES] = {0}; @@ -1656,7 +1656,7 @@ static int cmd_i3c_ccc_setvendor_bc(const struct shell *shell_ctx, size_t argc, dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } @@ -1673,7 +1673,7 @@ static int cmd_i3c_ccc_setvendor_bc(const struct shell *shell_ctx, size_t argc, ret = i3c_ccc_do_setvendor_all(dev, id, buf, data_length); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC VENDOR."); + shell_error(sh, "I3C: unable to send CCC VENDOR."); return ret; } @@ -1681,7 +1681,7 @@ static int cmd_i3c_ccc_setvendor_bc(const struct shell *shell_ctx, size_t argc, } /* i3c ccc getmxds [] */ -static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_ccc_getmxds(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1692,22 +1692,22 @@ static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } if (!(desc->bcr & I3C_BCR_MAX_DATA_SPEED_LIMIT)) { - shell_error(shell_ctx, "I3C: Device %s does not support max data speed limit", + shell_error(sh, "I3C: Device %s does not support max data speed limit", desc->dev->name); return -ENOTSUP; } @@ -1717,7 +1717,7 @@ static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char fmt = GETMXDS_FORMAT_3; defbyte = strtol(argv[3], NULL, 16); if (defbyte != GETMXDS_FORMAT_3_CRHDLY || defbyte != GETMXDS_FORMAT_3_WRRDTURN) { - shell_error(shell_ctx, "Invalid defining byte."); + shell_error(sh, "Invalid defining byte."); return -EINVAL; } } else { @@ -1726,13 +1726,13 @@ static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char ret = i3c_ccc_do_getmxds(desc, &mxds, fmt, defbyte); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to send CCC GETMXDS."); + shell_error(sh, "I3C: unable to send CCC GETMXDS."); return ret; } if (fmt == GETMXDS_FORMAT_3) { if (defbyte == GETMXDS_FORMAT_3_WRRDTURN) { - shell_print(shell_ctx, + shell_print(sh, "WRRDTURN: maxwr 0x%02x; maxrd 0x%02x; maxrdturn 0x%06x", mxds.fmt3.wrrdturn[0], mxds.fmt3.wrrdturn[1], sys_get_le24(&mxds.fmt3.wrrdturn[2])); @@ -1741,10 +1741,10 @@ static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char desc->data_speed.maxrd = mxds.fmt3.wrrdturn[1]; desc->data_speed.max_read_turnaround = sys_get_le24(&mxds.fmt3.wrrdturn[2]); } else if (defbyte == GETMXDS_FORMAT_3_CRHDLY) { - shell_print(shell_ctx, "CRHDLY1: 0x%02x", mxds.fmt3.crhdly1); + shell_print(sh, "CRHDLY1: 0x%02x", mxds.fmt3.crhdly1); } } else { - shell_print(shell_ctx, "GETMXDS: maxwr 0x%02x; maxrd 0x%02x; maxrdturn 0x%06x", + shell_print(sh, "GETMXDS: maxwr 0x%02x; maxrd 0x%02x; maxrdturn 0x%06x", mxds.fmt2.maxwr, mxds.fmt2.maxrd, sys_get_le24(mxds.fmt2.maxrdturn)); /* Update values in descriptor */ desc->data_speed.maxwr = mxds.fmt2.maxwr; @@ -1755,7 +1755,7 @@ static int cmd_i3c_ccc_getmxds(const struct shell *shell_ctx, size_t argc, char return ret; } -static int cmd_i3c_attach(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_attach(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1763,29 +1763,29 @@ static int cmd_i3c_attach(const struct shell *shell_ctx, size_t argc, char **arg dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_list_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_attach_i3c_device(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to attach device %s.", tdev->name); + shell_error(sh, "I3C: unable to attach device %s.", tdev->name); } return ret; } -static int cmd_i3c_reattach(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_reattach(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1794,17 +1794,17 @@ static int cmd_i3c_reattach(const struct shell *shell_ctx, size_t argc, char **a dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } @@ -1814,13 +1814,13 @@ static int cmd_i3c_reattach(const struct shell *shell_ctx, size_t argc, char **a ret = i3c_reattach_i3c_device(desc, old_dyn_addr); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to reattach device %s.", tdev->name); + shell_error(sh, "I3C: unable to reattach device %s.", tdev->name); } return ret; } -static int cmd_i3c_detach(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_detach(const struct shell *sh, size_t argc, char **argv) { const struct device *dev, *tdev; struct i3c_device_desc *desc; @@ -1828,29 +1828,29 @@ static int cmd_i3c_detach(const struct shell *shell_ctx, size_t argc, char **arg dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } tdev = device_get_binding(argv[ARGV_TDEV]); if (!tdev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); return -ENODEV; } desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); if (!desc) { - shell_error(shell_ctx, "I3C: Device %s not attached to bus.", tdev->name); + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); return -ENODEV; } ret = i3c_detach_i3c_device(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to detach device %s.", tdev->name); + shell_error(sh, "I3C: unable to detach device %s.", tdev->name); } return ret; } -static int cmd_i3c_i2c_attach(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_i2c_attach(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_i2c_device_desc *desc; @@ -1859,25 +1859,25 @@ static int cmd_i3c_i2c_attach(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } addr = strtol(argv[2], NULL, 16); desc = get_i3c_i2c_list_desc_from_addr(dev, addr); if (!desc) { - shell_error(shell_ctx, "I3C: I2C addr 0x%02x not listed with the bus.", addr); + shell_error(sh, "I3C: I2C addr 0x%02x not listed with the bus.", addr); return -ENODEV; } ret = i3c_attach_i2c_device(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to attach I2C addr 0x%02x.", addr); + shell_error(sh, "I3C: unable to attach I2C addr 0x%02x.", addr); } return ret; } -static int cmd_i3c_i2c_detach(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_i2c_detach(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_i2c_device_desc *desc; @@ -1886,19 +1886,19 @@ static int cmd_i3c_i2c_detach(const struct shell *shell_ctx, size_t argc, char * dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } addr = strtol(argv[2], NULL, 16); desc = get_i3c_i2c_list_desc_from_addr(dev, addr); if (!desc) { - shell_error(shell_ctx, "I3C: I2C addr 0x%02x not listed with the bus.", addr); + shell_error(sh, "I3C: I2C addr 0x%02x not listed with the bus.", addr); return -ENODEV; } ret = i3c_detach_i2c_device(desc); if (ret < 0) { - shell_error(shell_ctx, "I3C: unable to detach I2C addr 0x%02x.", addr); + shell_error(sh, "I3C: unable to detach I2C addr 0x%02x.", addr); } return ret; @@ -1926,7 +1926,7 @@ static int cmd_i3c_i2c_detach(const struct shell *shell_ctx, size_t argc, char * * https://manpages.debian.org/buster/i2c-tools/i2cdetect.8.en.html */ /* i3c i2c_scan */ -static int cmd_i3c_i2c_scan(const struct shell *shell_ctx, size_t argc, char **argv) +static int cmd_i3c_i2c_scan(const struct shell *sh, size_t argc, char **argv) { const struct device *dev; struct i3c_driver_data *data; @@ -1936,18 +1936,18 @@ static int cmd_i3c_i2c_scan(const struct shell *shell_ctx, size_t argc, char **a dev = device_get_binding(argv[ARGV_DEV]); if (!dev) { - shell_error(shell_ctx, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); return -ENODEV; } data = (struct i3c_driver_data *)dev->data; - shell_print(shell_ctx, " 0 1 2 3 4 5 6 7 8 9 a b c d e f"); + shell_print(sh, " 0 1 2 3 4 5 6 7 8 9 a b c d e f"); for (uint8_t i = 0; i <= last; i += 16) { - shell_fprintf(shell_ctx, SHELL_NORMAL, "%02x: ", i); + shell_fprintf(sh, SHELL_NORMAL, "%02x: ", i); for (uint8_t j = 0; j < 16; j++) { if (i + j < first || i + j > last) { - shell_fprintf(shell_ctx, SHELL_NORMAL, " "); + shell_fprintf(sh, SHELL_NORMAL, " "); continue; } @@ -1964,7 +1964,7 @@ static int cmd_i3c_i2c_scan(const struct shell *shell_ctx, size_t argc, char **a ret = i3c_attach_i2c_device(&desc); if (ret < 0) { - shell_error(shell_ctx, + shell_error(sh, "I3C: unable to attach I2C addr 0x%02x.", desc.addr); } @@ -1974,32 +1974,32 @@ static int cmd_i3c_i2c_scan(const struct shell *shell_ctx, size_t argc, char **a msgs[0].len = 0U; msgs[0].flags = I2C_MSG_WRITE | I2C_MSG_STOP; if (i2c_transfer(dev, &msgs[0], 1, i + j) == 0) { - shell_fprintf(shell_ctx, SHELL_NORMAL, "%02x ", i + j); + shell_fprintf(sh, SHELL_NORMAL, "%02x ", i + j); ++cnt; } else { - shell_fprintf(shell_ctx, SHELL_NORMAL, "-- "); + shell_fprintf(sh, SHELL_NORMAL, "-- "); } ret = i3c_detach_i2c_device(&desc); if (ret < 0) { - shell_error(shell_ctx, + shell_error(sh, "I3C: unable to detach I2C addr 0x%02x.", desc.addr); } } else if (slot == I3C_ADDR_SLOT_STATUS_I3C_DEV) { - shell_fprintf(shell_ctx, SHELL_NORMAL, "I3 "); + shell_fprintf(sh, SHELL_NORMAL, "I3 "); } else if (slot == I3C_ADDR_SLOT_STATUS_I2C_DEV) { - shell_fprintf(shell_ctx, SHELL_NORMAL, "I2 "); + shell_fprintf(sh, SHELL_NORMAL, "I2 "); } else if (slot == I3C_ADDR_SLOT_STATUS_RSVD) { - shell_fprintf(shell_ctx, SHELL_NORMAL, "RS "); + shell_fprintf(sh, SHELL_NORMAL, "RS "); } else { - shell_fprintf(shell_ctx, SHELL_NORMAL, "-- "); + shell_fprintf(sh, SHELL_NORMAL, "-- "); } } - shell_print(shell_ctx, ""); + shell_print(sh, ""); } - shell_print(shell_ctx, "%u additional devices found on %s", cnt, argv[ARGV_DEV]); + shell_print(sh, "%u additional devices found on %s", cnt, argv[ARGV_DEV]); return 0; } From 7a59ebf6afedfa07e0ac1653599abdc985b4c8b1 Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Fri, 13 Sep 2024 14:27:45 +0700 Subject: [PATCH 142/269] drivers: i3c: shell: use `shell_fprintf_normal` instead of `shell_fprintf` Due to the introduction of `shell_fprintf_normal` in PR #77192, we can minimize caller overhead by eliminating direct `color` parameter passing. Signed-off-by: Pisit Sawangvonganan --- drivers/i3c/i3c_shell.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index 593fa1dd6174c85..02f9e48ffa44bb0 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -1944,10 +1944,10 @@ static int cmd_i3c_i2c_scan(const struct shell *sh, size_t argc, char **argv) shell_print(sh, " 0 1 2 3 4 5 6 7 8 9 a b c d e f"); for (uint8_t i = 0; i <= last; i += 16) { - shell_fprintf(sh, SHELL_NORMAL, "%02x: ", i); + shell_fprintf_normal(sh, "%02x: ", i); for (uint8_t j = 0; j < 16; j++) { if (i + j < first || i + j > last) { - shell_fprintf(sh, SHELL_NORMAL, " "); + shell_fprintf_normal(sh, " "); continue; } @@ -1974,10 +1974,10 @@ static int cmd_i3c_i2c_scan(const struct shell *sh, size_t argc, char **argv) msgs[0].len = 0U; msgs[0].flags = I2C_MSG_WRITE | I2C_MSG_STOP; if (i2c_transfer(dev, &msgs[0], 1, i + j) == 0) { - shell_fprintf(sh, SHELL_NORMAL, "%02x ", i + j); + shell_fprintf_normal(sh, "%02x ", i + j); ++cnt; } else { - shell_fprintf(sh, SHELL_NORMAL, "-- "); + shell_fprintf_normal(sh, "-- "); } ret = i3c_detach_i2c_device(&desc); @@ -1987,13 +1987,13 @@ static int cmd_i3c_i2c_scan(const struct shell *sh, size_t argc, char **argv) desc.addr); } } else if (slot == I3C_ADDR_SLOT_STATUS_I3C_DEV) { - shell_fprintf(sh, SHELL_NORMAL, "I3 "); + shell_fprintf_normal(sh, "I3 "); } else if (slot == I3C_ADDR_SLOT_STATUS_I2C_DEV) { - shell_fprintf(sh, SHELL_NORMAL, "I2 "); + shell_fprintf_normal(sh, "I2 "); } else if (slot == I3C_ADDR_SLOT_STATUS_RSVD) { - shell_fprintf(sh, SHELL_NORMAL, "RS "); + shell_fprintf_normal(sh, "RS "); } else { - shell_fprintf(sh, SHELL_NORMAL, "-- "); + shell_fprintf_normal(sh, "-- "); } } shell_print(sh, ""); From e94e5eb10c333ace808f4bf6e1f86858041f1517 Mon Sep 17 00:00:00 2001 From: Corey Wharton Date: Mon, 9 Sep 2024 09:32:27 -0700 Subject: [PATCH 143/269] drivers: dac: add flag to channel config to support internal connections Allows user to connect DAC output to internal peripherals for HW and drivers that support it. Signed-off-by: Corey Wharton --- include/zephyr/drivers/dac.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/zephyr/drivers/dac.h b/include/zephyr/drivers/dac.h index 8e38432051ab3a6..e6f696fc9dc4c49 100644 --- a/include/zephyr/drivers/dac.h +++ b/include/zephyr/drivers/dac.h @@ -39,7 +39,12 @@ struct dac_channel_cfg { * This is relevant for instance if the output is directly connected to the load, * without an amplifierin between. The actual details on this are hardware dependent. */ - bool buffered; + bool buffered: 1; + /** Enable internal output path for this channel. This is relevant for channels that + * support directly connecting to on-chip peripherals via internal paths. The actual + * details on this are hardware dependent. + */ + bool internal: 1; }; /** From 834cc98f3919fca5eee0ac7930984da33a82f202 Mon Sep 17 00:00:00 2001 From: Corey Wharton Date: Mon, 9 Sep 2024 09:36:09 -0700 Subject: [PATCH 144/269] drivers: dac_stm32: add support for internally connected channels Adds support for configuring the STM32 DAC channel mode for internal connections. This is only enabled for SOCs that support it. Signed-off-by: Corey Wharton --- drivers/dac/dac_stm32.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/drivers/dac/dac_stm32.c b/drivers/dac/dac_stm32.c index a993145655e4e79..a20d583819b6ab5 100644 --- a/drivers/dac/dac_stm32.c +++ b/drivers/dac/dac_stm32.c @@ -89,7 +89,7 @@ static int dac_stm32_channel_setup(const struct device *dev, { struct dac_stm32_data *data = dev->data; const struct dac_stm32_cfg *cfg = dev->config; - uint32_t output_buffer; + uint32_t cfg_setting, channel; if ((channel_cfg->channel_id - STM32_FIRST_CHANNEL >= data->channel_count) || @@ -106,18 +106,33 @@ static int dac_stm32_channel_setup(const struct device *dev, return -ENOTSUP; } + channel = table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL]; + if (channel_cfg->buffered) { - output_buffer = LL_DAC_OUTPUT_BUFFER_ENABLE; + cfg_setting = LL_DAC_OUTPUT_BUFFER_ENABLE; + } else { + cfg_setting = LL_DAC_OUTPUT_BUFFER_DISABLE; + } + + LL_DAC_SetOutputBuffer(cfg->base, channel, cfg_setting); + +#if defined(LL_DAC_OUTPUT_CONNECT_INTERNAL) + /* If the DAC supports internal connections set it based on configuration */ + if (channel_cfg->internal) { + cfg_setting = LL_DAC_OUTPUT_CONNECT_INTERNAL; } else { - output_buffer = LL_DAC_OUTPUT_BUFFER_DISABLE; + cfg_setting = LL_DAC_OUTPUT_CONNECT_GPIO; } - LL_DAC_SetOutputBuffer(cfg->base, - table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL], - output_buffer); + LL_DAC_SetOutputConnection(cfg->base, channel, cfg_setting); +#else + if (channel_cfg->internal) { + LOG_ERR("Internal connections not supported"); + return -ENOTSUP; + } +#endif /* LL_DAC_OUTPUT_CONNECT_INTERNAL */ - LL_DAC_Enable(cfg->base, - table_channels[channel_cfg->channel_id - STM32_FIRST_CHANNEL]); + LL_DAC_Enable(cfg->base, channel); LOG_DBG("Channel setup succeeded!"); From 2b9ed72f9ebf8dc72db5edd9ff4bae8875165b73 Mon Sep 17 00:00:00 2001 From: Corey Wharton Date: Fri, 23 Aug 2024 10:31:11 -0700 Subject: [PATCH 145/269] drivers: dac_stm32: make pinctrl config in the device tree optional Now that we support internally connected channels we should make the pinctrl configuration optional. Signed-off-by: Corey Wharton --- drivers/dac/dac_stm32.c | 2 +- dts/bindings/dac/st,stm32-dac.yaml | 6 ------ 2 files changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/dac/dac_stm32.c b/drivers/dac/dac_stm32.c index a20d583819b6ab5..f2cbe9b15af5b65 100644 --- a/drivers/dac/dac_stm32.c +++ b/drivers/dac/dac_stm32.c @@ -159,7 +159,7 @@ static int dac_stm32_init(const struct device *dev) /* Configure dt provided device signals when available */ err = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); - if (err < 0) { + if ((err < 0) && (err != -ENOENT)) { LOG_ERR("DAC pinctrl setup failed (%d)", err); return err; } diff --git a/dts/bindings/dac/st,stm32-dac.yaml b/dts/bindings/dac/st,stm32-dac.yaml index c5c8321cbef9088..5b142d528bc1726 100644 --- a/dts/bindings/dac/st,stm32-dac.yaml +++ b/dts/bindings/dac/st,stm32-dac.yaml @@ -17,11 +17,5 @@ properties: "#io-channel-cells": const: 1 - pinctrl-0: - required: true - - pinctrl-names: - required: true - io-channel-cells: - output From d80174fadfd20f2e614f2c3b1f7697015e3b14f7 Mon Sep 17 00:00:00 2001 From: Corey Wharton Date: Mon, 9 Sep 2024 10:47:05 -0700 Subject: [PATCH 146/269] drivers: dac: add checks for internal channel config Return -ENOTSUP if these flags are specified but not supported. Signed-off-by: Corey Wharton --- drivers/dac/dac_ad559x.c | 5 +++++ drivers/dac/dac_ad569x.c | 5 +++++ drivers/dac/dac_ad56xx.c | 5 +++++ drivers/dac/dac_dacx0501.c | 5 +++++ drivers/dac/dac_dacx0508.c | 5 +++++ drivers/dac/dac_dacx3608.c | 5 +++++ drivers/dac/dac_esp32.c | 5 +++++ drivers/dac/dac_gd32.c | 5 +++++ drivers/dac/dac_ltc166x.c | 5 +++++ drivers/dac/dac_mcp4725.c | 4 ++++ drivers/dac/dac_mcp4728.c | 4 ++++ drivers/dac/dac_mcux_dac.c | 5 +++++ drivers/dac/dac_mcux_dac32.c | 5 +++++ drivers/dac/dac_mcux_gau.c | 11 ++++++++--- drivers/dac/dac_mcux_lpdac.c | 5 +++++ drivers/dac/dac_sam.c | 4 ++++ drivers/dac/dac_sam0.c | 4 ++++ 17 files changed, 84 insertions(+), 3 deletions(-) diff --git a/drivers/dac/dac_ad559x.c b/drivers/dac/dac_ad559x.c index 0dc1c3caa236c8e..e7cb90a9ac5ed61 100644 --- a/drivers/dac/dac_ad559x.c +++ b/drivers/dac/dac_ad559x.c @@ -43,6 +43,11 @@ static int dac_ad559x_channel_setup(const struct device *dev, return -EINVAL; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + data->dac_conf |= BIT(channel_cfg->channel_id); return mfd_ad559x_write_reg(config->mfd_dev, AD559X_REG_LDAC_EN, data->dac_conf); diff --git a/drivers/dac/dac_ad569x.c b/drivers/dac/dac_ad569x.c index ff10a6d336683de..afe3b095ba70295 100644 --- a/drivers/dac/dac_ad569x.c +++ b/drivers/dac/dac_ad569x.c @@ -77,6 +77,11 @@ static int ad569x_channel_setup(const struct device *dev, const struct dac_chann return -EINVAL; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + return 0; } diff --git a/drivers/dac/dac_ad56xx.c b/drivers/dac/dac_ad56xx.c index 2e757d26418c2df..232b6a289c3a01d 100644 --- a/drivers/dac/dac_ad56xx.c +++ b/drivers/dac/dac_ad56xx.c @@ -94,6 +94,11 @@ static int ad56xx_channel_setup(const struct device *dev, const struct dac_chann return -EINVAL; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + return 0; } diff --git a/drivers/dac/dac_dacx0501.c b/drivers/dac/dac_dacx0501.c index f8ee999dee10900..411011cfa4ec435 100644 --- a/drivers/dac/dac_dacx0501.c +++ b/drivers/dac/dac_dacx0501.c @@ -106,6 +106,11 @@ static int dacx0501_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + return 0; } diff --git a/drivers/dac/dac_dacx0508.c b/drivers/dac/dac_dacx0508.c index 49f8b71a818d58a..404709a3dfb7a86 100644 --- a/drivers/dac/dac_dacx0508.c +++ b/drivers/dac/dac_dacx0508.c @@ -163,6 +163,11 @@ static int dacx0508_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + data->configured |= BIT(channel_cfg->channel_id); return 0; diff --git a/drivers/dac/dac_dacx3608.c b/drivers/dac/dac_dacx3608.c index 98942595742cf8b..e2340422020c788 100644 --- a/drivers/dac/dac_dacx3608.c +++ b/drivers/dac/dac_dacx3608.c @@ -102,6 +102,11 @@ static int dacx3608_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + if (data->configured & BIT(channel_cfg->channel_id)) { LOG_DBG("Channel %d already configured", channel_cfg->channel_id); return 0; diff --git a/drivers/dac/dac_esp32.c b/drivers/dac/dac_esp32.c index 9c5d5775e9f35d6..6dcac59b3a03086 100644 --- a/drivers/dac/dac_esp32.c +++ b/drivers/dac/dac_esp32.c @@ -44,6 +44,11 @@ static int dac_esp32_channel_setup(const struct device *dev, return -EINVAL; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + dac_output_enable(channel_cfg->channel_id); return 0; diff --git a/drivers/dac/dac_gd32.c b/drivers/dac/dac_gd32.c index f92e126236f3a4a..be58e034c7e576f 100644 --- a/drivers/dac/dac_gd32.c +++ b/drivers/dac/dac_gd32.c @@ -115,6 +115,11 @@ static int dac_gd32_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + data->resolutions[dacx] = channel_cfg->resolution; dac_gd32_disable(dacx); diff --git a/drivers/dac/dac_ltc166x.c b/drivers/dac/dac_ltc166x.c index 81d579949c92d9d..ee804e4c46bc1dc 100644 --- a/drivers/dac/dac_ltc166x.c +++ b/drivers/dac/dac_ltc166x.c @@ -66,6 +66,11 @@ static int ltc166x_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + return 0; } diff --git a/drivers/dac/dac_mcp4725.c b/drivers/dac/dac_mcp4725.c index 8c727cf26a37d28..eb9286cbae4eb70 100644 --- a/drivers/dac/dac_mcp4725.c +++ b/drivers/dac/dac_mcp4725.c @@ -76,6 +76,10 @@ static int mcp4725_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + return -ENOTSUP; + } + return 0; } diff --git a/drivers/dac/dac_mcp4728.c b/drivers/dac/dac_mcp4728.c index ce685ace53ad465..e02e22f3cddf3ae 100644 --- a/drivers/dac/dac_mcp4728.c +++ b/drivers/dac/dac_mcp4728.c @@ -45,6 +45,10 @@ static int mcp4728_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + return -ENOTSUP; + } + return 0; } diff --git a/drivers/dac/dac_mcux_dac.c b/drivers/dac/dac_mcux_dac.c index bb167fa71c06967..8af883c6e0cd409 100644 --- a/drivers/dac/dac_mcux_dac.c +++ b/drivers/dac/dac_mcux_dac.c @@ -41,6 +41,11 @@ static int mcux_dac_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + DAC_GetDefaultConfig(&dac_config); dac_config.enableLowPowerMode = config->low_power; dac_config.referenceVoltageSource = config->reference; diff --git a/drivers/dac/dac_mcux_dac32.c b/drivers/dac/dac_mcux_dac32.c index 35d80dbda13fdfa..a1ba991b2c226a7 100644 --- a/drivers/dac/dac_mcux_dac32.c +++ b/drivers/dac/dac_mcux_dac32.c @@ -44,6 +44,11 @@ static int mcux_dac32_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + DAC32_GetDefaultConfig(&dac32_config); dac32_config.enableLowPowerMode = config->low_power; dac32_config.referenceVoltageSource = config->reference; diff --git a/drivers/dac/dac_mcux_gau.c b/drivers/dac/dac_mcux_gau.c index ba4835b1c704680..6924132afe9643d 100644 --- a/drivers/dac/dac_mcux_gau.c +++ b/drivers/dac/dac_mcux_gau.c @@ -38,20 +38,25 @@ static int nxp_gau_dac_channel_setup(const struct device *dev, { const struct nxp_gau_dac_config *config = dev->config; dac_channel_config_t dac_channel_config = {0}; + bool use_internal = true; if (channel_cfg->resolution != 10) { LOG_ERR("DAC only support 10 bit resolution"); return -EINVAL; } - if (channel_cfg->buffered) { + if (channel_cfg->internal && channel_cfg->buffered) { + LOG_ERR("DAC output can not be buffered and internal"); + return -EINVAL; + } else if (channel_cfg->buffered) { /* External and internal output are mutually exclusive */ LOG_WRN("Note: buffering DAC output to pad disconnects internal output"); + use_internal = false; } dac_channel_config.waveType = kDAC_WaveNormal; - dac_channel_config.outMode = channel_cfg->buffered ? - kDAC_ChannelOutputPAD : kDAC_ChannelOutputInternal; + dac_channel_config.outMode = + use_internal ? kDAC_ChannelOutputInternal : kDAC_ChannelOutputPAD; dac_channel_config.timingMode = kDAC_NonTimingCorrelated; dac_channel_config.enableTrigger = false; dac_channel_config.enableDMA = false; diff --git a/drivers/dac/dac_mcux_lpdac.c b/drivers/dac/dac_mcux_lpdac.c index d65624940e762fb..099033740e1bd2f 100644 --- a/drivers/dac/dac_mcux_lpdac.c +++ b/drivers/dac/dac_mcux_lpdac.c @@ -41,6 +41,11 @@ static int mcux_lpdac_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + LOG_ERR("Internal channels not supported"); + return -ENOTSUP; + } + DAC_GetDefaultConfig(&dac_config); dac_config.referenceVoltageSource = config->ref_voltage; #if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL diff --git a/drivers/dac/dac_sam.c b/drivers/dac/dac_sam.c index df8b96f66e9c78f..80fecfa3338e2dc 100644 --- a/drivers/dac/dac_sam.c +++ b/drivers/dac/dac_sam.c @@ -85,6 +85,10 @@ static int dac_sam_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + return -ENOTSUP; + } + /* Enable Channel */ dac->DACC_CHER = DACC_CHER_CH0 << channel_cfg->channel_id; diff --git a/drivers/dac/dac_sam0.c b/drivers/dac/dac_sam0.c index 95f561d4a6abb6b..d831eb44e75b315 100644 --- a/drivers/dac/dac_sam0.c +++ b/drivers/dac/dac_sam0.c @@ -63,6 +63,10 @@ static int dac_sam0_channel_setup(const struct device *dev, return -ENOTSUP; } + if (channel_cfg->internal) { + return -ENOSYS; + } + return 0; } From 3744dd828fb986e703ab3145d2924c9ca1532d43 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 13 Sep 2024 05:59:22 -0400 Subject: [PATCH 147/269] tests: kernel: fix test groups for semaphore/mutex define groups for semaphores and mutexes Signed-off-by: Anas Nashif --- tests/kernel/mutex/mutex_api/src/test_mutex_apis.c | 9 +++++++++ tests/kernel/semaphore/semaphore/src/main.c | 10 +++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/tests/kernel/mutex/mutex_api/src/test_mutex_apis.c b/tests/kernel/mutex/mutex_api/src/test_mutex_apis.c index 2f45e6840016d20..1a5c3211d452f0a 100644 --- a/tests/kernel/mutex/mutex_api/src/test_mutex_apis.c +++ b/tests/kernel/mutex/mutex_api/src/test_mutex_apis.c @@ -26,6 +26,15 @@ static struct k_thread tdata; static struct k_thread tdata2; static struct k_thread tdata3; + + +/** + * @defgroup kernel_mutex_tests Mutexes + * @ingroup all_tests + * @{ + * @} + */ + static void tThread_entry_lock_forever(void *p1, void *p2, void *p3) { zassert_false(k_mutex_lock((struct k_mutex *)p1, K_FOREVER) == 0, diff --git a/tests/kernel/semaphore/semaphore/src/main.c b/tests/kernel/semaphore/semaphore/src/main.c index c1efcb8889c9d23..97816a3a47af794 100644 --- a/tests/kernel/semaphore/semaphore/src/main.c +++ b/tests/kernel/semaphore/semaphore/src/main.c @@ -8,6 +8,14 @@ #include #include + +/** + * @defgroup kernel_semaphore_tests Semaphores + * @ingroup all_tests + * @{ + * @} + */ + /* Macro declarations */ #define SEM_INIT_VAL (0U) #define SEM_MAX_VAL (10U) @@ -271,7 +279,7 @@ ZTEST(semaphore, test_sem_thread2isr) } /** - * @brief Test semaphore initialization at running time + * @brief Test semaphore initialization at runtime * @details * - Initialize a semaphore with valid count and max limit. * - Initialize a semaphore with invalid max limit. From ac808d13dce2d2726cbe4c8b40d591ae7aba92cf Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 13 Sep 2024 06:11:13 -0400 Subject: [PATCH 148/269] doc: kernel: define additional doxygen groups Some groups are used by multiple files/tests, define them globally in doc/ Signed-off-by: Anas Nashif --- doc/_doxygen/groups.dox | 10 ++++++++++ .../kernel/mem_protect/mem_protect/src/mem_partition.c | 2 ++ 2 files changed, 12 insertions(+) diff --git a/doc/_doxygen/groups.dox b/doc/_doxygen/groups.dox index 08e04e2b40143a5..38edbb052b2dcfc 100644 --- a/doc/_doxygen/groups.dox +++ b/doc/_doxygen/groups.dox @@ -79,4 +79,14 @@ @{ @} +@brief Tests +@defgroup all_tests Tests +@{ +@} + +@defgroup kernel_memprotect_tests Memory Protection +@ingroup all_tests +@{ +@} + */ diff --git a/tests/kernel/mem_protect/mem_protect/src/mem_partition.c b/tests/kernel/mem_protect/mem_protect/src/mem_partition.c index 61f2c8a295295be..f6d35e2c25f0af0 100644 --- a/tests/kernel/mem_protect/mem_protect/src/mem_partition.c +++ b/tests/kernel/mem_protect/mem_protect/src/mem_partition.c @@ -7,6 +7,8 @@ #include #include "mem_protect.h" + + /* Add volatile to disable pre-calculation in compile stage in some * toolchain, such as arcmwdt toolchain. */ From ca09a4b91c4a977d743837419f11d7c9d373364e Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 13 Sep 2024 06:41:57 -0400 Subject: [PATCH 149/269] doc: kernel/arch: fix some wrong doxygen references Remove non-existing references and document parameters. Signed-off-by: Anas Nashif --- include/zephyr/arch/arc/v2/arcv2_irq_unit.h | 12 ++++++++---- kernel/sched.c | 2 +- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/zephyr/arch/arc/v2/arcv2_irq_unit.h b/include/zephyr/arch/arc/v2/arcv2_irq_unit.h index 18cb0fa2a47e570..a8f3760a21be515 100644 --- a/include/zephyr/arch/arc/v2/arcv2_irq_unit.h +++ b/include/zephyr/arch/arc/v2/arcv2_irq_unit.h @@ -199,9 +199,11 @@ bool z_arc_v2_irq_unit_is_in_isr(void) /** * @brief Sets an IRQ line to level/pulse trigger * - * Sets the IRQ line to trigger an interrupt based on the level or the - * edge of the signal. Valid values for are _ARC_V2_INT_LEVEL and + * Sets the IRQ line @p irq to trigger an interrupt based on the level or the + * edge of the signal. Valid values for @p trigger are _ARC_V2_INT_LEVEL and * _ARC_V2_INT_PULSE. + * @param irq IRQ line + * @param trigger Trigger state */ static ALWAYS_INLINE void z_arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger) @@ -217,8 +219,10 @@ void z_arc_v2_irq_unit_trigger_set(int irq, unsigned int trigger) /** * @brief Returns an IRQ line trigger type * - * Gets the IRQ line trigger type. - * Valid values for are _ARC_V2_INT_LEVEL and _ARC_V2_INT_PULSE. + * Gets the IRQ line @p irq trigger type. + * Valid values for @retval trigger are _ARC_V2_INT_LEVEL and _ARC_V2_INT_PULSE. + * + * @param irq IRQ line * * @return trigger state */ diff --git a/kernel/sched.c b/kernel/sched.c index 0740d25686b461d..6f57bd9558948bd 100644 --- a/kernel/sched.c +++ b/kernel/sched.c @@ -905,7 +905,7 @@ static inline void set_current(struct k_thread *new_thread) * function. * * @warning - * The @ref _current value may have changed after this call and not refer + * The _current value may have changed after this call and not refer * to the interrupted thread anymore. It might be necessary to make a local * copy before calling this function. * From 53dd8e884b3c3811b3f5aa13cd48f4d135c71e54 Mon Sep 17 00:00:00 2001 From: Yuval Peress Date: Thu, 12 Sep 2024 22:48:30 -0600 Subject: [PATCH 150/269] cpp: Fix warnings Fix warnings caught by running west build. Another fix will have to go in to see why twister was missing these. #78348 Signed-off-by: Yuval Peress --- include/zephyr/drivers/emul.h | 2 +- tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/zephyr/drivers/emul.h b/include/zephyr/drivers/emul.h index be4522c796480bf..c0830bb0205551b 100644 --- a/include/zephyr/drivers/emul.h +++ b/include/zephyr/drivers/emul.h @@ -114,7 +114,7 @@ struct emul { * the bus its on. Intended for use in other internal macros when declaring {bus}_emul * structs in peripheral emulators. */ -#define Z_EMUL_REG_BUS_IDENTIFIER(_dev_node_id) (_CONCAT(_CONCAT(__emulreg_, _dev_node_id), _bus)) +#define Z_EMUL_REG_BUS_IDENTIFIER(_dev_node_id) _CONCAT(_CONCAT(__emulreg_, _dev_node_id), _bus) /* Conditionally places text based on what bus _dev_node_id is on. */ #define Z_EMUL_BUS(_dev_node_id, _i2c, _espi, _spi, _mspi, _uart, _none) \ diff --git a/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp b/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp index 0dc90b36c328aaa..cf6c18de2ccdf4e 100644 --- a/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp +++ b/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp @@ -55,7 +55,7 @@ ZTEST_SUITE(i2c_emul_forwarding, NULL, i2c_emul_forwarding_setup, i2c_emul_forwa ZTEST(i2c_emul_forwarding, test_invalid_address_for_target) { - uint8_t data; + uint8_t data = 0; int rc = i2c_write(targets[0], &data, 1, emulated_target_config[0].address + 1); zassert_equal(-EINVAL, rc, "Expected %d (-EINVAL), but got %d", -EINVAL, rc); zexpect_equal(0, target_read_requested_0_fake.call_count); @@ -69,7 +69,7 @@ ZTEST(i2c_emul_forwarding, test_invalid_address_for_target) ZTEST(i2c_emul_forwarding, test_error_in_stop) { - uint8_t data; + uint8_t data = 0; target_stop_0_fake.return_val = -EINTR; zassert_equal(-EINTR, i2c_write(controller, &data, 1, emulated_target_config[0].address)); From c3942343054470732070c38bae322af3e472c9f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Thu, 29 Aug 2024 13:45:22 +0200 Subject: [PATCH 151/269] ci: doc: build the documentation using GitHub-hosted runners MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There is no reason to use our custom runners for docs build as it's equally fast on GH default runners and allows doc CI to be expedited more quickly even when our build farm is busy. Signed-off-by: Benjamin Cabé --- .github/workflows/doc-build.yml | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml index 34e3557b048265c..1872a8246040052 100644 --- a/.github/workflows/doc-build.yml +++ b/.github/workflows/doc-build.yml @@ -62,20 +62,13 @@ jobs: if: > github.repository_owner == 'zephyrproject-rtos' && ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' ) - runs-on: - group: zephyr-runner-v2-linux-x64-4xlarge + runs-on: ubuntu-22.04 timeout-minutes: 90 concurrency: group: doc-build-html-${{ github.ref }} cancel-in-progress: true steps: - - name: Print cloud service information - run: | - echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" - echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" - echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" - - name: install-pkgs run: | sudo apt-get update @@ -192,8 +185,7 @@ jobs: if: | github.event_name != 'pull_request' && github.repository_owner == 'zephyrproject-rtos' - runs-on: - group: zephyr-runner-v2-linux-x64-4xlarge + runs-on: ubuntu-22.04 container: texlive/texlive:latest timeout-minutes: 120 concurrency: @@ -205,12 +197,6 @@ jobs: run: | git config --global --add safe.directory ${GITHUB_WORKSPACE} - - name: Print cloud service information - run: | - echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}" - echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}" - echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}" - - name: checkout uses: actions/checkout@v4 From f6712c43d4ed5d5f74332904170038b18bcb33dd Mon Sep 17 00:00:00 2001 From: Rubin Gerritsen Date: Wed, 11 Sep 2024 14:06:11 +0200 Subject: [PATCH 152/269] tests: Bluetooth: Add some more tests for bt_le_create_conn() Adds coverage for attempting to connect while already connecting or connecting to a device that already exists. Signed-off-by: Rubin Gerritsen --- tests/bsim/bluetooth/host/central/prj.conf | 1 + .../host/central/src/dummy_peripheral.c | 66 ++++++++ tests/bsim/bluetooth/host/central/src/main.c | 143 ++++++++++++++++-- .../run_central_connect_to_existing.sh | 21 +++ .../run_central_connect_when_connecting.sh | 18 +++ 5 files changed, 238 insertions(+), 11 deletions(-) create mode 100644 tests/bsim/bluetooth/host/central/src/dummy_peripheral.c create mode 100755 tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_to_existing.sh create mode 100755 tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_when_connecting.sh diff --git a/tests/bsim/bluetooth/host/central/prj.conf b/tests/bsim/bluetooth/host/central/prj.conf index 1f446a5bb273aa9..684f25ff94554a2 100644 --- a/tests/bsim/bluetooth/host/central/prj.conf +++ b/tests/bsim/bluetooth/host/central/prj.conf @@ -1,3 +1,4 @@ CONFIG_ASSERT=y CONFIG_BT=y CONFIG_BT_CENTRAL=y +CONFIG_BT_PERIPHERAL=y diff --git a/tests/bsim/bluetooth/host/central/src/dummy_peripheral.c b/tests/bsim/bluetooth/host/central/src/dummy_peripheral.c new file mode 100644 index 000000000000000..e7a85a80e658b99 --- /dev/null +++ b/tests/bsim/bluetooth/host/central/src/dummy_peripheral.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "bstests.h" +#include "babblekit/testcase.h" +#include + +static K_SEM_DEFINE(sem_connected, 0, 1); + +static void connected_cb(struct bt_conn *conn, uint8_t err) +{ + TEST_ASSERT(conn); + TEST_ASSERT(err == 0, "Expected success"); + + k_sem_give(&sem_connected); + bt_conn_unref(conn); +} + +static struct bt_conn_cb conn_cb = { + .connected = connected_cb, +}; + +static void test_peripheral_dummy(void) +{ + int err; + const struct bt_data ad[] = { + BT_DATA_BYTES(BT_DATA_FLAGS, (BT_LE_AD_GENERAL | BT_LE_AD_NO_BREDR))}; + + bt_conn_cb_register(&conn_cb); + + bt_addr_le_t addr = {.type = BT_ADDR_LE_RANDOM, + .a.val = {0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0}}; + + err = bt_id_create(&addr, NULL); + TEST_ASSERT(err == 0, "Failed to create iD (err %d)", err); + + /* Initialize Bluetooth */ + err = bt_enable(NULL); + TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err); + + err = bt_le_adv_start(BT_LE_ADV_CONN_ONE_TIME, ad, ARRAY_SIZE(ad), NULL, 0); + TEST_ASSERT(err == 0, "Advertising failed to start (err %d)", err); + + err = k_sem_take(&sem_connected, K_FOREVER); + TEST_ASSERT(err == 0, "Failed getting connected timeout", err); + + TEST_PASS("Passed"); +} + +static const struct bst_test_instance test_def[] = { + { + .test_id = "peripheral_dummy", + .test_descr = "Connectable peripheral", + .test_tick_f = bst_tick, + .test_main_f = test_peripheral_dummy, + }, + BSTEST_END_MARKER, +}; + +struct bst_test_list *test_peripheral_install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, test_def); +} diff --git a/tests/bsim/bluetooth/host/central/src/main.c b/tests/bsim/bluetooth/host/central/src/main.c index 2e66f4179828bac..2068ecefc8d8ff2 100644 --- a/tests/bsim/bluetooth/host/central/src/main.c +++ b/tests/bsim/bluetooth/host/central/src/main.c @@ -8,17 +8,36 @@ #include "babblekit/testcase.h" #include +/* Include conn_internal for the purpose of checking reference counts. */ +#include "host/conn_internal.h" + +struct bst_test_list *test_peripheral_install(struct bst_test_list *tests); + +static K_SEM_DEFINE(sem_failed_to_connect, 0, 1); static K_SEM_DEFINE(sem_connected, 0, 1); -static void connected_cb(struct bt_conn *conn, uint8_t err) +static void connected_cb_expect_fail(struct bt_conn *conn, uint8_t err) { TEST_ASSERT(conn); TEST_ASSERT(err == BT_HCI_ERR_UNKNOWN_CONN_ID, "Expected connection timeout"); + k_sem_give(&sem_failed_to_connect); + bt_conn_unref(conn); +} + +static void connected_cb(struct bt_conn *conn, uint8_t err) +{ + TEST_ASSERT(conn); + TEST_ASSERT(err == BT_HCI_ERR_SUCCESS, "Expected connection establishment"); + k_sem_give(&sem_connected); bt_conn_unref(conn); } +static struct bt_conn_cb conn_cb_expect_fail = { + .connected = connected_cb_expect_fail, +}; + static struct bt_conn_cb conn_cb = { .connected = connected_cb, }; @@ -44,14 +63,14 @@ static void test_central_connect_timeout_with_timeout(uint32_t timeout_ms) .timeout = timeout_ms / 10, }; - k_sem_reset(&sem_connected); + k_sem_reset(&sem_failed_to_connect); const uint64_t conn_create_start = k_uptime_get(); err = bt_conn_le_create(&peer, &create_param, BT_LE_CONN_PARAM_DEFAULT, &conn); TEST_ASSERT(err == 0, "Failed starting initiator (err %d)", err); - err = k_sem_take(&sem_connected, K_MSEC(2 * expected_conn_timeout_ms)); + err = k_sem_take(&sem_failed_to_connect, K_MSEC(2 * expected_conn_timeout_ms)); TEST_ASSERT(err == 0, "Failed getting connected timeout within %d s (err %d)", 2 * expected_conn_timeout_ms, err); @@ -63,14 +82,15 @@ static void test_central_connect_timeout_with_timeout(uint32_t timeout_ms) TEST_PRINT("Connection timeout after %d ms", time_diff_ms); TEST_ASSERT(diff_to_expected_ms < 0.1 * expected_conn_timeout_ms, "Connection timeout not within 10%% of expected timeout. " - "Actual timeout: %d", time_diff_ms); + "Actual timeout: %d", + time_diff_ms); } static void test_central_connect_timeout(void) { int err; - bt_conn_cb_register(&conn_cb); + bt_conn_cb_register(&conn_cb_expect_fail); /* Initialize Bluetooth */ err = bt_enable(NULL); @@ -82,14 +102,118 @@ static void test_central_connect_timeout(void) TEST_PASS("Correct timeout"); } +static void test_central_connect_when_connecting(void) +{ + int err; + + bt_conn_cb_register(&conn_cb_expect_fail); + + /* Initialize Bluetooth */ + err = bt_enable(NULL); + TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err); + + struct bt_conn *conn; + + bt_addr_le_t peer = {.a.val = {0x01}}; + + const struct bt_conn_le_create_param create_param = { + .options = BT_CONN_LE_OPT_NONE, + .interval = BT_GAP_SCAN_FAST_INTERVAL, + .window = BT_GAP_SCAN_FAST_WINDOW, + }; + + k_sem_reset(&sem_failed_to_connect); + + err = bt_conn_le_create(&peer, &create_param, BT_LE_CONN_PARAM_DEFAULT, &conn); + TEST_ASSERT(err == 0, "Failed starting initiator (err %d)", err); + + /* Now we have a valid connection reference */ + atomic_val_t initial_refs = atomic_get(&conn->ref); + + TEST_ASSERT(initial_refs >= 1, "Expect to have at least once reference"); + + err = bt_conn_le_create(&peer, &create_param, BT_LE_CONN_PARAM_DEFAULT, &conn); + TEST_ASSERT(err == -EALREADY, "Expected to fail to create connection (err %d)", err); + + /* Expect the number of refs to be unchanged. */ + TEST_ASSERT(atomic_get(&conn->ref) == initial_refs, + "Expect number of references to be unchanged"); + + err = k_sem_take(&sem_failed_to_connect, K_FOREVER); + TEST_ASSERT(err == 0, "Failed getting connected timeout", err); + + TEST_ASSERT(atomic_get(&conn->ref) == 0, "Expect no more references"); + + TEST_PASS("Passed"); +} + +static void test_central_connect_to_existing(void) +{ + int err; + + bt_conn_cb_register(&conn_cb); + + /* Initialize Bluetooth */ + err = bt_enable(NULL); + TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err); + + struct bt_conn *conn; + + bt_addr_le_t peer = {.type = BT_ADDR_LE_RANDOM, + .a.val = {0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0}}; + + const struct bt_conn_le_create_param create_param = { + .options = BT_CONN_LE_OPT_NONE, + .interval = BT_GAP_SCAN_FAST_INTERVAL, + .window = BT_GAP_SCAN_FAST_WINDOW, + }; + + k_sem_reset(&sem_connected); + + err = bt_conn_le_create(&peer, &create_param, BT_LE_CONN_PARAM_DEFAULT, &conn); + TEST_ASSERT(err == 0, "Failed starting initiator (err %d)", err); + + err = k_sem_take(&sem_connected, K_FOREVER); + TEST_ASSERT(err == 0, "Failed establishing connection", err); + + /* Now we have a valid connection reference */ + atomic_val_t initial_refs = atomic_get(&conn->ref); + + TEST_ASSERT(initial_refs >= 1, "Expect to have at least once reference"); + + err = bt_conn_le_create(&peer, &create_param, BT_LE_CONN_PARAM_DEFAULT, &conn); + TEST_ASSERT(err == -EINVAL, "Expected to fail to create a connection (err %d)", err); + + /* Expect the number of refs to be unchanged. */ + TEST_ASSERT(atomic_get(&conn->ref) == initial_refs, + "Expect number of references to be unchanged"); + + TEST_PASS("Passed"); +} + static const struct bst_test_instance test_def[] = { { .test_id = "central_connect_timeout", .test_descr = "Verifies that the default connection timeout is used correctly", .test_tick_f = bst_tick, - .test_main_f = test_central_connect_timeout + .test_main_f = test_central_connect_timeout, + }, + { + .test_id = "central_connect_when_connecting", + .test_descr = "Verifies that the stack returns an error code when trying to connect" + " while already connecting", + .test_tick_f = bst_tick, + .test_main_f = test_central_connect_when_connecting, }, - BSTEST_END_MARKER + { + .test_id = "central_connect_to_existing", + .test_descr = + "Verifies that the stack returns an error code when trying to connect" + " to an existing device and does not unref the existing connection object.", + .test_tick_f = bst_tick, + .test_main_f = test_central_connect_to_existing, + }, + BSTEST_END_MARKER, }; static struct bst_test_list *test_central_install(struct bst_test_list *tests) @@ -97,10 +221,7 @@ static struct bst_test_list *test_central_install(struct bst_test_list *tests) return bst_add_tests(tests, test_def); } -bst_test_install_t test_installers[] = { - test_central_install, - NULL -}; +bst_test_install_t test_installers[] = {test_central_install, test_peripheral_install, NULL}; int main(void) { diff --git a/tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_to_existing.sh b/tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_to_existing.sh new file mode 100755 index 000000000000000..af64f6a14ad10d9 --- /dev/null +++ b/tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_to_existing.sh @@ -0,0 +1,21 @@ +#!/usr/bin/env bash +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +simulation_id="central_connect_timeout_to_existing" +verbosity_level=2 + +cd ${BSIM_OUT_PATH}/bin + +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_central_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central_connect_to_existing + +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_central_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral_dummy + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ + -D=2 -sim_length=60e6 $@ + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_when_connecting.sh b/tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_when_connecting.sh new file mode 100755 index 000000000000000..5d352adc0fe167f --- /dev/null +++ b/tests/bsim/bluetooth/host/central/tests_scripts/run_central_connect_when_connecting.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +simulation_id="central_connect_when_connecting" +verbosity_level=2 + +cd ${BSIM_OUT_PATH}/bin + +Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_central_prj_conf \ + -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central_connect_when_connecting + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \ + -D=1 -sim_length=60e6 $@ + +wait_for_background_jobs From de53fb471a3b84af3b72324c783cdfa4d70e7692 Mon Sep 17 00:00:00 2001 From: Marcio Ribeiro Date: Fri, 13 Sep 2024 10:29:26 -0300 Subject: [PATCH 153/269] drivers: i2s: esp32: remove unused code Removed unused code in I2S driver. Signed-off-by: Marcio Ribeiro --- drivers/i2s/i2s_esp32.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/i2s/i2s_esp32.c b/drivers/i2s/i2s_esp32.c index c97316392d1154a..6de53e56f52e674 100644 --- a/drivers/i2s/i2s_esp32.c +++ b/drivers/i2s/i2s_esp32.c @@ -323,7 +323,6 @@ static void i2s_esp32_rx_callback(const struct device *dma_dev, void *arg, uint3 int status) { const struct device *dev = (const struct device *)arg; - const struct i2s_esp32_cfg *dev_cfg = dev->config; struct i2s_esp32_data *const dev_data = dev->data; struct i2s_esp32_stream *stream = &dev_data->rx; int err; @@ -381,7 +380,6 @@ static void i2s_esp32_tx_callback(const struct device *dma_dev, void *arg, uint3 int status) { const struct device *dev = (const struct device *)arg; - const struct i2s_esp32_cfg *dev_cfg = dev->config; struct i2s_esp32_data *const dev_data = dev->data; struct i2s_esp32_stream *stream = &dev_data->tx; struct queue_item item; From bdd894ca5084118569557808c5fb1634643c38c1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonny=20Sv=C3=A4rd?= Date: Mon, 16 Sep 2024 16:41:13 +0200 Subject: [PATCH 154/269] modules: tflite-micro: Fix CMakeLists.txt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing file to source list Signed-off-by: Jonny Svärd --- modules/tflite-micro/CMakeLists.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/modules/tflite-micro/CMakeLists.txt b/modules/tflite-micro/CMakeLists.txt index 50a393557745389..327038d84ae3821 100644 --- a/modules/tflite-micro/CMakeLists.txt +++ b/modules/tflite-micro/CMakeLists.txt @@ -1,5 +1,5 @@ # Copyright (c) 2021 Intel Corporation -# Copyright 2022 Arm Limited and/or its affiliates +# Copyright 2022, 2024 Arm Limited and/or its affiliates # SPDX-License-Identifier: Apache-2.0 if(CONFIG_TENSORFLOW_LITE_MICRO) @@ -175,6 +175,7 @@ if(CONFIG_TENSORFLOW_LITE_MICRO) ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/squared_difference.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/squeeze.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/strided_slice.cc + ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/strided_slice_common.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/sub.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/sub_common.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/${CMSIS_NN_OPTIMIZED_KERNEL_DIR}/svdf.cc From 6194159608f6bc248612f2b2ca412f7756013a8a Mon Sep 17 00:00:00 2001 From: Wilfried Chauveau Date: Mon, 3 Jun 2024 08:36:36 +0100 Subject: [PATCH 155/269] scripts: twister: handlers: Enable BinaryHandler to run sysbuilt tests Running sysbuilt tests fails because of missing "run" target. This adds the default domain context to the command. Signed-off-by: Wilfried Chauveau --- scripts/pylib/twister/twisterlib/handlers.py | 2 +- scripts/tests/twister/test_handlers.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py index 90b834cd4025654..0ebab95434bf6a9 100755 --- a/scripts/pylib/twister/twisterlib/handlers.py +++ b/scripts/pylib/twister/twisterlib/handlers.py @@ -263,7 +263,7 @@ def _create_command(self, robot_test): "--variable", "RESC:@" + resc, "--variable", "UART:" + uart] elif self.call_make_run: - command = [self.generator_cmd, "run"] + command = [self.generator_cmd, "-C", self.get_default_domain_build_dir(), "run"] elif self.instance.testsuite.type == "unit": command = [self.binary] else: diff --git a/scripts/tests/twister/test_handlers.py b/scripts/tests/twister/test_handlers.py index 9c6a2f5b130b654..3475c65197e3488 100644 --- a/scripts/tests/twister/test_handlers.py +++ b/scripts/tests/twister/test_handlers.py @@ -419,7 +419,7 @@ def wait(self, *args, **kwargs): f'--suppressions={ZEPHYR_BASE}/scripts/valgrind.supp', '--log-file=build_dir/valgrind.log', '--track-origins=yes', 'generator']), - (False, True, False, 123, None, ['generator', 'run', '--seed=123']), + (False, True, False, 123, None, ['generator', '-C', 'build_dir', 'run', '--seed=123']), (False, False, False, None, ['ex1', 'ex2'], ['build_dir/zephyr/zephyr.exe', 'ex1', 'ex2']), ] From 643db3fa0b9e135b5fb2134705cb54b65a1ca7f0 Mon Sep 17 00:00:00 2001 From: Chekhov Ma Date: Thu, 9 May 2024 16:20:51 +0800 Subject: [PATCH 156/269] soc: imx93: enable flexcan driver - Add flexcan dts node and pinctrl. Signed-off-by: Chekhov Ma --- dts/arm64/nxp/nxp_mimx93_a55.dtsi | 24 ++++++++++++++++++++++++ soc/nxp/imx/imx9/imx93/a55/mmu_regions.c | 3 +++ 2 files changed, 27 insertions(+) diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi index 89018a8de238db1..abc12cffee6881d 100644 --- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi @@ -327,6 +327,30 @@ #size-cells = <0>; }; + flexcan1: can@443a0000 { + compatible = "nxp,flexcan-fd", "nxp,flexcan"; + reg = <0x443a0000 DT_SIZE_K(64)>; + interrupt-parent= <&gic>; + interrupts = , + ; + interrupt-names = "common", "error"; + clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; + clk-source = <0>; + status = "disabled"; + }; + + flexcan2: can@425b0000 { + compatible = "nxp,flexcan-fd", "nxp,flexcan"; + reg = <0x425b0000 DT_SIZE_K(64)>; + interrupt-parent= <&gic>; + interrupts = , + ; + interrupt-names = "common", "error"; + clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; + clk-source = <0>; + status = "disabled"; + }; + edma4: dma@42000000 { compatible = "nxp,edma"; reg = <0x42000000 (DT_SIZE_K(64) * 32)>; diff --git a/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c b/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c index 17aac7ee9eddb10..1052a55a5dce771 100644 --- a/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c +++ b/soc/nxp/imx/imx9/imx93/a55/mmu_regions.c @@ -32,6 +32,9 @@ static const struct arm_mmu_region mmu_regions[] = { MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_kinetis_lpuart, (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS)) + MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_flexcan, + (MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS)) + #if CONFIG_SOF MMU_REGION_FLAT_ENTRY("MU2_A", DT_REG_ADDR(DT_NODELABEL(mu2_a)), DT_REG_SIZE(DT_NODELABEL(mu2_a)), From 19949a0ccf06fef827ff281e547dbc4c4d4ab9ac Mon Sep 17 00:00:00 2001 From: Chekhov Ma Date: Fri, 24 May 2024 13:56:16 +0800 Subject: [PATCH 157/269] boards: imx93_evk: enable flexcan driver Add pinctrl for flexcan2 Add EXP_SEL gpio hog for board mux selection during boot. Add TJA1057 CAN PHY driver. Update supported features in board document Signed-off-by: Chekhov Ma --- boards/nxp/imx93_evk/Kconfig.defconfig | 12 +++++++++++ boards/nxp/imx93_evk/doc/index.rst | 6 ++++++ boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi | 9 +++++++++ .../nxp/imx93_evk/imx93_evk_mimx9352_a55.dts | 20 +++++++++++++++++++ .../nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml | 1 + 5 files changed, 48 insertions(+) diff --git a/boards/nxp/imx93_evk/Kconfig.defconfig b/boards/nxp/imx93_evk/Kconfig.defconfig index a2aeac0941fedc2..06b3e06736d55a2 100644 --- a/boards/nxp/imx93_evk/Kconfig.defconfig +++ b/boards/nxp/imx93_evk/Kconfig.defconfig @@ -5,6 +5,18 @@ if BOARD_IMX93_EVK if BOARD_IMX93_EVK_MIMX9352_A55 +if CAN + +# Enable board mux configure during init +config BOARD_MIMX93_EVK_EXP_SEL_INIT + default y + +# CAN Phy must be initialized after board mux +config CAN_TRANSCEIVER_INIT_PRIORITY + default 65 + +endif # CAN + if BOARD_MIMX93_EVK_EXP_SEL_INIT # Enable I2C, MFD, MFD_APD5585 and GPIO_ADP5585 diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst index 6b3c428eb32f199..c37ad2eea1e41cf 100644 --- a/boards/nxp/imx93_evk/doc/index.rst +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -66,6 +66,12 @@ hardware features: +-----------+------------+-------------------------------------+ | GPIO | on-chip | GPIO | +-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ | TPM | on-chip | TPM Counter | +-----------+------------+-------------------------------------+ | ENET | on-chip | ethernet port | diff --git a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi index 5399bf596fef287..8976def98b4b6a2 100644 --- a/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi +++ b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi @@ -83,6 +83,15 @@ }; }; + flexcan2_default: flexcan2_default { + group0 { + pinmux = <&iomuxc1_gpio_io25_can_tx_can2_tx>, + <&iomuxc1_gpio_io27_can_rx_can2_rx>; + slew-rate = "slightly_fast"; + drive-strength = "x5"; + }; + }; + pinmux_mdio: pinmux_mdio { group0 { pinmux = <&iomuxc1_enet2_mdc_enet_mdc_enet1_mdc>, diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts index 4703e734935ea5f..3a04d2003ee9a4c 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -17,6 +17,7 @@ zephyr,console = &lpuart2; zephyr,shell-uart = &lpuart2; zephyr,sram = &sram0; + zephyr,canbus = &flexcan2; }; cpus { @@ -66,10 +67,22 @@ }; board_exp_sel: board-exp-sel { + /* + * Kconfig BOARD_MIMX93_EVK_A55_EXP_SEL_INIT must be + * enabled to configure it during init. + */ compatible = "imx93evk-exp-sel"; mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>; mux = "A"; }; + + can_phy0: can-phy0 { + compatible = "nxp,tja1057", "can-transceiver-gpio"; + standby-gpios = <&gpio_exp0 8 GPIO_ACTIVE_HIGH>; + max-bitrate = <8000000>; + #phy-cells = <0>; + status = "okay"; + }; }; &enet { @@ -179,3 +192,10 @@ &gpio4{ status = "okay"; }; + +&flexcan2 { + pinctrl-0 = <&flexcan2_default>; + pinctrl-names = "default"; + phys = <&can_phy0>; + status = "okay"; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml index 067f9d6143ebae3..89cc546d7b3a039 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml @@ -17,6 +17,7 @@ supported: - uart - i2c - spi + - can testing: ignore_tags: - net From eab0e37e686c25ade2d3b5da915ddc2c4436b80c Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Fri, 30 Aug 2024 13:56:51 +0200 Subject: [PATCH 158/269] dts: arm: st: add digi-temp node in dtsi file add digital temperature node in board.dtsi file Signed-off-by: Fabrice DJIATSA --- dts/arm/st/h5/stm32h5.dtsi | 9 +++++++++ dts/arm/st/wba/stm32wba.dtsi | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index 2a086d3ff256fc7..32f39caf8fe19c7 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -613,6 +613,15 @@ <&rcc STM32_SRC_HSI48 USB_SEL(3)>; status = "disabled"; }; + + digi_die_temp: digi_dietemp@40008c00 { + compatible = "st,stm32-digi-temp"; + reg = <0x40008c00 0x400>; + interrupts = <113 0>; + interrupt-names = "digi_temp"; + clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000008>; + status = "disabled"; + }; }; die_temp: dietemp { diff --git a/dts/arm/st/wba/stm32wba.dtsi b/dts/arm/st/wba/stm32wba.dtsi index 5b402ae9501c577..bd9a601dcd72423 100644 --- a/dts/arm/st/wba/stm32wba.dtsi +++ b/dts/arm/st/wba/stm32wba.dtsi @@ -473,6 +473,17 @@ }; }; + die_temp: dietemp { + compatible = "st,stm32-temp-cal"; + ts-cal1-addr = <0x0BF90710>; + ts-cal2-addr = <0x0BF90742>; + ts-cal1-temp = <30>; + ts-cal2-temp = <130>; + ts-cal-vrefanalog = <3000>; + io-channels = <&adc4 13>; + status = "disabled"; + }; + bt_hci_wba: bt_hci_wba { compatible = "st,hci-stm32wba"; status = "okay"; From 0df9e2536b449548fb71a07d719cb0c96e4fa29a Mon Sep 17 00:00:00 2001 From: Fabrice DJIATSA Date: Thu, 29 Aug 2024 17:51:04 +0200 Subject: [PATCH 159/269] boards: st: add die_temp or digi node update die_temp node for some stm32 boards, need that for run sensor die_temp_polling samples. don't need to modify sample.yaml Signed-off-by: Fabrice DJIATSA --- boards/st/b_u585i_iot02a/b_u585i_iot02a.dts | 10 ++++++++++ boards/st/disco_l475_iot1/disco_l475_iot1.dts | 1 + boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts | 5 +++++ boards/st/nucleo_wb55rg/nucleo_wb55rg.dts | 2 +- boards/st/nucleo_wba55cg/nucleo_wba55cg.dts | 7 ++++++- boards/st/nucleo_wl55jc/nucleo_wl55jc.dts | 2 +- boards/st/stm32h573i_dk/stm32h573i_dk.dts | 5 +++++ boards/st/stm32h750b_dk/stm32h750b_dk.dts | 11 +++++++++++ 8 files changed, 40 insertions(+), 3 deletions(-) diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts index b452f4b3eba3946..0ac55be54ce175b 100644 --- a/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts @@ -26,6 +26,7 @@ led0 = &green_led_1; led1 = &red_led_1; sw0 = &user_button; + die-temp0 = &die_temp; }; octo_nor: memory@70000000 { @@ -87,3 +88,12 @@ status = "okay"; }; }; + +&die_temp { + status = "okay"; +}; + +&adc1 { + st,adc-prescaler = <4>; + status = "okay"; +}; diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1.dts b/boards/st/disco_l475_iot1/disco_l475_iot1.dts index af05f61c0d7f89a..fbea236337d4e04 100644 --- a/boards/st/disco_l475_iot1/disco_l475_iot1.dts +++ b/boards/st/disco_l475_iot1/disco_l475_iot1.dts @@ -75,6 +75,7 @@ accel0 = &lsm6dsl; volt-sensor0 = &vref; volt-sensor1 = &vbat; + die-temp0 = &die_temp; }; }; diff --git a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts index 8197b69868ec87c..9fc2e2d2a864dd6 100644 --- a/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts +++ b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts @@ -30,6 +30,7 @@ watchdog0 = &iwdg; volt-sensor0 = &vref1; volt-sensor1 = &vbat4; + die-temp0 = &die_temp; }; }; @@ -43,3 +44,7 @@ &gpdma1 { status = "okay"; }; + +&die_temp { + status = "okay"; +}; diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts index 4eb19294f0f8183..f1a0d055aa87f58 100644 --- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts @@ -179,7 +179,7 @@ }; &adc1 { - pinctrl-0 = <&adc1_in3_pc2>; + pinctrl-0 = <&adc1_in3_pc2 &adc1_in5_pa0>; pinctrl-names = "default"; st,adc-clock-source = ; st,adc-prescaler = <4>; diff --git a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts index c35ce85189103ed..d6e1c1f7a5d2e59 100644 --- a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts @@ -71,6 +71,7 @@ sw2 = &user_button_3; mcuboot-led0 = &blue_led_1; mcuboot-button0 = &user_button_1; + die-temp0 = &die_temp; }; }; @@ -144,13 +145,17 @@ }; &adc4 { - pinctrl-0 = <&adc4_in8_pa1>; + pinctrl-0 = <&adc4_in8_pa1 &adc4_in9_pa0>; pinctrl-names = "default"; st,adc-clock-source = ; st,adc-prescaler = <4>; status = "okay"; }; +&die_temp { + status = "okay"; +}; + stm32_lp_tick_source: &lptim1 { clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000800>, <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>; diff --git a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts index 6e37b1c148533a4..98fcc7057aef37a 100644 --- a/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts +++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts @@ -147,7 +147,7 @@ stm32_lp_tick_source: &lptim1 { &adc1 { - pinctrl-0 = <&adc_in5_pb1>; + pinctrl-0 = <&adc_in5_pb1 &adc_in0_pb13>; pinctrl-names = "default"; st,adc-clock-source = ; st,adc-prescaler = <4>; diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts index 82e4960973ca5e8..c64ff945106f230 100644 --- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts +++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts @@ -58,6 +58,7 @@ sw0 = &user_button; watchdog0 = &iwdg; die-temp0 = &die_temp; + die-temp1 = &digi_die_temp; volt-sensor0 = &vref; volt-sensor1 = &vbat; }; @@ -311,6 +312,10 @@ zephyr_udc0: &usb { status = "okay"; }; +&digi_die_temp { + status = "okay"; +}; + &vref { status = "okay"; }; diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.dts b/boards/st/stm32h750b_dk/stm32h750b_dk.dts index 6a0654a885b725a..14a6fe1fef1c3d1 100644 --- a/boards/st/stm32h750b_dk/stm32h750b_dk.dts +++ b/boards/st/stm32h750b_dk/stm32h750b_dk.dts @@ -64,6 +64,7 @@ led0 = &green_led; led1 = &red_led; sw0 = &user_button; + die-temp0 = &die_temp; }; }; @@ -232,3 +233,13 @@ <&rcc STM32_SRC_LSE RTC_SEL(1)>; status = "okay"; }; + +&die_temp { + status = "okay"; +}; + +&adc3 { + st,adc-clock-source = ; + st,adc-prescaler = <4>; + status = "okay"; +}; From adb83d26bf2705c7512bcd36704bbf0a5cd5bb32 Mon Sep 17 00:00:00 2001 From: Vit Stanicek Date: Mon, 9 Sep 2024 09:06:08 +0200 Subject: [PATCH 160/269] soc: mimxrt685s/cm33: Fix lockup on clock config Imply CONFIG_INIT_AUDIO_PLL on nxp,dmic driver selection on mimxrt685s/cm33. Make DMIC clock config dependent on the use of the RT685's audio PLL. Fixes a regression described in #77851. Signed-off-by: Vit Stanicek --- soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig | 3 +++ soc/nxp/imxrt/imxrt6xx/cm33/soc.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig index bfcc7d29f546221..4a961be41cf2328 100644 --- a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig @@ -55,6 +55,9 @@ endif # MBEDTLS config I2S_MCUX_FLEXCOMM select INIT_AUDIO_PLL +config AUDIO_DMIC_MCUX + select INIT_AUDIO_PLL + if MCUX_OS_TIMER config SYS_CLOCK_HW_CYCLES_PER_SEC diff --git a/soc/nxp/imxrt/imxrt6xx/cm33/soc.c b/soc/nxp/imxrt/imxrt6xx/cm33/soc.c index 3bbf672c372cd25..d829558754e67ef 100644 --- a/soc/nxp/imxrt/imxrt6xx/cm33/soc.c +++ b/soc/nxp/imxrt/imxrt6xx/cm33/soc.c @@ -317,7 +317,7 @@ static ALWAYS_INLINE void clock_init(void) CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider)); #endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) && CONFIG_INIT_AUDIO_PLL /* Using the Audio PLL as input clock leads to better clock dividers * for typical PCM sample rates ({8,16,24,32,48,96} kHz. */ From 87a18400dd6cff0bc76cdfeb2776739a203afefa Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Wed, 11 Sep 2024 13:23:43 +0100 Subject: [PATCH 161/269] mgmt: mcumgr: grp: os_mgmt: Add optional bootloader info hook Adds an optional hook that allows for appending additional responses to the bootloader info command Signed-off-by: Jamie McCrae --- .../mcumgr/grp/os_mgmt/os_mgmt_callbacks.h | 18 +++++++++++++ include/zephyr/mgmt/mcumgr/mgmt/callbacks.h | 10 +++++-- subsys/mgmt/mcumgr/grp/os_mgmt/Kconfig | 7 +++++ subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c | 26 +++++++++++++++++++ 4 files changed, 59 insertions(+), 2 deletions(-) diff --git a/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h b/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h index 07ff703957c12f8..56044c603a67b7a 100644 --- a/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h +++ b/include/zephyr/mgmt/mcumgr/grp/os_mgmt/os_mgmt_callbacks.h @@ -28,6 +28,24 @@ struct os_mgmt_reset_data { bool force; }; +/** + * Structure provided in the #MGMT_EVT_OP_OS_MGMT_BOOTLOADER_INFO notification callback: This + * callback function is used to add new fields to the bootloader info response. + */ +struct os_mgmt_bootloader_info_data { + /** + * The zcbor encoder which is currently being used to output group information, additional + * fields to the group can be added using this. + */ + zcbor_state_t *zse; + + /** Contains the number of decoded parameters. */ + const size_t *decoded; + + /** Contains the value of the query parameter. */ + struct zcbor_string *query; +}; + /** * @} */ diff --git a/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h b/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h index 61542e42f2963fa..c32dc6a544de312 100644 --- a/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h +++ b/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h @@ -206,10 +206,16 @@ enum os_mgmt_group_events { MGMT_EVT_OP_OS_MGMT_INFO_APPEND = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 2), /** Callback when a datetime get command has been received. */ - MGMT_EVT_OP_OS_MGMT_DATETIME_GET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 3), + MGMT_EVT_OP_OS_MGMT_DATETIME_GET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 3), /** Callback when a datetime set command has been received, data is struct rtc_time(). */ - MGMT_EVT_OP_OS_MGMT_DATETIME_SET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 4), + MGMT_EVT_OP_OS_MGMT_DATETIME_SET = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 4), + + /** + * Callback when a bootloader info command has been received, data is + * os_mgmt_bootloader_info_data. + */ + MGMT_EVT_OP_OS_MGMT_BOOTLOADER_INFO = MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 5), /** Used to enable all os_mgmt_group events. */ MGMT_EVT_OP_OS_MGMT_ALL = MGMT_DEF_EVT_OP_ALL(MGMT_EVT_GRP_OS), diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/Kconfig b/subsys/mgmt/mcumgr/grp/os_mgmt/Kconfig index 62245760a4757a0..bb2ae92053c59e5 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/Kconfig +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/Kconfig @@ -202,6 +202,13 @@ config MCUMGR_GRP_OS_BOOTLOADER_INFO Allows to query MCUmgr about bootloader used by device and various bootloader parameters. +config MCUMGR_GRP_OS_BOOTLOADER_INFO_HOOK + bool "Bootloader info hooks" + depends on MCUMGR_MGMT_NOTIFICATION_HOOKS + help + Supports adding custom responses to the bootloader info command by using registered + callbacks. Data can be appended to the struct provided in the callback. + endif # BOOTLOADER_MCUBOOT module = MCUMGR_GRP_OS diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c index 935f3e1552a5066..15342fcb93680c4 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c @@ -450,6 +450,17 @@ os_mgmt_bootloader_info(struct smp_streamer *ctxt) size_t decoded; bool ok; +#if defined(CONFIG_MCUMGR_GRP_OS_BOOTLOADER_INFO_HOOK) + enum mgmt_cb_return status; + int32_t err_rc; + uint16_t err_group; + struct os_mgmt_bootloader_info_data bootloader_info_data = { + .zse = zse, + .decoded = &decoded, + .query = &query + }; +#endif + struct zcbor_map_decode_key_val bootloader_info[] = { ZCBOR_MAP_DECODE_KEY_DECODER("query", zcbor_tstr_decode, &query), }; @@ -458,6 +469,21 @@ os_mgmt_bootloader_info(struct smp_streamer *ctxt) return MGMT_ERR_EINVAL; } +#if defined(CONFIG_MCUMGR_GRP_OS_BOOTLOADER_INFO_HOOK) + status = mgmt_callback_notify(MGMT_EVT_OP_OS_MGMT_BOOTLOADER_INFO, &bootloader_info_data, + sizeof(bootloader_info_data), &err_rc, &err_group); + + if (status != MGMT_CB_OK) { + if (status == MGMT_CB_ERROR_RC) { + return err_rc; + } + + ok = smp_add_cmd_err(zse, err_group, (uint16_t)err_rc); + + return ok ? MGMT_ERR_EOK : MGMT_ERR_EMSGSIZE; + } +#endif + /* If no parameter is recognized then just introduce the bootloader. */ if (decoded == 0) { ok = zcbor_tstr_put_lit(zse, "bootloader") && From c41d88740a45cd52a81f6227d91447336e0b27e5 Mon Sep 17 00:00:00 2001 From: Jamie McCrae Date: Wed, 11 Sep 2024 13:25:58 +0100 Subject: [PATCH 162/269] doc: release: 4.0: Add note on new MCUmgr bootloader info hook Adds a note on this newly added hook Signed-off-by: Jamie McCrae --- doc/releases/release-notes-4.0.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index 574b52915323ff1..64a2eb92a2c5098 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -317,6 +317,9 @@ Libraries / Subsystems supported groups. * Fixed formatting of milliseconds in :c:enum:`OS_MGMT_ID_DATETIME_STR` by adding leading zeros. + * Added support for custom os mgmt bootloader info responses using notification hooks, this + can be enabled witbh :kconfig:option`CONFIG_MCUMGR_GRP_OS_BOOTLOADER_INFO_HOOK`, the data + structure is :c:struct:`os_mgmt_bootloader_info_data`. * Logging From e20ef4443eba176dcb281dd1e69eda74fb7146ab Mon Sep 17 00:00:00 2001 From: Simon Walz Date: Mon, 16 Sep 2024 14:53:19 +0200 Subject: [PATCH 163/269] net: lwm2m: check lwm2m path level while getting the block ctx The Block1 context for composite operations is not found, as all path levels are compared. The incoming path level should therefore always be taken into account. Signed-off-by: Simon Walz --- subsys/net/lib/lwm2m/lwm2m_message_handling.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/subsys/net/lib/lwm2m/lwm2m_message_handling.c b/subsys/net/lib/lwm2m/lwm2m_message_handling.c index 77a007ffcee7fa7..1b136fd8fdcd7ee 100644 --- a/subsys/net/lib/lwm2m/lwm2m_message_handling.c +++ b/subsys/net/lib/lwm2m/lwm2m_message_handling.c @@ -175,8 +175,7 @@ static int get_block_ctx(const struct lwm2m_obj_path *path, struct lwm2m_block_c *ctx = NULL; for (i = 0; i < NUM_BLOCK1_CONTEXT; i++) { - if (memcmp(path, &block1_contexts[i].path, - sizeof(struct lwm2m_obj_path)) == 0) { + if (lwm2m_obj_path_equal(path, &block1_contexts[i].path)) { *ctx = &block1_contexts[i]; /* refresh timestamp */ (*ctx)->timestamp = k_uptime_get(); From 5af3fbadfdd05af356a8fa5ec9127b5a8ff508c1 Mon Sep 17 00:00:00 2001 From: Simon Walz Date: Mon, 16 Sep 2024 14:54:30 +0200 Subject: [PATCH 164/269] net: lwm2m: check each block for TLV header For composite operations, we should always check whether the TLV header is present. Otherwise, all blocks are assigned to one resource. Signed-off-by: Simon Walz --- subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c b/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c index e68c32a9f93359b..571c411f8c679f4 100644 --- a/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c +++ b/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c @@ -959,9 +959,11 @@ int do_write_op_tlv(struct lwm2m_message *msg) struct oma_tlv tlv; int ret; - /* In case of block transfer go directly to the - * message processing - consecutive blocks will not carry the TLV - * header. + /* In case of block transfer, check if there are any fragments + * left from the previous resource (instance). If this is the + * case, proceed directly to processing the message - + * consecutive blocks from the same resource do not carry the + * TLV header. */ if (msg->in.block_ctx != NULL && msg->in.block_ctx->ctx.current > 0) { msg->path.res_id = msg->in.block_ctx->path.res_id; @@ -971,7 +973,6 @@ int do_write_op_tlv(struct lwm2m_message *msg) return ret; } - return 0; } while (true) { From 2ba893e0cbfd44ec9a20bb596d490d2dac6883ac Mon Sep 17 00:00:00 2001 From: Armin Kessler Date: Thu, 12 Sep 2024 11:47:57 +0200 Subject: [PATCH 165/269] drivers: video: esp32s3 Add the missing calls to the sensors`video_stream_start()` and `video_stream_stop()` functions. Signed-off-by: Armin Kessler --- drivers/video/video_esp32_dvp.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/video/video_esp32_dvp.c b/drivers/video/video_esp32_dvp.c index 0d9c9dc6d870c8a..54a480e5424d091 100644 --- a/drivers/video/video_esp32_dvp.c +++ b/drivers/video/video_esp32_dvp.c @@ -194,6 +194,10 @@ static int video_esp32_stream_start(const struct device *dev) cam_hal_start_streaming(&data->hal); + if (video_stream_start(cfg->source_dev)) { + return -EIO; + } + data->is_streaming = true; return 0; @@ -207,6 +211,10 @@ static int video_esp32_stream_stop(const struct device *dev) LOG_DBG("Stop streaming"); + if (video_stream_stop(cfg->source_dev)) { + return -EIO; + } + data->is_streaming = false; ret = dma_stop(cfg->dma_dev, cfg->rx_dma_channel); if (ret) { From bd56fecc61e6580d41ee494a9d72e10c7fa81aa5 Mon Sep 17 00:00:00 2001 From: Robert Lubos Date: Fri, 13 Sep 2024 15:04:30 +0200 Subject: [PATCH 166/269] net: iface: Add missing interface mutex locks net_if_ipv4/6_addr_rm() were missing the iface mutex lock, this commit adds it. Signed-off-by: Robert Lubos --- subsys/net/ip/net_if.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c index da664cd28b02a64..54c4f24f3680ec2 100644 --- a/subsys/net/ip/net_if.c +++ b/subsys/net/ip/net_if.c @@ -1984,27 +1984,34 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface, bool net_if_ipv6_addr_rm(struct net_if *iface, const struct in6_addr *addr) { struct net_if_ipv6 *ipv6; + bool result = true; int ret; NET_ASSERT(addr); + net_if_lock(iface); + ipv6 = iface->config.ip.ipv6; if (!ipv6) { - return false; + result = false; + goto out; } ret = net_if_addr_unref(iface, AF_INET6, addr); if (ret > 0) { NET_DBG("Address %s still in use (ref %d)", net_sprint_ipv6_addr(addr), ret); - return false; - + result = false; + goto out; } else if (ret < 0) { NET_DBG("Address %s not found (%d)", net_sprint_ipv6_addr(addr), ret); } - return true; +out: + net_if_unlock(iface); + + return result; } bool z_impl_net_if_ipv6_addr_add_by_index(int index, @@ -4366,27 +4373,34 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface, bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr) { struct net_if_ipv4 *ipv4; + bool result = true; int ret; NET_ASSERT(addr); + net_if_lock(iface); + ipv4 = iface->config.ip.ipv4; if (!ipv4) { - return false; + result = false; + goto out; } ret = net_if_addr_unref(iface, AF_INET, addr); if (ret > 0) { NET_DBG("Address %s still in use (ref %d)", net_sprint_ipv4_addr(addr), ret); - return false; - + result = false; + goto out; } else if (ret < 0) { NET_DBG("Address %s not found (%d)", net_sprint_ipv4_addr(addr), ret); } - return true; +out: + net_if_unlock(iface); + + return result; } bool z_impl_net_if_ipv4_addr_add_by_index(int index, From 6d5cce662af01cb94b1734e164b8f34c9225f079 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Fri, 13 Sep 2024 15:29:48 +0200 Subject: [PATCH 167/269] Bluetooth: buf: Put command complete/status in sync buf pool Why is it ok to use the sync pool? Because command complete/status is processed in prio: that means on the same stack as the `bt_recv()` call from the driver. Why does it fix the issue? Because the complete/status event goes into a pool that is guaranteed to have one free buffer any time `bt_recv()` is not executing. Since the driver is the one calling bt_recv(), it (hopefully) will finish one `bt_recv()` before starting another one. Fixes #78223 Co-authored-by: Aleksander Wasaznik Signed-off-by: Aleksander Wasaznik Signed-off-by: Jonathan Rico --- subsys/bluetooth/host/buf.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/subsys/bluetooth/host/buf.c b/subsys/bluetooth/host/buf.c index 5706ea29a830c61..2e639488481712d 100644 --- a/subsys/bluetooth/host/buf.c +++ b/subsys/bluetooth/host/buf.c @@ -18,20 +18,12 @@ #include LOG_MODULE_REGISTER(bt_buf, CONFIG_BT_LOG_LEVEL); -#if defined(CONFIG_BT_CONN) -#if defined(CONFIG_BT_ISO) -#define MAX_EVENT_COUNT CONFIG_BT_MAX_CONN + CONFIG_BT_ISO_MAX_CHAN -#else -#define MAX_EVENT_COUNT CONFIG_BT_MAX_CONN -#endif /* CONFIG_BT_ISO */ -#elif defined(CONFIG_BT_ISO) -#define MAX_EVENT_COUNT CONFIG_BT_ISO_MAX_CHAN -#endif /* CONFIG_BT_CONN */ - -#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_ISO) -#define NUM_COMLETE_EVENT_SIZE BT_BUF_EVT_SIZE( \ - sizeof(struct bt_hci_cp_host_num_completed_packets) + \ - MAX_EVENT_COUNT * sizeof(struct bt_hci_handle_count)) +/* Events have a length field of 1 byte. This size fits all events. + * + * It's true that we don't put all kinds of events there (yet). However, the + * command complete event has an arbitrary payload, depending on opcode. + */ +#define SYNC_EVT_SIZE (BT_BUF_RESERVE + BT_HCI_EVT_HDR_SIZE + 255) /* Pool for RX HCI buffers that are always freed by `bt_recv` * before it returns. @@ -41,9 +33,7 @@ LOG_MODULE_REGISTER(bt_buf, CONFIG_BT_LOG_LEVEL); * the HCI transport to fill buffers in parallel with `bt_recv` * consuming them. */ -#define SYNC_EVT_SIZE NUM_COMLETE_EVENT_SIZE NET_BUF_POOL_FIXED_DEFINE(sync_evt_pool, 1, SYNC_EVT_SIZE, sizeof(struct bt_buf_data), NULL); -#endif /* CONFIG_BT_CONN || CONFIG_BT_ISO */ NET_BUF_POOL_FIXED_DEFINE(discardable_pool, CONFIG_BT_BUF_EVT_DISCARDABLE_COUNT, BT_BUF_EVT_SIZE(CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE), @@ -100,9 +90,11 @@ struct net_buf *bt_buf_get_evt(uint8_t evt, bool discardable, switch (evt) { #if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_ISO) case BT_HCI_EVT_NUM_COMPLETED_PACKETS: +#endif /* CONFIG_BT_CONN || CONFIG_BT_ISO */ + case BT_HCI_EVT_CMD_STATUS: + case BT_HCI_EVT_CMD_COMPLETE: buf = net_buf_alloc(&sync_evt_pool, timeout); break; -#endif /* CONFIG_BT_CONN || CONFIG_BT_ISO */ default: if (discardable) { buf = net_buf_alloc(&discardable_pool, timeout); From edeb529c9f8f13b0e44dd6ece21095297eb965b1 Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Tue, 10 Sep 2024 18:15:10 +0200 Subject: [PATCH 168/269] Bluetooth: Host: Add advertising events stress test More information in the test description. Why: At the time of writing, this test exposes a bug in the Bluetooth stack where all the RX buffers are in use, and the controller driver fails to synchronously allocate a command response buffer. This is manifested in an assertion failure in `hci_common.c`. Signed-off-by: Jonathan Rico --- tests/bsim/bluetooth/host/compile.sh | 1 + .../bluetooth/host/scan/slow/CMakeLists.txt | 27 ++++++ .../bsim/bluetooth/host/scan/slow/compile.sh | 14 ++++ tests/bsim/bluetooth/host/scan/slow/prj.conf | 21 +++++ tests/bsim/bluetooth/host/scan/slow/src/dut.c | 83 +++++++++++++++++++ .../bsim/bluetooth/host/scan/slow/src/main.c | 74 +++++++++++++++++ .../bsim/bluetooth/host/scan/slow/src/peer.c | 48 +++++++++++ .../host/scan/slow/test_scripts/run.sh | 27 ++++++ 8 files changed, 295 insertions(+) create mode 100644 tests/bsim/bluetooth/host/scan/slow/CMakeLists.txt create mode 100755 tests/bsim/bluetooth/host/scan/slow/compile.sh create mode 100644 tests/bsim/bluetooth/host/scan/slow/prj.conf create mode 100644 tests/bsim/bluetooth/host/scan/slow/src/dut.c create mode 100644 tests/bsim/bluetooth/host/scan/slow/src/main.c create mode 100644 tests/bsim/bluetooth/host/scan/slow/src/peer.c create mode 100755 tests/bsim/bluetooth/host/scan/slow/test_scripts/run.sh diff --git a/tests/bsim/bluetooth/host/compile.sh b/tests/bsim/bluetooth/host/compile.sh index b735ab26c1b73db..34a59bf8378787b 100755 --- a/tests/bsim/bluetooth/host/compile.sh +++ b/tests/bsim/bluetooth/host/compile.sh @@ -40,5 +40,6 @@ run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/privacy/legacy/compil run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/id/settings/compile.sh run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/scan/start_stop/compile.sh +run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/host/scan/slow/compile.sh wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/scan/slow/CMakeLists.txt b/tests/bsim/bluetooth/host/scan/slow/CMakeLists.txt new file mode 100644 index 000000000000000..c27b16b911ff532 --- /dev/null +++ b/tests/bsim/bluetooth/host/scan/slow/CMakeLists.txt @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) + +find_package(Zephyr HINTS $ENV{ZEPHYR_BASE}) +project(slow) + +# This contains a variety of helper functions that abstract away common tasks, +# like scanning, setting up a connection, querying the peer for a given +# characteristic, etc.. +add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib) +target_link_libraries(app PRIVATE testlib) + +# This contains babblesim-specific helpers, e.g. device synchronization. +add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit) +target_link_libraries(app PRIVATE babblekit) + +zephyr_include_directories( + $ENV{BSIM_COMPONENTS_PATH}/libUtilv1/src/ + $ENV{BSIM_COMPONENTS_PATH}/libPhyComv1/src/ +) + +target_sources(app PRIVATE + src/main.c + src/peer.c + src/dut.c +) diff --git a/tests/bsim/bluetooth/host/scan/slow/compile.sh b/tests/bsim/bluetooth/host/scan/slow/compile.sh new file mode 100755 index 000000000000000..b7b1eea135e73d4 --- /dev/null +++ b/tests/bsim/bluetooth/host/scan/slow/compile.sh @@ -0,0 +1,14 @@ +#!/usr/bin/env bash +# Copyright 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +set -eu +: "${ZEPHYR_BASE:?ZEPHYR_BASE must be defined}" + +INCR_BUILD=1 + +source ${ZEPHYR_BASE}/tests/bsim/compile.source + +app="$(guess_test_relpath)" compile + +wait_for_background_jobs diff --git a/tests/bsim/bluetooth/host/scan/slow/prj.conf b/tests/bsim/bluetooth/host/scan/slow/prj.conf new file mode 100644 index 000000000000000..232cf6467a9c8ee --- /dev/null +++ b/tests/bsim/bluetooth/host/scan/slow/prj.conf @@ -0,0 +1,21 @@ +CONFIG_BT=y +CONFIG_BT_BROADCASTER=y +CONFIG_BT_CENTRAL=y +CONFIG_BT_OBSERVER=y +CONFIG_BT_EXT_ADV=y +CONFIG_BT_DEVICE_NAME="Scanner Test" + +# Enable privacy with frequent address refreshes +CONFIG_BT_SMP=y +CONFIG_BT_PRIVACY=y +CONFIG_BT_RPA_TIMEOUT=2 + +# Log & debug options +CONFIG_LOG=y +CONFIG_LOG_RUNTIME_FILTERING=y +CONFIG_LOG_THREAD_ID_PREFIX=y + +CONFIG_ASSERT=y +CONFIG_THREAD_NAME=y +CONFIG_LOG_THREAD_ID_PREFIX=y +CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y diff --git a/tests/bsim/bluetooth/host/scan/slow/src/dut.c b/tests/bsim/bluetooth/host/scan/slow/src/dut.c new file mode 100644 index 000000000000000..878fdc44c91d696 --- /dev/null +++ b/tests/bsim/bluetooth/host/scan/slow/src/dut.c @@ -0,0 +1,83 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include "testlib/log_utils.h" +#include "babblekit/flags.h" +#include "babblekit/testcase.h" + +LOG_MODULE_REGISTER(dut, LOG_LEVEL_DBG); + +extern unsigned long runtime_log_level; + +static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, + struct net_buf_simple *ad) +{ + char addr_str[BT_ADDR_LE_STR_LEN]; + + k_msleep(500); /* simulate a slow memcpy (or user processing the scan data) */ + + bt_addr_le_to_str(addr, addr_str, sizeof(addr_str)); + LOG_DBG("Device found: %s (RSSI %d), type %u, AD data len %u", addr_str, rssi, type, + ad->len); +} + +#define BT_LE_SCAN_ACTIVE_CONTINUOUS_WITH_DUPLICATES \ + BT_LE_SCAN_PARAM(BT_LE_SCAN_TYPE_ACTIVE, 0, BT_GAP_SCAN_FAST_INTERVAL_MIN, \ + BT_GAP_SCAN_FAST_WINDOW) + +void entrypoint_dut(void) +{ + /* Test purpose: + * + * Verifies that the host can handle running out of HCI RX buffers. + * + * To test this, we use a scanner with privacy enabled and sleep a bit + * when we get every advertising report. This sleep period simulates a + * slow "memcpy" operation on actual hardware. In effect, this uses up + * the event buffer pools. + * + * A short RPA timeout is used to prompt the host into periodically + * sending a bunch of commands to the controller. Those commands should + * not fail. + * + * Note: This test only fails by the stack crashing. + * + * It is a regression test for + * https://github.com/zephyrproject-rtos/zephyr/issues/78223 + * + * Two devices: + * - `dut`: active-scans with privacy ON + * - `peer`: bog-standard advertiser + * + * [verdict] + * - dut is able to run for a long enough time without triggering asserts + */ + int err; + + TEST_START("DUT"); + + /* Set the log level given by the `log_level` CLI argument */ + bt_testlib_log_level_set("dut", runtime_log_level); + + err = bt_enable(NULL); + TEST_ASSERT(!err, "Bluetooth init failed (err %d)\n", err); + + LOG_DBG("Bluetooth initialised"); + + err = bt_le_scan_start(BT_LE_SCAN_ACTIVE_CONTINUOUS_WITH_DUPLICATES, device_found); + TEST_ASSERT(!err, "Scanner setup failed (err %d)\n", err); + LOG_DBG("Explicit scanner started"); + + /* 40 seconds ought to be enough for anyone */ + k_sleep(K_SECONDS(40)); + + TEST_PASS_AND_EXIT("DUT passed"); +} diff --git a/tests/bsim/bluetooth/host/scan/slow/src/main.c b/tests/bsim/bluetooth/host/scan/slow/src/main.c new file mode 100644 index 000000000000000..6bdf9f19d29ae64 --- /dev/null +++ b/tests/bsim/bluetooth/host/scan/slow/src/main.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "bs_tracing.h" +#include "bstests.h" +#include "babblekit/testcase.h" +#include "testlib/log_utils.h" + +extern void entrypoint_dut(void); +extern void entrypoint_peer(void); +extern enum bst_result_t bst_result; + +unsigned long runtime_log_level = LOG_LEVEL_INF; + +static void test_args(int argc, char *argv[]) +{ + size_t argn = 0; + const char *arg = argv[argn]; + + if (strcmp(arg, "log_level") == 0) { + + runtime_log_level = strtoul(argv[++argn], NULL, 10); + + if (runtime_log_level >= LOG_LEVEL_NONE && runtime_log_level <= LOG_LEVEL_DBG) { + TEST_PRINT("Runtime log level configuration: %d", runtime_log_level); + } else { + TEST_FAIL("Invalid arguments to set log level: %d", runtime_log_level); + } + } else { + TEST_PRINT("Default runtime log level configuration: INFO"); + } +} + +static void test_end_cb(void) +{ + if (bst_result != Passed) { + TEST_PRINT("Test failed."); + } +} + +static const struct bst_test_instance entrypoints[] = { + { + .test_id = "dut", + .test_delete_f = test_end_cb, + .test_main_f = entrypoint_dut, + .test_args_f = test_args, + }, + { + .test_id = "peer", + .test_delete_f = test_end_cb, + .test_main_f = entrypoint_peer, + .test_args_f = test_args, + }, + BSTEST_END_MARKER, +}; + +static struct bst_test_list *install(struct bst_test_list *tests) +{ + return bst_add_tests(tests, entrypoints); +}; + +bst_test_install_t test_installers[] = {install, NULL}; + +int main(void) +{ + bst_main(); + + return 0; +} diff --git a/tests/bsim/bluetooth/host/scan/slow/src/peer.c b/tests/bsim/bluetooth/host/scan/slow/src/peer.c new file mode 100644 index 000000000000000..15c95021cb1a1ca --- /dev/null +++ b/tests/bsim/bluetooth/host/scan/slow/src/peer.c @@ -0,0 +1,48 @@ +/* Copyright (c) 2024 Nordic Semiconductor ASA + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#include "testlib/log_utils.h" +#include "babblekit/flags.h" +#include "babblekit/testcase.h" + +LOG_MODULE_REGISTER(peer, LOG_LEVEL_DBG); + +extern unsigned long runtime_log_level; + +void entrypoint_peer(void) +{ + int err; + + TEST_START("peer"); + + /* Set the log level given by the `log_level` CLI argument */ + bt_testlib_log_level_set("peer", runtime_log_level); + + err = bt_enable(NULL); + TEST_ASSERT(!err, "Bluetooth init failed (err %d)\n", err); + + LOG_DBG("Bluetooth initialised"); + + struct bt_le_ext_adv *adv; + + struct bt_le_adv_param adv_param = BT_LE_ADV_PARAM_INIT( + BT_LE_ADV_OPT_EXT_ADV, BT_GAP_ADV_FAST_INT_MIN_1, BT_GAP_ADV_FAST_INT_MAX_1, NULL); + + err = bt_le_ext_adv_create(&adv_param, NULL, &adv); + TEST_ASSERT(!err, "Failed to create advertising set: %d", err); + LOG_DBG("Created extended advertising set."); + + err = bt_le_ext_adv_start(adv, BT_LE_EXT_ADV_START_DEFAULT); + TEST_ASSERT(!err, "Failed to start extended advertising: %d", err); + LOG_DBG("Started extended advertising."); + + TEST_PASS("Tester done"); +} diff --git a/tests/bsim/bluetooth/host/scan/slow/test_scripts/run.sh b/tests/bsim/bluetooth/host/scan/slow/test_scripts/run.sh new file mode 100755 index 000000000000000..0b893952d32e72c --- /dev/null +++ b/tests/bsim/bluetooth/host/scan/slow/test_scripts/run.sh @@ -0,0 +1,27 @@ +#!/usr/bin/env bash +# Copyright 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +source ${ZEPHYR_BASE}/tests/bsim/sh_common.source + +test_name="$(guess_test_long_name)" +test_exe="${BSIM_OUT_PATH}/bin/bs_${BOARD_TS}_${test_name}_prj_conf" + +simulation_id=${test_name} +verbosity_level=2 +zephyr_log_level=3 + +cd ${BSIM_OUT_PATH}/bin + +Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s="${simulation_id}" \ + -D=2 -sim_length=100e6 + +Execute "${test_exe}" \ + -v=${verbosity_level} -s="${simulation_id}" -d=1 \ + -testid=peer -argstest log_level ${zephyr_log_level} + +Execute "${test_exe}" \ + -v=${verbosity_level} -s="${simulation_id}" -d=0 \ + -testid=dut -argstest log_level ${zephyr_log_level} + +wait_for_background_jobs From 48938550af5d96ded6daff10f0908c026c12ba89 Mon Sep 17 00:00:00 2001 From: Raffael Rostagno Date: Fri, 13 Sep 2024 10:53:40 -0300 Subject: [PATCH 169/269] boards: esp8684_devkitm: Update doc and .yaml for SPI support Update esp8684_devkitm board files indicating SPI support. Signed-off-by: Raffael Rostagno --- boards/espressif/esp8684_devkitm/doc/index.rst | 4 ++++ boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml | 1 + 2 files changed, 5 insertions(+) diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst index 5dd05ab7ceca694..fe2ba1e60bf3b92 100644 --- a/boards/espressif/esp8684_devkitm/doc/index.rst +++ b/boards/espressif/esp8684_devkitm/doc/index.rst @@ -70,6 +70,10 @@ Current Zephyr's ESP8684-DevKitM board supports the following features: +------------+------------+-------------------------------------+ | LEDC | on-chip | pwm | +------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ For a getting started user guide, please check `ESP8684-DevKitM User Guide`_. diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml index c722560475fd7ee..e689bbfe6c13d57 100644 --- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml +++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml @@ -11,6 +11,7 @@ supported: - counter - entropy - pwm + - spi testing: ignore_tags: - net From 2ca59e799c02c3b4ea45ddee1bc5c3e30b386eec Mon Sep 17 00:00:00 2001 From: Jonathan Rico Date: Fri, 13 Sep 2024 16:25:13 +0200 Subject: [PATCH 170/269] Bluetooth: Host: Defer `conn.recycled()` to the syswq We don't own the thread that calls the final `bt_conn_unref()`. The users might not be aware that they are re-using that poor thread's stack. Putting it on the system workqueue gives a predictable stack size and thread priority for the invocation of the recycled handlers. Signed-off-by: Jonathan Rico --- subsys/bluetooth/host/conn.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c index 12e908926ca5f92..b8c835876c78b10 100644 --- a/subsys/bluetooth/host/conn.c +++ b/subsys/bluetooth/host/conn.c @@ -1475,6 +1475,18 @@ struct bt_conn *bt_conn_ref(struct bt_conn *conn) return conn; } +static K_SEM_DEFINE(pending_recycled_events, 0, K_SEM_MAX_LIMIT); + +static void recycled_work_handler(struct k_work *work) +{ + if (k_sem_take(&pending_recycled_events, K_NO_WAIT) == 0) { + notify_recycled_conn_slot(); + k_work_submit(work); + } +} + +static K_WORK_DEFINE(recycled_work, recycled_work_handler); + void bt_conn_unref(struct bt_conn *conn) { atomic_val_t old; @@ -1505,7 +1517,8 @@ void bt_conn_unref(struct bt_conn *conn) * to claim connection object as only the first claim will be served. */ if (deallocated) { - notify_recycled_conn_slot(); + k_sem_give(&pending_recycled_events); + k_work_submit(&recycled_work); } if (IS_ENABLED(CONFIG_BT_PERIPHERAL) && conn_type == BT_CONN_TYPE_LE && From ccc243c1298610c764ce8be86277a7bd7ecd6fbe Mon Sep 17 00:00:00 2001 From: Kapil Bhatt Date: Fri, 13 Sep 2024 20:44:06 +0530 Subject: [PATCH 171/269] modules: hostap: Add wifi statistics reset support This change will add an API to reset the wifi statistics when reset command is called. Signed-off-by: Kapil Bhatt --- modules/hostap/src/supp_api.c | 12 ++++++++++++ modules/hostap/src/supp_api.h | 8 ++++++++ modules/hostap/src/supp_main.c | 1 + 3 files changed, 21 insertions(+) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 1f108f19949ac9b..c2c34b81b8a6e34 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -1057,6 +1057,18 @@ int supplicant_get_stats(const struct device *dev, struct net_stats_wifi *stats) return wifi_mgmt_api->get_stats(dev, stats); } + +int supplicant_reset_stats(const struct device *dev) +{ + const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev); + + if (!wifi_mgmt_api || !wifi_mgmt_api->reset_stats) { + wpa_printf(MSG_WARNING, "Reset stats not supported"); + return -ENOTSUP; + } + + return wifi_mgmt_api->reset_stats(dev); +} #endif /* CONFIG_NET_STATISTICS_WIFI */ int supplicant_pmksa_flush(const struct device *dev) diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index 0111e69fd0897b2..99905cfa6742f5c 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -82,6 +82,14 @@ int supplicant_scan(const struct device *dev, struct wifi_scan_params *params, * @return 0 for OK; -1 for ERROR */ int supplicant_get_stats(const struct device *dev, struct net_stats_wifi *stats); +/** + * @brief Reset Wi-Fi statistics + * + * @param dev Wi-Fi interface name to use + * + * @return 0 for OK; -1 for ERROR + */ +int supplicant_reset_stats(const struct device *dev); #endif /* CONFIG_NET_STATISTICS_WIFI || __DOXYGEN__ */ /** Flush PMKSA cache entries diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 89e29ab0cba1ef3..39b11ae9913ec91 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -60,6 +60,7 @@ static const struct wifi_mgmt_ops mgmt_ops = { .iface_status = supplicant_status, #ifdef CONFIG_NET_STATISTICS_WIFI .get_stats = supplicant_get_stats, + .reset_stats = supplicant_reset_stats, #endif .set_power_save = supplicant_set_power_save, .set_twt = supplicant_set_twt, From 96386eac0ba27018b3a2daf2494929e433999a8d Mon Sep 17 00:00:00 2001 From: David van Rijn Date: Fri, 13 Sep 2024 17:36:07 +0200 Subject: [PATCH 172/269] cmake: Add REQUIRED option to devicetree getters namely: - dt_nodelabel - dt_alias - dt_prop these currently fail quietly. This can cause some very confusing errors later on. By adding `REQUIRED` to the function call one can easily generate a more clear message: required nodelabel not found: ... Signed-off-by: David van Rijn --- cmake/modules/extensions.cmake | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 7a8e50ccc24e38a..4d8422a3ced52b5 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -3636,9 +3636,11 @@ endfunction() # # : Return variable where the node path will be stored # NODELABEL KMp5qW$lWRHCOh+2}S#e+rLA?ijmpVfl! ziP%JH(49qv7tlml9`dvp#Thq1+X<~{}OqKEGX<`^>+9c|cOq7>leEM6YjWB^bj5`L4<WxV5DBdP$AJf?Gx z8vB$`8sJJl;KJJ-dnTY>HsG^We#MHi?9L@42O)ph+Im^lUBg@vSYF4kyF^HY3hKGF zCo|q&bzneM{a3tYTZ<`Bb9dV*?=>I)({*Eg0IVMS@2&* zF8F&l9>>2R40C>@B6lv&Ry2K3AB8CFob_iTaN^jvQ%nb$_@@I04Ys{chZD54ejNdb zto~P%tH@8bgoOBzRuF6a+d9|lAbH4U84H`2AsI()!kZ7cxvLM?pwMaHGxtuZcKP2zrh?>wqn#uq~25-e%ge zLAG*8SGb$KaQ}=!x@T|qL%0Y=l;b7gE>Ui`D^WX_4!WT=cuT#EMaW)wT-S!Ov(E1l z{=-My>wCc;pQ?tNVcfrqhS_{L4QN$6n0^eQcoJbuHsD3|9ezQ6(wBD9=OYXFLZi`U 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xS41U+rH8>C;SbAw7qGf;6$Go zebyPwsOlH|<;+oKnteT8{EbXIe3CjzK`gf-{edpI|3d^#KCI7roph!dkYu~iil*cv zSo3c&OZ+9sMwJ4cqS~MX#1xP@6^-PXACL{%BpexLY)nPL|7dGC$|Ib(P_hKa+0@Ql zswQ3{xJv~uLQv3#<{n1~9D?v)C>6=f4L|~GLBbzOu)9DApme>G0000A!8Y9BM|)K| z@8X(_3p~>VIWtAAa%_){%$2VgZ-y+KZ2-e2Sjx!1EY8P@KhVy&ZWRZ9$U* zQw02!f~*M%Fu%#}v+a@8A^_+)VW}q_EuC2G?@%2;0d66r>z`AY00000000000KrX^ AM*si- literal 0 HcmV?d00001 diff --git a/boards/dptechnics/walter/doc/index.rst b/boards/dptechnics/walter/doc/index.rst new file mode 100644 index 000000000000000..bb8d9eecbf530f5 --- /dev/null +++ b/boards/dptechnics/walter/doc/index.rst @@ -0,0 +1,276 @@ +.. _walter: + +DPTechnics Walter +################# + +Overview +******** + +Walter is a compact IoT development board that combines an Espressif ESP32-S3 SoC +with a Sequans Monarch 2 GM02SP LTE-M/NB-IoT/GNSS modem. +More information about Walter can be found on the `QuickSpot Website`_ and on the +`QuickSpot GitHub page`_. + +.. figure:: img/walter.webp + :align: center + :alt: DPTechnics Walter board + + DPTechnics Walter board (Credit: DPTechnics bv) + +Hardware +******** + +ESP32-S3-WROOM-1-N16R2 microcontroller: + +- Xtensa dual-core 32-bit LX7 CPU +- 16 MiB quad SPI flash memory +- 2 MiB quad SPI PSRAM +- 150 Mbps 802.11 b/g/n Wi-Fi 4 with on-board PCB antenna +- 2 Mbps Bluetooth 5 Low Energy with on-board PCB antenna + +Sequans Monarch 2 GM02SP modem: + +- Dual-mode LTE-M / NB-IoT (NB1, NB2) +- 3GPP LTE release 14 (Upgradable up to release 17) +- Ultra-low, deep-sleep mode in eDRX and PSM +- Adaptive +23 dBm, +20 dBm and +14 dBm output power +- Integrated LNA and SAW filter for GNSS reception +- Assisted and non-assisted GNSS with GPS and Galileo constellations +- Integrated SIM card +- Nano-SIM card slot +- u.FL RF connectors for GNSS and 5G antennas + +Inputs & outputs: + +- 24 GPIO pins for application use +- UART, SPI, I²C, CAN, I²S, and SD available on any of the GPIO pins +- ADC, DAC, and PWM integrated in ESP32-S3 +- 3.3 V software-controllable output +- USB Type-C connector for flashing and debugging +- 22 test points for production programming and testing +- On-board reset button + +Power supply + +- 5.0 V via USB Type-C +- 3.0 - 5.5 V via Vin pin +- Not allowed to use both power inputs simultaneously +- Designed for extremely low quiescent current + +Form factor + +- Easy to integrate via 2.54 mm headers +- 55 mm x 24.8 mm board dimensions +- Pin and footprint compatible with EOL Pycom GPy +- Breadboard friendly + +Supported Features +================== + +Current Zephyr's Walter board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ +| Cellular | on-board | modem_cellular | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +Simple boot +=========== + +The board could be loaded using the single binary image, without 2nd stage bootloader. +It is the default option when building the application without additional configuration. + +.. note:: + + Simple boot does not provide any security features nor OTA updates. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + + .. code:: cfg + + CONFIG_BOOTLOADER_MCUBOOT=y + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │   └── zephyr + │   ├── zephyr.elf + │   └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``walter`` board +configuration. Here is an example for the :zephyr:code-sample:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! walter/esp32s3/procpu + +Debugging +********* + +ESP32-S3 support on OpenOCD is available at `OpenOCD ESP32`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S3`_. + +Here is an example for building the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: walter/esp32s3/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. _`QuickSpot Website`: https://www.quickspot.io/ +.. _`QuickSpot GitHub page`: https://github.com/QuickSpot +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD ESP32`: https://github.com/openocd-org/openocd diff --git a/boards/dptechnics/walter/support/openocd.cfg b/boards/dptechnics/walter/support/openocd.cfg new file mode 100644 index 000000000000000..2f740b4a36ab1f4 --- /dev/null +++ b/boards/dptechnics/walter/support/openocd.cfg @@ -0,0 +1,7 @@ +set ESP_RTOS none +set ESP32_ONLYCPU 1 + +# Source the JTAG interface configuration file +source [find interface/esp_usb_jtag.cfg] +# Source the ESP32-S3 configuration file +source [find target/esp32s3.cfg] diff --git a/boards/dptechnics/walter/walter-pinctrl.dtsi b/boards/dptechnics/walter/walter-pinctrl.dtsi new file mode 100644 index 000000000000000..001d18be8dc09d8 --- /dev/null +++ b/boards/dptechnics/walter/walter-pinctrl.dtsi @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2024 DPTechnics bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +&pinctrl { + uart0_default: uart0_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + }; + + uart1_default: uart1_default { + group1 { + pinmux = ; + output-high; + }; + group2 { + pinmux = ; + bias-pull-up; + }; + group3 { + pinmux = ; + output-high; + }; + group4 { + pinmux = ; + }; + }; + + i2c0_default: i2c0_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + i2c1_default: i2c1_default { + group1 { + pinmux = , + ; + bias-pull-up; + drive-open-drain; + output-high; + }; + }; + + spim2_default: spim2_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + spim3_default: spim3_default { + group1 { + pinmux = , + , + ; + }; + group2 { + pinmux = ; + output-low; + }; + }; + + twai_default: twai_default { + group1 { + pinmux = , + ; + }; + }; +}; diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu.dts b/boards/dptechnics/walter/walter_esp32s3_appcpu.dts new file mode 100644 index 000000000000000..a2ef2198559c091 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_appcpu.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2024 DPTechnics bv + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include + +/ { + model = "DPTechnics Walter APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu.yaml b/boards/dptechnics/walter/walter_esp32s3_appcpu.yaml new file mode 100644 index 000000000000000..4c83151153e4e48 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: walter/esp32s3/appcpu +name: Walter APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: dptechnics diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig b/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig new file mode 100644 index 000000000000000..9abf2ff0430aba3 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.dts b/boards/dptechnics/walter/walter_esp32s3_procpu.dts new file mode 100644 index 000000000000000..310fa5d59df8b53 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_procpu.dts @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2024 DPTechnics bv + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "espressif/esp32s3/esp32s3_wroom_n16r2.dtsi" +#include "walter-pinctrl.dtsi" +#include + +/ { + model = "DPTechnics Walter PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + modem = &modem; + modem-uart = &uart1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + uart-0 = &usb_serial; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci = &esp32_bt_hci; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + hw-flow-control; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + modem: modem { + status = "okay"; + compatible = "sqn,gm02s"; + mdm-reset-gpios = <&gpio1 13 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&esp32_bt_hci { + status = "okay"; +}; diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.yaml b/boards/dptechnics/walter/walter_esp32s3_procpu.yaml new file mode 100644 index 000000000000000..839c29069a703ab --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_procpu.yaml @@ -0,0 +1,23 @@ +identifier: walter/esp32s3/procpu +name: Walter PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: dptechnics diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig b/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig new file mode 100644 index 000000000000000..59f3df7a866cb87 --- /dev/null +++ b/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y From 63051bf71af77e7c7fb009caab8c30c98917946a Mon Sep 17 00:00:00 2001 From: "Christopher J. Champagne" Date: Wed, 16 Aug 2023 13:44:19 +0000 Subject: [PATCH 181/269] xtensa: add kconfig to allow non-preemptible interrupts This adds a kconfig to enable making the interrupts non-preemptible by other interrupts. Enabling this will set the INTLEVEL to the max non-debug level before clearing the EXCM bit. Signed-off-by: Christopher J. Champagne Signed-off-by: Daniel Leung --- arch/xtensa/Kconfig | 6 ++++++ arch/xtensa/include/xtensa_asm2_s.h | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index af0e3ae12887dc3..8722c879e8b2302 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -157,6 +157,12 @@ endif # XTENSA_CPU_HAS_HIFI endmenu # Xtensa HiFi Options +config XTENSA_INTERRUPT_NONPREEMPTABLE + bool "Xtensa exceptions and interrupts cannot be pre-empted" + help + Allow use of medium and high priority interrupts without + pre-empting low priority interrupts and exceptions. + if CPU_HAS_MMU config XTENSA_MMU diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index 2f25fcdc9bc72ae..150df82c35cb6cb 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -430,6 +430,22 @@ _xstack_returned_\@: wur.THREADPTR a0 #endif /* XCHAL_HAVE_THREADPTR && CONFIG_USERSPACE */ +#ifdef CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE + + /* Setting the interrupt mask to the max non-debug level + * to prevent lower priority interrupts being preempted by + * high level interrupts until processing of that lower level + * interrupt has completed. + */ + rsr.ps a0 + movi a3, ~(PS_INTLEVEL_MASK) + and a0, a0, a3 + movi a3, PS_INTLEVEL(ZSR_RFI_LEVEL) + or a0, a0, a3 + wsr.ps a0 + +#else + /* There's a gotcha with level 1 handlers: the INTLEVEL field * gets left at zero and not set like high priority interrupts * do. That works fine for exceptions, but for L1 interrupts, @@ -450,7 +466,9 @@ _xstack_returned_\@: movi a3, PS_INTLEVEL(1) or a0, a0, a3 wsr.ps a0 + _not_l1: +#endif /* CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE */ /* Setting up the cross stack call below has states where the * resulting frames are invalid/non-reentrant, so we can't From 73699f2419964a2de5977c8b3c056451b1b74a3c Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Mon, 16 Sep 2024 16:33:00 -0300 Subject: [PATCH 182/269] boards: witte: linum: fix documentation by updating the correct link for the Linum defconfig file. Signed-off-by: Felipe Neves --- boards/witte/linum/doc/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst index a7998afe26129ea..bcbac19ecaa87e6 100644 --- a/boards/witte/linum/doc/index.rst +++ b/boards/witte/linum/doc/index.rst @@ -94,7 +94,7 @@ features: Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -:zephyr_file:`boards/witte_technology/linum/linum_defconfig` +:zephyr_file:`boards/witte/linum/linum_defconfig` Default Zephyr Peripheral Mapping: From e646f990932420d355f3f39b52ff42b106e5e067 Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Mon, 16 Sep 2024 16:40:15 -0300 Subject: [PATCH 183/269] boards: witte: linum: mention the board website location, it was placed in the documentation but it was not being mentioned. Signed-off-by: Felipe Neves --- boards/witte/linum/doc/index.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst index bcbac19ecaa87e6..537807a79790440 100644 --- a/boards/witte/linum/doc/index.rst +++ b/boards/witte/linum/doc/index.rst @@ -49,6 +49,8 @@ Expansion connector 2 features. - 6 PWM Channels - 10 ADCs +More information about the board, can be found at the `Witte Linum website`_. + Supported Features ================== From cc61e968607bc57720ce4e3f4eb5191d61af59c1 Mon Sep 17 00:00:00 2001 From: Andrea Merello Date: Mon, 16 Sep 2024 12:13:44 +0200 Subject: [PATCH 184/269] drivers: sensors: fix compile error due to conflicting types. Since b249535 (sensors: Add channel specifier) the signature of sensor_reconfigure_read_iodev() changed, but sensor_handlers.c apparently hasn't been updated. Fix compile time error by updating sensor_reconfigure_read_iodev() signature in sensor_handlers.c Signed-off-by: Andrea Merello --- drivers/sensor/sensor_handlers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/sensor/sensor_handlers.c b/drivers/sensor/sensor_handlers.c index ea82e20e9887ee9..74b81e3e53fd7fc 100644 --- a/drivers/sensor/sensor_handlers.c +++ b/drivers/sensor/sensor_handlers.c @@ -70,7 +70,7 @@ static inline int z_vrfy_sensor_get_decoder(const struct device *dev, static inline int z_vrfy_sensor_reconfigure_read_iodev(struct rtio_iodev *iodev, const struct device *sensor, - const enum sensor_channel *channels, + const struct sensor_chan_spec *channels, size_t num_channels) { K_OOPS(K_SYSCALL_OBJ(iodev, K_OBJ_RTIO_IODEV)); From 371a48ac16f8abb407adef7fbd3bdfd855c67d4a Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Tue, 10 Sep 2024 23:45:07 +0200 Subject: [PATCH 185/269] edtlib: Remove unreachable code This fixes the following error reported by ./scripts/ci/check_compliance.py: > 1 checks failed > ERROR : Test Pylint failed: > W0101:Unreachable code (unreachable) > File:scripts/dts/python-devicetree/src/devicetree/edtlib.py > Line:2271 > Column:16 > > Complete results in compliance.xml Signed-off-by: Reto Schneider --- scripts/dts/python-devicetree/src/devicetree/edtlib.py | 1 - 1 file changed, 1 deletion(-) diff --git a/scripts/dts/python-devicetree/src/devicetree/edtlib.py b/scripts/dts/python-devicetree/src/devicetree/edtlib.py index 088ef6e09967a29..e53925f96182d3c 100644 --- a/scripts/dts/python-devicetree/src/devicetree/edtlib.py +++ b/scripts/dts/python-devicetree/src/devicetree/edtlib.py @@ -2267,7 +2267,6 @@ def _init_compat2binding(self) -> None: _err( f"'{binding_path}' appears in binding directories " f"but isn't valid YAML: {e}") - continue # Convert the raw data to a Binding object, erroring out # if necessary. From 9d999149e3a962043edb27f896136a50d54d0a71 Mon Sep 17 00:00:00 2001 From: Keith Short Date: Fri, 13 Sep 2024 13:24:29 -0600 Subject: [PATCH 186/269] drivers: gpio: stm32: Fix compiler warning The local function ll_gpio_get_pin_pull() is not always referenced. Add the __maybe_unused attribute to avoid compiler warnings (which may be promoted to errors by downstream users). Signed-off-by: Keith Short --- drivers/gpio/gpio_stm32.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index fafa9b8d340a06f..407c1a414e6a7f6 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -179,7 +179,7 @@ static inline void ll_gpio_set_pin_pull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 #endif /* CONFIG_SOC_SERIES_STM32WB0X */ } -static inline uint32_t ll_gpio_get_pin_pull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__maybe_unused static inline uint32_t ll_gpio_get_pin_pull(GPIO_TypeDef *GPIOx, uint32_t Pin) { #if defined(CONFIG_SOC_SERIES_STM32WB0X) /* On STM32WB0, the PWRC PU/PD control registers should be used instead From 418b1e0e21460905113ae5ca93228fc40dbe048f Mon Sep 17 00:00:00 2001 From: Lukasz Mrugala Date: Thu, 12 Sep 2024 13:20:12 +0000 Subject: [PATCH 187/269] scripts: twister: Add TestCase status printing When at verbosity 1, we print out the status of TestInstances. This makes it harder to notice changes at TestCase level, which require perusing the logs. This adds TestCase status and reason printing if verbosity level is 2 or more. Reason printing is suppressed if the reason is empty or None. Signed-off-by: Lukasz Mrugala --- scripts/pylib/twister/twisterlib/runner.py | 7 +++++++ scripts/pylib/twister/twisterlib/statuses.py | 17 +++++++++++++++++ scripts/tests/twister/test_runner.py | 10 +++++++--- 3 files changed, 31 insertions(+), 3 deletions(-) diff --git a/scripts/pylib/twister/twisterlib/runner.py b/scripts/pylib/twister/twisterlib/runner.py index d2dbe968079b394..430e43846ea4e9d 100644 --- a/scripts/pylib/twister/twisterlib/runner.py +++ b/scripts/pylib/twister/twisterlib/runner.py @@ -1111,6 +1111,13 @@ def report_out(self, results): results.done, total_tests_width, total_to_do , instance.platform.name, instance.testsuite.name, status, more_info)) + if self.options.verbose > 1: + for tc in self.instance.testcases: + color = TwisterStatus.get_color(tc.status) + logger.info(f' {" ":<{total_tests_width+25+4}} {tc.name:<75} ' + f'{color}{str.upper(tc.status.value):<12}{Fore.RESET}' + f'{" " + tc.reason if tc.reason else ""}') + if instance.status in [TwisterStatus.ERROR, TwisterStatus.FAIL]: self.log_info_file(self.options.inline_logs) else: diff --git a/scripts/pylib/twister/twisterlib/statuses.py b/scripts/pylib/twister/twisterlib/statuses.py index 17b0709d75c4aa1..2983917467f4f40 100644 --- a/scripts/pylib/twister/twisterlib/statuses.py +++ b/scripts/pylib/twister/twisterlib/statuses.py @@ -5,7 +5,9 @@ """ Status classes to be used instead of str statuses. """ +from __future__ import annotations +from colorama import Fore from enum import Enum @@ -19,6 +21,21 @@ def _missing_(cls, value): if value is None: return TwisterStatus.NONE + @staticmethod + def get_color(status: TwisterStatus) -> str: + match(status): + case TwisterStatus.PASS: + color = Fore.GREEN + case TwisterStatus.SKIP | TwisterStatus.FILTER | TwisterStatus.BLOCK: + color = Fore.YELLOW + case TwisterStatus.FAIL | TwisterStatus.ERROR: + color = Fore.RED + case TwisterStatus.STARTED | TwisterStatus.NONE: + color = Fore.MAGENTA + case _: + color = Fore.RESET + return color + # All statuses below this comment can be used for TestCase BLOCK = 'blocked' STARTED = 'started' diff --git a/scripts/tests/twister/test_runner.py b/scripts/tests/twister/test_runner.py index 9cd4c2a8d80d1e3..8d7973f5e0554da 100644 --- a/scripts/tests/twister/test_runner.py +++ b/scripts/tests/twister/test_runner.py @@ -2008,9 +2008,13 @@ def test_projectbuilder_report_out( instance_mock.status = status instance_mock.reason = 'dummy reason' instance_mock.testsuite.name = 'dummy.testsuite.name' - instance_mock.testsuite.testcases = [mock.Mock() for _ in range(25)] - instance_mock.testcases = [mock.Mock() for _ in range(24)] + \ - [mock.Mock(status=TwisterStatus.SKIP)] + skip_mock_tc = mock.Mock(status=TwisterStatus.SKIP, reason='?') + skip_mock_tc.name = '?' + unknown_mock_tc = mock.Mock(status=mock.Mock(value='?'), reason='?') + unknown_mock_tc.name = '?' + instance_mock.testsuite.testcases = [unknown_mock_tc for _ in range(25)] + instance_mock.testcases = [unknown_mock_tc for _ in range(24)] + \ + [skip_mock_tc] env_mock = mock.Mock() pb = ProjectBuilder(instance_mock, env_mock, mocked_jobserver) From 6ec74d02b6e4356bce97cf6404fff8f0f98a5ca7 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 8 Jul 2024 15:18:49 -0400 Subject: [PATCH 188/269] cache: add new interface arch_cache_init() for initializing cache Add a new call for initializing cache on architectures that need that. Avoid using SYS_INIT for this and instead call the hook in a fixed place and run if implemented. Signed-off-by: Anas Nashif --- arch/arc/core/cache.c | 6 +++++- arch/arc/core/prep_c.c | 4 ++++ arch/arm/core/cortex_a_r/cache.c | 4 ++++ arch/arm/core/cortex_a_r/prep_c.c | 4 ++++ arch/arm/core/cortex_m/cache.c | 4 ++++ arch/arm/core/cortex_m/prep_c.c | 4 ++++ arch/arm64/core/prep_c.c | 4 ++++ arch/mips/core/prep_c.c | 4 ++++ arch/nios2/core/prep_c.c | 4 ++++ arch/riscv/core/prep_c.c | 4 ++++ arch/sparc/core/prep_c.c | 4 ++++ arch/x86/core/cache.c | 4 ++++ arch/x86/core/prep_c.c | 4 ++++ arch/xtensa/core/prep_c.c | 4 ++++ include/zephyr/arch/arm64/cache.h | 4 ++++ include/zephyr/arch/cache.h | 3 +++ include/zephyr/arch/xtensa/cache.h | 4 ++++ 17 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/arc/core/cache.c b/arch/arc/core/cache.c index 8c2aab29fed5dbf..2688d5b03ebfda4 100644 --- a/arch/arc/core/cache.c +++ b/arch/arc/core/cache.c @@ -227,4 +227,8 @@ static int init_dcache(void) return 0; } -SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); + +void arch_cache_init(void) +{ + init_dcache(); +} diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index 2eb93730b313f72..dfe7dad7008bb49 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -24,6 +24,7 @@ #include #include #include +#include /* XXX - keep for future use in full-featured cache APIs */ #if 0 @@ -135,6 +136,9 @@ void z_prep_c(void) dev_state_zero(); #endif z_data_copy(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif z_cstart(); CODE_UNREACHABLE; } diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c index 533666f04694023..31cf27a08e64569 100644 --- a/arch/arm/core/cortex_a_r/cache.c +++ b/arch/arm/core/cortex_a_r/cache.c @@ -217,3 +217,7 @@ int arch_icache_flush_and_invd_range(void *start_addr, size_t size) } #endif + +void arch_cache_init(void) +{ +} diff --git a/arch/arm/core/cortex_a_r/prep_c.c b/arch/arm/core/cortex_a_r/prep_c.c index e3ae589f76e0de1..74d0855a620d830 100644 --- a/arch/arm/core/cortex_a_r/prep_c.c +++ b/arch/arm/core/cortex_a_r/prep_c.c @@ -22,6 +22,7 @@ #include #include #include +#include #if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A) #include @@ -164,6 +165,9 @@ void z_prep_c(void) z_arm_init_stacks(); #endif z_arm_interrupt_init(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif #ifdef CONFIG_ARM_MPU z_arm_mpu_init(); z_arm_configure_static_mpu_regions(); diff --git a/arch/arm/core/cortex_m/cache.c b/arch/arm/core/cortex_m/cache.c index df746eb0474df90..a56996c8931a26b 100644 --- a/arch/arm/core/cortex_m/cache.c +++ b/arch/arm/core/cortex_m/cache.c @@ -110,3 +110,7 @@ int arch_icache_flush_and_invd_range(void *start_addr, size_t size) { return -ENOTSUP; } + +void arch_cache_init(void) +{ +} diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index d5fd0bbd498c0c0..ed8fb5ea85903c6 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -21,6 +21,7 @@ #include #include #include +#include #if defined(__GNUC__) /* @@ -198,6 +199,9 @@ void z_prep_c(void) #else z_arm_interrupt_init(); #endif /* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif z_cstart(); CODE_UNREACHABLE; } diff --git a/arch/arm64/core/prep_c.c b/arch/arm64/core/prep_c.c index 261824b79281c1d..11c7d2b112babb9 100644 --- a/arch/arm64/core/prep_c.c +++ b/arch/arm64/core/prep_c.c @@ -17,6 +17,7 @@ #include #include #include +#include extern void z_arm64_mm_init(bool is_primary_core); @@ -57,6 +58,9 @@ extern FUNC_NORETURN void arch_secondary_cpu_init(void); void z_arm64_secondary_prep_c(void) { arch_secondary_cpu_init(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif CODE_UNREACHABLE; } diff --git a/arch/mips/core/prep_c.c b/arch/mips/core/prep_c.c index bad0cc81de1b68f..0247f90df62490f 100644 --- a/arch/mips/core/prep_c.c +++ b/arch/mips/core/prep_c.c @@ -12,6 +12,7 @@ #include #include #include +#include static void interrupt_init(void) { @@ -51,6 +52,9 @@ void z_prep_c(void) z_bss_zero(); interrupt_init(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/nios2/core/prep_c.c b/arch/nios2/core/prep_c.c index dec82a67645ff0d..c59962059568268 100644 --- a/arch/nios2/core/prep_c.c +++ b/arch/nios2/core/prep_c.c @@ -22,6 +22,7 @@ #include #include #include +#include /** * @brief Prepare to and run C code @@ -49,6 +50,9 @@ void z_prep_c(void) */ z_nios2_dcache_flush_all(); #endif +#endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); #endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/riscv/core/prep_c.c b/arch/riscv/core/prep_c.c index 645dfa7f4ff6cda..e74a570cb666184 100644 --- a/arch/riscv/core/prep_c.c +++ b/arch/riscv/core/prep_c.c @@ -20,6 +20,7 @@ #include #include #include +#include #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) void soc_interrupt_init(void); @@ -42,6 +43,9 @@ void z_prep_c(void) z_data_copy(); #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT) soc_interrupt_init(); +#endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); #endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/sparc/core/prep_c.c b/arch/sparc/core/prep_c.c index 981b2d57d1e7ef1..5b4a440a63cd3e2 100644 --- a/arch/sparc/core/prep_c.c +++ b/arch/sparc/core/prep_c.c @@ -11,6 +11,7 @@ #include #include +#include /** * @brief Prepare to and run C code @@ -24,6 +25,9 @@ void z_prep_c(void) soc_prep_hook(); #endif z_data_copy(); +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif z_cstart(); CODE_UNREACHABLE; } diff --git a/arch/x86/core/cache.c b/arch/x86/core/cache.c index e80cb6d1dbf44e1..476632115c14673 100644 --- a/arch/x86/core/cache.c +++ b/arch/x86/core/cache.c @@ -119,3 +119,7 @@ int arch_dcache_flush_and_invd_range(void *start_addr, size_t size) { return arch_dcache_flush_range(start_addr, size); } + +void arch_cache_init(void) +{ +} diff --git a/arch/x86/core/prep_c.c b/arch/x86/core/prep_c.c index e71dcfc7883f92e..40b721c97a2e956 100644 --- a/arch/x86/core/prep_c.c +++ b/arch/x86/core/prep_c.c @@ -10,6 +10,7 @@ #include #include #include +#include extern FUNC_NORETURN void z_cstart(void); extern void x86_64_irq_init(void); @@ -76,6 +77,9 @@ FUNC_NORETURN void z_prep_c(void *arg) z_x86_set_stack_guard(z_interrupt_stacks[i]); } #endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/xtensa/core/prep_c.c b/arch/xtensa/core/prep_c.c index 3050f57a353c9bd..990915c5a46105f 100644 --- a/arch/xtensa/core/prep_c.c +++ b/arch/xtensa/core/prep_c.c @@ -6,6 +6,7 @@ #include #include #include +#include extern FUNC_NORETURN void z_cstart(void); @@ -71,6 +72,9 @@ void z_prep_c(void) memset(stack_start, 0xAA, stack_sz); } #endif +#if CONFIG_ARCH_CACHE + arch_cache_init(); +#endif #ifdef CONFIG_XTENSA_MMU xtensa_mmu_init(); diff --git a/include/zephyr/arch/arm64/cache.h b/include/zephyr/arch/arm64/cache.h index cddd901ba02ebfd..e0a7a6036e800bb 100644 --- a/include/zephyr/arch/arm64/cache.h +++ b/include/zephyr/arch/arm64/cache.h @@ -236,6 +236,10 @@ static ALWAYS_INLINE void arch_icache_disable(void) #endif /* CONFIG_ICACHE */ +static ALWAYS_INLINE void arch_cache_init(void) +{ +} + #ifdef __cplusplus } #endif diff --git a/include/zephyr/arch/cache.h b/include/zephyr/arch/cache.h index 1516f03ee729c8d..088de27c01802d3 100644 --- a/include/zephyr/arch/cache.h +++ b/include/zephyr/arch/cache.h @@ -349,6 +349,9 @@ void *arch_cache_uncached_ptr_get(void __sparse_cache *ptr); #define cache_uncached_ptr(ptr) arch_cache_uncached_ptr_get(ptr) #endif /* CONFIG_CACHE_DOUBLEMAP */ + +void arch_cache_init(void); + /** * @} */ diff --git a/include/zephyr/arch/xtensa/cache.h b/include/zephyr/arch/xtensa/cache.h index c5964c16ce70aa4..f090bbd165b3e21 100644 --- a/include/zephyr/arch/xtensa/cache.h +++ b/include/zephyr/arch/xtensa/cache.h @@ -331,6 +331,10 @@ static inline void *arch_cache_uncached_ptr_get(void *ptr) } #endif +static ALWAYS_INLINE void arch_cache_init(void) +{ +} + #ifdef __cplusplus } /* extern "C" */ From 2294da24d78ca55a77938b63c69c786a933a4a7c Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 8 Jul 2024 16:36:30 -0400 Subject: [PATCH 189/269] arc: start mpu in prep_c, do not use SYS_INIT Initialize MPU in prep_c similar to how all other architectures do it, avoid use of SYS_INIT. Signed-off-by: Anas Nashif --- arch/arc/core/mpu/arc_mpu_common_internal.h | 6 +----- arch/arc/core/mpu/arc_mpu_v4_internal.h | 10 ++++------ arch/arc/core/prep_c.c | 5 +++++ 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/arc/core/mpu/arc_mpu_common_internal.h b/arch/arc/core/mpu/arc_mpu_common_internal.h index a9ff5518b2fd339..15758ed15f66730 100644 --- a/arch/arc/core/mpu/arc_mpu_common_internal.h +++ b/arch/arc/core/mpu/arc_mpu_common_internal.h @@ -238,7 +238,7 @@ int arc_core_mpu_buffer_validate(const void *addr, size_t size, int write) * This function provides the default configuration mechanism for the Memory * Protection Unit (MPU). */ -static int arc_mpu_init(void) +void arc_mpu_init(void) { uint32_t num_regions = get_num_regions(); @@ -246,7 +246,6 @@ static int arc_mpu_init(void) if (mpu_config.num_regions > num_regions) { __ASSERT(0, "Request to configure: %u regions (supported: %u)\n", mpu_config.num_regions, num_regions); - return -EINVAL; } /* Disable MPU */ @@ -278,10 +277,7 @@ static int arc_mpu_init(void) /* Enable MPU */ arc_core_mpu_enable(); - - return 0; } -SYS_INIT(arc_mpu_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_COMMON_INTERNAL_H_ */ diff --git a/arch/arc/core/mpu/arc_mpu_v4_internal.h b/arch/arc/core/mpu/arc_mpu_v4_internal.h index 3bf6fca6c43b8c4..1323f1ebda298b7 100644 --- a/arch/arc/core/mpu/arc_mpu_v4_internal.h +++ b/arch/arc/core/mpu/arc_mpu_v4_internal.h @@ -814,7 +814,7 @@ int arc_core_mpu_buffer_validate(const void *addr, size_t size, int write) * This function provides the default configuration mechanism for the Memory * Protection Unit (MPU). */ -static int arc_mpu_init(void) +void arc_mpu_init(void) { uint32_t num_regions; uint32_t i; @@ -826,7 +826,7 @@ static int arc_mpu_init(void) __ASSERT(0, "Request to configure: %u regions (supported: %u)\n", mpu_config.num_regions, num_regions); - return -EINVAL; + return; } static_regions_num = 0U; @@ -851,7 +851,7 @@ static int arc_mpu_init(void) MPU_DYNAMIC_REGION_AREAS_NUM) { LOG_ERR("not enough dynamic regions %d", dynamic_regions_num); - return -EINVAL; + return; } dyn_reg_info[dynamic_regions_num].index = i; @@ -886,10 +886,8 @@ static int arc_mpu_init(void) /* Enable MPU */ arc_core_mpu_enable(); - return 0; + return; } -SYS_INIT(arc_mpu_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); #endif /* ZEPHYR_ARCH_ARC_CORE_MPU_ARC_MPU_V4_INTERNAL_H_ */ diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index dfe7dad7008bb49..e9b39dc54fccf72 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -115,6 +115,8 @@ static void dev_state_zero(void) #endif extern FUNC_NORETURN void z_cstart(void); +extern void arc_mpu_init(void); + /** * @brief Prepare to and run C code * @@ -138,6 +140,9 @@ void z_prep_c(void) z_data_copy(); #if CONFIG_ARCH_CACHE arch_cache_init(); +#endif +#ifdef CONFIG_ARC_MPU + arc_mpu_init(); #endif z_cstart(); CODE_UNREACHABLE; From 3e616cf4d321940f44fc3e8be6ea724b8211ca10 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 8 Jul 2024 16:38:41 -0400 Subject: [PATCH 190/269] arc: start secureshield in prep_c, do not use SYS_INIT Initialize secureshield in prep_c instead of using SYS_INIT. Signed-off-by: Anas Nashif --- arch/arc/core/prep_c.c | 4 ++++ arch/arc/core/secureshield/arc_sjli.c | 7 +------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c index e9b39dc54fccf72..bf3ab454a2c4249 100644 --- a/arch/arc/core/prep_c.c +++ b/arch/arc/core/prep_c.c @@ -116,6 +116,7 @@ static void dev_state_zero(void) extern FUNC_NORETURN void z_cstart(void); extern void arc_mpu_init(void); +extern void arc_secureshield_init(void); /** * @brief Prepare to and run C code @@ -143,6 +144,9 @@ void z_prep_c(void) #endif #ifdef CONFIG_ARC_MPU arc_mpu_init(); +#endif +#ifdef CONFIG_ARC_SECURE_FIRMWARE + arc_secureshield_init(); #endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/arc/core/secureshield/arc_sjli.c b/arch/arc/core/secureshield/arc_sjli.c index 22deebc27185a7d..e5b865445ee6de1 100644 --- a/arch/arc/core/secureshield/arc_sjli.c +++ b/arch/arc/core/secureshield/arc_sjli.c @@ -48,7 +48,7 @@ static void sjli_table_init(void) /* * @brief initialization of secureshield related functions. */ -static int arc_secureshield_init(void) +void arc_secureshield_init(void) { sjli_table_init(); @@ -60,9 +60,4 @@ static int arc_secureshield_init(void) * */ __asm__ volatile("sflag 0x20"); - - return 0; } - -SYS_INIT(arc_secureshield_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); From c9f7b512da0b63f95ebc412b4251754195c8355b Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 8 Jul 2024 16:42:16 -0400 Subject: [PATCH 191/269] arm: init null pointer detection in prep_c, do not use SYS_INIT Do not use SYS_INIT for initializing null pointer detection, call directly in prep_c. Signed-off-by: Anas Nashif --- arch/arm/core/cortex_m/debug.c | 5 +---- arch/arm/core/cortex_m/prep_c.c | 4 ++++ 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/core/cortex_m/debug.c b/arch/arm/core/cortex_m/debug.c index 8d83cd07f2fd043..61fb68145350799 100644 --- a/arch/arm/core/cortex_m/debug.c +++ b/arch/arm/core/cortex_m/debug.c @@ -58,7 +58,7 @@ BUILD_ASSERT(!(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE & (CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)), "the size of the partition must be power of 2"); -static int z_arm_debug_enable_null_pointer_detection(void) +int z_arm_debug_enable_null_pointer_detection(void) { z_arm_dwt_init(); @@ -118,7 +118,4 @@ static int z_arm_debug_enable_null_pointer_detection(void) return 0; } -SYS_INIT(z_arm_debug_enable_null_pointer_detection, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); - #endif /* CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT */ diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c index ed8fb5ea85903c6..10f78c44a25ba87 100644 --- a/arch/arm/core/cortex_m/prep_c.c +++ b/arch/arm/core/cortex_m/prep_c.c @@ -202,6 +202,10 @@ void z_prep_c(void) #if CONFIG_ARCH_CACHE arch_cache_init(); #endif + +#ifdef CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT + z_arm_debug_enable_null_pointer_detection(); +#endif z_cstart(); CODE_UNREACHABLE; } From 7e225efab74b700a046621a7304cb6d4ff7c0c2a Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 8 Jul 2024 17:08:30 -0400 Subject: [PATCH 192/269] arch: initialize irq_offload during boot, do not use SYS_INIT Do not use SYS_INIT for initializing irq_offload when enabled, instead using a new interface that is called during the boot process for all architectures. Signed-off-by: Anas Nashif --- arch/arc/core/irq_offload.c | 6 +----- arch/arc/include/arc_irq_offload.h | 4 +--- arch/arm/core/irq_offload.c | 4 ++++ arch/arm64/core/irq_offload.c | 4 ++++ arch/mips/core/irq_offload.c | 4 ++++ arch/nios2/core/irq_offload.c | 4 ++++ arch/posix/core/irq.c | 4 ++++ arch/riscv/core/irq_offload.c | 4 ++++ arch/sparc/core/irq_offload.c | 4 ++++ arch/x86/core/ia32/irq_offload.c | 4 ++++ arch/x86/core/intel64/irq_offload.c | 6 +----- arch/xtensa/core/irq_offload.c | 4 ++++ include/zephyr/arch/arch_interface.h | 7 +++++++ kernel/init.c | 3 +++ 14 files changed, 49 insertions(+), 13 deletions(-) diff --git a/arch/arc/core/irq_offload.c b/arch/arc/core/irq_offload.c index b658b8e353d46c7..d1a3f900ca3f0b3 100644 --- a/arch/arc/core/irq_offload.c +++ b/arch/arc/core/irq_offload.c @@ -54,7 +54,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) } /* need to be executed on every core in the system */ -int arc_irq_offload_init(void) +void arch_irq_offload_init(void) { IRQ_CONNECT(IRQ_OFFLOAD_LINE, IRQ_OFFLOAD_PRIO, arc_irq_offload_handler, NULL, 0); @@ -64,8 +64,4 @@ int arc_irq_offload_init(void) * with generic irq_enable() but via z_arc_v2_irq_unit_int_enable(). */ z_arc_v2_irq_unit_int_enable(IRQ_OFFLOAD_LINE); - - return 0; } - -SYS_INIT(arc_irq_offload_init, POST_KERNEL, 0); diff --git a/arch/arc/include/arc_irq_offload.h b/arch/arc/include/arc_irq_offload.h index c38d0a24b68e8fc..243b4655652281a 100644 --- a/arch/arc/include/arc_irq_offload.h +++ b/arch/arc/include/arc_irq_offload.h @@ -9,11 +9,9 @@ #ifdef CONFIG_IRQ_OFFLOAD -int arc_irq_offload_init(const struct device *unused); - static inline void arc_irq_offload_init_smp(void) { - arc_irq_offload_init(NULL); + arch_irq_offload_init(); } #else diff --git a/arch/arm/core/irq_offload.c b/arch/arm/core/irq_offload.c index 5dc1feccf7ab8f6..65349de331b0ca0 100644 --- a/arch/arm/core/irq_offload.c +++ b/arch/arm/core/irq_offload.c @@ -42,3 +42,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) offload_routine = NULL; k_sched_unlock(); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/arm64/core/irq_offload.c b/arch/arm64/core/irq_offload.c index 1d5e3c829b88eb0..4488e26849c0867 100644 --- a/arch/arm64/core/irq_offload.c +++ b/arch/arm64/core/irq_offload.c @@ -23,3 +23,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) : [svid] "i" (_SVC_CALL_IRQ_OFFLOAD), "r" (x0), "r" (x1)); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/mips/core/irq_offload.c b/arch/mips/core/irq_offload.c index 2a62ae071e0b129..5c85ada4d61cfe7 100644 --- a/arch/mips/core/irq_offload.c +++ b/arch/mips/core/irq_offload.c @@ -48,3 +48,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/nios2/core/irq_offload.c b/arch/nios2/core/irq_offload.c index d33882f9f021a74..0c918896be958cc 100644 --- a/arch/nios2/core/irq_offload.c +++ b/arch/nios2/core/irq_offload.c @@ -41,3 +41,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/posix/core/irq.c b/arch/posix/core/irq.c index 11d99e782b12d14..a1d3568c154e027 100644 --- a/arch/posix/core/irq.c +++ b/arch/posix/core/irq.c @@ -14,6 +14,10 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) { posix_irq_offload(routine, parameter); } + +void arch_irq_offload_init(void) +{ +} #endif void arch_irq_enable(unsigned int irq) diff --git a/arch/riscv/core/irq_offload.c b/arch/riscv/core/irq_offload.c index d325bc2dcd68e22..73d4b04c2a160da 100644 --- a/arch/riscv/core/irq_offload.c +++ b/arch/riscv/core/irq_offload.c @@ -11,3 +11,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) { arch_syscall_invoke2((uintptr_t)routine, (uintptr_t)parameter, RV_ECALL_IRQ_OFFLOAD); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/sparc/core/irq_offload.c b/arch/sparc/core/irq_offload.c index cd5acc08ba2a645..f36e957084b26b3 100644 --- a/arch/sparc/core/irq_offload.c +++ b/arch/sparc/core/irq_offload.c @@ -39,3 +39,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/x86/core/ia32/irq_offload.c b/arch/x86/core/ia32/irq_offload.c index 71e8363ece3825f..c7d68b34370d54a 100644 --- a/arch/x86/core/ia32/irq_offload.c +++ b/arch/x86/core/ia32/irq_offload.c @@ -47,3 +47,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/arch/x86/core/intel64/irq_offload.c b/arch/x86/core/intel64/irq_offload.c index c2771d735cfc25d..03ae8a9439b3dd6 100644 --- a/arch/x86/core/intel64/irq_offload.c +++ b/arch/x86/core/intel64/irq_offload.c @@ -44,11 +44,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) arch_irq_unlock(key); } -int irq_offload_init(void) +void arch_irq_offload_init(void) { x86_irq_funcs[CONFIG_IRQ_OFFLOAD_VECTOR - IV_IRQS] = dispatcher; - - return 0; } - -SYS_INIT(irq_offload_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/arch/xtensa/core/irq_offload.c b/arch/xtensa/core/irq_offload.c index c142bfc5fc66948..0e83520c809575d 100644 --- a/arch/xtensa/core/irq_offload.c +++ b/arch/xtensa/core/irq_offload.c @@ -37,3 +37,7 @@ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter) :: "r"(intenable), "r"(BIT(ZSR_IRQ_OFFLOAD_INT))); arch_irq_unlock(key); } + +void arch_irq_offload_init(void) +{ +} diff --git a/include/zephyr/arch/arch_interface.h b/include/zephyr/arch/arch_interface.h index 4411dfe3ddeb8aa..6721cec1171714d 100644 --- a/include/zephyr/arch/arch_interface.h +++ b/include/zephyr/arch/arch_interface.h @@ -455,6 +455,13 @@ bool arch_irq_is_used(unsigned int irq); * @param parameter Value to pass to the function when invoked */ void arch_irq_offload(irq_offload_routine_t routine, const void *parameter); + + +/** + * Initialize the architecture-specific portion of the irq_offload subsystem + */ +void arch_irq_offload_init(void); + #endif /* CONFIG_IRQ_OFFLOAD */ /** @} */ diff --git a/kernel/init.c b/kernel/init.c index a6afabc2a2e884e..1c24c5fc2b25145 100644 --- a/kernel/init.c +++ b/kernel/init.c @@ -516,6 +516,9 @@ static void bg_thread_main(void *unused1, void *unused2, void *unused3) #endif /* CONFIG_MMU */ z_sys_post_kernel = true; +#if CONFIG_IRQ_OFFLOAD + arch_irq_offload_init(); +#endif z_sys_init_run_level(INIT_LEVEL_POST_KERNEL); #if CONFIG_SOC_LATE_INIT_HOOK soc_late_init_hook(); From 328f52b0ce2df5abd13abc0fd5f9a29258db0dd2 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 8 Jul 2024 17:11:10 -0400 Subject: [PATCH 193/269] x86: init spec_ctrl in prep_c, do not use SYS_INIT Do not use SYS_INIT, call init script directly. Signed-off-by: Anas Nashif --- arch/x86/core/prep_c.c | 7 +++++++ arch/x86/core/spec_ctrl.c | 3 +-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/core/prep_c.c b/arch/x86/core/prep_c.c index 40b721c97a2e956..96c76f6af26b57d 100644 --- a/arch/x86/core/prep_c.c +++ b/arch/x86/core/prep_c.c @@ -19,6 +19,10 @@ extern void x86_64_irq_init(void); __pinned_data x86_boot_arg_t x86_cpu_boot_arg; #endif + + +extern int spec_ctrl_init(void); + /* Early global initialization functions, C domain. This runs only on the first * CPU for SMP systems. */ @@ -80,6 +84,9 @@ FUNC_NORETURN void z_prep_c(void *arg) #if CONFIG_ARCH_CACHE arch_cache_init(); #endif +#if defined(CONFIG_X86_DISABLE_SSBD) || defined(CONFIG_X86_ENABLE_EXTENDED_IBRS) + spec_ctrl_init(); +#endif z_cstart(); CODE_UNREACHABLE; diff --git a/arch/x86/core/spec_ctrl.c b/arch/x86/core/spec_ctrl.c index 50daa74bd1aec51..f5358e596ee82d6 100644 --- a/arch/x86/core/spec_ctrl.c +++ b/arch/x86/core/spec_ctrl.c @@ -17,7 +17,7 @@ */ #if defined(CONFIG_X86_DISABLE_SSBD) || defined(CONFIG_X86_ENABLE_EXTENDED_IBRS) -static int spec_ctrl_init(void) +int spec_ctrl_init(void) { uint32_t enable_bits = 0U; @@ -43,5 +43,4 @@ static int spec_ctrl_init(void) return 0; } -SYS_INIT(spec_ctrl_init, PRE_KERNEL_1, 0); #endif /* CONFIG_X86_DISABLE_SSBD || CONFIG_X86_ENABLE_EXTENDED_IBRS */ From 7c90f1bca13a5974e3dfa4332b92cf203d5fb26b Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Mon, 8 Jul 2024 17:17:09 -0400 Subject: [PATCH 194/269] arch: arm64: init xen in arch_kernel_init() Call xen_enlighten_init() from arch_kernel_init() instead of using SYS_INIT. Signed-off-by: Anas Nashif --- arch/arm64/core/xen/enlighten.c | 4 +--- arch/arm64/include/kernel_arch_func.h | 5 +++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/core/xen/enlighten.c b/arch/arm64/core/xen/enlighten.c index 164947a09ffdccb..91bf014b76212e6 100644 --- a/arch/arm64/core/xen/enlighten.c +++ b/arch/arm64/core/xen/enlighten.c @@ -42,7 +42,7 @@ static int xen_map_shared_info(const shared_info_t *shared_page) return HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp); } -static int xen_enlighten_init(void) +int xen_enlighten_init(void) { int ret = 0; shared_info_t *info = (shared_info_t *) shared_info_buf; @@ -66,5 +66,3 @@ static int xen_enlighten_init(void) return 0; } - -SYS_INIT(xen_enlighten_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/arch/arm64/include/kernel_arch_func.h b/arch/arm64/include/kernel_arch_func.h index cc91abc3b49f3f1..d2c346be1f02c34 100644 --- a/arch/arm64/include/kernel_arch_func.h +++ b/arch/arm64/include/kernel_arch_func.h @@ -28,8 +28,13 @@ extern "C" { #ifndef _ASMLANGUAGE +extern void xen_enlighten_init(void); + static ALWAYS_INLINE void arch_kernel_init(void) { +#ifdef CONFIG_XEN + xen_enlighten_init(); +#endif } static inline void arch_switch(void *switch_to, void **switched_from) From 998aea814ef734027f8013148c1a17ec1ba9b30a Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Mon, 16 Sep 2024 07:51:00 +0900 Subject: [PATCH 195/269] tests: build_all: sensor: Fix i2c duplicate address The address after @91 is messed up, so I fixed it. Signed-off-by: TOKITA Hiroshi --- tests/drivers/build_all/sensor/i2c.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi index 0e6a810ba7ee1b0..390c0e3d03e79d6 100644 --- a/tests/drivers/build_all/sensor/i2c.dtsi +++ b/tests/drivers/build_all/sensor/i2c.dtsi @@ -1064,7 +1064,7 @@ test_i2c_lm95234: lm95234@90 { status = "okay"; }; -test_i2c_sht21@91 { +test_i2c_sht21: sht21@91 { compatible = "sensirion,sht21"; reg = <0x91>; }; @@ -1074,9 +1074,9 @@ test_i2c_lsm9ds1: lsm9ds1@92 { reg = <0x92>; }; -test_i2c_icm42670: icm42670@92 { +test_i2c_icm42670: icm42670@93 { compatible = "invensense,icm42670"; - reg = <0x92>; + reg = <0x93>; int-gpios = <&test_gpio 0 0>; accel-hz = <800>; accel-fs = <16>; @@ -1084,23 +1084,23 @@ test_i2c_icm42670: icm42670@92 { gyro-fs = <2000>; }; -test_i2c_fxls8974: fxls8974@93 { +test_i2c_fxls8974: fxls8974@94 { compatible = "nxp,fxls8974"; - reg = <0x93>; + reg = <0x94>; reset-gpios = <&test_gpio 0 0>; int1-gpios = <&test_gpio 0 0>; int2-gpios = <&test_gpio 0 0>; }; -test_i2c_bmp180: bmp180@94 { +test_i2c_bmp180: bmp180@95 { compatible = "bosch,bmp180"; - reg = <0x94>; + reg = <0x95>; osr-press = <0x01>; }; -test_i2c_apds9253: apds9253@91 { +test_i2c_apds9253: apds9253@96 { compatible = "avago,apds9253"; - reg = <0x91>; + reg = <0x96>; int-gpios = <&test_gpio 0 0>; gain = ; rate = ; From a9c305d9835ded3b5d1ecc74efb98c5906dfbf1d Mon Sep 17 00:00:00 2001 From: TOKITA Hiroshi Date: Mon, 16 Sep 2024 06:57:30 +0900 Subject: [PATCH 196/269] tests: drivers: Fix adc labels in sensors test Use `test_adc` in io-channels to be consistent in whole tests/drivers/build_all/sensor/adc.dtsi file. Signed-off-by: TOKITA Hiroshi --- tests/drivers/build_all/sensor/adc.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/drivers/build_all/sensor/adc.dtsi b/tests/drivers/build_all/sensor/adc.dtsi index 08fd72694f85764..1b29685b98d8021 100644 --- a/tests/drivers/build_all/sensor/adc.dtsi +++ b/tests/drivers/build_all/sensor/adc.dtsi @@ -85,7 +85,7 @@ test_murata_ncp15wb473: murata-ncp15wb473 { test_tdk_ntcg163jf103ft1: tdk-ntcg163jf103ft1 { compatible = "tdk,ntcg163jf103ft1"; - io-channels = <&adc0 0>; + io-channels = <&test_adc 0>; pullup-uv = <3300000>; pullup-ohm = <0>; pulldown-ohm = <10000>; @@ -94,7 +94,7 @@ test_tdk_ntcg163jf103ft1: tdk-ntcg163jf103ft1 { test_lm35: lm35 { compatible = "lm35"; - io-channels = <&adc0 0>; + io-channels = <&test_adc 0>; status = "okay"; }; From 1036310e8b976c26e4e04da83652f950a58ea2ca Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Thu, 12 Sep 2024 15:28:08 -0700 Subject: [PATCH 197/269] drivers: i3c: set vendor ccc command target arg to const The target argument was not const. Set it to be const. Signed-off-by: Ryan McClelland --- drivers/i3c/i3c_ccc.c | 24 ++++++++++++++++++------ include/zephyr/drivers/i3c/ccc.h | 6 +++--- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/i3c/i3c_ccc.c b/drivers/i3c/i3c_ccc.c index d9624c7d212ce8d..c7473e9e28091e7 100644 --- a/drivers/i3c/i3c_ccc.c +++ b/drivers/i3c/i3c_ccc.c @@ -663,7 +663,10 @@ int i3c_ccc_do_getcaps(const struct i3c_device_desc *target, return ret; } -int i3c_ccc_do_setvendor(struct i3c_device_desc *target, uint8_t id, uint8_t *payload, size_t len) +int i3c_ccc_do_setvendor(const struct i3c_device_desc *target, + uint8_t id, + uint8_t *payload, + size_t len) { struct i3c_ccc_payload ccc_payload; @@ -682,7 +685,10 @@ int i3c_ccc_do_setvendor(struct i3c_device_desc *target, uint8_t id, uint8_t *pa return i3c_do_ccc(target->bus, &ccc_payload); } -int i3c_ccc_do_getvendor(struct i3c_device_desc *target, uint8_t id, uint8_t *payload, size_t len, +int i3c_ccc_do_getvendor(const struct i3c_device_desc *target, + uint8_t id, + uint8_t *payload, + size_t len, size_t *num_xfer) { struct i3c_ccc_payload ccc_payload; @@ -715,8 +721,12 @@ int i3c_ccc_do_getvendor(struct i3c_device_desc *target, uint8_t id, uint8_t *pa return ret; } -int i3c_ccc_do_getvendor_defbyte(struct i3c_device_desc *target, uint8_t id, uint8_t defbyte, - uint8_t *payload, size_t len, size_t *num_xfer) +int i3c_ccc_do_getvendor_defbyte(const struct i3c_device_desc *target, + uint8_t id, + uint8_t defbyte, + uint8_t *payload, + size_t len, + size_t *num_xfer) { struct i3c_ccc_payload ccc_payload; struct i3c_ccc_target_payload ccc_tgt_payload; @@ -750,8 +760,10 @@ int i3c_ccc_do_getvendor_defbyte(struct i3c_device_desc *target, uint8_t id, uin return ret; } -int i3c_ccc_do_setvendor_all(const struct device *controller, uint8_t id, uint8_t *payload, - size_t len) +int i3c_ccc_do_setvendor_all(const struct device *controller, + uint8_t id, + uint8_t *payload, + size_t len) { struct i3c_ccc_payload ccc_payload; diff --git a/include/zephyr/drivers/i3c/ccc.h b/include/zephyr/drivers/i3c/ccc.h index e538187aa22d71e..93b2e7a4a88e150 100644 --- a/include/zephyr/drivers/i3c/ccc.h +++ b/include/zephyr/drivers/i3c/ccc.h @@ -1782,7 +1782,7 @@ static inline int i3c_ccc_do_getcaps_fmt2(const struct i3c_device_desc *target, * * @return @see i3c_do_ccc */ -int i3c_ccc_do_setvendor(struct i3c_device_desc *target, +int i3c_ccc_do_setvendor(const struct i3c_device_desc *target, uint8_t id, uint8_t *payload, size_t len); @@ -1801,7 +1801,7 @@ int i3c_ccc_do_setvendor(struct i3c_device_desc *target, * * @return @see i3c_do_ccc */ -int i3c_ccc_do_getvendor(struct i3c_device_desc *target, +int i3c_ccc_do_getvendor(const struct i3c_device_desc *target, uint8_t id, uint8_t *payload, size_t len, @@ -1823,7 +1823,7 @@ int i3c_ccc_do_getvendor(struct i3c_device_desc *target, * * @return @see i3c_do_ccc */ -int i3c_ccc_do_getvendor_defbyte(struct i3c_device_desc *target, +int i3c_ccc_do_getvendor_defbyte(const struct i3c_device_desc *target, uint8_t id, uint8_t defbyte, uint8_t *payload, From 86f7ccf10addf38b1826cef4666834f7c770c8ce Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Fri, 13 Sep 2024 21:40:10 -0700 Subject: [PATCH 198/269] drivers: i3c: shell: add i3c speed command Add a shell command to set the i3c scl speed. Signed-off-by: Ryan McClelland --- drivers/i3c/i3c_shell.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index 02f9e48ffa44bb0..db3483ef0fca59c 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -303,6 +303,39 @@ static int cmd_i3c_info(const struct shell *sh, size_t argc, char **argv) return 0; } +/* i3c speed */ +static int cmd_i3c_speed(const struct shell *sh, size_t argc, char **argv) +{ + const struct device *dev; + struct i3c_config_controller config; + uint32_t speed; + int ret; + + dev = device_get_binding(argv[ARGV_DEV]); + if (!dev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[1]); + return -ENODEV; + } + + speed = strtol(argv[ARGV_DEV + 1], NULL, 10); + + ret = i3c_config_get(dev, I3C_CONFIG_CONTROLLER, &config); + if (ret != 0) { + shell_error(sh, "I3C: Failed to retrieve configuration"); + return ret; + } + + config.scl.i3c = speed; + + ret = i3c_configure(dev, I3C_CONFIG_CONTROLLER, &config); + if (ret != 0) { + shell_error(sh, "I3C: Failed to configure device"); + return ret; + } + + return ret; +} + /* i3c recover */ static int cmd_i3c_recover(const struct shell *sh, size_t argc, char **argv) { @@ -2199,6 +2232,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE( "Get I3C device info\n" "Usage: info []", cmd_i3c_info, 2, 1), + SHELL_CMD_ARG(speed, &dsub_i3c_device_attached_name, + "Set I3C device speed\n" + "Usage: speed ", + cmd_i3c_speed, 3, 0), SHELL_CMD_ARG(recover, &dsub_i3c_device_name, "Recover I3C bus\n" "Usage: recover ", From d6bff46d99b6f784592a0eca821f44f3b1fa75eb Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Thu, 12 Sep 2024 16:35:41 -0700 Subject: [PATCH 199/269] drivers: i3c: shell: add ibi shell commands This adds ibi commands for hot-join, controller request, and target interrupt request. Signed-off-by: Ryan McClelland --- drivers/i3c/i3c_shell.c | 109 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index db3483ef0fca59c..bfdff08fb41d7ef 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -2037,6 +2037,89 @@ static int cmd_i3c_i2c_scan(const struct shell *sh, size_t argc, char **argv) return 0; } +#ifdef I3C_USE_IBI +/* i3c ibi hj */ +static void cmd_i3c_ibi_hj(const struct shell *sh, size_t argc, char **argv) +{ + const struct device *dev; + struct i3c_ibi request; + int ret; + + dev = device_get_binding(argv[ARGV_DEV]); + if (!dev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + return -ENODEV; + } + + request.ibi_type = I3C_IBI_HOTJOIN; + ret = i3c_ibi_raise(dev, &request); + if (ret != 0) { + shell_error(sh, "I3C: Unable to issue IBI HJ"); + return ret; + } + + shell_print(sh, "I3C: Issued IBI HJ"); +} + +/* i3c ibi cr */ +static void cmd_i3c_ibi_cr(const struct shell *sh, size_t argc, char **argv) +{ + const struct device *dev; + struct i3c_ibi request; + int ret; + + dev = device_get_binding(argv[ARGV_DEV]); + if (!dev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + return -ENODEV; + } + + request.ibi_type = I3C_IBI_CONTROLLER_ROLE_REQUEST; + ret = i3c_ibi_raise(dev, &request); + if (ret != 0) { + shell_error(sh, "I3C: Unable to issue IBI CR"); + return ret; + } + + shell_print(sh, "I3C: Issued IBI CR"); +} + +/* i3c ibi tir []*/ +static void cmd_i3c_ibi_tir(const struct shell *sh, size_t argc, char **argv) +{ + const struct device *dev; + struct i3c_ibi request; + uint16_t data_length; + char **data; + uint8_t buf[MAX_I3C_BYTES]; + int ret; + + dev = device_get_binding(argv[ARGV_DEV]); + if (!dev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + return -ENODEV; + } + + data = argv[3]; + data_length = argc - 3; + for (i = 0; i < data_length; i++) { + buf[i] = (uint8_t)strtol(data[i], NULL, 16); + } + + request.ibi_type = I3C_IBI_TARGET_INTR; + request.payload = buf; + request.payload_len = data_length; + + ret = i3c_ibi_raise(dev, &request); + if (ret != 0) { + shell_error(sh, "I3C: Unable to issue IBI TIR"); + return ret; + } + + shell_print(sh, "I3C: Issued IBI TIR"); +} +#endif + static void i3c_device_list_target_name_get(size_t idx, struct shell_static_entry *entry) { if (idx < ARRAY_SIZE(i3c_list)) { @@ -2079,6 +2162,26 @@ static void i3c_device_name_get(size_t idx, struct shell_static_entry *entry) SHELL_DYNAMIC_CMD_CREATE(dsub_i3c_device_name, i3c_device_name_get); +#ifdef I3C_USE_IBI +/* L2 I3C IBI Shell Commands*/ +SHELL_STATIC_SUBCMD_SET_CREATE( + sub_i3c_ibi_cmds, + SHELL_CMD_ARG(hj, &dsub_i3c_device_name, + "Send IBI HJ\n" + "Usage: ibi hj ", + cmd_i3c_ibi_hj, 2, 0), + SHELL_CMD_ARG(tir, &dsub_i3c_device_name, + "Send IBI TIR\n" + "Usage: ibi tir [, ...]", + cmd_i3c_ibi_tir, 2, MAX_I3C_BYTES), + SHELL_CMD_ARG(cr, &dsub_i3c_device_name, + "Send IBI CR\n" + "Usage: ibi cr ", + cmd_i3c_ibi_cr, 2, 0), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); +#endif + /* L2 I3C CCC Shell Commands*/ SHELL_STATIC_SUBCMD_SET_CREATE( sub_i3c_ccc_cmds, @@ -2284,6 +2387,12 @@ SHELL_STATIC_SUBCMD_SET_CREATE( "Send I3C CCC\n" "Usage: ccc ", NULL, 3, 0), +#ifdef I3C_USE_IBI + SHELL_CMD_ARG(ibi, &sub_i3c_ibi_cmds, + "Send I3C IBI\n" + "Usage: ibi ", + NULL, 3, 0), +#endif SHELL_SUBCMD_SET_END /* Array terminated. */ ); From a338f7c710bf2c0f62d376890eeb128f13c2c779 Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Fri, 13 Sep 2024 23:17:10 -0700 Subject: [PATCH 200/269] drivers: i3c: shell: add hdr ddr shell commands Add read and write hdr ddr shell commands. Signed-off-by: Ryan McClelland --- drivers/i3c/i3c_shell.c | 123 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index bfdff08fb41d7ef..298c71b590734ef 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -508,6 +508,101 @@ static int cmd_i3c_read(const struct shell *sh, size_t argc, char **argv) return ret; } +/* i3c hdr ddr read <7b cmd> [, ...] */ +static int cmd_i3c_hdr_ddr_write(const struct shell *sh, size_t argc, char **argv) +{ + const struct device *dev, *tdev; + struct i3c_device_desc *desc; + uint8_t buf[MAX_I3C_BYTES]; + uint8_t cmd; + uint8_t data_length; + uint8_t i; + int ret; + + dev = device_get_binding(argv[ARGV_DEV]); + if (!dev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + return -ENODEV; + } + tdev = device_get_binding(argv[ARGV_TDEV]); + if (!tdev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + return -ENODEV; + } + desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); + if (!desc) { + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); + return -ENODEV; + } + + cmd = strtol(argv[3], NULL, 16); + + data_length = argc - 4; + if (data_length > MAX_I3C_BYTES) { + shell_info(sh, "Too many bytes provided, limit is %d", MAX_I3C_BYTES); + } + + for (i = 0; i < data_length; i++) { + buf[i] = (uint8_t)strtol(argv[4 + i], NULL, 16); + } + + ret = i3c_hdr_ddr_write(desc, cmd, buf, data_length); + if (ret != 0) { + shell_error(sh, "I3C: unable to perform HDR DDR write."); + return ret; + } + + return ret; +} + +/* i3c hdr ddr read <7b cmd> [] */ +static int cmd_i3c_hdr_ddr_read(const struct shell *sh, size_t argc, char **argv) +{ + const struct device *dev, *tdev; + struct i3c_device_desc *desc; + uint8_t buf[MAX_I3C_BYTES]; + int num_bytes; + uint8_t cmd; + int ret; + + dev = device_get_binding(argv[ARGV_DEV]); + if (!dev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_DEV]); + return -ENODEV; + } + tdev = device_get_binding(argv[ARGV_TDEV]); + if (!tdev) { + shell_error(sh, "I3C: Device driver %s not found.", argv[ARGV_TDEV]); + return -ENODEV; + } + desc = get_i3c_attached_desc_from_dev_name(dev, tdev->name); + if (!desc) { + shell_error(sh, "I3C: Device %s not attached to bus.", tdev->name); + return -ENODEV; + } + + cmd = strtol(argv[3], NULL, 16); + + if (argc > 4) { + num_bytes = strtol(argv[4], NULL, 16); + if (num_bytes > MAX_I3C_BYTES) { + num_bytes = MAX_I3C_BYTES; + } + } else { + num_bytes = MAX_I3C_BYTES; + } + + ret = i3c_hdr_ddr_read(desc, cmd, buf, num_bytes); + if (ret != 0) { + shell_error(sh, "I3C: unable to perform HDR DDR read."); + return ret; + } + + shell_hexdump(sh, buf, num_bytes); + + return ret; +} + /* i3c ccc rstdaa */ static int cmd_i3c_ccc_rstdaa(const struct shell *sh, size_t argc, char **argv) { @@ -2182,6 +2277,30 @@ SHELL_STATIC_SUBCMD_SET_CREATE( ); #endif +/* L3 I3C HDR DDR Shell Commands*/ +SHELL_STATIC_SUBCMD_SET_CREATE( + sub_i3c_hdr_ddr_cmds, + SHELL_CMD_ARG(write, &dsub_i3c_device_attached_name, + "Send HDR DDR Write\n" + "Usage: hdr ddr write <7b cmd> [, ...]", + cmd_i3c_hdr_ddr_write, 4, MAX_I3C_BYTES), + SHELL_CMD_ARG(read, &dsub_i3c_device_attached_name, + "Send HDR DDR Read\n" + "Usage: hdr ddr read <7b cmd> ", + cmd_i3c_hdr_ddr_read, 5, 0), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); + +/* L2 I3C HDR Shell Commands*/ +SHELL_STATIC_SUBCMD_SET_CREATE( + sub_i3c_hdr_cmds, + SHELL_CMD_ARG(ddr, &sub_i3c_hdr_ddr_cmds, + "Send HDR DDR\n" + "Usage: hdr ddr ", + NULL, 2, 0), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); + /* L2 I3C CCC Shell Commands*/ SHELL_STATIC_SUBCMD_SET_CREATE( sub_i3c_ccc_cmds, @@ -2387,6 +2506,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE( "Send I3C CCC\n" "Usage: ccc ", NULL, 3, 0), + SHELL_CMD_ARG(hdr, &sub_i3c_hdr_cmds, + "Send I3C HDR\n" + "Usage: hdr ", + NULL, 3, 0), #ifdef I3C_USE_IBI SHELL_CMD_ARG(ibi, &sub_i3c_ibi_cmds, "Send I3C IBI\n" From cf2ccbf85ed9439591bbda4fae84f407e3ce4727 Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Fri, 13 Sep 2024 20:18:39 -0700 Subject: [PATCH 201/269] drivers: i3c: add missing parameter to doxygen for deftgts The dev argument was missing for the doxygen for the function i3c_bus_deftgts. Add a comment for it. Signed-off-by: Ryan McClelland --- include/zephyr/drivers/i3c.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/zephyr/drivers/i3c.h b/include/zephyr/drivers/i3c.h index c910db02125cadc..41bf2762ea74585 100644 --- a/include/zephyr/drivers/i3c.h +++ b/include/zephyr/drivers/i3c.h @@ -2098,6 +2098,8 @@ bool i3c_bus_has_sec_controller(const struct device *dev); * * This builds the payload required for DEFTGTS and transmits it out * + * @param dev Pointer to controller device driver instance. + * * @retval 0 if successful. * @retval -ENOMEM No memory to build the payload. * @retval -EIO General Input/Output error. From 93dc6113bcb7773c64df80abb1683529a37dcb4f Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Sat, 14 Sep 2024 18:13:01 -0700 Subject: [PATCH 202/269] drivers: i3c: fix static addr for deftgts AC The Active Controller data struct for static addr is to always be 0x7E. This is so the active controller can be identified according to section 5.1.9.3.7 of the I3C v1.1.1 Specification. Signed-off-by: Ryan McClelland --- drivers/i3c/i3c_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/i3c_common.c b/drivers/i3c/i3c_common.c index b700a5a6720ce70..b7b39f08085690f 100644 --- a/drivers/i3c/i3c_common.c +++ b/drivers/i3c/i3c_common.c @@ -719,7 +719,7 @@ int i3c_bus_deftgts(const struct device *dev) deftgts->active_controller.addr = config_target.dynamic_addr << 1; deftgts->active_controller.dcr = config_target.dcr; deftgts->active_controller.bcr = config_target.bcr; - deftgts->active_controller.static_addr = config_target.static_addr << 1; + deftgts->active_controller.static_addr = I3C_BROADCAST_ADDR << 1; /* * Loop through each attached I3C device and add it to the payload From d2b0f70ddcbb03f17d810ece814ed7d102af2dcc Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Thu, 12 Sep 2024 15:33:21 -0700 Subject: [PATCH 203/269] drivers: i3c: add helper for if target is controller capable Add the function, i3c_device_is_controller_capable, to determine if a target is controller capable. Signed-off-by: Ryan McClelland --- drivers/i3c/i3c_common.c | 3 +-- include/zephyr/drivers/i3c.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/i3c_common.c b/drivers/i3c/i3c_common.c index b7b39f08085690f..237e215766b7ee7 100644 --- a/drivers/i3c/i3c_common.c +++ b/drivers/i3c/i3c_common.c @@ -670,8 +670,7 @@ bool i3c_bus_has_sec_controller(const struct device *dev) SYS_SLIST_FOR_EACH_NODE(&data->attached_dev.devices.i3c, node) { struct i3c_device_desc *i3c_desc = CONTAINER_OF(node, struct i3c_device_desc, node); - if (I3C_BCR_DEVICE_ROLE(i3c_desc->bcr) == - I3C_BCR_DEVICE_ROLE_I3C_CONTROLLER_CAPABLE) { + if (i3c_device_is_controller_capable(i3c_desc)) { return true; } } diff --git a/include/zephyr/drivers/i3c.h b/include/zephyr/drivers/i3c.h index 41bf2762ea74585..a5c88e9a5853167 100644 --- a/include/zephyr/drivers/i3c.h +++ b/include/zephyr/drivers/i3c.h @@ -1762,6 +1762,23 @@ static inline int i3c_device_is_ibi_capable(struct i3c_device_desc *target) == I3C_BCR_IBI_REQUEST_CAPABLE; } +/** + * @brief Check if the target is controller capable + * + * This reads the BCR from the device descriptor struct to determine + * whether the target is controller capable + * + * Note that BCR must have been obtained from device and + * i3c_device_desc::bcr must be set. + * + * @return True if target is controller capable, false otherwise. + */ +static inline int i3c_device_is_controller_capable(struct i3c_device_desc *target) +{ + return I3C_BCR_DEVICE_ROLE(target->bcr) + == I3C_BCR_DEVICE_ROLE_I3C_CONTROLLER_CAPABLE; +} + /** @} */ /** @@ -2089,6 +2106,8 @@ int i3c_device_basic_info_get(struct i3c_device_desc *target); * This reads the BCR from the device descriptor struct of all targets * to determine whether a device is a secondary controller. * + * @param dev Pointer to controller device driver instance. + * * @return True if the bus has a secondary controller, false otherwise. */ bool i3c_bus_has_sec_controller(const struct device *dev); From b0442e24f1ce4aebb12f4ab830e99745f3bf138a Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Fri, 13 Sep 2024 22:39:56 -0700 Subject: [PATCH 204/269] drivers: i3c: shell: record getcaps in to desc from shell Record the getcaps values in to the i3c desc from the shell command. Signed-off-by: Ryan McClelland --- drivers/i3c/i3c_shell.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c index 298c71b590734ef..f9e58483560a4e6 100644 --- a/drivers/i3c/i3c_shell.c +++ b/drivers/i3c/i3c_shell.c @@ -1662,6 +1662,7 @@ static int cmd_i3c_ccc_getcaps(const struct shell *sh, size_t argc, char **argv) shell_print(sh, "GETCAPS: 0x%02x; 0x%02x; 0x%02x; 0x%02x", caps.fmt1.getcaps[0], caps.fmt1.getcaps[1], caps.fmt1.getcaps[2], caps.fmt1.getcaps[3]); + memcpy(&desc->getcaps, &caps, sizeof(desc->getcaps)); } return ret; From b15c5d7e8bb4c00f9f8ad277e34ed0e68b1fba89 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 00:51:42 +0200 Subject: [PATCH 205/269] boards: nxp: imx93_evk: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x2) don't match for > /enet@42890000/mdio/phy@0 Signed-off-by: Reto Schneider --- boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts index 3a04d2003ee9a4c..8fbf9edf6ba9316 100644 --- a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -102,7 +102,7 @@ pinctrl-0 = <&pinmux_mdio>; pinctrl-names = "default"; status = "okay"; - phy: phy@0 { + phy: phy@2 { compatible = "realtek,rtl8211f"; reg = <2>; status = "okay"; From d35293c137ae9045bf4c001dce03b4093611210d Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 00:57:11 +0200 Subject: [PATCH 206/269] boards: nxp: imx8mp_evk: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x1) don't match for > /soc/enet@30be0000/mdio/phy@0 Signed-off-by: Reto Schneider --- boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts index 5f977acfca5bee6..3822987d2a44315 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts @@ -56,7 +56,7 @@ pinctrl-0 = <&pinmux_mdio>; pinctrl-names = "default"; status = "okay"; - phy: phy@0 { + phy: phy@1 { compatible = "realtek,rtl8211f"; reg = <1>; status = "okay"; From 06aa38e69039003bdccb2f477820b53db7067405 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:21:02 +0200 Subject: [PATCH 207/269] boards: nxp: usb_kw24d512: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x70000) don't match for > /soc/flash-controller@40020000/flash@0/partitions/partition@700000 Signed-off-by: Reto Schneider --- boards/nxp/usb_kw24d512/usb_kw24d512.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512.dts b/boards/nxp/usb_kw24d512/usb_kw24d512.dts index 6b0dbdb666839fe..59e616a605e7438 100644 --- a/boards/nxp/usb_kw24d512/usb_kw24d512.dts +++ b/boards/nxp/usb_kw24d512/usb_kw24d512.dts @@ -106,7 +106,7 @@ zephyr_udc0: &usbd { label = "image-0"; reg = <0x00000000 0x00070000>; }; - storage_partition: partition@700000 { + storage_partition: partition@70000 { label = "storage"; reg = <0x00070000 0x00010000>; }; From a23e2e2ed54d29e4129d49b351acb6d6a186c369 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:25:47 +0200 Subject: [PATCH 208/269] boards: nxp: frdm_mcxn236: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x88000) don't match for > /flash-controller@43000/flash@0/partitions/partition@80000 Signed-off-by: Reto Schneider --- boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi index a108bd2158694bb..b4631c79afad69f 100644 --- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi +++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi @@ -107,7 +107,7 @@ label = "image-0"; reg = <0x00010000 DT_SIZE_K(480)>; }; - slot1_partition: partition@80000 { + slot1_partition: partition@88000 { label = "image-1"; reg = <0x0088000 DT_SIZE_K(472)>; }; From 17efac3b48ae02a0d18365d368892865f34e4f2a Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:59:24 +0200 Subject: [PATCH 209/269] boards: nxp: frdm_kw41z: Fix unit and first address mismatch This fixes the following warnings: > devicetree error: unit address and first address in 'reg' (0x70000) > don't match for > /soc/flash-controller@40020000/flash@0/partitions/partition@700000 Signed-off-by: Reto Schneider --- boards/nxp/frdm_kw41z/frdm_kw41z.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nxp/frdm_kw41z/frdm_kw41z.dts b/boards/nxp/frdm_kw41z/frdm_kw41z.dts index baea825f872a43c..47b44f3e6179aec 100644 --- a/boards/nxp/frdm_kw41z/frdm_kw41z.dts +++ b/boards/nxp/frdm_kw41z/frdm_kw41z.dts @@ -184,7 +184,7 @@ label = "image-0"; reg = <0x00000000 0x00070000>; }; - storage_partition: partition@700000 { + storage_partition: partition@70000 { label = "storage"; reg = <0x00070000 0x00010000>; }; From 00670814616bbcdd54700a50505a0e15d7574bd1 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Sat, 14 Sep 2024 16:55:49 +0200 Subject: [PATCH 210/269] boards: nxp: imx8mp: Fix unit and first address mismatch This fixes the following warning: > devicetree error: unit address and first address in 'reg' (0x1) don't > match for /soc/enet@30be0000/mdio/phy@0 Signed-off-by: Reto Schneider --- boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts index 634092adbd4e503..692435c87d3079a 100644 --- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts @@ -54,7 +54,7 @@ pinctrl-0 = <&pinmux_mdio>; pinctrl-names = "default"; status = "okay"; - phy: phy@0 { + phy: phy@1 { compatible = "realtek,rtl8211f"; reg = <1>; status = "okay"; From ddcc07fc686a36290b591dc31c9320f4edb65606 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:32:33 +0200 Subject: [PATCH 211/269] dts: arm: nxp: lpc55S1x: Fix unit and first address mismatch This fixes the following warnings: > unit address and first address in 'reg' (0x40094000) don't match for > /soc/peripheral@40000000/usbhs@144000 Signed-off-by: Reto Schneider --- dts/arm/nxp/nxp_lpc55S1x_common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi index 2755e7bd86870e9..671797d07ab6b42 100644 --- a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi @@ -319,7 +319,7 @@ status = "okay"; }; - usbhs: usbhs@144000 { + usbhs: usbhs@94000 { compatible = "nxp,lpcip3511"; reg = <0x94000 0x1000>; interrupts = <47 1>; From b80f7b90ad610cf65cc323ca414469c126bcfc6c Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:08:23 +0200 Subject: [PATCH 212/269] dts: arm: nxp: lpc55S1x: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x3fc70) don't match for > /soc/peripheral@40000000/flash-controller@34000/flash@9fc70 Signed-off-by: Reto Schneider --- dts/arm/nxp/nxp_lpc55S1x_common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi index 671797d07ab6b42..34a8eec8db2c2c7 100644 --- a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi @@ -102,7 +102,7 @@ status = "disabled"; }; - uuid: flash@9fc70 { + uuid: flash@3fc70 { compatible = "nxp,lpc-uid"; reg = <0x3fc70 0x10>; }; From e2ae547be33e3040bca68fb23175c2f69de7c989 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:33:03 +0200 Subject: [PATCH 213/269] dts: arm: nxp: lpc55S2x: Fix unit and first address mismatch This fixes the following warnings: > unit address and first address in 'reg' (0x40094000) don't match for > /soc/peripheral@40000000/usbhs@144000 Signed-off-by: Reto Schneider --- dts/arm/nxp/nxp_lpc55S2x_common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi index 9f659c830d78813..184c2feeaddb21f 100644 --- a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi @@ -313,7 +313,7 @@ clocks = <&syscon MCUX_LPADC1_CLK>; }; - usbhs: usbhs@144000 { + usbhs: usbhs@94000 { compatible = "nxp,lpcip3511"; reg = <0x94000 0x1000>; interrupts = <47 1>; From c883f34e632e235a970deefb577aa6d49149fb75 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:10:07 +0200 Subject: [PATCH 214/269] dts: arm: nxp: lpc55S0x: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x3fc70) don't match for > /soc/peripheral@40000000/flash-controller@34000/flash@9fc70 Signed-off-by: Reto Schneider --- dts/arm/nxp/nxp_lpc55S0x_common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/arm/nxp/nxp_lpc55S0x_common.dtsi b/dts/arm/nxp/nxp_lpc55S0x_common.dtsi index 60888d4ea0f7baf..a478c4a0b5b0d5d 100644 --- a/dts/arm/nxp/nxp_lpc55S0x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S0x_common.dtsi @@ -95,7 +95,7 @@ status = "disabled"; }; - uuid: flash@9fc70 { + uuid: flash@3fc70 { compatible = "nxp,lpc-uid"; reg = <0x3fc70 0x10>; }; From 63cd2f65803dde07b7cebbab34570954102b70a3 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 00:59:16 +0200 Subject: [PATCH 215/269] boards: google: twinkie_v2: Fix unit and first address mismatch This fixes the following kind of warnings: > unit address and first address in 'reg' (0xf) don't match for > /soc/adc@40012400/channel@15 Signed-off-by: Reto Schneider --- boards/google/twinkie_v2/google_twinkie_v2.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/boards/google/twinkie_v2/google_twinkie_v2.dts b/boards/google/twinkie_v2/google_twinkie_v2.dts index 1f918f848ed4a08..7eafd8e3612d061 100644 --- a/boards/google/twinkie_v2/google_twinkie_v2.dts +++ b/boards/google/twinkie_v2/google_twinkie_v2.dts @@ -123,7 +123,7 @@ zephyr,resolution = <12>; }; - channel@15 { + channel@f { reg = <15>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; @@ -132,7 +132,7 @@ zephyr,resolution = <12>; }; - channel@17 { + channel@11 { reg = <17>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; @@ -141,7 +141,7 @@ zephyr,resolution = <12>; }; - channel@18 { + channel@12 { reg = <18>; zephyr,gain = "ADC_GAIN_1"; zephyr,reference = "ADC_REF_INTERNAL"; From 9bba5141f59d60fdb4f1c455cce807aeea59a829 Mon Sep 17 00:00:00 2001 From: Arrel Neumiller Date: Sun, 15 Sep 2024 11:53:59 +0100 Subject: [PATCH 216/269] doc: i2c, i3c: remove unnecessary preposition 'in' This commit removes the preposition "in" from the phrase "in particularly"in the I2C and I3C Controller API sections to improve readability. Signed-off-by: Arrel Neumiller --- doc/hardware/peripherals/i2c.rst | 2 +- doc/hardware/peripherals/i3c.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/hardware/peripherals/i2c.rst b/doc/hardware/peripherals/i2c.rst index 3b1209e30e9053b..44ee179c2fe42e6 100644 --- a/doc/hardware/peripherals/i2c.rst +++ b/doc/hardware/peripherals/i2c.rst @@ -27,7 +27,7 @@ I2C Controller API ================== Zephyr's I2C controller API is used when an I2C peripheral controls the bus, -in particularly the start and stop conditions and the clock. This is +particularly the start and stop conditions and the clock. This is the most common mode, used to interact with I2C devices like sensors and serial memory. diff --git a/doc/hardware/peripherals/i3c.rst b/doc/hardware/peripherals/i3c.rst index 347d8944ef171dd..21d3ded1941b952 100644 --- a/doc/hardware/peripherals/i3c.rst +++ b/doc/hardware/peripherals/i3c.rst @@ -21,7 +21,7 @@ I3C Controller API ****************** Zephyr's I3C controller API is used when an I3C controller controls -the bus, in particularly the start and stop conditions and the clock. +the bus, particularly the start and stop conditions and the clock. This is the most common mode, used to interact with I3C target devices such as sensors. From c24e8a382083aaaab6d3dde94b85af0991c895bf Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Sat, 14 Sep 2024 15:10:43 -0300 Subject: [PATCH 217/269] drivers: video: gc2145: fixes the prefix of the compatible driver, use galaxycore instead of gc. Signed-off-by: Felipe Neves --- drivers/video/Kconfig.gc2145 | 2 +- drivers/video/gc2145.c | 2 +- dts/bindings/video/{gc,gc2145.yaml => galaxycore,gc2145.yaml} | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) rename dts/bindings/video/{gc,gc2145.yaml => galaxycore,gc2145.yaml} (91%) diff --git a/drivers/video/Kconfig.gc2145 b/drivers/video/Kconfig.gc2145 index beda489c1eb3bfa..7f1bcc8326aae3e 100644 --- a/drivers/video/Kconfig.gc2145 +++ b/drivers/video/Kconfig.gc2145 @@ -4,7 +4,7 @@ config VIDEO_GC2145 bool "GC2145 CMOS digital image sensor" select I2C - depends on DT_HAS_GC_GC2145_ENABLED + depends on DT_HAS_GALAXYCORE_GC2145_ENABLED default y help Enable driver for GC2145 CMOS digital image sensor device. diff --git a/drivers/video/gc2145.c b/drivers/video/gc2145.c index 321acf8382719af..19404c27e9cf6f7 100644 --- a/drivers/video/gc2145.c +++ b/drivers/video/gc2145.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define DT_DRV_COMPAT gc_gc2145 +#define DT_DRV_COMPAT galaxycore_gc2145 #include #include diff --git a/dts/bindings/video/gc,gc2145.yaml b/dts/bindings/video/galaxycore,gc2145.yaml similarity index 91% rename from dts/bindings/video/gc,gc2145.yaml rename to dts/bindings/video/galaxycore,gc2145.yaml index a3ff89d831fdc9c..d74a4b609736d1e 100644 --- a/dts/bindings/video/gc,gc2145.yaml +++ b/dts/bindings/video/galaxycore,gc2145.yaml @@ -3,7 +3,7 @@ description: Galaxy Core GC2145 CMOS video sensor -compatible: "gc,gc2145" +compatible: "galaxycore,gc2145" include: i2c-device.yaml From 3ccd52b65732415a713113bfd664dbeeaf29073e Mon Sep 17 00:00:00 2001 From: Quy Tran Date: Fri, 13 Sep 2024 08:26:44 +0000 Subject: [PATCH 218/269] drivers: spi: update casting for MSTP register Update casting for MSTP register in SPI driver Signed-off-by: Quy Tran --- drivers/spi/spi_b_renesas_ra8.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi_b_renesas_ra8.c b/drivers/spi/spi_b_renesas_ra8.c index 58b0b86ffca82ed..17b0c3c586b38fc 100644 --- a/drivers/spi/spi_b_renesas_ra8.c +++ b/drivers/spi/spi_b_renesas_ra8.c @@ -729,8 +729,8 @@ static void ra_spi_eri_isr(const struct device *dev) .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(index)), \ .clock_subsys = \ { \ - .mstp = (uint32_t *)DT_INST_CLOCKS_CELL_BY_NAME(index, spiclk, \ - mstp), \ + .mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_NAME(index, spiclk, \ + mstp), \ .stop_bit = DT_INST_CLOCKS_CELL_BY_NAME(index, spiclk, stop_bit), \ }, \ }; \ From f5981e5d8c36a2ffe4ad5b9b5ec53c9ac305e688 Mon Sep 17 00:00:00 2001 From: Emil Lindqvist Date: Sat, 14 Sep 2024 08:39:56 +0200 Subject: [PATCH 219/269] net: shell: increase number of arguments to net suspend command Increased variable to the mandatory amount of commands, since the comment of SHELL_SUBCMD_ADD states "Number of mandatory arguments including command name" but net suspend takes the interface number to suspend Signed-off-by: Emil Lindqvist --- subsys/net/lib/shell/suspend.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/subsys/net/lib/shell/suspend.c b/subsys/net/lib/shell/suspend.c index cfa01375cacb392..5ec6f586c2ae84f 100644 --- a/subsys/net/lib/shell/suspend.c +++ b/subsys/net/lib/shell/suspend.c @@ -56,4 +56,4 @@ static int cmd_net_suspend(const struct shell *sh, size_t argc, char *argv[]) SHELL_SUBCMD_ADD((net), suspend, NULL, "Suspend a network interface", - cmd_net_suspend, 1, 0); + cmd_net_suspend, 2, 0); From a6f57960cdc7507eb88e2924ed398d136e68b623 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 11:22:49 -0700 Subject: [PATCH 220/269] doc: relnotes/4.0: Add info about CVE-2024-8798 Information about CVE-2024-8798 in release notes. Signed-off-by: Flavio Ceolin --- doc/releases/release-notes-4.0.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index 3c98a554b743487..4bf2f9e36d99858 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -21,6 +21,8 @@ The following CVEs are addressed by this release: More detailed information can be found in: https://docs.zephyrproject.org/latest/security/vulnerabilities.html +* CVE-2024-8798: Under embargo until 2024-11-22 + API Changes *********** From 311b7ac3ec0f30c6b5e6925c673e5b736d21fea7 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 11:27:56 -0700 Subject: [PATCH 221/269] doc: security: Add CVE under embargo Add an entry to CVE-2024-8798 Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index 27306d487ef8cf1..c725e536b9bf2f5 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1786,3 +1786,8 @@ CVE-2024-6444 ------------- Under embargo until 2024-09-22 + +CVE-2024-8798 +------------- + +Under embargo until 2024-11-22 From 1142f95c8cc8b2ae6dff2eaeff3bdc958bf051c4 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 11:36:22 -0700 Subject: [PATCH 222/269] doc: security: Disclose CVE-2024-5754 Disclose information about published CVE. Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index c725e536b9bf2f5..59a77f60cba1af5 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1745,7 +1745,24 @@ This has been fixed in main for v3.7.0 CVE-2024-5754 ------------- -Under embargo until 2024-09-04 +BT: Encryption procedure host vulnerability + +- `Zephyr project bug tracker GHSA-gvv5-66hw-5qrc + `_ + +This has been fixed in main for v3.7.0 + +- `PR 7395 fix for main + `_ + +- `PR 74124 fix for 3.6 + `_ + +- `PR 74123 fix for 3.5 + `_ + +- `PR 74122 fix for 2.7 + `_ CVE-2024-5931 ------------- From 2f5b9577de87b710f4dcab4cbff6a0f9505fcb4d Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 11:56:20 -0700 Subject: [PATCH 223/269] doc: security: Disclose CVE-2024-6258 Disclose information about published CVE. Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index 59a77f60cba1af5..35aec607ca6fe69 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1782,7 +1782,15 @@ Under embargo until 2024-09-11 CVE-2024-6258 ------------- -Under embargo until 2024-09-05 +BT: Missing length checks of net_buf in rfcomm_handle_data + +- `Zephyr project bug tracker GHSA-7833-fcpm-3ggm + `_ + +This has been fixed in main for v3.7.0 + +- `PR 74640 fix for main + `_ CVE-2024-6259 ------------- From 38db894cd96c938732249d1679754a7345954e60 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 12:36:08 -0700 Subject: [PATCH 224/269] doc: security: Disclose CVE-2024-5931 Disclose information about published CVE. Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index 35aec607ca6fe69..b3ab346c865999d 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1767,7 +1767,19 @@ This has been fixed in main for v3.7.0 CVE-2024-5931 ------------- -Under embargo until 2024-09-10 +BT: Unchecked user input in bap_broadcast_assistant + +- `Zephyr project bug tracker GHSA-r8h3-64gp-wv7f + `_ + +This has been fixed in main for v3.7.0 + +- `PR 74062 fix for main + `_ + +- `PR 77966 fix for 3.6 + `_ + CVE-2024-6135 ------------- From a4dcb8d25912abb5f2fd6784c118b30c8be5eace Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 12:46:57 -0700 Subject: [PATCH 225/269] doc: security: Disclose CVE-2024-6135 Disclose information about published CVE. Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index b3ab346c865999d..aa90a4815ad992d 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1784,7 +1784,18 @@ This has been fixed in main for v3.7.0 CVE-2024-6135 ------------- -Under embargo until 2024-09-11 +BT:Classic: Multiple missing buf length checks + +- `Zephyr project bug tracker GHSA-2mp4-4g6f-cqcx + `_ + +This has been fixed in main for v3.7.0 + +- `PR 74283 fix for main + `_ + +- `PR 77964 fix for 3.6 + `_ CVE-2024-6137 ------------- From d8df6abd6930ce7c334512af7e3e91f8274dd393 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 13:00:42 -0700 Subject: [PATCH 226/269] doc: security: Disclose CVE-2024-6137 Disclose information about published CVE. Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index aa90a4815ad992d..8867e6798a62f4a 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1800,7 +1800,15 @@ This has been fixed in main for v3.7.0 CVE-2024-6137 ------------- -Under embargo until 2024-09-11 +BT: Classic: SDP OOB access in get_att_search_list + +- `Zephyr project bug tracker GHSA-pm38-7g85-cf4f + `_ + +This has been fixed in main for v3.7.0 + +- `PR 75575 fix for main + `_ CVE-2024-6258 ------------- From d9bdb4af20b687897a0fca319c4a92e55ef3cfa7 Mon Sep 17 00:00:00 2001 From: Flavio Ceolin Date: Fri, 13 Sep 2024 13:11:39 -0700 Subject: [PATCH 227/269] doc: security: Disclose CVE-2024-6259 Disclose information about published CVE. Signed-off-by: Flavio Ceolin --- doc/security/vulnerabilities.rst | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst index 8867e6798a62f4a..70e26555897e3f2 100644 --- a/doc/security/vulnerabilities.rst +++ b/doc/security/vulnerabilities.rst @@ -1826,7 +1826,18 @@ This has been fixed in main for v3.7.0 CVE-2024-6259 ------------- -Under embargo until 2024-09-12 +BT: HCI: adv_ext_report Improper discarding in adv_ext_report + +- `Zephyr project bug tracker GHSA-p5j7-v26w-wmcp + `_ + +This has been fixed in main for v3.7.0 + +- `PR 74639 fix for main + `_ + +- `PR 77960 fix for 3.6 + `_ CVE-2024-6442 ------------- From 0b24b960fe1f20bc7a4de7993c511295dbb7e21f Mon Sep 17 00:00:00 2001 From: Shrek Wang Date: Sat, 14 Sep 2024 11:10:39 +0800 Subject: [PATCH 228/269] net: Add onlink and forwarding check to IPv6-prepare Deadloop happens when CONFIG_NET_ROUTING and VLAN are enabled. In function net_ipv6_prepare_for_send(), pkt->iface will be updated with net_pkt_set_iface(pkt, iface) in 2 scenarios: 1. ip_hdr->dst is onlink 2. check_route or nbr_lookup VLAN is virtual-iface which attaches to a physical-iface. Each time a packet being sent to a VLAN port will invoke twice of the net_send_data(). The 1st time, pkt->iface is set to virtual iface and the 2nd time to physical iface. However in above 2 scenarios, at the 2nd time of calling the net_send_data(), the pkt-iface will be changed back to virtual iface. The system runs into a deadloop. This can be proved by enabling CONFIG_NET_ROUTING with the VLAN sample. The main purpose for net_ipv6_prepare_for_send() is to set the right ll_dst address. If the ll_dst address is already set, then no need to go through it again. If the packet has done with the forwarding and set the ll_dst, then no need to check_route again. And, the pkt->iface will not be changed back to virtual iface. Fixes: #77402 Signed-off-by: Shrek Wang --- subsys/net/ip/ipv6_nbr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/subsys/net/ip/ipv6_nbr.c b/subsys/net/ip/ipv6_nbr.c index b1928f7d1384be6..6677df73ae8598a 100644 --- a/subsys/net/ip/ipv6_nbr.c +++ b/subsys/net/ip/ipv6_nbr.c @@ -852,7 +852,9 @@ enum net_verdict net_ipv6_prepare_for_send(struct net_pkt *pkt) */ if ((net_pkt_lladdr_dst(pkt)->addr && ((IS_ENABLED(CONFIG_NET_ROUTING) && - net_ipv6_is_ll_addr((struct in6_addr *)ip_hdr->dst)) || + (net_ipv6_is_ll_addr((struct in6_addr *)ip_hdr->dst) || + net_if_ipv6_addr_onlink(NULL, (struct in6_addr *)ip_hdr->dst) || + net_pkt_forwarding(pkt))) || !IS_ENABLED(CONFIG_NET_ROUTING))) || net_ipv6_is_addr_mcast((struct in6_addr *)ip_hdr->dst) || /* Workaround Linux bug, see: From 83212147b2ba305be7e41779849ca0a0c9875709 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Wed, 28 Aug 2024 13:26:04 +0800 Subject: [PATCH 229/269] shell: kernel_service: reorg the commands Split the `kernel_service.c` into multiple subcommand files, each file would register with the main `kernel` cmd based on the dependencies in Kconfig/CMakeLists.txt. This greatly reduces the number of precompiler directives. Signed-off-by: Yong Cong Sin Signed-off-by: Yong Cong Sin --- subsys/shell/modules/CMakeLists.txt | 8 +- subsys/shell/modules/Kconfig | 25 +- subsys/shell/modules/kernel_service.c | 693 ------------------ .../modules/kernel_service/CMakeLists.txt | 21 + subsys/shell/modules/kernel_service/Kconfig | 32 + subsys/shell/modules/kernel_service/cycles.c | 21 + subsys/shell/modules/kernel_service/heap.c | 36 + .../modules/kernel_service/kernel_shell.c | 10 + .../modules/kernel_service/kernel_shell.h | 29 + .../shell/modules/kernel_service/log-level.c | 45 ++ subsys/shell/modules/kernel_service/reboot.c | 42 ++ subsys/shell/modules/kernel_service/sleep.c | 31 + .../kernel_service/thread/CMakeLists.txt | 18 + .../modules/kernel_service/thread/Kconfig | 54 ++ .../modules/kernel_service/thread/list.c | 124 ++++ .../modules/kernel_service/thread/mask.c | 160 ++++ .../shell/modules/kernel_service/thread/pin.c | 51 ++ .../modules/kernel_service/thread/stacks.c | 91 +++ .../modules/kernel_service/thread/thread.c | 44 ++ .../modules/kernel_service/thread/unwind.c | 55 ++ subsys/shell/modules/kernel_service/uptime.c | 52 ++ subsys/shell/modules/kernel_service/version.c | 22 + 22 files changed, 944 insertions(+), 720 deletions(-) delete mode 100644 subsys/shell/modules/kernel_service.c create mode 100644 subsys/shell/modules/kernel_service/CMakeLists.txt create mode 100644 subsys/shell/modules/kernel_service/Kconfig create mode 100644 subsys/shell/modules/kernel_service/cycles.c create mode 100644 subsys/shell/modules/kernel_service/heap.c create mode 100644 subsys/shell/modules/kernel_service/kernel_shell.c create mode 100644 subsys/shell/modules/kernel_service/kernel_shell.h create mode 100644 subsys/shell/modules/kernel_service/log-level.c create mode 100644 subsys/shell/modules/kernel_service/reboot.c create mode 100644 subsys/shell/modules/kernel_service/sleep.c create mode 100644 subsys/shell/modules/kernel_service/thread/CMakeLists.txt create mode 100644 subsys/shell/modules/kernel_service/thread/Kconfig create mode 100644 subsys/shell/modules/kernel_service/thread/list.c create mode 100644 subsys/shell/modules/kernel_service/thread/mask.c create mode 100644 subsys/shell/modules/kernel_service/thread/pin.c create mode 100644 subsys/shell/modules/kernel_service/thread/stacks.c create mode 100644 subsys/shell/modules/kernel_service/thread/thread.c create mode 100644 subsys/shell/modules/kernel_service/thread/unwind.c create mode 100644 subsys/shell/modules/kernel_service/uptime.c create mode 100644 subsys/shell/modules/kernel_service/version.c diff --git a/subsys/shell/modules/CMakeLists.txt b/subsys/shell/modules/CMakeLists.txt index d002604c6ae07db..dccce335b1a89bc 100644 --- a/subsys/shell/modules/CMakeLists.txt +++ b/subsys/shell/modules/CMakeLists.txt @@ -1,9 +1,9 @@ # SPDX-License-Identifier: Apache-2.0 -zephyr_sources_ifdef( - CONFIG_KERNEL_SHELL - kernel_service.c - ) +add_subdirectory_ifdef(CONFIG_KERNEL_SHELL + kernel_service +) + zephyr_sources_ifdef( CONFIG_DEVICE_SHELL device_service.c diff --git a/subsys/shell/modules/Kconfig b/subsys/shell/modules/Kconfig index 86e9ac49a9bb624..84e4a879f83a71b 100644 --- a/subsys/shell/modules/Kconfig +++ b/subsys/shell/modules/Kconfig @@ -3,29 +3,6 @@ # Copyright (c) 2016 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -config KERNEL_SHELL - bool "Kernel shell" - default y if !SHELL_MINIMAL - imply INIT_STACKS - imply THREAD_MONITOR - imply THREAD_NAME - imply THREAD_STACK_INFO - help - This shell provides access to basic kernel data like version, uptime - and other useful information. - -config KERNEL_SHELL_REBOOT_DELAY - int "Delay between reception of shell reboot command and reboot (ms)" - depends on KERNEL_SHELL - depends on REBOOT - default 0 - help - This delay allows time for the shell to successfully echo the reboot - command input before the reboot abruptly terminates it. This can help - external systems that interact with the shell and require the reboot - command's echo to successfully complete to synchronise with the - device. - config DEVICE_SHELL bool "Device shell" default y if !SHELL_MINIMAL @@ -45,3 +22,5 @@ config DEVMEM_SHELL select POSIX_C_LIB_EXT help This shell command provides read/write access to physical memory. + +rsource "kernel_service/Kconfig" diff --git a/subsys/shell/modules/kernel_service.c b/subsys/shell/modules/kernel_service.c deleted file mode 100644 index ea75550c6723dae..000000000000000 --- a/subsys/shell/modules/kernel_service.c +++ /dev/null @@ -1,693 +0,0 @@ -/* - * Copyright (c) 2018 Nordic Semiconductor ASA - * Copyright (c) 2016 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_SYS_HEAP_RUNTIME_STATS) && (K_HEAP_MEM_POOL_SIZE > 0) -#include -#endif -#if defined(CONFIG_LOG_RUNTIME_FILTERING) -#include -#endif -#include - -#if defined(CONFIG_THREAD_MAX_NAME_LEN) -#define THREAD_MAX_NAM_LEN CONFIG_THREAD_MAX_NAME_LEN -#else -#define THREAD_MAX_NAM_LEN 10 -#endif - -static int cmd_kernel_version(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); - - shell_print(sh, "Zephyr version %s", KERNEL_VERSION_STRING); - return 0; -} - -#define MINUTES_FACTOR (MSEC_PER_SEC * SEC_PER_MIN) -#define HOURS_FACTOR (MINUTES_FACTOR * MIN_PER_HOUR) -#define DAYS_FACTOR (HOURS_FACTOR * HOUR_PER_DAY) - -static int cmd_kernel_uptime(const struct shell *sh, size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); - - int64_t milliseconds = k_uptime_get(); - int64_t days; - int64_t hours; - int64_t minutes; - int64_t seconds; - - if (argc == 1) { - shell_print(sh, "Uptime: %llu ms", milliseconds); - return 0; - } - - /* No need to enable the getopt and getopt_long for just one option. */ - if (strcmp("-p", argv[1]) && strcmp("--pretty", argv[1]) != 0) { - shell_error(sh, "Unsupported option: %s", argv[1]); - return -EIO; - } - - days = milliseconds / DAYS_FACTOR; - milliseconds %= DAYS_FACTOR; - hours = milliseconds / HOURS_FACTOR; - milliseconds %= HOURS_FACTOR; - minutes = milliseconds / MINUTES_FACTOR; - milliseconds %= MINUTES_FACTOR; - seconds = milliseconds / MSEC_PER_SEC; - milliseconds = milliseconds % MSEC_PER_SEC; - - shell_print(sh, - "uptime: %llu days, %llu hours, %llu minutes, %llu seconds, %llu milliseconds", - days, hours, minutes, seconds, milliseconds); - - return 0; -} - -static int cmd_kernel_cycles(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); - - shell_print(sh, "cycles: %u hw cycles", k_cycle_get_32()); - return 0; -} - -#if defined(CONFIG_INIT_STACKS) && defined(CONFIG_THREAD_STACK_INFO) && \ - defined(CONFIG_THREAD_MONITOR) -static void shell_tdata_dump(const struct k_thread *cthread, void *user_data) -{ - struct k_thread *thread = (struct k_thread *)cthread; - const struct shell *sh = (const struct shell *)user_data; - unsigned int pcnt; - size_t unused; - size_t size = thread->stack_info.size; - const char *tname; - int ret; - char state_str[32]; - -#ifdef CONFIG_THREAD_RUNTIME_STATS - k_thread_runtime_stats_t rt_stats_thread; - k_thread_runtime_stats_t rt_stats_all; -#endif - - tname = k_thread_name_get(thread); - - shell_print(sh, "%s%p %-10s", - (thread == k_current_get()) ? "*" : " ", - thread, - tname ? tname : "NA"); - /* Cannot use lld as it's less portable. */ - shell_print(sh, "\toptions: 0x%x, priority: %d timeout: %" PRId64, - thread->base.user_options, - thread->base.prio, - (int64_t)thread->base.timeout.dticks); - shell_print(sh, "\tstate: %s, entry: %p", - k_thread_state_str(thread, state_str, sizeof(state_str)), - thread->entry.pEntry); - -#ifdef CONFIG_SCHED_CPU_MASK - shell_print(sh, "\tcpu_mask: 0x%x", thread->base.cpu_mask); -#endif /* CONFIG_SCHED_CPU_MASK */ - -#ifdef CONFIG_THREAD_RUNTIME_STATS - ret = 0; - - if (k_thread_runtime_stats_get(thread, &rt_stats_thread) != 0) { - ret++; - } - - if (k_thread_runtime_stats_all_get(&rt_stats_all) != 0) { - ret++; - } - - if (ret == 0) { - pcnt = (rt_stats_thread.execution_cycles * 100U) / - rt_stats_all.execution_cycles; - - /* - * z_prf() does not support %llu by default unless - * CONFIG_MINIMAL_LIBC_LL_PRINTF=y. So do conditional - * compilation to avoid blindly enabling this kconfig - * so it won't increase RAM/ROM usage too much on 32-bit - * targets. - */ - shell_print(sh, "\tTotal execution cycles: %u (%u %%)", - (uint32_t)rt_stats_thread.execution_cycles, - pcnt); -#ifdef CONFIG_SCHED_THREAD_USAGE_ANALYSIS - shell_print(sh, "\tCurrent execution cycles: %u", - (uint32_t)rt_stats_thread.current_cycles); - shell_print(sh, "\tPeak execution cycles: %u", - (uint32_t)rt_stats_thread.peak_cycles); - shell_print(sh, "\tAverage execution cycles: %u", - (uint32_t)rt_stats_thread.average_cycles); -#endif - } else { - shell_print(sh, "\tTotal execution cycles: ? (? %%)"); -#ifdef CONFIG_SCHED_THREAD_USAGE_ANALYSIS - shell_print(sh, "\tCurrent execution cycles: ?"); - shell_print(sh, "\tPeak execution cycles: ?"); - shell_print(sh, "\tAverage execution cycles: ?"); -#endif - } -#endif - - ret = k_thread_stack_space_get(thread, &unused); - if (ret) { - shell_print(sh, - "Unable to determine unused stack size (%d)\n", - ret); - } else { - /* Calculate the real size reserved for the stack */ - pcnt = ((size - unused) * 100U) / size; - - shell_print(sh, - "\tstack size %zu, unused %zu, usage %zu / %zu (%u %%)\n", - size, unused, size - unused, size, pcnt); - } - -} - -static int cmd_kernel_thread_list(const struct shell *sh, size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); - - shell_print(sh, "Scheduler: %u since last call", sys_clock_elapsed()); - shell_print(sh, "Threads:"); - - /* - * Use the unlocked version as the callback itself might call - * arch_irq_unlock. - */ - k_thread_foreach_unlocked(shell_tdata_dump, (void *)sh); - - return 0; -} - -static void shell_stack_dump(const struct k_thread *thread, void *user_data) -{ - const struct shell *sh = (const struct shell *)user_data; - unsigned int pcnt; - size_t unused; - size_t size = thread->stack_info.size; - const char *tname; - int ret; - - ret = k_thread_stack_space_get(thread, &unused); - if (ret) { - shell_print(sh, - "Unable to determine unused stack size (%d)\n", - ret); - return; - } - - tname = k_thread_name_get((struct k_thread *)thread); - - /* Calculate the real size reserved for the stack */ - pcnt = ((size - unused) * 100U) / size; - - shell_print( - (const struct shell *)user_data, "%p %-" STRINGIFY(THREAD_MAX_NAM_LEN) "s " - "(real size %4zu):\tunused %4zu\tusage %4zu / %4zu (%2u %%)", - thread, tname ? tname : "NA", size, unused, size - unused, size, pcnt); -} - -K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, - CONFIG_ISR_STACK_SIZE); - -static int cmd_kernel_thread_stacks(const struct shell *sh, size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); - char pad[THREAD_MAX_NAM_LEN] = { 0 }; - - memset(pad, ' ', MAX((THREAD_MAX_NAM_LEN - strlen("IRQ 00")), 1)); - - /* - * Use the unlocked version as the callback itself might call - * arch_irq_unlock. - */ - k_thread_foreach_unlocked(shell_stack_dump, (void *)sh); - - /* Placeholder logic for interrupt stack until we have better - * kernel support, including dumping arch-specific exception-related - * stack buffers. - */ - unsigned int num_cpus = arch_num_cpus(); - - for (int i = 0; i < num_cpus; i++) { - size_t unused; - const uint8_t *buf = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]); - size_t size = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[i]); - int err = z_stack_space_get(buf, size, &unused); - - (void)err; - __ASSERT_NO_MSG(err == 0); - - shell_print(sh, - "%p IRQ %02d %s(real size %4zu):\tunused %4zu\tusage %4zu / %4zu (%2zu %%)", - &z_interrupt_stacks[i], i, pad, size, unused, size - unused, size, - ((size - unused) * 100U) / size); - } - - return 0; -} -#endif /* CONFIG_INIT_STACKS & CONFIG_THREAD_STACK_INFO & CONFIG_THREAD_MONITOR */ - -struct thread_entry { - const struct k_thread *const thread; - bool valid; -}; - -static void thread_valid_cb(const struct k_thread *cthread, void *user_data) -{ - struct thread_entry *entry = user_data; - - if (cthread == entry->thread) { - entry->valid = true; - } -} - -__maybe_unused -static bool thread_is_valid(const struct k_thread *thread) -{ - struct thread_entry entry = { - .thread = thread, - .valid = false, - }; - - k_thread_foreach(thread_valid_cb, &entry); - - return entry.valid; -} - -#if defined(CONFIG_ARCH_STACKWALK) - -static bool print_trace_address(void *arg, unsigned long ra) -{ - const struct shell *sh = arg; -#ifdef CONFIG_SYMTAB - uint32_t offset = 0; - const char *name = symtab_find_symbol_name(ra, &offset); - - shell_print(sh, "ra: %p [%s+0x%x]", (void *)ra, name, offset); -#else - shell_print(sh, "ra: %p", (void *)ra); -#endif - - return true; -} - -static int cmd_kernel_thread_unwind(const struct shell *sh, size_t argc, char **argv) -{ - struct k_thread *thread; - int err = 0; - - if (argc == 1) { - thread = _current; - } else { - thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); - if (err != 0) { - shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); - return err; - } - - if (!thread_is_valid(thread)) { - shell_error(sh, "Invalid thread id %p", (void *)thread); - return -EINVAL; - } - } - shell_print(sh, "Unwinding %p %s", (void *)thread, thread->name); - - arch_stack_walk(print_trace_address, (void *)sh, thread, NULL); - - return 0; -} - -#endif /* CONFIG_ARCH_STACKWALK */ - -#ifdef CONFIG_SCHED_CPU_MASK -static int cmd_kernel_thread_mask_clear(const struct shell *sh, size_t argc, char **argv) -{ - ARG_UNUSED(argc); - - int rc, err = 0; - struct k_thread *thread; - - thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); - if (err != 0) { - shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); - return err; - } - - if (!thread_is_valid(thread)) { - shell_error(sh, "Invalid thread id %p", (void *)thread); - return -EINVAL; - } - - rc = k_thread_cpu_mask_clear(thread); - if (rc != 0) { - shell_error(sh, "Failed - %d", rc); - } else { - shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, - thread->base.cpu_mask); - } - - return rc; -} - -static int cmd_kernel_thread_mask_enable_all(const struct shell *sh, size_t argc, char **argv) -{ - ARG_UNUSED(argc); - - int rc, err = 0; - struct k_thread *thread; - - thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); - if (err != 0) { - shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); - return err; - } - - if (!thread_is_valid(thread)) { - shell_error(sh, "Invalid thread id %p", (void *)thread); - return -EINVAL; - } - - rc = k_thread_cpu_mask_enable_all(thread); - if (rc != 0) { - shell_error(sh, "Failed - %d", rc); - } else { - shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, - thread->base.cpu_mask); - } - - return rc; -} - -static int cmd_kernel_thread_mask_enable(const struct shell *sh, size_t argc, char **argv) -{ - ARG_UNUSED(argc); - - int rc, cpu, err = 0; - struct k_thread *thread; - - thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); - if (err != 0) { - shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); - return err; - } - - if (!thread_is_valid(thread)) { - shell_error(sh, "Invalid thread id %p", (void *)thread); - return -EINVAL; - } - - cpu = (int)shell_strtol(argv[2], 10, &err); - if (err != 0) { - shell_error(sh, "Unable to parse CPU ID %s (err %d)", argv[2], err); - return err; - } - - rc = k_thread_cpu_mask_enable(thread, cpu); - if (rc != 0) { - shell_error(sh, "Failed - %d", rc); - } else { - shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, - thread->base.cpu_mask); - } - - return rc; -} - -static int cmd_kernel_thread_mask_disable(const struct shell *sh, size_t argc, char **argv) -{ - ARG_UNUSED(argc); - - int rc, cpu, err = 0; - struct k_thread *thread; - - thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); - if (err != 0) { - shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); - return err; - } - - if (!thread_is_valid(thread)) { - shell_error(sh, "Invalid thread id %p", (void *)thread); - return -EINVAL; - } - - cpu = (int)shell_strtol(argv[2], 10, &err); - if (err != 0) { - shell_error(sh, "Unable to parse CPU ID %s (err %d)", argv[2], err); - return err; - } - - rc = k_thread_cpu_mask_disable(thread, cpu); - if (rc != 0) { - shell_error(sh, "Failed - %d", rc); - } else { - shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, - thread->base.cpu_mask); - } - - return rc; -} - -SHELL_STATIC_SUBCMD_SET_CREATE(sub_kernel_thread_mask, - SHELL_CMD_ARG(clear, NULL, - "Sets all CPU enable masks to zero.\n" - "Usage: kernel thread mask clear ", - cmd_kernel_thread_mask_clear, 2, 0), - SHELL_CMD_ARG(enable_all, NULL, - "Sets all CPU enable masks to one.\n" - "Usage: kernel thread mask enable_all ", - cmd_kernel_thread_mask_enable_all, 2, 0), - SHELL_CMD_ARG(enable, NULL, - "Enable thread to run on specified CPU.\n" - "Usage: kernel thread mask enable ", - cmd_kernel_thread_mask_enable, 3, 0), - SHELL_CMD_ARG(disable, NULL, - "Prevent thread to run on specified CPU.\n" - "Usage: kernel thread mask disable ", - cmd_kernel_thread_mask_disable, 3, 0), - SHELL_SUBCMD_SET_END /* Array terminated. */ -); - -static int cmd_kernel_thread_pin(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(argc); - - int cpu, err = 0; - struct k_thread *thread; - - thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); - if (err != 0) { - shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); - return err; - } - - if (!thread_is_valid(thread)) { - shell_error(sh, "Invalid thread id %p", (void *)thread); - return -EINVAL; - } - - cpu = shell_strtoul(argv[2], 10, &err); - if (err != 0) { - shell_error(sh, "Unable to parse CPU ID %s (err %d)", argv[2], err); - return err; - } - - shell_print(sh, "Pinning %p %s to CPU %d", (void *)thread, thread->name, cpu); - err = k_thread_cpu_pin(thread, cpu); - if (err != 0) { - shell_error(sh, "Failed - %d", err); - } else { - shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, - thread->base.cpu_mask); - } - - return err; -} -#endif /* CONFIG_SCHED_CPU_MASK */ - -SHELL_STATIC_SUBCMD_SET_CREATE(sub_kernel_thread, -#if defined(CONFIG_INIT_STACKS) && defined(CONFIG_THREAD_STACK_INFO) && \ - defined(CONFIG_THREAD_MONITOR) - SHELL_CMD(stacks, NULL, "List threads stack usage.", cmd_kernel_thread_stacks), - SHELL_CMD(list, NULL, "List kernel threads.", cmd_kernel_thread_list), -#endif -#if defined(CONFIG_ARCH_STACKWALK) - SHELL_CMD_ARG(unwind, NULL, "Unwind a thread.", cmd_kernel_thread_unwind, 1, 1), -#endif /* CONFIG_ARCH_STACKWALK */ -#if defined(CONFIG_SCHED_CPU_MASK) - SHELL_CMD_ARG(mask, &sub_kernel_thread_mask, "Configure thread CPU mask affinity.", NULL, 2, - 0), - SHELL_CMD_ARG(pin, NULL, - "Pin thread to a CPU.\n" - "Usage: kernel pin ", - cmd_kernel_thread_pin, 3, 0), -#endif /* CONFIG_SCHED_CPU_MASK */ - SHELL_SUBCMD_SET_END /* Array terminated. */ -); - -#if defined(CONFIG_SYS_HEAP_RUNTIME_STATS) && (K_HEAP_MEM_POOL_SIZE > 0) -extern struct sys_heap _system_heap; - -static int cmd_kernel_heap(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); - - int err; - struct sys_memory_stats stats; - - err = sys_heap_runtime_stats_get(&_system_heap, &stats); - if (err) { - shell_error(sh, "Failed to read kernel system heap statistics (err %d)", err); - return -ENOEXEC; - } - - shell_print(sh, "free: %zu", stats.free_bytes); - shell_print(sh, "allocated: %zu", stats.allocated_bytes); - shell_print(sh, "max. allocated: %zu", stats.max_allocated_bytes); - - return 0; -} -#endif - -static int cmd_kernel_sleep(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(sh); - ARG_UNUSED(argc); - - uint32_t ms; - int err = 0; - - ms = shell_strtoul(argv[1], 10, &err); - - if (!err) { - k_msleep(ms); - } else { - shell_error(sh, "Unable to parse input (err %d)", err); - return err; - } - - return 0; -} - -#if defined(CONFIG_LOG_RUNTIME_FILTERING) -static int cmd_kernel_log_level_set(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); - int err = 0; - - uint8_t severity = shell_strtoul(argv[2], 10, &err); - - if (err) { - shell_error(sh, "Unable to parse log severity (err %d)", err); - - return err; - } - - if (severity > LOG_LEVEL_DBG) { - shell_error(sh, "Invalid log level: %d", severity); - shell_help(sh); - return SHELL_CMD_HELP_PRINTED; - } - - int source_id = log_source_id_get(argv[1]); - - /* log_filter_set() takes an int16_t for the source ID */ - if (source_id < 0) { - shell_error(sh, "Unable to find log source: %s", argv[1]); - } - - log_filter_set(NULL, 0, (int16_t)source_id, severity); - - return 0; -} -#endif - -#if defined(CONFIG_REBOOT) -static int cmd_kernel_reboot_warm(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); -#if (CONFIG_KERNEL_SHELL_REBOOT_DELAY > 0) - k_sleep(K_MSEC(CONFIG_KERNEL_SHELL_REBOOT_DELAY)); -#endif - sys_reboot(SYS_REBOOT_WARM); - return 0; -} - -static int cmd_kernel_reboot_cold(const struct shell *sh, - size_t argc, char **argv) -{ - ARG_UNUSED(argc); - ARG_UNUSED(argv); -#if (CONFIG_KERNEL_SHELL_REBOOT_DELAY > 0) - k_sleep(K_MSEC(CONFIG_KERNEL_SHELL_REBOOT_DELAY)); -#endif - sys_reboot(SYS_REBOOT_COLD); - return 0; -} - -SHELL_STATIC_SUBCMD_SET_CREATE(sub_kernel_reboot, - SHELL_CMD(cold, NULL, "Cold reboot.", cmd_kernel_reboot_cold), - SHELL_CMD(warm, NULL, "Warm reboot.", cmd_kernel_reboot_warm), - SHELL_SUBCMD_SET_END /* Array terminated. */ -); -#endif - -SHELL_STATIC_SUBCMD_SET_CREATE(sub_kernel, - SHELL_CMD(cycles, NULL, "Kernel cycles.", cmd_kernel_cycles), -#if defined(CONFIG_REBOOT) - SHELL_CMD(reboot, &sub_kernel_reboot, "Reboot.", cmd_kernel_reboot_cold), -#endif - SHELL_CMD(thread, &sub_kernel_thread, "Kernel threads.", NULL), -#if defined(CONFIG_SYS_HEAP_RUNTIME_STATS) && (K_HEAP_MEM_POOL_SIZE > 0) - SHELL_CMD(heap, NULL, "System heap usage statistics.", cmd_kernel_heap), -#endif - SHELL_CMD_ARG(uptime, NULL, "Kernel uptime. Can be called with the -p or --pretty options", - cmd_kernel_uptime, 1, 1), - SHELL_CMD(version, NULL, "Kernel version.", cmd_kernel_version), - SHELL_CMD_ARG(sleep, NULL, "ms", cmd_kernel_sleep, 2, 0), -#if defined(CONFIG_LOG_RUNTIME_FILTERING) - SHELL_CMD_ARG(log-level, NULL, " ", - cmd_kernel_log_level_set, 3, 0), -#endif - SHELL_SUBCMD_SET_END /* Array terminated. */ -); - -SHELL_CMD_REGISTER(kernel, &sub_kernel, "Kernel commands", NULL); diff --git a/subsys/shell/modules/kernel_service/CMakeLists.txt b/subsys/shell/modules/kernel_service/CMakeLists.txt new file mode 100644 index 000000000000000..0bc582df690ae96 --- /dev/null +++ b/subsys/shell/modules/kernel_service/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Meta Platforms +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + # Main command + kernel_shell.c + # Subcommand starts here + cycles.c + sleep.c + uptime.c + version.c +) + +# Conditional subcommands +zephyr_sources_ifdef(CONFIG_SYS_HEAP_RUNTIME_STATS heap.c) + +zephyr_sources_ifdef(CONFIG_LOG_RUNTIME_FILTERING log-level.c) + +zephyr_sources_ifdef(CONFIG_REBOOT reboot.c) + +add_subdirectory_ifdef(CONFIG_KERNEL_THREAD_SHELL thread) diff --git a/subsys/shell/modules/kernel_service/Kconfig b/subsys/shell/modules/kernel_service/Kconfig new file mode 100644 index 000000000000000..f0c276796991ae4 --- /dev/null +++ b/subsys/shell/modules/kernel_service/Kconfig @@ -0,0 +1,32 @@ +# Kernel service configuration options + +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config KERNEL_SHELL + bool "Kernel shell" + default y if !SHELL_MINIMAL + imply INIT_STACKS + imply THREAD_MONITOR + imply THREAD_NAME + imply THREAD_STACK_INFO + help + This shell provides access to basic kernel data like version, uptime + and other useful information. + +if KERNEL_SHELL + +config KERNEL_SHELL_REBOOT_DELAY + int "Delay between reception of shell reboot command and reboot (ms)" + depends on REBOOT + default 0 + help + This delay allows time for the shell to successfully echo the reboot + command input before the reboot abruptly terminates it. This can help + external systems that interact with the shell and require the reboot + command's echo to successfully complete to synchronise with the + device. + +rsource "thread/Kconfig" + +endif # KERNEL_SHELL diff --git a/subsys/shell/modules/kernel_service/cycles.c b/subsys/shell/modules/kernel_service/cycles.c new file mode 100644 index 000000000000000..d6b9da83fa4b000 --- /dev/null +++ b/subsys/shell/modules/kernel_service/cycles.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +static int cmd_kernel_cycles(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); + + shell_print(sh, "cycles: %u hw cycles", k_cycle_get_32()); + return 0; +} + +KERNEL_CMD_ADD(cycles, NULL, "Kernel cycles.", cmd_kernel_cycles); diff --git a/subsys/shell/modules/kernel_service/heap.c b/subsys/shell/modules/kernel_service/heap.c new file mode 100644 index 000000000000000..f6c5a050ed6f74d --- /dev/null +++ b/subsys/shell/modules/kernel_service/heap.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#if K_HEAP_MEM_POOL_SIZE > 0 +#include + +extern struct sys_heap _system_heap; + +static int cmd_kernel_heap(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); + + int err; + struct sys_memory_stats stats; + + err = sys_heap_runtime_stats_get(&_system_heap, &stats); + if (err) { + shell_error(sh, "Failed to read kernel system heap statistics (err %d)", err); + return -ENOEXEC; + } + + shell_print(sh, "free: %zu", stats.free_bytes); + shell_print(sh, "allocated: %zu", stats.allocated_bytes); + shell_print(sh, "max. allocated: %zu", stats.max_allocated_bytes); + + return 0; +} + +KERNEL_CMD_ADD(heap, NULL, "System heap usage statistics.", cmd_kernel_heap); + +#endif /* K_HEAP_MEM_POOL_SIZE > 0 */ diff --git a/subsys/shell/modules/kernel_service/kernel_shell.c b/subsys/shell/modules/kernel_service/kernel_shell.c new file mode 100644 index 000000000000000..1ac045a266d1e03 --- /dev/null +++ b/subsys/shell/modules/kernel_service/kernel_shell.c @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +SHELL_SUBCMD_SET_CREATE(kernel_cmds, (kernel)); +SHELL_CMD_REGISTER(kernel, &kernel_cmds, "Kernel commands", NULL); diff --git a/subsys/shell/modules/kernel_service/kernel_shell.h b/subsys/shell/modules/kernel_service/kernel_shell.h new file mode 100644 index 000000000000000..ca0523ad9ea6f81 --- /dev/null +++ b/subsys/shell/modules/kernel_service/kernel_shell.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SUBSYS_SHELL_MODULES_KERNEL_SERVICE_KERNEL_SHELL_H_ +#define ZEPHYR_SUBSYS_SHELL_MODULES_KERNEL_SERVICE_KERNEL_SHELL_H_ + +#include + +/* Add command to the set of kernel subcommands, see `SHELL_SUBCMD_ADD` */ +#define KERNEL_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, _mand, _opt) \ + SHELL_SUBCMD_ADD((kernel), _syntax, _subcmd, _help, _handler, _mand, _opt); + +#define KERNEL_CMD_ADD(_syntax, _subcmd, _help, _handler) \ + KERNEL_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, 0, 0); + +/* Add command to the set of `kernel thread` subcommands */ +#define KERNEL_THREAD_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, _mand, _opt) \ + SHELL_SUBCMD_ADD((thread), _syntax, _subcmd, _help, _handler, _mand, _opt); + +#define KERNEL_THREAD_CMD_ADD(_syntax, _subcmd, _help, _handler) \ + KERNEL_THREAD_CMD_ARG_ADD(_syntax, _subcmd, _help, _handler, 0, 0); + +/* Internal function to check if a thread pointer is valid */ +bool z_thread_is_valid(const struct k_thread *thread); + +#endif /* ZEPHYR_SUBSYS_SHELL_MODULES_KERNEL_SERVICE_KERNEL_SHELL_H_ */ diff --git a/subsys/shell/modules/kernel_service/log-level.c b/subsys/shell/modules/kernel_service/log-level.c new file mode 100644 index 000000000000000..70a3142d00b1766 --- /dev/null +++ b/subsys/shell/modules/kernel_service/log-level.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +static int cmd_kernel_log_level_set(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + + int err = 0; + + uint8_t severity = shell_strtoul(argv[2], 10, &err); + + if (err) { + shell_error(sh, "Unable to parse log severity (err %d)", err); + + return err; + } + + if (severity > LOG_LEVEL_DBG) { + shell_error(sh, "Invalid log level: %d", severity); + shell_help(sh); + return SHELL_CMD_HELP_PRINTED; + } + + int source_id = log_source_id_get(argv[1]); + + /* log_filter_set() takes an int16_t for the source ID */ + if (source_id < 0) { + shell_error(sh, "Unable to find log source: %s", argv[1]); + } + + log_filter_set(NULL, 0, (int16_t)source_id, severity); + + return 0; +} + +KERNEL_CMD_ARG_ADD(log_level, NULL, " ", cmd_kernel_log_level_set, 3, + 0); diff --git a/subsys/shell/modules/kernel_service/reboot.c b/subsys/shell/modules/kernel_service/reboot.c new file mode 100644 index 000000000000000..b537ea716ebda99 --- /dev/null +++ b/subsys/shell/modules/kernel_service/reboot.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +static int cmd_kernel_reboot_warm(const struct shell *sh, + size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); +#if (CONFIG_KERNEL_SHELL_REBOOT_DELAY > 0) + k_sleep(K_MSEC(CONFIG_KERNEL_SHELL_REBOOT_DELAY)); +#endif + sys_reboot(SYS_REBOOT_WARM); + return 0; +} + +static int cmd_kernel_reboot_cold(const struct shell *sh, + size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); +#if (CONFIG_KERNEL_SHELL_REBOOT_DELAY > 0) + k_sleep(K_MSEC(CONFIG_KERNEL_SHELL_REBOOT_DELAY)); +#endif + sys_reboot(SYS_REBOOT_COLD); + return 0; +} + +SHELL_STATIC_SUBCMD_SET_CREATE(sub_kernel_reboot, + SHELL_CMD(cold, NULL, "Cold reboot.", cmd_kernel_reboot_cold), + SHELL_CMD(warm, NULL, "Warm reboot.", cmd_kernel_reboot_warm), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); + +KERNEL_CMD_ADD(reboot, &sub_kernel_reboot, "Reboot.", cmd_kernel_reboot_cold); diff --git a/subsys/shell/modules/kernel_service/sleep.c b/subsys/shell/modules/kernel_service/sleep.c new file mode 100644 index 000000000000000..3931bb749442086 --- /dev/null +++ b/subsys/shell/modules/kernel_service/sleep.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +static int cmd_kernel_sleep(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + + uint32_t ms; + int err = 0; + + ms = shell_strtoul(argv[1], 10, &err); + + if (!err) { + k_msleep(ms); + } else { + shell_error(sh, "Unable to parse input (err %d)", err); + return err; + } + + return 0; +} + +KERNEL_CMD_ARG_ADD(sleep, NULL, "ms", cmd_kernel_sleep, 2, 0); diff --git a/subsys/shell/modules/kernel_service/thread/CMakeLists.txt b/subsys/shell/modules/kernel_service/thread/CMakeLists.txt new file mode 100644 index 000000000000000..25690a550d02771 --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Meta Platforms +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(../) + +# Main command +zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL thread.c) + +# Subcommands +zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_LIST list.c) + +zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_MASK mask.c) + +zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_MASK pin.c) + +zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_STACKS stacks.c) + +zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_UNWIND unwind.c) diff --git a/subsys/shell/modules/kernel_service/thread/Kconfig b/subsys/shell/modules/kernel_service/thread/Kconfig new file mode 100644 index 000000000000000..4a6ccf10981c727 --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/Kconfig @@ -0,0 +1,54 @@ +# Kernel thread configuration options + +# Copyright (c) 2024 Meta Platforms +# SPDX-License-Identifier: Apache-2.0 + +config KERNEL_THREAD_SHELL + bool + help + Internal helper macro to determine if the main `thread` command + should be compiled. + +config KERNEL_THREAD_SHELL_LIST + bool + default y + depends on INIT_STACKS + depends on THREAD_MONITOR + depends on THREAD_STACK_INFO + select KERNEL_THREAD_SHELL + help + Internal helper macro to compile the `list` subcommand + +config KERNEL_THREAD_SHELL_STACKS + bool + default y + depends on INIT_STACKS + depends on THREAD_MONITOR + depends on THREAD_STACK_INFO + select KERNEL_THREAD_SHELL + help + Internal helper macro to compile the `stacks` subcommand + +config KERNEL_THREAD_SHELL_MASK + bool + default y + depends on SCHED_CPU_MASK + select KERNEL_THREAD_SHELL + help + Internal helper macro to compile the `mask` subcommand + +config KERNEL_THREAD_SHELL_PIN + bool + default y + depends on SCHED_CPU_MASK + select KERNEL_THREAD_SHELL + help + Internal helper macro to compile the `pin` subcommand + +config KERNEL_THREAD_SHELL_UNWIND + bool + default y + depends on ARCH_STACKWALK + select KERNEL_THREAD_SHELL + help + Internal helper macro to compile the `unwind` subcommand diff --git a/subsys/shell/modules/kernel_service/thread/list.c b/subsys/shell/modules/kernel_service/thread/list.c new file mode 100644 index 000000000000000..655881342e2d34b --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/list.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include +#include + +static void shell_tdata_dump(const struct k_thread *cthread, void *user_data) +{ + struct k_thread *thread = (struct k_thread *)cthread; + const struct shell *sh = (const struct shell *)user_data; + unsigned int pcnt; + size_t unused; + size_t size = thread->stack_info.size; + const char *tname; + int ret; + char state_str[32]; + +#ifdef CONFIG_THREAD_RUNTIME_STATS + k_thread_runtime_stats_t rt_stats_thread; + k_thread_runtime_stats_t rt_stats_all; +#endif /* CONFIG_THREAD_RUNTIME_STATS */ + + tname = k_thread_name_get(thread); + + shell_print(sh, "%s%p %-10s", + (thread == k_current_get()) ? "*" : " ", + thread, + tname ? tname : "NA"); + /* Cannot use lld as it's less portable. */ + shell_print(sh, "\toptions: 0x%x, priority: %d timeout: %" PRId64, + thread->base.user_options, + thread->base.prio, + (int64_t)thread->base.timeout.dticks); + shell_print(sh, "\tstate: %s, entry: %p", + k_thread_state_str(thread, state_str, sizeof(state_str)), + thread->entry.pEntry); + +#ifdef CONFIG_SCHED_CPU_MASK + shell_print(sh, "\tcpu_mask: 0x%x", thread->base.cpu_mask); +#endif /* CONFIG_SCHED_CPU_MASK */ + +#ifdef CONFIG_THREAD_RUNTIME_STATS + ret = 0; + + if (k_thread_runtime_stats_get(thread, &rt_stats_thread) != 0) { + ret++; + } + + if (k_thread_runtime_stats_all_get(&rt_stats_all) != 0) { + ret++; + } + + if (ret == 0) { + pcnt = (rt_stats_thread.execution_cycles * 100U) / + rt_stats_all.execution_cycles; + + /* + * z_prf() does not support %llu by default unless + * CONFIG_MINIMAL_LIBC_LL_PRINTF=y. So do conditional + * compilation to avoid blindly enabling this kconfig + * so it won't increase RAM/ROM usage too much on 32-bit + * targets. + */ + shell_print(sh, "\tTotal execution cycles: %u (%u %%)", + (uint32_t)rt_stats_thread.execution_cycles, + pcnt); +#ifdef CONFIG_SCHED_THREAD_USAGE_ANALYSIS + shell_print(sh, "\tCurrent execution cycles: %u", + (uint32_t)rt_stats_thread.current_cycles); + shell_print(sh, "\tPeak execution cycles: %u", + (uint32_t)rt_stats_thread.peak_cycles); + shell_print(sh, "\tAverage execution cycles: %u", + (uint32_t)rt_stats_thread.average_cycles); +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ + } else { + shell_print(sh, "\tTotal execution cycles: ? (? %%)"); +#ifdef CONFIG_SCHED_THREAD_USAGE_ANALYSIS + shell_print(sh, "\tCurrent execution cycles: ?"); + shell_print(sh, "\tPeak execution cycles: ?"); + shell_print(sh, "\tAverage execution cycles: ?"); +#endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ + } +#endif /* CONFIG_THREAD_RUNTIME_STATS */ + + ret = k_thread_stack_space_get(thread, &unused); + if (ret) { + shell_print(sh, + "Unable to determine unused stack size (%d)\n", + ret); + } else { + /* Calculate the real size reserved for the stack */ + pcnt = ((size - unused) * 100U) / size; + + shell_print(sh, + "\tstack size %zu, unused %zu, usage %zu / %zu (%u %%)\n", + size, unused, size - unused, size, pcnt); + } + +} + +static int cmd_kernel_thread_list(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); + + shell_print(sh, "Scheduler: %u since last call", sys_clock_elapsed()); + shell_print(sh, "Threads:"); + + /* + * Use the unlocked version as the callback itself might call + * arch_irq_unlock. + */ + k_thread_foreach_unlocked(shell_tdata_dump, (void *)sh); + + return 0; +} + +KERNEL_THREAD_CMD_ADD(list, NULL, "List kernel threads.", cmd_kernel_thread_list); diff --git a/subsys/shell/modules/kernel_service/thread/mask.c b/subsys/shell/modules/kernel_service/thread/mask.c new file mode 100644 index 000000000000000..0da1ad39fa8af46 --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/mask.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +static int cmd_kernel_thread_mask_clear(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + + int rc, err = 0; + struct k_thread *thread; + + thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); + if (err != 0) { + shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); + return err; + } + + if (!z_thread_is_valid(thread)) { + shell_error(sh, "Invalid thread id %p", (void *)thread); + return -EINVAL; + } + + rc = k_thread_cpu_mask_clear(thread); + if (rc != 0) { + shell_error(sh, "Failed - %d", rc); + } else { + shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, + thread->base.cpu_mask); + } + + return rc; +} + +static int cmd_kernel_thread_mask_enable_all(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + + int rc, err = 0; + struct k_thread *thread; + + thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); + if (err != 0) { + shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); + return err; + } + + if (!z_thread_is_valid(thread)) { + shell_error(sh, "Invalid thread id %p", (void *)thread); + return -EINVAL; + } + + rc = k_thread_cpu_mask_enable_all(thread); + if (rc != 0) { + shell_error(sh, "Failed - %d", rc); + } else { + shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, + thread->base.cpu_mask); + } + + return rc; +} + +static int cmd_kernel_thread_mask_enable(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + + int rc, cpu, err = 0; + struct k_thread *thread; + + thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); + if (err != 0) { + shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); + return err; + } + + if (!z_thread_is_valid(thread)) { + shell_error(sh, "Invalid thread id %p", (void *)thread); + return -EINVAL; + } + + cpu = (int)shell_strtol(argv[2], 10, &err); + if (err != 0) { + shell_error(sh, "Unable to parse CPU ID %s (err %d)", argv[2], err); + return err; + } + + rc = k_thread_cpu_mask_enable(thread, cpu); + if (rc != 0) { + shell_error(sh, "Failed - %d", rc); + } else { + shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, + thread->base.cpu_mask); + } + + return rc; +} + +static int cmd_kernel_thread_mask_disable(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + + int rc, cpu, err = 0; + struct k_thread *thread; + + thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); + if (err != 0) { + shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); + return err; + } + + if (!z_thread_is_valid(thread)) { + shell_error(sh, "Invalid thread id %p", (void *)thread); + return -EINVAL; + } + + cpu = (int)shell_strtol(argv[2], 10, &err); + if (err != 0) { + shell_error(sh, "Unable to parse CPU ID %s (err %d)", argv[2], err); + return err; + } + + rc = k_thread_cpu_mask_disable(thread, cpu); + if (rc != 0) { + shell_error(sh, "Failed - %d", rc); + } else { + shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, + thread->base.cpu_mask); + } + + return rc; +} + +SHELL_STATIC_SUBCMD_SET_CREATE(sub_kernel_thread_mask, + SHELL_CMD_ARG(clear, NULL, + "Sets all CPU enable masks to zero.\n" + "Usage: kernel thread mask clear ", + cmd_kernel_thread_mask_clear, 2, 0), + SHELL_CMD_ARG(enable_all, NULL, + "Sets all CPU enable masks to one.\n" + "Usage: kernel thread mask enable_all ", + cmd_kernel_thread_mask_enable_all, 2, 0), + SHELL_CMD_ARG(enable, NULL, + "Enable thread to run on specified CPU.\n" + "Usage: kernel thread mask enable ", + cmd_kernel_thread_mask_enable, 3, 0), + SHELL_CMD_ARG(disable, NULL, + "Prevent thread to run on specified CPU.\n" + "Usage: kernel thread mask disable ", + cmd_kernel_thread_mask_disable, 3, 0), + SHELL_SUBCMD_SET_END /* Array terminated. */ +); + +KERNEL_THREAD_CMD_ARG_ADD(mask, &sub_kernel_thread_mask, "Configure thread CPU mask affinity.", + NULL, 2, 0); diff --git a/subsys/shell/modules/kernel_service/thread/pin.c b/subsys/shell/modules/kernel_service/thread/pin.c new file mode 100644 index 000000000000000..de70b7b58220008 --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/pin.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Meta Platforms + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +static int cmd_kernel_thread_pin(const struct shell *sh, + size_t argc, char **argv) +{ + ARG_UNUSED(argc); + + int cpu, err = 0; + struct k_thread *thread; + + thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); + if (err != 0) { + shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); + return err; + } + + if (!z_thread_is_valid(thread)) { + shell_error(sh, "Invalid thread id %p", (void *)thread); + return -EINVAL; + } + + cpu = shell_strtoul(argv[2], 10, &err); + if (err != 0) { + shell_error(sh, "Unable to parse CPU ID %s (err %d)", argv[2], err); + return err; + } + + shell_print(sh, "Pinning %p %s to CPU %d", (void *)thread, thread->name, cpu); + err = k_thread_cpu_pin(thread, cpu); + if (err != 0) { + shell_error(sh, "Failed - %d", err); + } else { + shell_print(sh, "%p %s cpu_mask: 0x%x", (void *)thread, thread->name, + thread->base.cpu_mask); + } + + return err; +} + +KERNEL_THREAD_CMD_ARG_ADD(pin, NULL, + "Pin thread to a CPU.\n" + "Usage: kernel pin ", + cmd_kernel_thread_pin, 3, 0); diff --git a/subsys/shell/modules/kernel_service/thread/stacks.c b/subsys/shell/modules/kernel_service/thread/stacks.c new file mode 100644 index 000000000000000..dc884516a5a9115 --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/stacks.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +#include + +#include + +#if defined(CONFIG_THREAD_MAX_NAME_LEN) +#define THREAD_MAX_NAM_LEN CONFIG_THREAD_MAX_NAME_LEN +#else +#define THREAD_MAX_NAM_LEN 10 +#endif + +static void shell_stack_dump(const struct k_thread *thread, void *user_data) +{ + const struct shell *sh = (const struct shell *)user_data; + unsigned int pcnt; + size_t unused; + size_t size = thread->stack_info.size; + const char *tname; + int ret; + + ret = k_thread_stack_space_get(thread, &unused); + if (ret) { + shell_print(sh, + "Unable to determine unused stack size (%d)\n", + ret); + return; + } + + tname = k_thread_name_get((struct k_thread *)thread); + + /* Calculate the real size reserved for the stack */ + pcnt = ((size - unused) * 100U) / size; + + shell_print( + (const struct shell *)user_data, "%p %-" STRINGIFY(THREAD_MAX_NAM_LEN) "s " + "(real size %4zu):\tunused %4zu\tusage %4zu / %4zu (%2u %%)", + thread, tname ? tname : "NA", size, unused, size - unused, size, pcnt); +} + +K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, + CONFIG_ISR_STACK_SIZE); + +static int cmd_kernel_thread_stacks(const struct shell *sh, size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); + char pad[THREAD_MAX_NAM_LEN] = { 0 }; + + memset(pad, ' ', MAX((THREAD_MAX_NAM_LEN - strlen("IRQ 00")), 1)); + + /* + * Use the unlocked version as the callback itself might call + * arch_irq_unlock. + */ + k_thread_foreach_unlocked(shell_stack_dump, (void *)sh); + + /* Placeholder logic for interrupt stack until we have better + * kernel support, including dumping arch-specific exception-related + * stack buffers. + */ + unsigned int num_cpus = arch_num_cpus(); + + for (int i = 0; i < num_cpus; i++) { + size_t unused; + const uint8_t *buf = K_KERNEL_STACK_BUFFER(z_interrupt_stacks[i]); + size_t size = K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[i]); + int err = z_stack_space_get(buf, size, &unused); + + (void)err; + __ASSERT_NO_MSG(err == 0); + + shell_print(sh, + "%p IRQ %02d %s(real size %4zu):\tunused %4zu\tusage %4zu / %4zu (%2zu %%)", + &z_interrupt_stacks[i], i, pad, size, unused, size - unused, size, + ((size - unused) * 100U) / size); + } + + return 0; +} + +KERNEL_THREAD_CMD_ADD(stacks, NULL, "List threads stack usage.", cmd_kernel_thread_stacks); diff --git a/subsys/shell/modules/kernel_service/thread/thread.c b/subsys/shell/modules/kernel_service/thread/thread.c new file mode 100644 index 000000000000000..dc9bf6ceec96480 --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/thread.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2024 Meta Platforms + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +#include +#include +#include + +struct thread_entry { + const struct k_thread *const thread; + bool valid; +}; + +static void thread_valid_cb(const struct k_thread *cthread, void *user_data) +{ + struct thread_entry *entry = user_data; + + if (cthread == entry->thread) { + entry->valid = true; + } +} + +bool z_thread_is_valid(const struct k_thread *thread) +{ + struct thread_entry entry = { + .thread = thread, + .valid = false, + }; + + k_thread_foreach(thread_valid_cb, &entry); + + return entry.valid; +} + +SHELL_SUBCMD_SET_CREATE(sub_kernel_thread, (thread)); +KERNEL_CMD_ADD(thread, &sub_kernel_thread, "Kernel threads.", NULL); diff --git a/subsys/shell/modules/kernel_service/thread/unwind.c b/subsys/shell/modules/kernel_service/thread/unwind.c new file mode 100644 index 000000000000000..e75df2d4864790b --- /dev/null +++ b/subsys/shell/modules/kernel_service/thread/unwind.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2024 Meta Platforms + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include +#include + +static bool print_trace_address(void *arg, unsigned long ra) +{ + const struct shell *sh = arg; +#ifdef CONFIG_SYMTAB + uint32_t offset = 0; + const char *name = symtab_find_symbol_name(ra, &offset); + + shell_print(sh, "ra: %p [%s+0x%x]", (void *)ra, name, offset); +#else + shell_print(sh, "ra: %p", (void *)ra); +#endif + + return true; +} + +static int cmd_kernel_thread_unwind(const struct shell *sh, size_t argc, char **argv) +{ + struct k_thread *thread; + int err = 0; + + if (argc == 1) { + thread = _current; + } else { + thread = UINT_TO_POINTER(shell_strtoull(argv[1], 16, &err)); + if (err != 0) { + shell_error(sh, "Unable to parse thread ID %s (err %d)", argv[1], err); + return err; + } + + if (!z_thread_is_valid(thread)) { + shell_error(sh, "Invalid thread id %p", (void *)thread); + return -EINVAL; + } + } + shell_print(sh, "Unwinding %p %s", (void *)thread, thread->name); + + arch_stack_walk(print_trace_address, (void *)sh, thread, NULL); + + return 0; +} + +KERNEL_THREAD_CMD_ARG_ADD(unwind, NULL, "Unwind a thread.", cmd_kernel_thread_unwind, 1, 1); diff --git a/subsys/shell/modules/kernel_service/uptime.c b/subsys/shell/modules/kernel_service/uptime.c new file mode 100644 index 000000000000000..c00f4f1607153b1 --- /dev/null +++ b/subsys/shell/modules/kernel_service/uptime.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +#define MINUTES_FACTOR (MSEC_PER_SEC * SEC_PER_MIN) +#define HOURS_FACTOR (MINUTES_FACTOR * MIN_PER_HOUR) +#define DAYS_FACTOR (HOURS_FACTOR * HOUR_PER_DAY) + +static int cmd_kernel_uptime(const struct shell *sh, size_t argc, char **argv) +{ + int64_t milliseconds = k_uptime_get(); + int64_t days; + int64_t hours; + int64_t minutes; + int64_t seconds; + + if (argc == 1) { + shell_print(sh, "Uptime: %llu ms", milliseconds); + return 0; + } + + /* No need to enable the getopt and getopt_long for just one option. */ + if (strcmp("-p", argv[1]) && strcmp("--pretty", argv[1]) != 0) { + shell_error(sh, "Unsupported option: %s", argv[1]); + return -EIO; + } + + days = milliseconds / DAYS_FACTOR; + milliseconds %= DAYS_FACTOR; + hours = milliseconds / HOURS_FACTOR; + milliseconds %= HOURS_FACTOR; + minutes = milliseconds / MINUTES_FACTOR; + milliseconds %= MINUTES_FACTOR; + seconds = milliseconds / MSEC_PER_SEC; + milliseconds = milliseconds % MSEC_PER_SEC; + + shell_print(sh, + "uptime: %llu days, %llu hours, %llu minutes, %llu seconds, %llu milliseconds", + days, hours, minutes, seconds, milliseconds); + + return 0; +} + +KERNEL_CMD_ARG_ADD(uptime, NULL, "Kernel uptime. Can be called with the -p or --pretty options", + cmd_kernel_uptime, 1, 1); diff --git a/subsys/shell/modules/kernel_service/version.c b/subsys/shell/modules/kernel_service/version.c new file mode 100644 index 000000000000000..fd1903cbc6679ad --- /dev/null +++ b/subsys/shell/modules/kernel_service/version.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA + * Copyright (c) 2016 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel_shell.h" + +#include + +static int cmd_kernel_version(const struct shell *sh, + size_t argc, char **argv) +{ + ARG_UNUSED(argc); + ARG_UNUSED(argv); + + shell_print(sh, "Zephyr version %s", KERNEL_VERSION_STRING); + return 0; +} + +KERNEL_CMD_ADD(version, NULL, "Kernel version.", cmd_kernel_version); From aa9446ca6bec779d1def8d9b06669930d8f7484f Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Wed, 28 Aug 2024 13:51:54 +0800 Subject: [PATCH 230/269] shell: modules: kernel: cleanup `thread list` subcmd Parts related to the thread runtime stats are somewhat standalone, refactor it out instead of having two #ifdef and two places. Signed-off-by: Yong Cong Sin Signed-off-by: Yong Cong Sin --- .../modules/kernel_service/thread/list.c | 71 ++++++++++--------- .../modules/kernel_service/thread/thread.c | 2 - .../modules/kernel_service/thread/unwind.c | 2 - 3 files changed, 37 insertions(+), 38 deletions(-) diff --git a/subsys/shell/modules/kernel_service/thread/list.c b/subsys/shell/modules/kernel_service/thread/list.c index 655881342e2d34b..b0a9304f8d6318b 100644 --- a/subsys/shell/modules/kernel_service/thread/list.c +++ b/subsys/shell/modules/kernel_service/thread/list.c @@ -10,43 +10,13 @@ #include #include -static void shell_tdata_dump(const struct k_thread *cthread, void *user_data) -{ - struct k_thread *thread = (struct k_thread *)cthread; - const struct shell *sh = (const struct shell *)user_data; - unsigned int pcnt; - size_t unused; - size_t size = thread->stack_info.size; - const char *tname; - int ret; - char state_str[32]; - #ifdef CONFIG_THREAD_RUNTIME_STATS +static void rt_stats_dump(const struct shell *sh, struct k_thread *thread) +{ k_thread_runtime_stats_t rt_stats_thread; k_thread_runtime_stats_t rt_stats_all; -#endif /* CONFIG_THREAD_RUNTIME_STATS */ - - tname = k_thread_name_get(thread); - - shell_print(sh, "%s%p %-10s", - (thread == k_current_get()) ? "*" : " ", - thread, - tname ? tname : "NA"); - /* Cannot use lld as it's less portable. */ - shell_print(sh, "\toptions: 0x%x, priority: %d timeout: %" PRId64, - thread->base.user_options, - thread->base.prio, - (int64_t)thread->base.timeout.dticks); - shell_print(sh, "\tstate: %s, entry: %p", - k_thread_state_str(thread, state_str, sizeof(state_str)), - thread->entry.pEntry); - -#ifdef CONFIG_SCHED_CPU_MASK - shell_print(sh, "\tcpu_mask: 0x%x", thread->base.cpu_mask); -#endif /* CONFIG_SCHED_CPU_MASK */ - -#ifdef CONFIG_THREAD_RUNTIME_STATS - ret = 0; + int ret = 0; + unsigned int pcnt; if (k_thread_runtime_stats_get(thread, &rt_stats_thread) != 0) { ret++; @@ -86,8 +56,41 @@ static void shell_tdata_dump(const struct k_thread *cthread, void *user_data) shell_print(sh, "\tAverage execution cycles: ?"); #endif /* CONFIG_SCHED_THREAD_USAGE_ANALYSIS */ } +} #endif /* CONFIG_THREAD_RUNTIME_STATS */ +static void shell_tdata_dump(const struct k_thread *cthread, void *user_data) +{ + struct k_thread *thread = (struct k_thread *)cthread; + const struct shell *sh = (const struct shell *)user_data; + unsigned int pcnt; + size_t unused; + size_t size = thread->stack_info.size; + const char *tname; + int ret; + char state_str[32]; + + tname = k_thread_name_get(thread); + + shell_print(sh, "%s%p %-10s", + (thread == k_current_get()) ? "*" : " ", + thread, + tname ? tname : "NA"); + /* Cannot use lld as it's less portable. */ + shell_print(sh, "\toptions: 0x%x, priority: %d timeout: %" PRId64, + thread->base.user_options, + thread->base.prio, + (int64_t)thread->base.timeout.dticks); + shell_print(sh, "\tstate: %s, entry: %p", + k_thread_state_str(thread, state_str, sizeof(state_str)), + thread->entry.pEntry); + +#ifdef CONFIG_SCHED_CPU_MASK + shell_print(sh, "\tcpu_mask: 0x%x", thread->base.cpu_mask); +#endif /* CONFIG_SCHED_CPU_MASK */ + + IF_ENABLED(CONFIG_THREAD_RUNTIME_STATS, (rt_stats_dump(sh, thread))); + ret = k_thread_stack_space_get(thread, &unused); if (ret) { shell_print(sh, diff --git a/subsys/shell/modules/kernel_service/thread/thread.c b/subsys/shell/modules/kernel_service/thread/thread.c index dc9bf6ceec96480..ecc0660138f2885 100644 --- a/subsys/shell/modules/kernel_service/thread/thread.c +++ b/subsys/shell/modules/kernel_service/thread/thread.c @@ -1,7 +1,5 @@ /* * Copyright (c) 2024 Meta Platforms - * Copyright (c) 2018 Nordic Semiconductor ASA - * Copyright (c) 2016 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/subsys/shell/modules/kernel_service/thread/unwind.c b/subsys/shell/modules/kernel_service/thread/unwind.c index e75df2d4864790b..903f05822b14a9a 100644 --- a/subsys/shell/modules/kernel_service/thread/unwind.c +++ b/subsys/shell/modules/kernel_service/thread/unwind.c @@ -1,7 +1,5 @@ /* * Copyright (c) 2024 Meta Platforms - * Copyright (c) 2018 Nordic Semiconductor ASA - * Copyright (c) 2016 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ From 53f547b7371fec71aa068db94203cef7b1a335a6 Mon Sep 17 00:00:00 2001 From: Luis Ubieda Date: Fri, 16 Aug 2024 17:32:59 -0400 Subject: [PATCH 231/269] serial: bluetooth: Maximize notification payload size based on ATT MTU By keeping track of run-time ATT MTU of all connected peers, it's possible to increase the notification payload size; thus increasing data-throughput sent over Bluetooth. Note that this assumes the Bluetooth connection is properly configured (with the corresponding connection parameters) to optimize performance. This is application-specific and shall be examined on each scenario for optimal performance. Signed-off-by: Luis Ubieda --- drivers/serial/uart_bt.c | 44 +++++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/serial/uart_bt.c b/drivers/serial/uart_bt.c index bb7207cfe2fe5ca..b90fb1bc5bb8688 100644 --- a/drivers/serial/uart_bt.c +++ b/drivers/serial/uart_bt.c @@ -18,6 +18,8 @@ LOG_MODULE_REGISTER(uart_nus, CONFIG_UART_LOG_LEVEL); K_THREAD_STACK_DEFINE(nus_work_queue_stack, CONFIG_UART_BT_WORKQUEUE_STACK_SIZE); static struct k_work_q nus_work_queue; +#define UART_BT_MTU_INVALID 0xFFFF + struct uart_bt_data { struct { struct bt_nus_inst *inst; @@ -78,6 +80,38 @@ static void bt_received(struct bt_conn *conn, const void *data, uint16_t len, vo k_work_submit_to_queue(&nus_work_queue, &dev_data->uart.cb_work); } +static void foreach_conn_handler_get_att_mtu(struct bt_conn *conn, void *data) +{ + uint16_t *min_att_mtu = (uint16_t *)data; + uint16_t conn_att_mtu = 0; + struct bt_conn_info conn_info; + int err; + + err = bt_conn_get_info(conn, &conn_info); + if (!err && conn_info.state == BT_CONN_STATE_CONNECTED) { + conn_att_mtu = bt_gatt_get_uatt_mtu(conn); + + if (conn_att_mtu > 0) { + *min_att_mtu = MIN(*min_att_mtu, conn_att_mtu); + } + } +} + +static inline uint16_t get_max_chunk_size(void) +{ + uint16_t min_att_mtu = UART_BT_MTU_INVALID; + + bt_conn_foreach(BT_CONN_TYPE_LE, foreach_conn_handler_get_att_mtu, &min_att_mtu); + + if (min_att_mtu == UART_BT_MTU_INVALID) { + /** Default ATT MTU */ + min_att_mtu = 23; + } + + /** ATT NTF Payload overhead: opcode (1 octet) + attribute (2 octets) */ + return (min_att_mtu - 1 - 2); +} + static void cb_work_handler(struct k_work *work) { struct uart_bt_data *dev_data = CONTAINER_OF(work, struct uart_bt_data, uart.cb_work); @@ -99,13 +133,13 @@ static void tx_work_handler(struct k_work *work) __ASSERT_NO_MSG(dev_data); + uint16_t chunk_size = get_max_chunk_size(); do { - /** Using Minimum MTU at this point to guarantee all connected - * peers will receive the data, without keeping track of MTU - * size per-connection. This has the trade-off of limiting - * throughput but allows multi-connection support. + /** The chunk size is based on the smallest MTU among all + * peers, and the same chunk is sent to everyone. This avoids + * managing separate read pointers: one per connection. */ - len = ring_buf_get_claim(dev_data->uart.tx_ringbuf, &data, 20); + len = ring_buf_get_claim(dev_data->uart.tx_ringbuf, &data, chunk_size); if (len > 0) { err = bt_nus_inst_send(NULL, dev_data->bt.inst, data, len); if (err) { From a8ae883e4d49c3ba9e73979a286968d21c8a2d1f Mon Sep 17 00:00:00 2001 From: Ryan McClelland Date: Tue, 17 Sep 2024 14:16:35 -0700 Subject: [PATCH 232/269] modules: tflite-micro: add batch_matmul.cc to cmakelists.txt batch_matmul.cc was missing from the CMakeLists.txt for tflite-micro. Add it. Signed-off-by: Ryan McClelland --- modules/tflite-micro/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/modules/tflite-micro/CMakeLists.txt b/modules/tflite-micro/CMakeLists.txt index 327038d84ae3821..c0893a7d807e0a4 100644 --- a/modules/tflite-micro/CMakeLists.txt +++ b/modules/tflite-micro/CMakeLists.txt @@ -91,6 +91,7 @@ if(CONFIG_TENSORFLOW_LITE_MICRO) ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/add_n.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/arg_min_max.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/assign_variable.cc + ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/batch_matmul.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/batch_to_space_nd.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/broadcast_args.cc ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/broadcast_to.cc From a9800e2ea7b1f14af8030b6c9927d69cedb2d64f Mon Sep 17 00:00:00 2001 From: Pisit Sawangvonganan Date: Mon, 16 Sep 2024 12:36:55 +0700 Subject: [PATCH 233/269] style: drivers: adjust `return` usage in `void functions` For code clarity, this commit adjusts the use of `return` statements in functions with a void return type as follows: - Transform `return foo();` into separate statements: `foo();` `return;` - Remove unnecessary `return` statements when they don't affect control flow. Signed-off-by: Pisit Sawangvonganan --- drivers/can/can_sja1000.c | 2 +- drivers/fpga/fpga_mpfs.c | 2 +- drivers/i2c/i2c_npcx_controller.c | 15 +++++++++------ drivers/i3c/i3c_npcx.c | 6 ++++-- drivers/serial/uart_cc13xx_cc26xx.c | 8 ++------ drivers/spi/spi_pw.c | 2 +- drivers/usb/udc/udc_nrf.c | 3 ++- drivers/wifi/nrfwifi/src/shim.c | 2 +- include/zephyr/drivers/can.h | 2 +- .../drivers/interrupt_controller/intel_vtd.h | 2 +- include/zephyr/drivers/sip_svc/sip_svc_driver.h | 2 +- include/zephyr/drivers/usb_c/usbc_tcpc.h | 4 ++-- 12 files changed, 26 insertions(+), 24 deletions(-) diff --git a/drivers/can/can_sja1000.c b/drivers/can/can_sja1000.c index 758715bb443034a..dcdb22d6f6bc1b2 100644 --- a/drivers/can/can_sja1000.c +++ b/drivers/can/can_sja1000.c @@ -23,7 +23,7 @@ static inline void can_sja1000_write_reg(const struct device *dev, uint8_t reg, { const struct can_sja1000_config *config = dev->config; - return config->write_reg(dev, reg, val); + config->write_reg(dev, reg, val); } static inline uint8_t can_sja1000_read_reg(const struct device *dev, uint8_t reg) diff --git a/drivers/fpga/fpga_mpfs.c b/drivers/fpga/fpga_mpfs.c index d8c777a45015e66..2a18950b2ec165d 100644 --- a/drivers/fpga/fpga_mpfs.c +++ b/drivers/fpga/fpga_mpfs.c @@ -58,7 +58,7 @@ static inline uint32_t scb_read(mm_reg_t add, mm_reg_t offset) static inline void scb_write(mm_reg_t add, mm_reg_t offset, uint32_t val) { - return sys_write32(val, add + offset); + sys_write32(val, add + offset); } /*This function add the index of new image into the spi directory at offset 0x004. diff --git a/drivers/i2c/i2c_npcx_controller.c b/drivers/i2c/i2c_npcx_controller.c index cf45a83ae2b7938..8adcf792e6af67d 100644 --- a/drivers/i2c/i2c_npcx_controller.c +++ b/drivers/i2c/i2c_npcx_controller.c @@ -593,7 +593,7 @@ static void i2c_ctrl_handle_write_int_event(const struct device *dev) } } - return i2c_ctrl_notify(dev, 0); + i2c_ctrl_notify(dev, 0); } static void i2c_ctrl_handle_read_int_event(const struct device *dev) @@ -667,7 +667,7 @@ static void i2c_ctrl_handle_read_int_event(const struct device *dev) data->oper_state = NPCX_I2C_READ_SUSPEND; } - return i2c_ctrl_notify(dev, 0); + i2c_ctrl_notify(dev, 0); } static int i2c_ctrl_proc_write_msg(const struct device *dev, @@ -871,7 +871,8 @@ static void i2c_ctrl_isr(const struct device *dev) #ifdef CONFIG_I2C_TARGET if (atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) { - return i2c_ctrl_target_isr(dev, status); + i2c_ctrl_target_isr(dev, status); + return; } #endif @@ -906,16 +907,18 @@ static void i2c_ctrl_isr(const struct device *dev) data->oper_state = NPCX_I2C_WAIT_STOP; /* No such device or address */ - return i2c_ctrl_notify(dev, -ENXIO); + i2c_ctrl_notify(dev, -ENXIO); + return; } /* START, tx FIFO empty or rx FIFO full has occurred */ if (IS_BIT_SET(status, NPCX_SMBST_SDAST)) { if (data->is_write) { - return i2c_ctrl_handle_write_int_event(dev); + i2c_ctrl_handle_write_int_event(dev); } else { - return i2c_ctrl_handle_read_int_event(dev); + i2c_ctrl_handle_read_int_event(dev); } + return; } /* Clear unexpected status bits */ diff --git a/drivers/i3c/i3c_npcx.c b/drivers/i3c/i3c_npcx.c index 5c19d17e8f7fa4f..9ace1040bdcde62 100644 --- a/drivers/i3c/i3c_npcx.c +++ b/drivers/i3c/i3c_npcx.c @@ -1776,7 +1776,8 @@ static void npcx_i3c_isr(const struct device *dev) /* MDMA write */ if (get_oper_state(dev) == NPCX_I3C_WR) { - return i3c_ctrl_notify(dev); + i3c_ctrl_notify(dev); + return; } } @@ -1785,7 +1786,8 @@ static void npcx_i3c_isr(const struct device *dev) /* MDMA read */ if (get_oper_state(dev) == NPCX_I3C_RD) { - return i3c_ctrl_notify(dev); + i3c_ctrl_notify(dev); + return; } } diff --git a/drivers/serial/uart_cc13xx_cc26xx.c b/drivers/serial/uart_cc13xx_cc26xx.c index e5bbf40b394d37e..ae74e74d8ce7f0a 100644 --- a/drivers/serial/uart_cc13xx_cc26xx.c +++ b/drivers/serial/uart_cc13xx_cc26xx.c @@ -339,18 +339,14 @@ static void uart_cc13xx_cc26xx_irq_err_enable(const struct device *dev) { const struct uart_cc13xx_cc26xx_config *config = dev->config; - return UARTIntEnable(config->reg, - UART_INT_OE | UART_INT_BE | UART_INT_PE | - UART_INT_FE); + UARTIntEnable(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); } static void uart_cc13xx_cc26xx_irq_err_disable(const struct device *dev) { const struct uart_cc13xx_cc26xx_config *config = dev->config; - return UARTIntDisable(config->reg, - UART_INT_OE | UART_INT_BE | UART_INT_PE | - UART_INT_FE); + UARTIntDisable(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); } static int uart_cc13xx_cc26xx_irq_is_pending(const struct device *dev) diff --git a/drivers/spi/spi_pw.c b/drivers/spi/spi_pw.c index 58fa33f0c799eb2..72268f588523454 100644 --- a/drivers/spi/spi_pw.c +++ b/drivers/spi/spi_pw.c @@ -31,7 +31,7 @@ static void spi_pw_reg_write(const struct device *dev, uint32_t offset, uint32_t val) { - return sys_write32(val, DEVICE_MMIO_GET(dev) + offset); + sys_write32(val, DEVICE_MMIO_GET(dev) + offset); } static void spi_pw_ssp_reset(const struct device *dev) diff --git a/drivers/usb/udc/udc_nrf.c b/drivers/usb/udc/udc_nrf.c index 4076713f6b13ff0..c6951074c854931 100644 --- a/drivers/usb/udc/udc_nrf.c +++ b/drivers/usb/udc/udc_nrf.c @@ -177,7 +177,8 @@ static void udc_event_xfer_in(const struct device *dev, udc_ep_set_busy(dev, ep, false); if (ep == USB_CONTROL_EP_IN) { - return udc_event_xfer_ctrl_in(dev, buf); + udc_event_xfer_ctrl_in(dev, buf); + return; } udc_submit_ep_event(dev, buf, 0); diff --git a/drivers/wifi/nrfwifi/src/shim.c b/drivers/wifi/nrfwifi/src/shim.c index 1c62d22905517b6..19660f727e7bd19 100644 --- a/drivers/wifi/nrfwifi/src/shim.c +++ b/drivers/wifi/nrfwifi/src/shim.c @@ -585,7 +585,7 @@ static void *zep_shim_work_alloc(int type) static void zep_shim_work_free(void *item) { - return work_free(item); + work_free(item); } static void zep_shim_work_init(void *item, void (*callback)(unsigned long data), diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h index 0d72cc64148525a..bea1715c27e0ef3 100644 --- a/include/zephyr/drivers/can.h +++ b/include/zephyr/drivers/can.h @@ -1425,7 +1425,7 @@ static inline void z_impl_can_remove_rx_filter(const struct device *dev, int fil { const struct can_driver_api *api = (const struct can_driver_api *)dev->api; - return api->remove_rx_filter(dev, filter_id); + api->remove_rx_filter(dev, filter_id); } /** diff --git a/include/zephyr/drivers/interrupt_controller/intel_vtd.h b/include/zephyr/drivers/interrupt_controller/intel_vtd.h index b91834c74a84480..ecf8681379ed8dc 100644 --- a/include/zephyr/drivers/interrupt_controller/intel_vtd.h +++ b/include/zephyr/drivers/interrupt_controller/intel_vtd.h @@ -215,7 +215,7 @@ static inline void vtd_set_irte_msi(const struct device *dev, const struct vtd_driver_api *api = (const struct vtd_driver_api *)dev->api; - return api->set_irte_msi(dev, irte_idx, msi); + api->set_irte_msi(dev, irte_idx, msi); } static inline bool vtd_irte_is_msi(const struct device *dev, diff --git a/include/zephyr/drivers/sip_svc/sip_svc_driver.h b/include/zephyr/drivers/sip_svc/sip_svc_driver.h index 07b8f7f8675419c..560b9a7953e901f 100644 --- a/include/zephyr/drivers/sip_svc/sip_svc_driver.h +++ b/include/zephyr/drivers/sip_svc/sip_svc_driver.h @@ -224,7 +224,7 @@ static inline void z_impl_sip_svc_plat_update_trans_id(const struct device *dev, "sip_svc_plat_update_trans_id func shouldn't be NULL"); __ASSERT(request, "request shouldn't be NULL"); - return api->sip_svc_plat_update_trans_id(dev, request, trans_id); + api->sip_svc_plat_update_trans_id(dev, request, trans_id); } /** diff --git a/include/zephyr/drivers/usb_c/usbc_tcpc.h b/include/zephyr/drivers/usb_c/usbc_tcpc.h index 7b94e3f93a88a5c..232906d710e5860 100644 --- a/include/zephyr/drivers/usb_c/usbc_tcpc.h +++ b/include/zephyr/drivers/usb_c/usbc_tcpc.h @@ -356,7 +356,7 @@ static inline void tcpc_set_vconn_cb(const struct device *dev, __ASSERT(api->set_vconn_cb != NULL, "Callback pointer should not be NULL"); - return api->set_vconn_cb(dev, vconn_cb); + api->set_vconn_cb(dev, vconn_cb); } /** @@ -378,7 +378,7 @@ static inline void tcpc_set_vconn_discharge_cb(const struct device *dev, __ASSERT(api->set_vconn_discharge_cb != NULL, "Callback pointer should not be NULL"); - return api->set_vconn_discharge_cb(dev, cb); + api->set_vconn_discharge_cb(dev, cb); } /** From 5dcc9370ec558d59d0e0115f8f8a401f93283363 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 00:47:52 +0200 Subject: [PATCH 234/269] boards: infineon: cyw920829m2: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x60000) don't match for > /qspi_flash@40890000/flash@60000000/partitions/storage_partition@70000 Signed-off-by: Reto Schneider --- boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts index 00c5c4decc422e2..83825dd8693ce2e 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts @@ -120,7 +120,7 @@ uart2: &scb2 { #address-cells = <1>; #size-cells = <1>; - storage_partition: storage_partition@70000 { + storage_partition: storage_partition@60000 { compatible = "soc-nv-flash"; reg = <0x60000 DT_SIZE_K(64)>; }; From f28ddf5a8e781c19862043872d4602787be61486 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 00:41:52 +0200 Subject: [PATCH 235/269] boards: nordic: nrf52805: Fix slot1_partition base address This prevents an overlap with `storage_partition` Additionally, it fixes the following warning: > unit address and first address in 'reg' (0x20000) don't match for > /soc/flash-controller@4001e000/flash@0/partitions/partition@19000 Signed-off-by: Reto Schneider --- boards/nordic/nrf52dk/nrf52dk_nrf52805.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts index 1f3e96ad7e554c5..fd84761fe1b8405 100644 --- a/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts @@ -144,9 +144,9 @@ label = "image-0"; reg = <0x0000C000 0xe000>; }; - slot1_partition: partition@19000 { + slot1_partition: partition@1a000 { label = "image-1"; - reg = <0x00020000 0xe000>; + reg = <0x0001a000 0xe000>; }; storage_partition: partition@28000 { label = "storage"; From 01418564bc6b51efb490124ebf94a4135815b56a Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Thu, 12 Sep 2024 13:25:18 +0300 Subject: [PATCH 236/269] boards: nxp: imx95_evk: add M7 DDR board variant Add DDR variant of the i.MX95 EVK board (M7 core). Using this variant, one can run Zephyr from DDR instead of ITCM/DTCM as it's the case for the M7 "base" board. Signed-off-by: Laurentiu Mihalcea --- boards/nxp/imx95_evk/Kconfig.imx95_evk | 2 +- boards/nxp/imx95_evk/board.yml | 2 ++ boards/nxp/imx95_evk/doc/index.rst | 28 ++++++++++++++++--- .../imx95_evk/imx95_evk_mimx9596_m7_ddr.dts | 23 +++++++++++++++ .../imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml | 18 ++++++++++++ .../imx95_evk_mimx9596_m7_ddr_defconfig | 22 +++++++++++++++ 6 files changed, 90 insertions(+), 5 deletions(-) create mode 100644 boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.dts create mode 100644 boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml create mode 100644 boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig diff --git a/boards/nxp/imx95_evk/Kconfig.imx95_evk b/boards/nxp/imx95_evk/Kconfig.imx95_evk index 5be2c15d2c0b60b..b37b19bdfc5b66e 100644 --- a/boards/nxp/imx95_evk/Kconfig.imx95_evk +++ b/boards/nxp/imx95_evk/Kconfig.imx95_evk @@ -2,6 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_IMX95_EVK - select SOC_MIMX9596_M7 if BOARD_IMX95_EVK_MIMX9596_M7 + select SOC_MIMX9596_M7 if BOARD_IMX95_EVK_MIMX9596_M7 || BOARD_IMX95_EVK_MIMX9596_M7_DDR select SOC_MIMX9596_A55 if BOARD_IMX95_EVK_MIMX9596_A55 || BOARD_IMX95_EVK_MIMX9596_A55_SMP select SOC_PART_NUMBER_MIMX9596AVZXN diff --git a/boards/nxp/imx95_evk/board.yml b/boards/nxp/imx95_evk/board.yml index 75001d3ffc18521..149090744573a8e 100644 --- a/boards/nxp/imx95_evk/board.yml +++ b/boards/nxp/imx95_evk/board.yml @@ -6,3 +6,5 @@ board: variants: - name: smp cpucluster: a55 + - name: ddr + cpucluster: m7 diff --git a/boards/nxp/imx95_evk/doc/index.rst b/boards/nxp/imx95_evk/doc/index.rst index 3b7a69ceece2684..078b0abcdac653c 100644 --- a/boards/nxp/imx95_evk/doc/index.rst +++ b/boards/nxp/imx95_evk/doc/index.rst @@ -224,26 +224,46 @@ multiple elements required, like ELE+V2X firmware, System Manager, TCM OEI, Cort image and so on. The steps making flash.bin and programming should refer to ``Getting Started with -MCUXpresso SDK for IMX95LPD5EVK-19.pdf`` in i.MX95 `MCUX SDK release`_. +MCUXpresso SDK for IMX95LPD5EVK-19.pdf`` in i.MX95 `MCUX SDK release`_. Note that +for the DDR variant, one should use the Makefile targets containing the ``ddr`` keyword. See ``4.2 Run an example application``, just rename ``zephyr.bin`` to ``m7_image.bin`` to make flash.bin and program to SD/eMMC. -Here is an example for the :zephyr:code-sample:`hello_world` application. +Zephyr supports two M7-based i.MX95 boards: ``imx95_evk/mimx9596/m7`` and +``imx95_evk/mimx9596/m7/ddr``. The main difference between them is the memory +used. ``imx95_evk/mimx9596/m7`` uses TCM (ITCM for code and, generally, read-only +data and DTCM for R/W data), while ``imx95_evk/mimx9596/m7/ddr`` uses DDR. + +1. Building the :zephyr:code-sample:`hello_world` application for the TCM-based board .. zephyr-app-commands:: :zephyr-app: samples/hello_world :board: imx95_evk/mimx9596/m7 :goals: build -After making flash.bin and program to SD/eMMC, open a serial terminal, reset the board, -and you should see the following message in the terminal: +2. Building the :zephyr:code-sample:`hello_world` application for the DDR-based board + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx95_evk/mimx9596/m7/ddr + :goals: build + +After making flash.bin and program to SD/eMMC, open a serial terminal, and reset the +board. For the ``imx95_evk/mimx9596/m7`` board you should see something like: .. code-block:: console *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 *** Hello World! imx95_evk/mimx9596/m7 +while, for the ``imx95_evk/mimx9596/m7/ddr`` board, you should get the following output: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-4569-g483c01ca11a7 *** + Hello World! imx95_evk/mimx9596/m7/ddr + .. _System Control and Management Interface (SCMI): https://developer.arm.com/documentation/den0056/latest/ diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.dts new file mode 100644 index 000000000000000..3590fccb970c15b --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "imx95_evk_mimx9596_m7.dts" + +/ { + model = "NXP i.MX95 EVK board DDR variant"; + + chosen { + zephyr,sram = &ddr; + /delete-property/ zephyr,flash; + }; + + ddr: memory@80000000 { + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(4)>; + }; +}; diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml new file mode 100644 index 000000000000000..b1f0b22dfc9f8d7 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx95_evk/mimx9596/m7/ddr +name: NXP i.MX95 EVK DDR variant +type: mcu +arch: arm +ram: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig new file mode 100644 index 000000000000000..f89de52c0365c70 --- /dev/null +++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig @@ -0,0 +1,22 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial interface-related configurations +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y + +# SCMI-related configurations +CONFIG_MBOX=y +CONFIG_MBOX_INIT_PRIORITY=0 +CONFIG_ARM_SCMI=y + +# kernel-related configurations +CONFIG_XIP=n From 4f93c84a94cf15945a09cc8d55036151f9901f1a Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Thu, 20 Jun 2024 14:47:02 +0900 Subject: [PATCH 237/269] hostap: add AP network security type DPP Add DPP security type for AP DPP support. Signed-off-by: Fengming Ye --- include/zephyr/net/wifi.h | 6 ++++-- modules/hostap/src/supp_api.c | 19 +++++++++++++++++++ subsys/net/l2/wifi/wifi_shell.c | 4 ++-- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/include/zephyr/net/wifi.h b/include/zephyr/net/wifi.h index f719ebf52b0d88d..f8a2645f558b809 100644 --- a/include/zephyr/net/wifi.h +++ b/include/zephyr/net/wifi.h @@ -66,12 +66,14 @@ enum wifi_security_type { WIFI_SECURITY_TYPE_WPA_PSK, /** WPA/WPA2/WPA3 PSK security. */ WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL, + /** DPP security */ + WIFI_SECURITY_TYPE_DPP, -/** @cond INTERNAL_HIDDEN */ + /** @cond INTERNAL_HIDDEN */ __WIFI_SECURITY_TYPE_AFTER_LAST, WIFI_SECURITY_TYPE_MAX = __WIFI_SECURITY_TYPE_AFTER_LAST - 1, WIFI_SECURITY_TYPE_UNKNOWN -/** @endcond */ + /** @endcond */ }; /** Helper function to get user-friendly security type name. */ diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index c2c34b81b8a6e34..aa78968a69f5a1c 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -1373,6 +1373,25 @@ int hapd_config_network(struct hostapd_iface *iface, goto out; } iface->bss[0]->conf->sae_pwe = 2; + } else if (params->security == WIFI_SECURITY_TYPE_DPP) { + if (!hostapd_cli_cmd_v("set wpa 2")) { + goto out; + } + if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK DPP")) { + goto out; + } + if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) { + goto out; + } + if (!hostapd_cli_cmd_v("set wpa_pairwise CCMP")) { + goto out; + } + if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) { + goto out; + } + if (!hostapd_cli_cmd_v("set dpp_configurator_connectivity 1")) { + goto out; + } } } else { if (!hostapd_cli_cmd_v("set wpa 0")) { diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 9b25f2f65f838e0..24af79c46aca3c1 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -2539,7 +2539,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_cmd_ap, "-p --passphrase= (valid only for secure SSIDs)\n" "-k --key-mgmt= (valid only for secure SSIDs)\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE, 4:WAPI, 5:EAP-TLS, 6:WEP\n" - "7: WPA-PSK\n" + "7: WPA-PSK, 11: DPP\n" "-w --ieee-80211w= (optional: needs security type to be specified)\n" "0:Disable, 1:Optional, 2:Required\n" "-b --band= (2 -2.6GHz, 5 - 5Ghz, 6 - 6GHz)\n" @@ -2657,7 +2657,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(wifi_commands, "[-p, --psk]: Passphrase (valid only for secure SSIDs)\n" "[-k, --key-mgmt]: Key Management type (valid only for secure SSIDs)\n" "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE-HNP, 4:SAE-H2E, 5:SAE-AUTO, 6:WAPI," - " 7:EAP-TLS, 8:WEP, 9: WPA-PSK, 10: WPA-Auto-Personal\n" + " 7:EAP-TLS, 8:WEP, 9: WPA-PSK, 10: WPA-Auto-Personal, 11: DPP\n" "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n" ": 0:Disable, 1:Optional, 2:Required.\n" "[-m, --bssid]: MAC address of the AP (BSSID).\n" From a1eee8ac0c4a9be31aee3d8b2e554777d99fc6d8 Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Thu, 20 Jun 2024 14:55:17 +0900 Subject: [PATCH 238/269] hostap: add AP DPP dispatch mgmt api Add hostapd mgmt ops, some use same api as wpa_supplicant, and DPP use different ops. supplicant_dpp_dispatch use wpa_cli and hapd_dpp_dispatch use hostapd_cli. And use common DPP param parse. Signed-off-by: Fengming Ye --- modules/hostap/src/supp_api.c | 80 ++++++++++++++++++++++++++++------ modules/hostap/src/supp_api.h | 16 +++++-- modules/hostap/src/supp_main.c | 14 +++++- 3 files changed, 93 insertions(+), 17 deletions(-) diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index aa78968a69f5a1c..941c55ca821d973 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -1695,16 +1695,10 @@ static void dpp_ssid_bin2str(char *dst, uint8_t *src, int max_len) #define SUPPLICANT_DPP_CMD_BUF_SIZE 384 #define STR_CUR_TO_END(cur) (cur) = (&(cur)[0] + strlen((cur))) -int supplicant_dpp_dispatch(const struct device *dev, - struct wifi_dpp_params *params) +static int dpp_params_to_cmd(struct wifi_dpp_params *params, char *cmd, size_t max_len) { - char *pos; - static char dpp_cmd_buf[SUPPLICANT_DPP_CMD_BUF_SIZE] = {0}; - char *end = &dpp_cmd_buf[SUPPLICANT_DPP_CMD_BUF_SIZE - 2]; - - memset(dpp_cmd_buf, 0x0, SUPPLICANT_DPP_CMD_BUF_SIZE); - - pos = &dpp_cmd_buf[0]; + char *pos = cmd; + char *end = cmd + max_len; switch (params->action) { case WIFI_DPP_CONFIGURATOR_ADD: @@ -1882,12 +1876,72 @@ int supplicant_dpp_dispatch(const struct device *dev, break; default: wpa_printf(MSG_ERROR, "Unknown DPP action"); - return -1; + return -EINVAL; } - wpa_printf(MSG_DEBUG, "%s", dpp_cmd_buf); - if (zephyr_wpa_cli_cmd_resp(dpp_cmd_buf, params->resp)) { - return -1; + return 0; +} + +int supplicant_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params) +{ + int ret; + char *cmd = NULL; + + if (params == NULL) { + return -EINVAL; + } + + cmd = os_zalloc(SUPPLICANT_DPP_CMD_BUF_SIZE); + if (cmd == NULL) { + return -ENOMEM; + } + + /* leave one byte always be 0 */ + ret = dpp_params_to_cmd(params, cmd, SUPPLICANT_DPP_CMD_BUF_SIZE - 2); + if (ret) { + os_free(cmd); + return ret; + } + + wpa_printf(MSG_DEBUG, "wpa_cli %s", cmd); + if (zephyr_wpa_cli_cmd_resp(cmd, params->resp)) { + os_free(cmd); + return -ENOEXEC; } + + os_free(cmd); + return 0; +} + +#ifdef CONFIG_WIFI_NM_HOSTAPD_AP +int hapd_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params) +{ + int ret; + char *cmd = NULL; + + if (params == NULL) { + return -EINVAL; + } + + cmd = os_zalloc(SUPPLICANT_DPP_CMD_BUF_SIZE); + if (cmd == NULL) { + return -ENOMEM; + } + + /* leave one byte always be 0 */ + ret = dpp_params_to_cmd(params, cmd, SUPPLICANT_DPP_CMD_BUF_SIZE - 2); + if (ret) { + os_free(cmd); + return ret; + } + + wpa_printf(MSG_DEBUG, "hostapd_cli %s", cmd); + if (zephyr_hostapd_cli_cmd_resp(cmd, params->resp)) { + os_free(cmd); + return -ENOEXEC; + } + + os_free(cmd); return 0; } +#endif /* CONFIG_WIFI_NM_HOSTAPD_AP */ diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h index 99905cfa6742f5c..bfc3a2735e64e99 100644 --- a/modules/hostap/src/supp_api.h +++ b/modules/hostap/src/supp_api.h @@ -261,12 +261,22 @@ int supplicant_ap_sta_disconnect(const struct device *dev, #endif /* CONFIG_AP */ /** - * @brief Dispatch DPP operations + * @brief Dispatch DPP operations for STA * * @param dev Wi-Fi interface name to use * @param dpp_params DPP action enum and params in string * @return 0 for OK; -1 for ERROR */ -int supplicant_dpp_dispatch(const struct device *dev, - struct wifi_dpp_params *params); +int supplicant_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params); + +#ifdef CONFIG_WIFI_NM_HOSTAPD_AP +/** + * @brief Dispatch DPP operations for AP + * + * @param dev Wi-Fi interface name to use + * @param dpp_params DPP action enum and params in string + * @return 0 for OK; -1 for ERROR + */ +int hapd_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params); +#endif /* CONFIG_WIFI_NM_HOSTAPD_AP */ #endif /* ZEPHYR_SUPP_MGMT_H */ diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 39b11ae9913ec91..1cacd9c2559f1ee 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -88,8 +88,20 @@ static const struct wifi_mgmt_ops mgmt_ops = { }; DEFINE_WIFI_NM_INSTANCE(wifi_supplicant, &mgmt_ops); + #ifdef CONFIG_WIFI_NM_HOSTAPD_AP -DEFINE_WIFI_NM_INSTANCE(hostapd, &mgmt_ops); +static const struct wifi_mgmt_ops mgmt_ap_ops = { + .set_btwt = supplicant_set_btwt, + .ap_enable = supplicant_ap_enable, + .ap_disable = supplicant_ap_disable, + .ap_sta_disconnect = supplicant_ap_sta_disconnect, + .ap_bandwidth = supplicant_ap_bandwidth, +#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP + .dpp_dispatch = hapd_dpp_dispatch, +#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */ +}; + +DEFINE_WIFI_NM_INSTANCE(hostapd, &mgmt_ap_ops); #endif #define WRITE_TIMEOUT 100 /* ms */ From 5e9377e051bdb9c0f73789e97bb62b0f445fc3de Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Thu, 20 Jun 2024 15:00:38 +0900 Subject: [PATCH 239/269] hostap: add AP DPP wpa_msg event handler Hostapd has TODO in hostapd_dpp_handle_config_obj, to save DPP connector using wpa_msg. AP DPP needs to use dpp_connector, dpp_netaccesskey and dpp_csign in DPP Peer Discovery handshake in hostapd_dpp_rx_peer_disc_req. So add AP DPP wpa_msg event handler to store these info. Signed-off-by: Fengming Ye --- modules/hostap/src/supp_events.c | 39 ++++++++++++++++++++++++++++++++ modules/hostap/src/supp_events.h | 3 +++ 2 files changed, 42 insertions(+) diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c index d666a60e025239b..617779b4d441653 100644 --- a/modules/hostap/src/supp_events.c +++ b/modules/hostap/src/supp_events.c @@ -437,3 +437,42 @@ int supplicant_generate_state_event(const char *ifname, return 0; } + +#if defined(CONFIG_WIFI_NM_HOSTAPD_AP) && defined(CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP) +void hostapd_handle_dpp_event(void *ctx, char *buf, size_t len) +{ + struct hostapd_data *hapd = (struct hostapd_data *)ctx; + + if (hapd == NULL) { + return; + } + + struct hostapd_bss_config *conf = hapd->conf; + + if (conf == NULL || !(conf->wpa_key_mgmt & WPA_KEY_MGMT_DPP)) { + return; + } + + /* check hostapd */ + if (!strncmp(buf, DPP_EVENT_CONNECTOR, sizeof(DPP_EVENT_CONNECTOR) - 1)) { + if (conf->dpp_connector) { + os_free(conf->dpp_connector); + } + + conf->dpp_connector = os_strdup(buf + sizeof(DPP_EVENT_CONNECTOR) - 1); + } else if (!strncmp(buf, DPP_EVENT_C_SIGN_KEY, sizeof(DPP_EVENT_C_SIGN_KEY) - 1)) { + if (conf->dpp_csign) { + wpabuf_free(conf->dpp_csign); + } + + conf->dpp_csign = wpabuf_parse_bin(buf + sizeof(DPP_EVENT_C_SIGN_KEY) - 1); + } else if (!strncmp(buf, DPP_EVENT_NET_ACCESS_KEY, sizeof(DPP_EVENT_NET_ACCESS_KEY) - 1)) { + if (conf->dpp_netaccesskey) { + wpabuf_free(conf->dpp_netaccesskey); + } + + conf->dpp_netaccesskey = + wpabuf_parse_bin(buf + sizeof(DPP_EVENT_NET_ACCESS_KEY) - 1); + } +} +#endif /* CONFIG_WIFI_NM_HOSTAPD_AP && CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */ diff --git a/modules/hostap/src/supp_events.h b/modules/hostap/src/supp_events.h index dc922940d788227..308a9e49734d510 100644 --- a/modules/hostap/src/supp_events.h +++ b/modules/hostap/src/supp_events.h @@ -63,6 +63,9 @@ int supplicant_send_wifi_mgmt_ap_sta_event(void *ctx, enum net_event_wifi_cmd event, void *data); #endif /* CONFIG_AP */ +#if defined(CONFIG_WIFI_NM_HOSTAPD_AP) && defined(CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP) +void hostapd_handle_dpp_event(void *ctx, char *buf, size_t len); +#endif #define REASON_CODE_LEN 18 #define NM_WIFI_EVENT_STR_LEN 64 From 0961928b3a6b665a071e0cf0d4eca2949f85db3b Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Thu, 20 Jun 2024 15:09:45 +0900 Subject: [PATCH 240/269] hostap: add dispatch for hostapd and wpa_supplicant wpa_msg When we have coexistence of hostapd and wpa_supplicant, wpa_msg has different implementation. So to let them work together, we need to have common implementation for wpa_msg and dispatch msgs for hostapd and wpa_supplicant. So add register zephyr_hostap_ctrl_iface_msg_cb, and judge if ctx is hostapd by the first integer where ctx points to. Signed-off-by: Fengming Ye --- modules/hostap/src/supp_main.c | 44 ++++++++++++++++++++++++++++++++++ modules/hostap/src/supp_main.h | 3 +++ 2 files changed, 47 insertions(+) diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c index 1cacd9c2559f1ee..a4b25b354765beb 100644 --- a/modules/hostap/src/supp_main.c +++ b/modules/hostap/src/supp_main.c @@ -134,6 +134,9 @@ static struct hapd_global hglobal; #define HOSTAPD_CLEANUP_INTERVAL 10 #endif /* HOSTAPD_CLEANUP_INTERVAL */ +static void zephyr_hostap_ctrl_iface_msg_cb(void *ctx, int level, enum wpa_msg_type type, + const char *txt, size_t len); + static int hostapd_periodic_call(struct hostapd_iface *iface, void *ctx) { hostapd_periodic_iface(iface); @@ -333,6 +336,9 @@ static int add_interface(struct supplicant_context *ctx, struct net_if *iface) supplicant_generate_state_event(ifname, NET_EVENT_SUPPLICANT_CMD_READY, 0); } +#ifdef CONFIG_WIFI_NM_HOSTAPD_AP + wpa_msg_register_cb(zephyr_hostap_ctrl_iface_msg_cb); +#endif ret = 0; out: @@ -954,6 +960,8 @@ static struct hostapd_iface *hostapd_interface_init(struct hapd_interfaces *inte return NULL; } + iface->bss[0]->is_hostapd = 1; + return iface; } @@ -1052,6 +1060,41 @@ static void zephyr_hostapd_init(struct supplicant_context *ctx) out: return; } + +static const char *zephyr_hostap_msg_ifname_cb(void *ctx) +{ + if (ctx == NULL) { + return NULL; + } + + if ((*((int *)ctx)) == 0) { + struct wpa_supplicant *wpa_s = ctx; + + return wpa_s->ifname; + } + + struct hostapd_data *hapd = ctx; + + if (hapd && hapd->conf) { + return hapd->conf->iface; + } + + return NULL; +} + +static void zephyr_hostap_ctrl_iface_msg_cb(void *ctx, int level, enum wpa_msg_type type, + const char *txt, size_t len) +{ + if (ctx == NULL) { + return; + } + + if ((*((int *)ctx)) == 0) { + wpa_supplicant_msg_send(ctx, level, type, txt, len); + } else { + hostapd_msg_send(ctx, level, type, txt, len); + } +} #endif static void handler(void) @@ -1107,6 +1150,7 @@ static void handler(void) #ifdef CONFIG_WIFI_NM_HOSTAPD_AP zephyr_hostapd_init(ctx); + wpa_msg_register_ifname_cb(zephyr_hostap_msg_ifname_cb); #endif (void)wpa_supplicant_run(ctx->supplicant); diff --git a/modules/hostap/src/supp_main.h b/modules/hostap/src/supp_main.h index 7fc03fd9140b0c8..03f7461555e4957 100644 --- a/modules/hostap/src/supp_main.h +++ b/modules/hostap/src/supp_main.h @@ -23,6 +23,9 @@ struct wpa_global *zephyr_get_default_supplicant_context(void); struct wpa_supplicant *zephyr_get_handle_by_ifname(const char *ifname); #ifdef CONFIG_WIFI_NM_HOSTAPD_AP struct hostapd_iface *zephyr_get_hapd_handle_by_ifname(const char *ifname); +void wpa_supplicant_msg_send(void *ctx, int level, enum wpa_msg_type type, const char *txt, + size_t len); +void hostapd_msg_send(void *ctx, int level, enum wpa_msg_type type, const char *buf, size_t len); #endif struct wpa_supplicant_event_msg { #ifdef CONFIG_WIFI_NM_HOSTAPD_AP From 23d2281d6a723afeaff05c803f5a5dbcd16d27d3 Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Fri, 30 Aug 2024 16:26:35 +0900 Subject: [PATCH 241/269] wifi: shell: add AP DPP shell commands Add AP DPP shell commands by expanding wifi_cmd_dpp. Signed-off-by: Fengming Ye --- subsys/net/l2/wifi/wifi_shell.c | 122 ++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 24af79c46aca3c1..070420afc0852ef 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -2514,6 +2514,108 @@ static int cmd_wifi_dpp_resp_timeout_set(const struct shell *sh, size_t argc, ch return 0; } +static int cmd_wifi_dpp_ap_btstrap_gen(const struct shell *sh, size_t argc, char *argv[]) +{ + int ret; + struct net_if *iface = net_if_get_wifi_sap(); + struct wifi_dpp_params params = {0}; + + params.action = WIFI_DPP_BOOTSTRAP_GEN; + + ret = parse_dpp_args_btstrap_gen(sh, argc, argv, ¶ms); + if (ret) { + PR_ERROR("parse DPP args fail\n"); + return -EINVAL; + } + + if (net_mgmt(NET_REQUEST_WIFI_DPP, iface, ¶ms, sizeof(params))) { + PR_WARNING("Failed to request DPP action\n"); + return -ENOEXEC; + } + return 0; +} + +static int cmd_wifi_dpp_ap_btstrap_get_uri(const struct shell *sh, size_t argc, char *argv[]) +{ + int ret = 0; + struct net_if *iface = net_if_get_wifi_sap(); + struct wifi_dpp_params params = {0}; + + params.action = WIFI_DPP_BOOTSTRAP_GET_URI; + + if (argc >= 2) { + params.id = shell_strtol(argv[1], 10, &ret); + } + + if (ret) { + PR_ERROR("parse DPP args fail\n"); + return -EINVAL; + } + + if (net_mgmt(NET_REQUEST_WIFI_DPP, iface, ¶ms, sizeof(params))) { + PR_WARNING("Failed to request DPP action\n"); + return -ENOEXEC; + } + return 0; +} + +static int cmd_wifi_dpp_ap_qr_code(const struct shell *sh, size_t argc, char *argv[]) +{ + struct net_if *iface = net_if_get_wifi_sap(); + struct wifi_dpp_params params = {0}; + + params.action = WIFI_DPP_QR_CODE; + + if (argc >= 2) { + strncpy(params.dpp_qr_code, argv[1], WIFI_DPP_QRCODE_MAX_LEN); + } + + if (net_mgmt(NET_REQUEST_WIFI_DPP, iface, ¶ms, sizeof(params))) { + PR_WARNING("Failed to request DPP action\n"); + return -ENOEXEC; + } + return 0; +} + +static int cmd_wifi_dpp_ap_auth_init(const struct shell *sh, size_t argc, char *argv[]) +{ + int ret = 0; + struct net_if *iface = net_if_get_wifi_sap(); + struct wifi_dpp_params params = {0}; + int opt; + int opt_index = 0; + struct getopt_state *state; + static struct option long_options[] = {{"peer", required_argument, 0, 'p'}, {0, 0, 0, 0}}; + + params.action = WIFI_DPP_AUTH_INIT; + + while ((opt = getopt_long(argc, argv, "p:", long_options, &opt_index)) != -1) { + state = getopt_state_get(); + switch (opt) { + case 'p': + params.auth_init.peer = shell_strtol(optarg, 10, &ret); + break; + default: + PR_ERROR("Invalid option %c\n", optopt); + return -EINVAL; + } + + if (ret) { + PR_ERROR("Invalid argument %d ret %d\n", opt_index, ret); + return -EINVAL; + } + } + + /* AP DPP auth only act as enrollee */ + params.auth_init.role = WIFI_DPP_ROLE_ENROLLEE; + + if (net_mgmt(NET_REQUEST_WIFI_DPP, iface, ¶ms, sizeof(params))) { + PR_WARNING("Failed to request DPP action\n"); + return -ENOEXEC; + } + return 0; +} + static int cmd_wifi_pmksa_flush(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_wifi_sta(); @@ -2641,6 +2743,26 @@ SHELL_STATIC_SUBCMD_SET_CREATE( " Set DPP RX response wait timeout ms:\n" "\n", cmd_wifi_dpp_resp_timeout_set, 2, 0), + SHELL_CMD_ARG(ap_btstrap_gen, NULL, + " AP DPP bootstrap generate:\n" + "[-t --type <1/2/3>]: Bootstrap type. 1: qr_code, 2: pkex, 3: nfc." + " Currently only support qr_code\n" + "[-o --opclass ]\n" + "[-h --channel ]\n" + "[-a --mac ]\n", + cmd_wifi_dpp_ap_btstrap_gen, 1, 8), + SHELL_CMD_ARG(ap_btstrap_get_uri, NULL, + " AP get DPP bootstrap uri by id:\n" + "\n", + cmd_wifi_dpp_ap_btstrap_get_uri, 2, 0), + SHELL_CMD_ARG(ap_qr_code, NULL, + " AP Input QR code:\n" + "\n", + cmd_wifi_dpp_ap_qr_code, 2, 0), + SHELL_CMD_ARG(ap_auth_init, NULL, + "AP DPP start auth request as enrollee:\n" + "-p --peer \n", + cmd_wifi_dpp_ap_auth_init, 3, 0), SHELL_SUBCMD_SET_END ); From 27d882e740bf883a43efe5067e3adc5ce8cdeb39 Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Mon, 24 Jun 2024 12:08:32 +0900 Subject: [PATCH 242/269] hostap: add hostapd cli shell command Add hostapd_cli shell command for test. Signed-off-by: Fengming Ye --- modules/hostap/src/wpa_cli.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/modules/hostap/src/wpa_cli.c b/modules/hostap/src/wpa_cli.c index 1ea6be54a5da870..406008da101aae6 100644 --- a/modules/hostap/src/wpa_cli.c +++ b/modules/hostap/src/wpa_cli.c @@ -13,6 +13,9 @@ #include #include "wpa_cli_zephyr.h" +#ifdef CONFIG_WIFI_NM_HOSTAPD_AP +#include "hostapd_cli_zephyr.h" +#endif static int cmd_wpa_cli(const struct shell *sh, size_t argc, @@ -32,6 +35,24 @@ static int cmd_wpa_cli(const struct shell *sh, return zephyr_wpa_ctrl_zephyr_cmd(argc - 1, &argv[1]); } +#ifdef CONFIG_WIFI_NM_HOSTAPD_AP +static int cmd_hostapd_cli(const struct shell *sh, size_t argc, const char *argv[]) +{ + ARG_UNUSED(sh); + + if (argc == 1) { + shell_error(sh, "Missing argument"); + return -EINVAL; + } + + argv[argc] = "interactive"; + argc++; + + /* Remove hostapd_cli from the argument list */ + return zephyr_hostapd_ctrl_zephyr_cmd(argc - 1, &argv[1]); +} +#endif + /* Persisting with "wpa_cli" naming for compatibility with Wi-Fi * certification applications and scripts. */ @@ -39,3 +60,7 @@ SHELL_CMD_REGISTER(wpa_cli, NULL, "wpa_cli commands (only for internal use)", cmd_wpa_cli); +#ifdef CONFIG_WIFI_NM_HOSTAPD_AP +SHELL_CMD_REGISTER(hostapd_cli, NULL, "hostapd_cli commands (only for internal use)", + cmd_hostapd_cli); +#endif From c642b44c9564ad6b4ef9f4f6853056a58f00ebad Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Tue, 25 Jun 2024 11:40:52 +0900 Subject: [PATCH 243/269] net: wifi_mgmt: add DPP reconfig support Hostap does not support wpa_cli DPP reconfig command. So add wifi_mgmt DPP reconfig command and api. Signed-off-by: Fengming Ye --- include/zephyr/net/wifi_mgmt.h | 6 +++++- modules/hostap/src/supp_api.c | 3 +++ subsys/net/l2/wifi/wifi_shell.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h index a64ea9a74ef80ad..db90f27500d120f 100644 --- a/include/zephyr/net/wifi_mgmt.h +++ b/include/zephyr/net/wifi_mgmt.h @@ -871,7 +871,9 @@ enum wifi_dpp_op { /** Set configurator parameters */ WIFI_DPP_SET_CONF_PARAM, /** Set DPP rx response wait timeout */ - WIFI_DPP_SET_WAIT_RESP_TIME + WIFI_DPP_SET_WAIT_RESP_TIME, + /** Reconfigure DPP network */ + WIFI_DPP_RECONFIG }; /** Wi-Fi DPP crypto Elliptic Curves */ @@ -1008,6 +1010,8 @@ struct wifi_dpp_params { int id; /** Timeout for DPP frame response rx */ int dpp_resp_wait_time; + /** network id for reconfig */ + int network_id; /** DPP QR-CODE, max for SHA512 */ uint8_t dpp_qr_code[WIFI_DPP_QRCODE_MAX_LEN + 1]; /** Request response reusing request buffer. diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c index 941c55ca821d973..6ba2c650027e1d0 100644 --- a/modules/hostap/src/supp_api.c +++ b/modules/hostap/src/supp_api.c @@ -1874,6 +1874,9 @@ static int dpp_params_to_cmd(struct wifi_dpp_params *params, char *cmd, size_t m snprintf(pos, end - pos, "SET dpp_resp_wait_time %d", params->dpp_resp_wait_time); break; + case WIFI_DPP_RECONFIG: + snprintf(pos, end - pos, "DPP_RECONFIG %d", params->network_id); + break; default: wpa_printf(MSG_ERROR, "Unknown DPP action"); return -EINVAL; diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c index 070420afc0852ef..64bee4035ae9ff1 100644 --- a/subsys/net/l2/wifi/wifi_shell.c +++ b/subsys/net/l2/wifi/wifi_shell.c @@ -2616,6 +2616,30 @@ static int cmd_wifi_dpp_ap_auth_init(const struct shell *sh, size_t argc, char * return 0; } +static int cmd_wifi_dpp_reconfig(const struct shell *sh, size_t argc, char *argv[]) +{ + int ret = 0; + struct net_if *iface = net_if_get_wifi_sta(); + struct wifi_dpp_params params = {0}; + + params.action = WIFI_DPP_RECONFIG; + + if (argc >= 2) { + params.network_id = shell_strtol(argv[1], 10, &ret); + } + + if (ret) { + PR_ERROR("parse DPP args fail\n"); + return -EINVAL; + } + + if (net_mgmt(NET_REQUEST_WIFI_DPP, iface, ¶ms, sizeof(params))) { + PR_WARNING("Failed to request DPP action\n"); + return -ENOEXEC; + } + return 0; +} + static int cmd_wifi_pmksa_flush(const struct shell *sh, size_t argc, char *argv[]) { struct net_if *iface = net_if_get_wifi_sta(); @@ -2763,6 +2787,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE( "AP DPP start auth request as enrollee:\n" "-p --peer \n", cmd_wifi_dpp_ap_auth_init, 3, 0), + SHELL_CMD_ARG(reconfig, NULL, + " reconfig network by id:\n" + "\n", + cmd_wifi_dpp_reconfig, 2, 0), SHELL_SUBCMD_SET_END ); From e829b868fcb0168d26c3ee0eb3fbfb223a162277 Mon Sep 17 00:00:00 2001 From: Fengming Ye Date: Fri, 30 Aug 2024 15:52:32 +0900 Subject: [PATCH 244/269] west.yml: update hostap revision Update hostap revision to get hostapd DPP support. Signed-off-by: Fengming Ye --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 3dbc398e3af591c..5a44e6260557179 100644 --- a/west.yml +++ b/west.yml @@ -259,7 +259,7 @@ manifest: - hal - name: hostap path: modules/lib/hostap - revision: 7761b17eea9a2442af6ea9df830904fa4ba7bbca + revision: cbae0170437dbe196d436b2b53d7aefb97044b0c - name: libmetal revision: a6851ba6dba8c9e87d00c42f171a822f7a29639b path: modules/hal/libmetal From 74c5c84c66d59320ab39b58662d60e6cb6f188c2 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Thu, 12 Sep 2024 10:09:04 +0200 Subject: [PATCH 245/269] west.yml: Update hal_stm32 with a fix on the stm32h7/L4/F7 drivers Update stm32H7xx_hal driver partial update to v1.11.3 Update STM32L4xx to 1.18.1 Update stm32F7xx README patch list module hal_stm32 is now: c4099c229323f305eef75ff6ba93ee9b89827581 Signed-off-by: Francois Ramu --- west.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/west.yml b/west.yml index 5a44e6260557179..49bc40e1e4f757e 100644 --- a/west.yml +++ b/west.yml @@ -233,7 +233,7 @@ manifest: groups: - hal - name: hal_stm32 - revision: 1e6116bd2a36db976d955ee772d21f329e529873 + revision: c4099c229323f305eef75ff6ba93ee9b89827581 path: modules/hal/stm32 groups: - hal From 119b238594971a41dc55609d7509677efc675a6c Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Wed, 18 Sep 2024 16:43:53 +0800 Subject: [PATCH 246/269] doc: release: 4.0: add missing colon Add missing colon to the entry introduced in #78285. Signed-off-by: Yong Cong Sin Signed-off-by: Yong Cong Sin --- doc/releases/release-notes-4.0.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index 4bf2f9e36d99858..a6964e8a3c32eb3 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -322,7 +322,7 @@ Libraries / Subsystems * Fixed formatting of milliseconds in :c:enum:`OS_MGMT_ID_DATETIME_STR` by adding leading zeros. * Added support for custom os mgmt bootloader info responses using notification hooks, this - can be enabled witbh :kconfig:option`CONFIG_MCUMGR_GRP_OS_BOOTLOADER_INFO_HOOK`, the data + can be enabled witbh :kconfig:option:`CONFIG_MCUMGR_GRP_OS_BOOTLOADER_INFO_HOOK`, the data structure is :c:struct:`os_mgmt_bootloader_info_data`. * Logging From fc741d53444c0b571c8264c5e6447946cc2fc191 Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Wed, 18 Sep 2024 10:29:05 +0200 Subject: [PATCH 247/269] compliance: Revert "scripts: handle auto defined ZEPHYR__MODULE" With the requirement in #78316 for Zephyr modules to always define ZEPHYR__MODULE Kconfig setting then there is no longer a need for this commit. Simplify check_compliance by reverting ths commit. This reverts commit 35e28e6315893f573ca0de8e5fd5a29e849435f9. Signed-off-by: Torsten Rasmussen --- scripts/ci/check_compliance.py | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 58a2e6da6bb996f..0acc142c68f28d3 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -387,6 +387,11 @@ def get_modules(self, modules_file, settings_file): This is needed to complete Kconfig sanity tests. """ + if self.no_modules: + with open(modules_file, 'w') as fp_module_file: + fp_module_file.write("# Empty\n") + return + # Invoke the script directly using the Python executable since this is # not a module nor a pip-installed Python utility zephyr_module_path = os.path.join(ZEPHYR_BASE, "scripts", @@ -414,18 +419,6 @@ def get_modules(self, modules_file, settings_file): )) fp_module_file.write(content) - if self.no_modules: - module_define_content = "" - module_definition = re.compile('config ZEPHYR_.*_MODULE.*').search - with open(modules_file, 'r+') as fp_module_file: - for line in fp_module_file: - if module_definition(line): - module_define_content += line - module_define_content += "\tbool\n" - fp_module_file.seek(0) - fp_module_file.write(module_define_content) - fp_module_file.truncate() - def get_module_setting_root(self, root, settings_file): """ Parse the Zephyr module generated settings file given by 'settings_file' From db88324f2606631ffe058cd0e086065f86d28273 Mon Sep 17 00:00:00 2001 From: Johan Hedberg Date: Wed, 18 Sep 2024 09:34:59 +0200 Subject: [PATCH 248/269] scripts: check_compliance: Fix incorrect soc root lookup The script was only looking at the Zephyr base repository and failing to look for soc roots e.g. in other modules. Signed-off-by: Johan Hedberg --- scripts/ci/check_compliance.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 0acc142c68f28d3..1a45e32a7411deb 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -543,7 +543,7 @@ def get_v2_model(self, kconfig_dir, settings_file): kconfig_soc_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.soc') kconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig') - root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]}) + root_args = argparse.Namespace(**{'soc_roots': soc_roots}) v2_systems = list_hardware.find_v2_systems(root_args) soc_folders = {soc.folder for soc in v2_systems.get_socs()} From 106b2013bb5b657deb4360a50aea0c0292b1304e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sp=C3=A4tling?= Date: Mon, 16 Sep 2024 14:10:03 +0200 Subject: [PATCH 249/269] dts: adding flexible memory controller (fmc) to H56x, H533 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As requested in https://github.com/zephyrproject-rtos/zephyr/issues/77888 I'm adding the DT basics for the flexible memory controller. Signed-off-by: Thorsten Spätling --- dts/arm/st/h5/stm32h533.dtsi | 7 +++++++ dts/arm/st/h5/stm32h562.dtsi | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/dts/arm/st/h5/stm32h533.dtsi b/dts/arm/st/h5/stm32h533.dtsi index bd781b87cd9cdeb..fff14197c46ebc8 100644 --- a/dts/arm/st/h5/stm32h533.dtsi +++ b/dts/arm/st/h5/stm32h533.dtsi @@ -16,5 +16,12 @@ reg = <0x42021400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>; }; + + fmc: memory-controller@47000400 { + compatible = "st,stm32-fmc"; + reg = <0x47000400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00010000>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index 08e830fbeb52146..130ec20437fb719 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -465,6 +465,13 @@ interrupts = <79 0>; status = "disabled"; }; + + fmc: memory-controller@47000400 { + compatible = "st,stm32-fmc"; + reg = <0x47000400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00010000>; + status = "disabled"; + }; }; smbus3: smbus3 { From 531bbbdf656412601a68579c10a79d90676c1949 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 16 Sep 2024 14:05:04 +0200 Subject: [PATCH 250/269] Revert "ace: mm: tlb: Check tlb translation enabled before flushing cache" This reverts commit 311ddf90e297631c640aea2616fa501486399614. That commit breaks firmware boot on both MTL and LNL. Signed-off-by: Guennadi Liakhovetski --- drivers/mm/mm_drv_intel_adsp_mtl_tlb.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c index 0477296409d586e..5b0bc5e576be05a 100644 --- a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c +++ b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c @@ -338,7 +338,6 @@ static int sys_mm_drv_unmap_page_wflush(void *virt, bool flush_data) k_spinlock_key_t key; uint32_t entry_idx, bank_idx; uint16_t *tlb_entries = UINT_TO_POINTER(TLB_BASE); - uint16_t entry; uintptr_t pa; int ret = 0; @@ -360,17 +359,6 @@ static int sys_mm_drv_unmap_page_wflush(void *virt, bool flush_data) key = k_spin_lock(&tlb_lock); - entry_idx = get_tlb_entry_idx(va); - entry = tlb_entries[entry_idx]; - - /* Check if the translation is enabled in the TLB entry. - * Attempt to flush the cache of an inactive address will result in a cpu exception. - */ - if (!(entry & TLB_ENABLE_BIT)) { - ret = -EFAULT; - goto out_unlock; - } - /* * Flush the cache to make sure the backing physical page * has the latest data. @@ -383,7 +371,8 @@ static int sys_mm_drv_unmap_page_wflush(void *virt, bool flush_data) #endif } - pa = tlb_entry_to_pa(entry); + entry_idx = get_tlb_entry_idx(va); + pa = tlb_entry_to_pa(tlb_entries[entry_idx]); /* Restore default entry settings with cleared the enable bit. */ tlb_entries[entry_idx] = 0; @@ -406,7 +395,6 @@ static int sys_mm_drv_unmap_page_wflush(void *virt, bool flush_data) } } -out_unlock: k_spin_unlock(&tlb_lock, key); out: From b63af212357c3973fe7d15e701d1916e76d612d9 Mon Sep 17 00:00:00 2001 From: Henrik Brix Andersen Date: Mon, 16 Sep 2024 10:47:50 +0200 Subject: [PATCH 251/269] doc: develop: manifests: external: add CANnectivity USB to CAN adapter Add a reference to the CANnectivity USB to CAN adapter firmware as an external module. Signed-off-by: Henrik Brix Andersen --- .../manifest/external/cannectivity.rst | 57 +++++++++++++++++++ doc/develop/manifest/external/dummy.rst | 19 ------- 2 files changed, 57 insertions(+), 19 deletions(-) create mode 100644 doc/develop/manifest/external/cannectivity.rst delete mode 100644 doc/develop/manifest/external/dummy.rst diff --git a/doc/develop/manifest/external/cannectivity.rst b/doc/develop/manifest/external/cannectivity.rst new file mode 100644 index 000000000000000..51a2ab5d20f11c6 --- /dev/null +++ b/doc/develop/manifest/external/cannectivity.rst @@ -0,0 +1,57 @@ +.. _external_module_cannectivity: + +CANnectivity USB to CAN adapter firmware +######################################## + +Introduction +************ + +`CANnectivity`_ is an open source firmware for Universal Serial Bus (USB) to Controller Area Network +(CAN) adapters. + +The firmware implements the Geschwister Schneider USB/CAN device protocol (often referred to as +"gs_usb"). This protocol is supported by the Linux kernel SocketCAN `gs_usb driver`_, by +`python-can`_, and by many other software packages. + +The firmware, which is based on Zephyr RTOS, allows turning your favorite microcontroller +development board into a full-fledged USB to CAN adapter. + +CANnectivity is licensed under the Apache-2.0 license. + +Usage with Zephyr +***************** + +The CANnectivity firmware repository is a Zephyr :ref:`module ` which allows for reuse of +its components (i.e. the "gs_usb" protocol implementation) outside of the CANnectivity firmware +application. + +To pull in CANnectivity as a Zephyr module, either add it as a West project in the ``west.yaml`` +file or pull it in by adding a submanifest (e.g. ``zephyr/submanifests/cannectivity.yaml``) file +with the following content and run ``west update``: + +.. code-block:: yaml + + manifest: + projects: + - name: cannectivity + url: https://github.com/CANnectivity/cannectivity.git + revision: main + path: custom/cannectivity # adjust the path as needed + +Once CANnectivity is added as a Zephyr module, the "gs_usb" implementation can be reused outside of +the CANnectivity firmware application by including its header: + +.. code-block:: c + + #include + +Please see the header file for the API details. + +.. _CANnectivity: + https://github.com/CANnectivity/cannectivity + +.. _gs_usb driver: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/can/usb/gs_usb.c + +.. _python-can: + https://python-can.readthedocs.io/en/stable/interfaces/gs_usb.html diff --git a/doc/develop/manifest/external/dummy.rst b/doc/develop/manifest/external/dummy.rst deleted file mode 100644 index 258619d4be6f246..000000000000000 --- a/doc/develop/manifest/external/dummy.rst +++ /dev/null @@ -1,19 +0,0 @@ -.. _external_module_dummy: - -Add Your External Module Here -############################# - -Introduction -************ - -Short intro into the module and how it relates to Zephyr. - -Usage with Zephyr -***************** - -How to use this module with Zephyr. Provide all the details. - -Reference -********* - -External references and links. From ff8cbd1eda82ada26e81fabb55d832fb6f395957 Mon Sep 17 00:00:00 2001 From: Reto Schneider Date: Fri, 13 Sep 2024 01:27:58 +0200 Subject: [PATCH 252/269] dts: nios2: intel: Fix unit and first address mismatch This fixes the following warning: > unit address and first address in 'reg' (0x1002c0) don't match for > /soc/dma@100200 Signed-off-by: Reto Schneider --- dts/nios2/intel/nios2f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/nios2/intel/nios2f.dtsi b/dts/nios2/intel/nios2f.dtsi index 955d666312511ac..532db6380be3340 100644 --- a/dts/nios2/intel/nios2f.dtsi +++ b/dts/nios2/intel/nios2f.dtsi @@ -59,7 +59,7 @@ interrupts = <4 10>; }; - dma: dma@100200 { + dma: dma@1002c0 { compatible = "altr,msgdma"; reg = <0x1002c0 0x30>; interrupts = <3 3>; From a3d9ede3415098f2f8dce29fbd2bc985ce039636 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Thu, 12 Sep 2024 14:06:33 +0800 Subject: [PATCH 253/269] drivers: counter: shell: change callback functions to static These callback functions are not used outside of the file, make them `static` Signed-off-by: Yong Cong Sin Signed-off-by: Yong Cong Sin --- drivers/counter/counter_timer_shell.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/counter/counter_timer_shell.c b/drivers/counter/counter_timer_shell.c index 0f04f43d9fb9312..d5ab8c2e1df6f9a 100644 --- a/drivers/counter/counter_timer_shell.c +++ b/drivers/counter/counter_timer_shell.c @@ -22,14 +22,14 @@ static struct k_sem timer_sem; -void timer_top_handler(const struct device *counter_dev, void *user_data) +static void timer_top_handler(const struct device *counter_dev, void *user_data) { ARG_UNUSED(counter_dev); k_sem_give(&timer_sem); } -void timer_alarm_handler(const struct device *counter_dev, uint8_t chan_id, +static void timer_alarm_handler(const struct device *counter_dev, uint8_t chan_id, uint32_t ticks, void *user_data) { ARG_UNUSED(counter_dev); From 7ebd3decd8e1c47b8dfbf58e34f6681015183f20 Mon Sep 17 00:00:00 2001 From: Yong Cong Sin Date: Thu, 12 Sep 2024 14:12:00 +0800 Subject: [PATCH 254/269] drivers: counter: shell: device name autocompletion Add timer device name autocompletion to the commands. Signed-off-by: Yong Cong Sin Signed-off-by: Yong Cong Sin --- drivers/counter/counter_timer_shell.c | 67 +++++++++++++++++---------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/drivers/counter/counter_timer_shell.c b/drivers/counter/counter_timer_shell.c index d5ab8c2e1df6f9a..80aef168a91a4ff 100644 --- a/drivers/counter/counter_timer_shell.c +++ b/drivers/counter/counter_timer_shell.c @@ -37,18 +37,29 @@ static void timer_alarm_handler(const struct device *counter_dev, uint8_t chan_i k_sem_give(&timer_sem); } -static int cmd_timer_free_running(const struct shell *shctx, size_t argc, char **argv) +static inline int parse_device(const struct shell *shctx, size_t argc, char *argv[], + const struct device **timer_dev) { ARG_UNUSED(argc); - int err = 0; - const struct device *timer_dev; - timer_dev = device_get_binding(argv[ARGV_DEV]); - if (!timer_dev) { + *timer_dev = device_get_binding(argv[ARGV_DEV]); + if (*timer_dev == NULL) { shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]); return -ENODEV; } + return 0; +} + +static int cmd_timer_free_running(const struct shell *shctx, size_t argc, char **argv) +{ + const struct device *timer_dev; + int err = parse_device(shctx, argc, argv, &timer_dev); + + if (err != 0) { + return err; + } + /* start timer in free running mode */ err = counter_start(timer_dev); if (err != 0) { @@ -63,14 +74,12 @@ static int cmd_timer_free_running(const struct shell *shctx, size_t argc, char * static int cmd_timer_stop(const struct shell *shctx, size_t argc, char **argv) { - ARG_UNUSED(argc); uint32_t ticks1 = 0, ticks2 = 0; const struct device *timer_dev; + int err = parse_device(shctx, argc, argv, &timer_dev); - timer_dev = device_get_binding(argv[ARGV_DEV]); - if (!timer_dev) { - shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]); - return -ENODEV; + if (err != 0) { + return err; } counter_stop(timer_dev); @@ -90,19 +99,16 @@ static int cmd_timer_stop(const struct shell *shctx, size_t argc, char **argv) static int cmd_timer_oneshot(const struct shell *shctx, size_t argc, char **argv) { - ARG_UNUSED(argc); - int err = 0; unsigned long delay = 0; unsigned long channel = 0; const struct device *timer_dev; + int err = parse_device(shctx, argc, argv, &timer_dev); struct counter_alarm_cfg alarm_cfg; k_sem_init(&timer_sem, 0, 1); - timer_dev = device_get_binding(argv[ARGV_DEV]); - if (!timer_dev) { - shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]); - return -ENODEV; + if (err != 0) { + return err; } delay = shell_strtoul(argv[ARGV_ONESHOT_TIME], 10, &err); @@ -146,17 +152,15 @@ static int cmd_timer_periodic(const struct shell *shctx, size_t argc, char **arg { ARG_UNUSED(argc); uint32_t count = 0; - int err = 0; unsigned long delay = 0; const struct device *timer_dev; + int err = parse_device(shctx, argc, argv, &timer_dev); struct counter_top_cfg top_cfg; k_sem_init(&timer_sem, 0, 1); - timer_dev = device_get_binding(argv[ARGV_DEV]); - if (!timer_dev) { - shell_error(shctx, "Timer: Device %s not found", argv[ARGV_DEV]); - return -ENODEV; + if (err != 0) { + return err; } delay = shell_strtoul(argv[ARGV_PERIODIC_TIME], 10, &err); @@ -193,17 +197,30 @@ static int cmd_timer_periodic(const struct shell *shctx, size_t argc, char **arg return 0; } +/* Device name autocompletion support */ +static void device_name_get(size_t idx, struct shell_static_entry *entry) +{ + const struct device *dev = shell_device_lookup(idx, "timer"); + + entry->syntax = (dev != NULL) ? dev->name : NULL; + entry->handler = NULL; + entry->help = NULL; + entry->subcmd = NULL; +} + +SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get); + SHELL_STATIC_SUBCMD_SET_CREATE(sub_timer, - SHELL_CMD_ARG(periodic, NULL, + SHELL_CMD_ARG(periodic, &dsub_device_name, "timer periodic ", cmd_timer_periodic, 3, 0), - SHELL_CMD_ARG(oneshot, NULL, + SHELL_CMD_ARG(oneshot, &dsub_device_name, "timer oneshot ", cmd_timer_oneshot, 4, 0), - SHELL_CMD_ARG(freerun, NULL, + SHELL_CMD_ARG(freerun, &dsub_device_name, "timer freerun ", cmd_timer_free_running, 2, 0), - SHELL_CMD_ARG(stop, NULL, + SHELL_CMD_ARG(stop, &dsub_device_name, "timer stop ", cmd_timer_stop, 2, 0), SHELL_SUBCMD_SET_END /* array terminated. */ From 6582529d1f3646229af53876edd8b580737cffa8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tomasz=20Mo=C5=84?= Date: Wed, 11 Sep 2024 12:53:25 +0200 Subject: [PATCH 255/269] drivers: usb: udc_dwc2: Restrict TxFIFO to SPRAM size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not allocate TxFIFO in a way that could corrupt Endpoint Information Controller data (stored at DFIFO Depth address) or access locations outside the SPRAM. Signed-off-by: Tomasz Moń --- drivers/usb/udc/udc_dwc2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/usb/udc/udc_dwc2.c b/drivers/usb/udc/udc_dwc2.c index cb617dfef7718d2..dc520abe78a08be 100644 --- a/drivers/usb/udc/udc_dwc2.c +++ b/drivers/usb/udc/udc_dwc2.c @@ -1763,6 +1763,11 @@ static int dwc2_set_dedicated_fifo(const struct device *dev, return -ENOMEM; } + /* Do not allocate TxFIFO outside the SPRAM */ + if (txfaddr + txfdep > priv->dfifodepth) { + return -ENOMEM; + } + /* Set FIFO depth (32-bit words) and address */ dwc2_set_txf(dev, ep_idx - 1, txfdep, txfaddr); } else { From 3c092f9274577c16e0c8d959ce2f0ff03471e078 Mon Sep 17 00:00:00 2001 From: Xudong Zheng <7pkvm5aw@slicealias.com> Date: Fri, 13 Sep 2024 13:56:30 -0400 Subject: [PATCH 256/269] dts: bindings: clock: rpi_pico: add XOSC definition This defines raspberrypi,pico-xosc along with a configurable startup delay multiplier. On some boards, the XOSC takes longer to stabilize. Signed-off-by: Xudong Zheng <7pkvm5aw@slicealias.com> --- dts/arm/rpi_pico/rp2040.dtsi | 3 ++- dts/bindings/clock/raspberrypi,pico-xosc.yaml | 14 ++++++++++++++ modules/hal_rpi_pico/pico/config_autogen.h | 5 +++++ 3 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 dts/bindings/clock/raspberrypi,pico-xosc.yaml diff --git a/dts/arm/rpi_pico/rp2040.dtsi b/dts/arm/rpi_pico/rp2040.dtsi index 0fc727b8e90bc42..1709d01c970d4d1 100644 --- a/dts/arm/rpi_pico/rp2040.dtsi +++ b/dts/arm/rpi_pico/rp2040.dtsi @@ -157,8 +157,9 @@ }; xosc: xosc { - compatible = "raspberrypi,pico-clock"; + compatible = "raspberrypi,pico-xosc"; clock-frequency = <12000000>; + startup-delay-multiplier = <64>; #clock-cells = <0>; }; diff --git a/dts/bindings/clock/raspberrypi,pico-xosc.yaml b/dts/bindings/clock/raspberrypi,pico-xosc.yaml new file mode 100644 index 000000000000000..de01d3c4d5e9f95 --- /dev/null +++ b/dts/bindings/clock/raspberrypi,pico-xosc.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Xudong Zheng +# SPDX-License-Identifier: Apache-2.0 + +description: | + The representation of Raspberry Pi Pico external oscillator + +compatible: "raspberrypi,pico-xosc" + +include: raspberrypi,pico-clock.yaml + +properties: + startup-delay-multiplier: + type: int + description: Startup delay multiplier diff --git a/modules/hal_rpi_pico/pico/config_autogen.h b/modules/hal_rpi_pico/pico/config_autogen.h index e8fe4d17579eba3..87d5edd628ccf45 100644 --- a/modules/hal_rpi_pico/pico/config_autogen.h +++ b/modules/hal_rpi_pico/pico/config_autogen.h @@ -32,6 +32,11 @@ /* Disable binary info */ #define PICO_NO_BINARY_INFO 1 +#ifdef CONFIG_DT_HAS_RASPBERRYPI_PICO_XOSC_ENABLED +#include +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER DT_PROP(DT_NODELABEL(xosc), startup_delay_multiplier) +#endif + /* Zephyr compatible way of forcing inline */ #ifndef __always_inline #define __always_inline ALWAYS_INLINE From 03d9f636eae7b5ff57334268c617e787fabe847f Mon Sep 17 00:00:00 2001 From: Peter Mitsis Date: Wed, 4 Sep 2024 18:51:42 +0000 Subject: [PATCH 257/269] arch: Simplify find_lsb_set() Rather than testing each bit until the lowest set bit is found, we can massage the input parameter to easily clear all bits except the lowest set bit. When only one bit is set, both find_lsb_set() and find_msb_set() return the same value. Signed-off-by: Peter Mitsis --- include/zephyr/arch/common/ffs.h | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/include/zephyr/arch/common/ffs.h b/include/zephyr/arch/common/ffs.h index 11f85659c2194a8..2660faa2e3fbe87 100644 --- a/include/zephyr/arch/common/ffs.h +++ b/include/zephyr/arch/common/ffs.h @@ -57,26 +57,13 @@ static ALWAYS_INLINE unsigned int find_lsb_set(uint32_t op) #else /* - * Toolchain does not have __builtin_ffs(). - * Need to do this manually. + * Toolchain does not have __builtin_ffs(). Leverage find_lsb_set() + * by first clearing all but the lowest set bit. */ - int bit; - if (op == 0) { - return 0; - } + op = op ^ (op & (op - 1)); - for (bit = 0; bit < 32; bit++) { - if ((op & (1 << bit)) != 0) { - return (bit + 1); - } - } - - /* - * This should never happen but we need to keep - * compiler happy. - */ - return 0; + return find_msb_set(op); #endif /* CONFIG_TOOLCHAIN_HAS_BUILTIN_FFS */ } From 145dbf820d560669da95e730fccc3ec58dcee5f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 23 Aug 2024 14:42:20 +0200 Subject: [PATCH 258/269] doc: Increase navigation depth in side nav bar MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increase navigation depth by 1 to enable "local" toc navigation in the side bar for those pages that are deeper in the documentation tree. Signed-off-by: Benjamin Cabé --- doc/conf.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/conf.py b/doc/conf.py index 4d3e2d8b5c0cfd8..8359d3d4049ca04 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -161,7 +161,8 @@ html_theme = "sphinx_rtd_theme" html_theme_options = { "logo_only": True, - "prev_next_buttons_location": None + "prev_next_buttons_location": None, + "navigation_depth": 5, } html_baseurl = "https://docs.zephyrproject.org/latest/" html_title = "Zephyr Project Documentation" From 47a7da9e9f44d51a43b0e3c0951732c3b05f46cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Benjamin=20Cab=C3=A9?= Date: Fri, 23 Aug 2024 15:09:08 +0200 Subject: [PATCH 259/269] doc: Overhaul doc guidelines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Improved document structure (was *very* flat before) by adding more meaningful top-level headings and re-ordering some of the existing sections - Provide detailed and structured docs for all the custom Sphinx roles and directives available in Zephyr, including moving the docs for ``.. zephyr-app-commands`` directive and `:dtcompatible:` roles away from the extensions' source files to align with how Sphinx typically handles docs for custom roles/directives. - Added more content regarding diagrams guidelines, images, cross-referencing of Doxygen documentation, ... Signed-off-by: Benjamin Cabé --- doc/_extensions/zephyr/application.py | 87 --- doc/_extensions/zephyr/domain.py | 27 - doc/_extensions/zephyr/dtcompatible-role.py | 30 +- doc/contribute/documentation/guidelines.rst | 819 +++++++++++++++----- 4 files changed, 643 insertions(+), 320 deletions(-) diff --git a/doc/_extensions/zephyr/application.py b/doc/_extensions/zephyr/application.py index 88d2f8fc33363fd..d59cb4294b14b8a 100644 --- a/doc/_extensions/zephyr/application.py +++ b/doc/_extensions/zephyr/application.py @@ -20,93 +20,6 @@ class ZephyrAppCommandsDirective(Directive): r''' This is a Zephyr directive for generating consistent documentation of the shell commands needed to manage (build, flash, etc.) an application. - - For example, to generate commands to build samples/hello_world for - qemu_x86 use:: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: qemu_x86 - :goals: build - - Directive options: - - \:tool: - which tool to use. Valid options are currently 'cmake', 'west' and 'all'. - The default is 'west'. - - \:app: - path to the application to build. - - \:zephyr-app: - path to the application to build, this is an app present in the upstream - zephyr repository. Mutually exclusive with \:app:. - - \:cd-into: - if set, build instructions are given from within the \:app: folder, - instead of outside of it. - - \:generator: - which build system to generate. Valid options are - currently 'ninja' and 'make'. The default is 'ninja'. This option - is not case sensitive. - - \:host-os: - which host OS the instructions are for. Valid options are - 'unix', 'win' and 'all'. The default is 'all'. - - \:board: - if set, the application build will target the given board. - - \:shield: - if set, the application build will target the given shield. - Multiple shields can be provided in a comma separated list. - - \:conf: - if set, the application build will use the given configuration - file. If multiple conf files are provided, enclose the - space-separated list of files with quotes, e.g., "a.conf b.conf". - - \:gen-args: - if set, additional arguments to the CMake invocation - - \:build-args: - if set, additional arguments to the build invocation - - \:snippets: - if set, indicates the application should be compiled with the listed snippets. - Multiple snippets can be provided in a comma separated list. - - \:build-dir: - if set, the application build directory will *APPEND* this - (relative, Unix-separated) path to the standard build directory. This is - mostly useful for distinguishing builds for one application within a - single page. - - \:build-dir-fmt: - if set, assume that "west config build.dir-fmt" has been set to this - path. Exclusive with 'build-dir' and depends on 'tool=west'. - - \:goals: - a whitespace-separated list of what to do with the app (in - 'build', 'flash', 'debug', 'debugserver', 'run'). Commands to accomplish - these tasks will be generated in the right order. - - \:maybe-skip-config: - if set, this indicates the reader may have already - created a build directory and changed there, and will tweak the text to - note that doing so again is not necessary. - - \:compact: - if set, the generated output is a single code block with no - additional comment lines - - \:west-args: - if set, additional arguments to the west invocation (ignored for CMake) - - \:flash-args: - if set, additional arguments to the flash invocation - ''' has_content = False required_arguments = 0 diff --git a/doc/_extensions/zephyr/domain.py b/doc/_extensions/zephyr/domain.py index c5b4c27bb12a33c..e4c1ade96427fe4 100644 --- a/doc/_extensions/zephyr/domain.py +++ b/doc/_extensions/zephyr/domain.py @@ -5,9 +5,6 @@ Copyright (c) 2023 The Linux Foundation SPDX-License-Identifier: Apache-2.0 -Introduction -============ - This extension adds a new ``zephyr`` domain for handling the documentation of various entities specific to the Zephyr RTOS project (ex. code samples). @@ -15,35 +12,11 @@ ---------- - ``zephyr:code-sample::`` - Defines a code sample. - The directive takes an ID as the main argument, and accepts ``:name:`` (human-readable short name - of the sample) and ``:relevant-api:`` (a space separated list of Doxygen group(s) for APIs the - code sample is a good showcase of) as options. - The content of the directive is used as the description of the code sample. - - Example: - - ``` - .. zephyr:code-sample:: blinky - :name: Blinky - :relevant-api: gpio_interface - - Blink an LED forever using the GPIO API. - ``` Roles ----- - ``:zephyr:code-sample:`` - References a code sample. - The role takes the ID of the code sample as the argument. The role renders as a link to the code - sample, and the link text is the name of the code sample (or a custom text if an explicit name is - provided). - - Example: - - ``` - Check out :zephyr:code-sample:`sample-foo` for an example of how to use the foo API. You may - also be interested in :zephyr:code-sample:`this one `. - ``` """ from typing import Any, Dict, Iterator, List, Tuple diff --git a/doc/_extensions/zephyr/dtcompatible-role.py b/doc/_extensions/zephyr/dtcompatible-role.py index 3cfb59121f4e4f0..5cda7d348924da1 100644 --- a/doc/_extensions/zephyr/dtcompatible-role.py +++ b/doc/_extensions/zephyr/dtcompatible-role.py @@ -6,33 +6,9 @@ A Sphinx extension for documenting devicetree content. It adds a role and a directive with the same name, 'dtcompatible'. -:dtcompatible:`vnd,foo` - - This role can be used inline to make a reference to the generated - documentation for a devicetree - compatible given as argument. - - For example, :dtcompatible:`vnd,foo` would create a reference to the - generated documentation page for the devicetree binding handling - compatible "vnd,foo". - - There may be more than one page for a single compatible. For example, - that happens if a binding behaves differently depending on the bus the - node is on. If that occurs, the reference points at a "disambiguation" - page which links out to all the possibilities, similarly to how Wikipedia - disambiguation pages work. - - The Zephyr documentation uses the standard :option: role to refer - to Kconfig options. The :dtcompatible: option is like that, except - using its own role to avoid using one that already has a standard meaning. - (The :option: role is meant for documenting options to command-line programs, - not Kconfig symbols.) - -.. dtcompatible:: vnd,foo - - This directive marks the page where the :dtcompatible: role link goes. - Do not use it directly. The generated bindings documentation puts these - in the right places. +The directive marks the page where the :dtcompatible: role link goes. +Do not use it directly. The generated bindings documentation puts these +in the right places. """ def setup(app): diff --git a/doc/contribute/documentation/guidelines.rst b/doc/contribute/documentation/guidelines.rst index 12e0b3f6d446cd5..a919443529cae78 100644 --- a/doc/contribute/documentation/guidelines.rst +++ b/doc/contribute/documentation/guidelines.rst @@ -30,18 +30,42 @@ This document provides a quick reference for commonly used reST and Sphinx-defined directives and roles used to create the documentation you're reading. +Content Structure +***************** + +Tabs, spaces, and indenting +=========================== + +Indenting is significant in reST file content, and using spaces is +preferred. Extra indenting can (unintentionally) change the way content +is rendered too. For lists and directives, indent the content text to +the first non-white space in the preceding line. For example:: + + * List item that spans multiple lines of text + showing where to indent the continuation line. + + 1. And for numbered list items, the continuation + line should align with the text of the line above. + + .. code-block:: + + The text within a directive block should align with the + first character of the directive name. + +Refer to the Zephyr :ref:`coding_style` for additional requirements. + Headings -******** +======== -While reST allows use of both and overline and matching underline to +While reST allows use of both an overline and matching underline to indicate a heading, we only use an underline indicator for headings. -* Document title (h1) use "#" for the underline character -* First section heading level (h2) use "*" -* Second section heading level (h3) use "=" -* Third section heading level (h4) use "-" +* Document title (h1) use ``#`` for the underline character +* First section heading level (h2) use ``*`` +* Second section heading level (h3) use ``=`` +* Third section heading level (h4) use ``-`` -The heading underline must be at least as long as the title it's under. +The heading underline must be the same length as the heading text. For example:: @@ -54,21 +78,8 @@ For example:: ********************* -Content Highlighting -******************** - -Some common reST inline markup samples: - -* one asterisk: ``*text*`` for emphasis (*italics*), -* two asterisks: ``**text**`` for strong emphasis (**boldface**), and -* two backquotes: ````text```` for ``inline code`` samples. - -If asterisks or backquotes appear in running text and could be confused with -inline markup delimiters, you can eliminate the confusion by adding a -backslash (``\``) before it. - Lists -***** +===== For bullet lists, place an asterisk (``*``) or hyphen (``-``) at the start of a paragraph and indent continuation lines with two @@ -130,7 +141,7 @@ Would be rendered as: clean state. Multi-column lists -****************** +================== If you have a long bullet list of items, where each item is short, you can indicate the list items should be rendered in multiple columns with @@ -170,7 +181,7 @@ available width of the display window, reducing to one column on narrow directive because it misbehaves on smaller screens. Tables -****** +====== There are a few ways to create tables, each with their limitations or quirks. `Grid tables @@ -247,128 +258,183 @@ columns, you can specify ``:widths: 1 2 2``. If you'd like the browser to set the column widths automatically based on the column contents, you can use ``:widths: auto``. -File names and Commands -*********************** +Tabbed Content +============== -Sphinx extends reST by supporting additional inline markup elements (called -"roles") used to tag text with special -meanings and allow style output formatting. (You can refer to the `Sphinx Inline Markup`_ -documentation for the full list). +As introduced in the :ref:`getting_started`, you can provide alternative +content to the reader via a tabbed interface. When the reader clicks on +a tab, the content for that tab is displayed, for example:: -For example, there are roles for marking :file:`filenames` -(``:file:`name```) and command names such as :command:`make` -(``:command:`make```). You can also use the \`\`inline code\`\` -markup (double backticks) to indicate a ``filename``. - -For references to files that are in the Zephyr GitHub tree, a special -role can be used that creates a hyperlink to that file. For example a -reference to the reST file used to create this document can be generated -using ``:zephyr_file:`doc/contribute/documentation/guidelines.rst``` that will -show up as :zephyr_file:`doc/contribute/documentation/guidelines.rst`, a link to -the "blob" file in the github repo. There's also a -``:zephyr_raw:`doc/contribute/documentation/guidelines.rst``` role that will -link to the "raw" content, -:zephyr_raw:`doc/contribute/documentation/guidelines.rst`. (You can click on -these links to see the difference.) + .. tabs:: -.. _internal-linking: + .. tab:: Apples -Internal Cross-Reference Linking -******************************** + Apples are green, or sometimes red. -Traditional ReST links are only supported within the current file using the -notation:: + .. tab:: Pears - Refer to the `internal-linking`_ page + Pears are green. -which renders as, + .. tab:: Oranges - Refer to the `internal-linking`_ page + Oranges are orange. -Note the use of a trailing -underscore to indicate an outbound link. In this example, the label was -added immediately before a heading, so the text that's displayed is the -heading text itself. You can change the text that's displayed as the -link writing this as:: +will display as: - Refer to the `show this text instead `_ page +.. tabs:: -which renders as, + .. tab:: Apples - Refer to the `show this text instead `_ page + Apples are green, or sometimes red. + .. tab:: Pears -External Cross-Reference Linking -******************************** + Pears are green. -With Sphinx's help, we can create -link-references to any tagged text within the Zephyr Project documentation. + .. tab:: Oranges -Target locations in a document are defined with a label directive:: + Oranges are orange. - .. _my label name: +Tabs can also be grouped, so that changing the current tab in one area +changes all tabs with the same name throughout the page. For example: - Heading - ======= +.. tabs:: -Note the leading underscore indicating an inbound link. -The content immediately following -this label must be a heading, and is the target for a ``:ref:`my label name``` -reference from anywhere within the Zephyr documentation. -The heading text is shown when referencing this label. -You can also change the text that's displayed for this link, such as:: + .. group-tab:: Linux - :ref:`some other text ` + Linux Line 1 + .. group-tab:: macOS -To enable easy cross-page linking within the site, each file should have -a reference label before its title so it can -be referenced from another file. These reference labels must be unique -across the whole site, so generic names such as "samples" should be -avoided. For example the top of this document's .rst file is:: + macOS Line 1 - .. _doc_guidelines: + .. group-tab:: Windows - Documentation Guidelines for the Zephyr Project - ############################################### + Windows Line 1 +.. tabs:: -Other .rst documents can link to this document using the ``:ref:`doc_guidelines``` tag and -it will show up as :ref:`doc_guidelines`. This type of internal cross reference works across -multiple files, and the link text is obtained from the document source so if the title changes, -the link text will update as well. + .. group-tab:: Linux -You can also define links to any URL and then reference it in your document. -For example, with this label definition in the document:: + Linux Line 2 - .. _Zephyr Wikipedia Page: - https://en.wikipedia.org/wiki/Zephyr_(operating_system) + .. group-tab:: macOS -you can reference it with:: + macOS Line 2 - Read the `Zephyr Wikipedia Page`_ for more information about the - project. + .. group-tab:: Windows + + Windows Line 2 + +In this latter case, we're using ``.. group-tab::`` instead of simply +``.. tab::``. Under the hood, we're using the `sphinx-tabs +`_ extension that's included +in the Zephyr setup. Within a tab, you can have most any content *other +than a heading* (code-blocks, ordered and unordered lists, pictures, +paragraphs, and such). You can read more about sphinx-tabs from the +link above. + + +Text Formatting +*************** + +ReSTructuredText supports a variety of text formatting options. This section provides a quick +reference for some of the most commonly used text formatting options in Zephyr documentation. For an +exhaustive list, refer to the `reStructuredText Quick Reference`_, +`reStructuredText Interpreted Text Roles`_ as well as the `additional roles provided by Sphinx`_. + +.. _reStructuredText Quick Reference: http://docutils.sourceforge.io/docs/user/rst/quickref.html +.. _reStructuredText Interpreted Text Roles: https://docutils.sourceforge.io/docs/ref/rst/roles.html +.. _additional roles provided by Sphinx: https://www.sphinx-doc.org/en/master/usage/restructuredtext/roles.html + +Content Highlighting +==================== + +Some common reST inline markup samples: + +* one asterisk: ``*text*`` for emphasis (*italics*), +* two asterisks: ``**text**`` for strong emphasis (**boldface**), and +* two backquotes: ````text```` for ``inline code`` samples. + +If asterisks or backquotes appear in running text and could be confused with +inline markup delimiters, you can eliminate the confusion by adding a +backslash (``\``) before it. + +File Names and Commands +======================= + +Sphinx extends reST by supporting additional inline markup elements (called +"roles") used to tag text with special +meanings and allow style output formatting. (You can refer to the `Sphinx Inline Markup`_ +documentation for the full list). + +While double quotes can be used for rendering text as "code", you are encouraged to use the +following roles for marking up file names, command names, and other "special" text. + +* :rst:role:`file` for file names, e.g., ``:file:`CMakeLists.txt``` will render as + :file:`CMakeLists.txt` + + .. note:: + + In case you want to indicate a "variable" file path, you may use curly braces to enclose the + variable part of the path, e.g., ``:file:`{boardname}_defconfig``` will render as + :file:`{boardname}_defconfig`. + +* :rst:role:`command` for command names, e.g., ``:command:`make``` will render as :command:`make` + +* :rst:role:`envvar` for environment variables, e.g., ``:envvar:`ZEPHYR_BASE``` will render as + :envvar:`ZEPHYR_BASE` + +For creating references to files that are hosted in the Zephyr organization on GitHub, refer to +:ref:`linking_to_zephyr_files` section below. + +User Interaction +================ + +When documenting user interactions, such as key combinations or GUI interactions, use the following +roles to highlight the commands in a meaningful way: + +* :rst:role:`kbd` for keyboard input, e.g., ``:kbd:`Ctrl-C``` will render as :kbd:`Ctrl-C` + +* :rst:role:`menuselection` for menu selections, e.g., ``:menuselection:`File --> Open``` will render + as :menuselection:`File --> Open` + +* :rst:role:`guilabel` for GUI labels, e.g., ``:guilabel:`Cancel``` will render as :guilabel:`Cancel` + +Mathematical Formulas +===================== + +You can include mathematical formulas using either the :rst:role:`math` role or :rst:dir:`math` +directive. The directive provides more flexibility in case you have a more complex formula. + +The input language for mathematics is LaTeX markup. Example:: + + The answer to life, the universe, and everything is :math:`30 + 2^2 + \sqrt{64} = 42`. + +This would render as: + + The answer to life, the universe, and everything is :math:`30 + 2^2 + \sqrt{64} = 42`. Non-ASCII Characters -******************** +==================== You can insert non-ASCII characters such as a Trademark symbol (|trade|), by using the notation ``|trade|``. Available replacement names are defined in an include file used during the Sphinx processing of the reST files. The names of these replacement characters are the same as used in HTML -entities used to insert characters in HTML, e.g., \™ and are defined in the -file ``sphinx_build/substitutions.txt`` as listed here: +entities used to insert characters in HTML, e.g., ``\™`` and are defined in the +file :zephyr_file:`doc/substitutions.txt` as listed below: .. literalinclude:: ../../substitutions.txt :language: rst We've kept the substitutions list small but others can be added as -needed by submitting a change to the ``substitutions.txt`` file. +needed by submitting a change to the :zephyr_file:`doc/substitutions.txt` file. -Code and Command Examples -************************* +Code Blocks and Command Examples +================================ -Use the reST ``code-block`` directive to create a highlighted block of +Use the reST :rst:dir:`code-block` directive to create a highlighted block of fixed-width text, typically used for showing formatted code or console commands and output. Smart syntax highlighting is also supported (using the Pygments package). You can also directly specify the highlighting language. @@ -384,7 +450,7 @@ For example:: uint32_t data; } __packed; -Note the blank line between the ``code-block`` directive and the first +Note the blank line between the :rst:dir:`code-block` directive and the first line of the code-block body, and the body content is indented three spaces (to the first non-white space of the directive name). @@ -504,13 +570,128 @@ Would display as: There's a shorthand for writing code blocks too: end the introductory paragraph with a double colon (``::``) and indent the code block content that follows it by three spaces. On output, only one colon will be shown. The code block will have no highlighting (i.e. ``none``). You may however use -the ``.. highlight::`` directive to customize the default language used in your document (see for +the :rst:dir:`highlight` directive to customize the default language used in your document (see for example how this is done at the beginning of this very document). + +Links and Cross-References +************************** + +.. _internal-linking: + +Cross-referencing internal content +================================== + +Traditional ReST links are only supported within the current file using the +notation:: + + Refer to the `internal-linking`_ page + +which renders as, + + Refer to the `internal-linking`_ page + +Note the use of a trailing +underscore to indicate an outbound link. In this example, the label was +added immediately before a heading, so the text that's displayed is the +heading text itself. You can change the text that's displayed as the +link writing this as:: + + Refer to the `show this text instead `_ page + +which renders as, + + Refer to the `show this text instead `_ page + + +Cross-referencing external content +================================== + +With Sphinx's help, we can create +link-references to any tagged text within the Zephyr Project documentation. + +Target locations in a document are defined with a label directive:: + + .. _my label name: + + Heading + ======= + +Note the leading underscore indicating an inbound link. +The content immediately following +this label must be a heading, and is the target for a ``:ref:`my label name``` +reference from anywhere within the Zephyr documentation. +The heading text is shown when referencing this label. +You can also change the text that's displayed for this link, such as:: + + :ref:`some other text ` + + +To enable easy cross-page linking within the site, each file should have +a reference label before its title so it can +be referenced from another file. These reference labels must be unique +across the whole site, so generic names such as "samples" should be +avoided. For example the top of this document's .rst file is:: + + .. _doc_guidelines: + + Documentation Guidelines for the Zephyr Project + ############################################### + + +Other .rst documents can link to this document using the ``:ref:`doc_guidelines``` tag and +it will show up as :ref:`doc_guidelines`. This type of internal cross reference works across +multiple files, and the link text is obtained from the document source so if the title changes, +the link text will update as well. + +You can also define links to any URL and then reference it in your document. +For example, with this label definition in the document:: + + .. _Zephyr Wikipedia Page: + https://en.wikipedia.org/wiki/Zephyr_(operating_system) + +you can reference it with:: + + Read the `Zephyr Wikipedia Page`_ for more information about the + project. + + +Cross-referencing C documentation +================================= + +.. rst:role:: c:member + c:data + c:var + c:func + c:macro + c:struct + c:union + c:enum + c:enumerator + c:type + + You may use these roles to cross-reference the Doxygen documentation of C functions, macros, + types, etc. + + They are rendered in the HTML output as links to the corresponding Doxygen documentation for the + item. For example:: + + Check out :c:function:`gpio_pin_configure` for more information. + + Will render as: + + Check out :c:func:`gpio_pin_configure` for more information. + + You may provide a custom link text, similar to the built-in :rst:role:`ref` role. + + +Visual Elements +*************** + Images -****** +====== -Images are included in documentation by using an image directive:: +Images are included in the documentation by using an :rst:dir:`image` directive:: .. image:: ../../images/doc-gen-flow.png :align: center @@ -525,121 +706,401 @@ or if you'd like to add an image caption, use:: The file name specified is relative to the document source file, and we recommend putting images into an ``images`` folder where the document -source is found. The usual image formats handled by a web browser are -supported: JPEG, PNG, GIF, and SVG. Keep the image size only as large -as needed, generally at least 500 px wide but no more than 1000 px, and -no more than 250 KB unless a particularly large image is needed for -clarity. +source is found. -Tabs, spaces, and indenting -*************************** +The usual image formats handled by a web browser are supported: WebP, PNG, GIF, +JPEG, and SVG. -Indenting is significant in reST file content, and using spaces is -preferred. Extra indenting can (unintentionally) change the way content -is rendered too. For lists and directives, indent the content text to -the first non-white space in the preceding line. For example:: +Keep the image size only as large as needed, generally at least 500 px wide but +no more than 1000 px, and no more than 100 KB unless a particularly large image +is needed for clarity. - * List item that spans multiple lines of text - showing where to indent the continuation line. +Recommended image formats based on content +------------------------------------------ - 1. And for numbered list items, the continuation - line should align with the text of the line above. +* **Screenshots**: WebP or PNG. +* **Diagrams**: Consider using Graphviz for simple diagrams (see + `dedicated section `_ below. If using an external tool, SVG is preferred. +* **Photos** (ex. boards): WebP. Use transparency if possible/available. - .. code-block:: - The text within a directive block should align with the - first character of the directive name. +.. _graphviz_diagrams: -Refer to the Zephyr :ref:`coding_style` for additional requirements. +Graphviz +======== -zephyr-app-commands Directive -***************************** +`Graphviz`_ is a tool for creating diagrams specified in a simple text language. As it's important +to allow for diagrams used in the documentation to be easily maintained, we encourage the use of +Graphviz for creating diagrams. Graphviz is particularly well suited for creating state diagrams, flow +charts, and other types of diagrams that can be expressed as a graph. -.. include:: ../../_extensions/zephyr/application.py - :start-line: 10 - :start-after: ''' - :end-before: ''' +To include a Graphviz diagram in a document, use the :rst:dir:`graphviz` directive. For example:: -For example, the ``.. zephyr-app-commands`` listed above would -render like this in the generated HTML output: + .. graphviz:: -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: qemu_x86 - :goals: build + digraph G { + rankdir=LR; + A -> B; + B -> C; + C -> D; + } -Alternative Tabbed Content -************************** +Would render as: -As introduced in the :ref:`getting_started`, you can provide alternative -content to the reader via a tabbed interface. When the reader clicks on -a tab, the content for that tab is displayed, for example:: + .. graphviz:: - .. tabs:: + digraph G { + rankdir=LR; + A -> B; + B -> C; + C -> D; + } - .. tab:: Apples +Please refer to the `Graphviz documentation`_ for more information on how to create diagrams using +Graphviz's DOT language. - Apples are green, or sometimes red. +.. _Graphviz: https://graphviz.org +.. _Graphviz documentation: https://graphviz.org/documentation - .. tab:: Pears - Pears are green. +Custom Sphinx Roles and Directives +********************************** - .. tab:: Oranges +The Zephyr documentation uses custom Sphinx roles and directives to provide additional functionality +and to make it easier to write and maintain consistent documentation. - Oranges are orange. +Application build commands +========================== -will display as: +.. rst:directive:: .. zephyr-app-commands:: -.. tabs:: + Generate consistent documentation of the shell commands needed to manage (build, flash, etc.) an + application - .. tab:: Apples + For example, to generate commands to build ``samples/hello_world`` for ``qemu_x86`` use:: - Apples are green, or sometimes red. + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: qemu_x86 + :goals: build - .. tab:: Pears + This wil render as: - Pears are green. + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: qemu_x86 + :goals: build - .. tab:: Oranges + .. rubric:: Options - Oranges are orange. + .. rst:directive:option:: tool + :type: string -Tabs can also be grouped, so that changing the current tab in one area -changes all tabs with the same name throughout the page. For example: + Which tool to use. Valid options are currently ``cmake``, ``west`` and ``all``. + The default is ``west``. -.. tabs:: + .. rst:directive:option:: app + :type: string - .. group-tab:: Linux + Path to the application to build. - Linux Line 1 + .. rst:directive:option:: zephyr-app + :type: string - .. group-tab:: macOS + Path to the application to build, this is an app present in the upstream zephyr repository. + Mutually exclusive with ``:app:``. - macOS Line 1 + .. rst:directive:option:: cd-into + :type: no value - .. group-tab:: Windows + If set, build instructions are given from within the ``:app:`` folder, instead of outside of + it. - Windows Line 1 + .. rst:directive:option:: generator + :type: string -.. tabs:: + Which build system to generate. - .. group-tab:: Linux + Valid options are currently ``ninja`` and ``make``. The default is ``ninja``. This option is + not case sensitive. - Linux Line 2 + .. rst:directive:option:: host-os - .. group-tab:: macOS + Which host OS the instructions are for. - macOS Line 2 + Valid options are ``unix``, ``win`` and ``all``. The default is ``all``. - .. group-tab:: Windows + .. rst:directive:option:: board + :type: string - Windows Line 2 + If set, build commands will target the given board. -In this latter case, we're using ``.. group-tab::`` instead of simply -``.. tab::``. Under the hood, we're using the `sphinx-tabs -`_ extension that's included -in the Zephyr setup. Within a tab, you can have most any content *other -than a heading* (code-blocks, ordered and unordered lists, pictures, -paragraphs, and such). You can read more about sphinx-tabs from the -link above. + .. rst:directive:option:: shield + :type: string + + If set, build commands will target the given shield. + + Multiple shields can be provided in a comma separated list. + + .. rst:directive:option:: conf + + If set, build commands will use the given configuration file(s). + + If multiple configuration files are provided, enclose the space-separated list of files with + double quotes, e.g., `"a.conf b.conf"`. + + .. rst:directive:option:: gen-args + :type: string + + If set, indicates additional arguments to the CMake invocation. + + .. rst:directive:option:: build-args + :type: string + + If set, indicates additional arguments to the build invocation. + + .. rst:directive:option:: west-args + :type: string + + If set, additional arguments to the west invocation (ignored for ``:tool: cmake``). + + .. rst:directive:option:: flash-args + :type: string + + If set, additional arguments to the flash invocation. + + .. rst:directive:option:: snippets + :type: string + + If set, indicates the application should be compiled with the listed snippets. + + Multiple snippets can be provided in a comma separated list. + + .. rst:directive:option:: build-dir + :type: string + + If set, the application build directory will *APPEND* this relative, Unix-separated, path to + the standard build directory. This is mostly useful for distinguishing builds for one + application within a single page. + + .. rst:directive:option:: build-dir-fmt + :type: string + + If set, assume that `west config build.dir-fmt`` has been set to this path. + + Exclusive with ``:build-dir:`` and depends on ``:tool: west``. + + .. rst:directive:option:: goals + :type: string + + A whitespace-separated list of what to do with the app (any of ``build``, ``flash``, + ``debug``, ``debugserver``, ``run``). + + Commands to accomplish these tasks will be generated in the right order. + + .. rst:directive:option:: maybe-skip-config + :type: no value + + If set, this indicates the reader may have already created a build directory and changed + there, and will tweak the text to note that doing so again is not necessary. + + .. rst:directive:option:: compact + :type: no value + + If set, the generated output is a single code block with no additional comment lines. + + +.. _linking_to_zephyr_files: + +Cross-referencing files in the Zephyr tree +========================================== + +Special roles are available to reference files in the Zephyr tree. For example, referencing this +very file can be done using the :rst:role:`zephyr_file` role, like this:: + + Check out :zephyr_file:`doc/contribute/documentation/guidelines.rst` for more information. + +This would render as: + + Check out :zephyr_file:`doc/contribute/documentation/guidelines.rst` for more information. + +You may use the :rst:role:`zephyr_raw` role instead if you want to reference the "raw" content. + +.. rst:role:: zephyr_file + + This role is used to reference a file in the Zephyr tree. For example:: + + Check out :zephyr_file:`doc/contribute/documentation/guidelines.rst` for more information. + + Will render as: + + Check out :zephyr_file:`doc/contribute/documentation/guidelines.rst` for more information. + +.. rst:role:: zephyr_raw + + This role is used to reference the raw content of a file in the Zephyr tree. For example:: + + Check out :zephyr_raw:`doc/contribute/documentation/guidelines.rst` for more information. + + Will render as: + + Check out :zephyr_raw:`doc/contribute/documentation/guidelines.rst` for more information. + +.. rst:role:: module_file + + This role is used to reference a module in the Zephyr tree. For example:: + + Check out :module_file:`hal_stm32:CMakeLists.txt` for more information. + + Will render as: + + Check out :module_file:`hal_stm32:CMakeLists.txt` for more information. + + +Cross-referencing GitHub issues and pull requests +================================================= + +.. rst:role:: github + + This role is used to reference a GitHub issue or pull request. + + For example, to reference issue #1234:: + + Check out :github:`1234` for more background about this known issue. + + This will render as: + + Check out :github:`1234` for more background about this known issue. + +Doxygen API documentation +========================= + +.. app.add_directive("doxygengroup", DoxygenGroupDirective) +.. app.add_role_to_domain("c", "group", CXRefRole()) + +.. rst:directive:: .. doxygengroup:: name + + This directive is used to output a short description of a Doxygen group and a link to the + corresponding Doxygen-generated documentation. + + All the code samples (declared using the :rst:dir:`zephyr:code-sample` directive) indicating the + group as relevant will automatically be list and referenced in the rendered output. + + For example:: + + .. doxygengroup:: can_interface + + Will render as: + + .. doxygengroup:: can_interface + +.. rst:role:: c:group + + This role is used to reference a Doxygen group in the Zephyr tree. In the HTML documentation, + they are rendered as links to the corresponding Doxygen-generated documentation for the group. + For example:: + + Check out :c:group:`gpio_interface` for more information. + + Will render as: + + Check out :c:group:`gpio_interface` for more information. + + You may provide a custom link text, similar to the built-in :rst:role:`ref` role. + + +Kconfig options +=============== + +If you want to reference a Kconfig option from a document, you can use the +:rst:role:`kconfig:option` role and provide the name of the option you want to reference. The role +will automatically generate a link to the documentation of the Kconfig option when building HTML +output. + +Make sure to use the full name of the Kconfig option, including the ``CONFIG_`` prefix. + +.. rst:role:: kconfig:option + + This role is used to reference a Kconfig option in the Zephyr tree. For example:: + + Check out :kconfig:option:`CONFIG_GPIO` for more information. + + Will render as: + + Check out :kconfig:option:`CONFIG_GPIO` for more information. + +Devicetree bindings +=================== + +If you want to reference a Devicetree binding from a document, you can use the +:rst:role:`dtcompatible` role and provide the compatible string of the binding you want to +reference. The role will automatically generate a link to the documentation of the binding when +building HTML output. + +.. rst:role:: dtcompatible + + This role can be used inline to make a reference to the generated documentation for the + Devicetree compatible given as argument. + + There may be more than one page for a single compatible. For example, that happens if a binding + behaves differently depending on the bus the node is on. If that occurs, the reference points at + a "disambiguation" page which links out to all the possibilities, similarly to how Wikipedia + disambiguation pages work. Example:: + + Check out :dtcompatible:`zephyr,input-longpress` for more information. + + Will render as: + + Check out :dtcompatible:`zephyr,input-longpress` for more information. + +Code samples +============ + +.. rst:directive:: .. zephyr:code-sample:: id + + This directive is used to describe a code sample, including which noteworthy APIs it may be + exercising. + + For example:: + + .. zephyr:code-sample:: blinky + :name: Blinky + :relevant-api: gpio_interface + + Blink an LED forever using the GPIO API. + + The content of the directive is used as the description of the code sample. + + .. rubric:: Options + + .. rst:directive:option:: name + :type: text + + Indicates the human-readable short name of the sample. + + .. rst:directive:option:: relevant-api + :type: text + + Optional space-separated list of Doxygen group names that correspond to the APIs exercised + by the code sample. + +.. rst:role:: zephyr:code-sample + + This role is used to reference a code sample described using :rst:dir:`zephyr:code-sample`. + + For example:: + + Check out :zephyr:code-sample:`blinky` for more information. + + Will render as: + + Check out :zephyr:code-sample:`blinky` for more information. + + This can be used exactly like the built-in :rst:role:`ref` role, i.e. you may provide a custom + link text. For example:: + + Check out :zephyr:code-sample:`blinky code sample ` for more information. + + Will render as: + + Check out :zephyr:code-sample:`blinky code sample ` for more information. From 2cef27865f51c66cdd69c764114b8c34045009c7 Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Wed, 3 Jul 2024 10:45:24 +0200 Subject: [PATCH 260/269] drivers: flash: cc13xx_cc26xx: Add support of write to flash from flash Currently, if we try to write data from a memory mapped flash address to the flash then we get a -EINVAL error. This could break the settings subsystem when we use NVS backend. In order to make it work, add a buffer and use it when we want to write data that is located in flash address space. This has been tested using sample/subsys/settings/ Signed-off-by: Alexandre Bailon --- drivers/flash/soc_flash_cc13xx_cc26xx.c | 49 ++++++++++++++++++------- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/drivers/flash/soc_flash_cc13xx_cc26xx.c b/drivers/flash/soc_flash_cc13xx_cc26xx.c index c1cabf0acc09972..f1cb7c464119f17 100644 --- a/drivers/flash/soc_flash_cc13xx_cc26xx.c +++ b/drivers/flash/soc_flash_cc13xx_cc26xx.c @@ -21,6 +21,7 @@ #define FLASH_ERASE_SIZE DT_PROP(SOC_NV_FLASH_NODE, erase_block_size) #define FLASH_WRITE_SIZE DT_PROP(SOC_NV_FLASH_NODE, write_block_size) +#define WRITE_BUFFER_LEN (32) struct flash_priv { struct k_sem mutex; @@ -161,6 +162,26 @@ static int flash_cc13xx_cc26xx_erase(const struct device *dev, off_t offs, return rc; } +static int flash_cc13xx_cc26xx_buffered_write(off_t offs, const void *data, size_t size) +{ + uint8_t write_buffer[WRITE_BUFFER_LEN]; + int rc; + + for (int i = 0; i < size; i += WRITE_BUFFER_LEN) { + size_t len = MIN(size - i, WRITE_BUFFER_LEN); + + memcpy(write_buffer, (uint8_t *)data + i, len); + rc = FlashProgram(write_buffer, offs, len); + if (rc != FAPI_STATUS_SUCCESS) { + rc = -EIO; + break; + } + offs += len; + } + + return rc; +} + static int flash_cc13xx_cc26xx_write(const struct device *dev, off_t offs, const void *data, size_t size) { @@ -181,16 +202,6 @@ static int flash_cc13xx_cc26xx_write(const struct device *dev, off_t offs, return -EINVAL; } - /* - * From TI's HAL 'driverlib/flash.h': - * - * The pui8DataBuffer pointer can not point to flash. - */ - if ((data >= (void *)FLASH_ADDR) && - (data <= (void *)(FLASH_ADDR + FLASH_SIZE))) { - return -EINVAL; - } - if (flash_cc13xx_cc26xx_range_protected(offs, size)) { return -EINVAL; } @@ -206,9 +217,21 @@ static int flash_cc13xx_cc26xx_write(const struct device *dev, off_t offs, while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) { ; } - rc = FlashProgram((uint8_t *)data, offs, size); - if (rc != FAPI_STATUS_SUCCESS) { - rc = -EIO; + + /* + * From TI's HAL 'driverlib/flash.h': + * + * The pui8DataBuffer pointer can not point to flash. + * Use a buffer in this situation. + */ + if ((data >= (void *)FLASH_ADDR) && + (data <= (void *)(FLASH_ADDR + FLASH_SIZE))) { + rc = flash_cc13xx_cc26xx_buffered_write(offs, data, size); + } else { + rc = FlashProgram((uint8_t *)data, offs, size); + if (rc != FAPI_STATUS_SUCCESS) { + rc = -EIO; + } } irq_unlock(key); From c75186f5cacd792453cb1d0ad72d3fb856cb5b4f Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Fri, 24 May 2024 14:14:37 +0200 Subject: [PATCH 261/269] samples: subsys: settings: Add configuration for cc1352p7 Add configuration needed to run the sample on cc1352p7 SoC. Signed-off-by: Alexandre Bailon --- samples/subsys/settings/socs/cc1352p7.conf | 1 + 1 file changed, 1 insertion(+) create mode 100644 samples/subsys/settings/socs/cc1352p7.conf diff --git a/samples/subsys/settings/socs/cc1352p7.conf b/samples/subsys/settings/socs/cc1352p7.conf new file mode 100644 index 000000000000000..ca92a061c6a370a --- /dev/null +++ b/samples/subsys/settings/socs/cc1352p7.conf @@ -0,0 +1 @@ +CONFIG_NVS=y From f44072c299cfd88a86e5cabb82422b33bc5e8e18 Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Mon, 29 Apr 2024 12:31:30 +0200 Subject: [PATCH 262/269] drivers: ieee802154: cc13xx_cc26xx: Fixup a bus error Sometime, the radio causes a bus error. This happens because we cast a struct and access to a member that doesn't exists in the original struct. This updates the driver to use the right struct to make the cast safe. Signed-off-by: Alexandre Bailon --- drivers/ieee802154/ieee802154_cc13xx_cc26xx.c | 6 ++++++ drivers/ieee802154/ieee802154_cc13xx_cc26xx.h | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c index 263b98d2823d79f..06e6e6aaab6321c 100644 --- a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c +++ b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c @@ -777,7 +777,13 @@ static struct ieee802154_cc13xx_cc26xx_data ieee802154_cc13xx_cc26xx_data = { }, .cmd_radio_setup = { +#if defined(CONFIG_SOC_CC1352R) || defined(CONFIG_SOC_CC2652R) || \ + defined(CONFIG_SOC_CC1352R7) || defined(CONFIG_SOC_CC2652R7) .commandNo = CMD_RADIO_SETUP, +#elif defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC2652P) || \ + defined(CONFIG_SOC_CC1352P7) || defined(CONFIG_SOC_CC2652P7) + .commandNo = CMD_RADIO_SETUP_PA, +#endif /* CONFIG_SOC_CCxx52x */ .status = IDLE, .pNextOp = NULL, .startTrigger.triggerType = TRIG_NOW, diff --git a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h index 185e445a175de05..4d4ee4588df42c9 100644 --- a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h +++ b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.h @@ -80,7 +80,15 @@ struct ieee802154_cc13xx_cc26xx_data { volatile rfc_CMD_IEEE_CSMA_t cmd_ieee_csma; volatile rfc_CMD_IEEE_TX_t cmd_ieee_tx; volatile rfc_CMD_IEEE_RX_ACK_t cmd_ieee_rx_ack; +#if defined(CONFIG_SOC_CC1352R) || defined(CONFIG_SOC_CC2652R) || \ + defined(CONFIG_SOC_CC1352R7) || defined(CONFIG_SOC_CC2652R7) volatile rfc_CMD_RADIO_SETUP_t cmd_radio_setup; +#elif defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC2652P) || \ + defined(CONFIG_SOC_CC1352P7) || defined(CONFIG_SOC_CC2652P7) + volatile rfc_CMD_RADIO_SETUP_PA_t cmd_radio_setup; +#else + BUILD_ASSERT(false, "unknown model"); +#endif /* CONFIG_SOC_CCxx52x */ volatile int16_t saved_cmdhandle; }; From 3341298c0cf0079ab77f1c34fdaf86f9dd795e19 Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Fri, 12 Apr 2024 20:56:57 +0200 Subject: [PATCH 263/269] drivers: ieee802154: cc13xx_cc26xx: Enable support of OpenThread L2 This updates the driver to enable support of OpenThread L2. Signed-off-by: Alexandre Bailon --- drivers/ieee802154/ieee802154_cc13xx_cc26xx.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c index 06e6e6aaab6321c..62f0a151b3d7838 100644 --- a/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c +++ b/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c @@ -31,6 +31,10 @@ LOG_MODULE_REGISTER(ieee802154_cc13xx_cc26xx); #include "ieee802154_cc13xx_cc26xx.h" +#if defined(CONFIG_NET_L2_OPENTHREAD) +#include +#endif + /* Overrides from SmartRF Studio 7 2.13.0 */ static uint32_t overrides[] = { /* DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3). */ @@ -802,11 +806,21 @@ static struct ieee802154_cc13xx_cc26xx_data ieee802154_cc13xx_cc26xx_data = { }; #if defined(CONFIG_NET_L2_IEEE802154) +#define L2 IEEE802154_L2 +#define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(IEEE802154_L2) +#define MTU IEEE802154_MTU +#elif defined(CONFIG_NET_L2_OPENTHREAD) +#define L2 OPENTHREAD_L2 +#define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(OPENTHREAD_L2) +#define MTU 1280 +#endif + +#if defined(CONFIG_NET_L2_IEEE802154) || defined(CONFIG_NET_L2_PHY_IEEE802154) NET_DEVICE_DT_INST_DEFINE(0, ieee802154_cc13xx_cc26xx_init, NULL, &ieee802154_cc13xx_cc26xx_data, NULL, CONFIG_IEEE802154_CC13XX_CC26XX_INIT_PRIO, - &ieee802154_cc13xx_cc26xx_radio_api, IEEE802154_L2, - NET_L2_GET_CTX_TYPE(IEEE802154_L2), IEEE802154_MTU); + &ieee802154_cc13xx_cc26xx_radio_api, L2, + L2_CTX_TYPE, MTU); #else DEVICE_DT_INST_DEFINE(0, ieee802154_cc13xx_cc26xx_init, NULL, &ieee802154_cc13xx_cc26xx_data, NULL, POST_KERNEL, From 7a49ed899d9f2ad8210671fbd8cc81fe1314188a Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Sun, 18 Aug 2024 19:35:27 +0200 Subject: [PATCH 264/269] boards: ti: launchxl: Add support of UART1 Some examples may require the usage of a second UART. This adds UART1 to common launchxl.dtsi in order to make it available for these examples. Signed-off-by: Alexandre Bailon --- boards/ti/common/launchxl-pinctrl.dtsi | 11 +++++++++++ boards/ti/common/launchxl.dtsi | 7 +++++++ 2 files changed, 18 insertions(+) diff --git a/boards/ti/common/launchxl-pinctrl.dtsi b/boards/ti/common/launchxl-pinctrl.dtsi index a522a57d8aa1232..192d49e08aaa1b6 100644 --- a/boards/ti/common/launchxl-pinctrl.dtsi +++ b/boards/ti/common/launchxl-pinctrl.dtsi @@ -18,6 +18,17 @@ input-enable; }; + /* UART1 */ + uart1_tx_default: uart1_tx_default { + pinmux = <22 IOC_PORT_MCU_UART1_TX>; + bias-disable; + }; + uart1_rx_default: uart1_rx_default { + pinmux = <24 IOC_PORT_MCU_UART1_RX>; + bias-disable; + input-enable; + }; + /* I2C0 */ i2c0_scl_default: i2c0_scl_default { pinmux = <4 IOC_PORT_MCU_I2C_MSSCL>; diff --git a/boards/ti/common/launchxl.dtsi b/boards/ti/common/launchxl.dtsi index 9b2b58a9d88c0f5..479489f83b60a91 100644 --- a/boards/ti/common/launchxl.dtsi +++ b/boards/ti/common/launchxl.dtsi @@ -76,6 +76,13 @@ pinctrl-names = "default"; }; +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default>; + pinctrl-names = "default"; +}; + &i2c0 { status = "okay"; pinctrl-0 = <&i2c0_scl_default &i2c0_sda_default>; From 80bf9bf5c8bd9b32fc7de56986dc4c8b9f7bdab3 Mon Sep 17 00:00:00 2001 From: Alexandre Bailon Date: Fri, 12 Apr 2024 21:02:51 +0200 Subject: [PATCH 265/269] openthread: coprocessor: Enable support of cc1352p7 lp This adds a dt overlay to enable support of cc1352p7 lp to the openthread coprocessor sample application. Signed-off-by: Alexandre Bailon --- .../coprocessor/boards/cc1352p7_lp.overlay | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 samples/net/openthread/coprocessor/boards/cc1352p7_lp.overlay diff --git a/samples/net/openthread/coprocessor/boards/cc1352p7_lp.overlay b/samples/net/openthread/coprocessor/boards/cc1352p7_lp.overlay new file mode 100644 index 000000000000000..8e5042621b0d9e4 --- /dev/null +++ b/samples/net/openthread/coprocessor/boards/cc1352p7_lp.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Alexandre Bailon + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /* Use XDS110 UART for the NCP */ + zephyr,ot-uart = &uart0; + /* Use UART1 for debugging / zephyr console */ + zephyr,shell-uart = &uart1; + zephyr,console = &uart1; + }; +}; + +&uart1 { + status = "okay"; +}; From 9d9089edd09919c90c4224222fc2c560410e6c85 Mon Sep 17 00:00:00 2001 From: Arkadiusz Cholewinski Date: Wed, 26 Jun 2024 15:24:10 +0200 Subject: [PATCH 266/269] ztest: Add Support for Multiple Test Runs. Introduces new kconfig options to enable multiple test runs in the ztest. Signed-off-by: Arkadiusz Cholewinski --- doc/develop/test/ztest.rst | 12 +++++--- subsys/testsuite/ztest/Kconfig | 33 ++++++++++++++++----- subsys/testsuite/ztest/src/ztest.c | 8 ++++- tests/net/lib/lwm2m/block_transfer/prj.conf | 1 + tests/subsys/ipc/pbuf/prj.conf | 1 + tests/subsys/modem/backends/uart/prj.conf | 3 +- tests/ztest/base/prj_verbose_0.conf | 5 ++-- tests/ztest/base/prj_verbose_1.conf | 5 ++-- tests/ztest/base/src/main.c | 4 +-- 9 files changed, 53 insertions(+), 19 deletions(-) diff --git a/doc/develop/test/ztest.rst b/doc/develop/test/ztest.rst index a14ebad2d42dbf9..8e5ccddd6a92c87 100644 --- a/doc/develop/test/ztest.rst +++ b/doc/develop/test/ztest.rst @@ -602,11 +602,15 @@ randomize the order. The output from the test will display the seed for failed tests. For native simulator builds you can provide the seed as an argument to twister with ``--seed``. -Static configuration of ZTEST_SHUFFLE contains: - - - :kconfig:option:`CONFIG_ZTEST_SHUFFLE_SUITE_REPEAT_COUNT` - Number of iterations the test suite will run. - - :kconfig:option:`CONFIG_ZTEST_SHUFFLE_TEST_REPEAT_COUNT` - Number of iterations the test will run. +Repeating Tests +*********************** +By default the tests are executed once. The test cases and test suites +may be executed multiple times. Enable :kconfig:option:`CONFIG_ZTEST_REPEAT` to +execute the tests multiple times. By default the multiplication factors are 3, which +means every test suite is executed 3 times and every test case is executed 3 times. This can +be changed by the :kconfig:option:`CONFIG_ZTEST_SUITE_REPEAT_COUNT` and +:kconfig:option:`CONFIG_ZTEST_TEST_REPEAT_COUNT` Kconfig options. Test Selection ************** diff --git a/subsys/testsuite/ztest/Kconfig b/subsys/testsuite/ztest/Kconfig index 04ad029985822f8..02eb742dcf1ba15 100644 --- a/subsys/testsuite/ztest/Kconfig +++ b/subsys/testsuite/ztest/Kconfig @@ -150,22 +150,41 @@ config ZTEST_SHUFFLE if ZTEST_SHUFFLE config ZTEST_SHUFFLE_SUITE_REPEAT_COUNT - int "Number of iterations the test suite will run" + int "[DEPRECATED] Number of iterations the test suite will run" default 3 help - This rule will execute a test suite N number of times. The tests - per suite will be shuffled on each iteration. The test order will likely - be different per iteration. + This is used to execute a test suite N number of times. + [DEPRECATED] use ZTEST_SUITE_REPEAT_COUNT instead. config ZTEST_SHUFFLE_TEST_REPEAT_COUNT - int "Number of iterations the test will run" + int "[DEPRECATED] Number of iterations the test will run" default 3 help - This rule will execute a test N number of times. The test order will - likely be different per iteration. + This is used to execute a test case N number of times. + [DEPRECATED] use ZTEST_TEST_REPEAT_COUNT instead. endif #ZTEST_SHUFFLE +config ZTEST_REPEAT + bool "Repeat the tests and suites" + help + This rule will repeat the tests and the test suites. + +if ZTEST_REPEAT +config ZTEST_SUITE_REPEAT_COUNT + int "Number of iterations the test suite will run" + default 3 + help + This rule will execute a test suite N number of times. + +config ZTEST_TEST_REPEAT_COUNT + int "Number of iterations the test will run" + default 3 + help + This rule will execute a test N number of times. + +endif #ZTEST_REPEAT + config ZTEST_SUMMARY bool "Display test summary" default y diff --git a/subsys/testsuite/ztest/src/ztest.c b/subsys/testsuite/ztest/src/ztest.c index 279ca4d9ac0a16d..396cf65b638a09e 100644 --- a/subsys/testsuite/ztest/src/ztest.c +++ b/subsys/testsuite/ztest/src/ztest.c @@ -30,9 +30,15 @@ static bool failed_expectation; #include #include #include - +#ifndef CONFIG_ZTEST_REPEAT #define NUM_ITER_PER_SUITE CONFIG_ZTEST_SHUFFLE_SUITE_REPEAT_COUNT #define NUM_ITER_PER_TEST CONFIG_ZTEST_SHUFFLE_TEST_REPEAT_COUNT +#endif +#endif /* CONFIG_ZTEST_SHUFFLE */ + +#ifdef CONFIG_ZTEST_REPEAT +#define NUM_ITER_PER_SUITE CONFIG_ZTEST_SUITE_REPEAT_COUNT +#define NUM_ITER_PER_TEST CONFIG_ZTEST_TEST_REPEAT_COUNT #else #define NUM_ITER_PER_SUITE 1 #define NUM_ITER_PER_TEST 1 diff --git a/tests/net/lib/lwm2m/block_transfer/prj.conf b/tests/net/lib/lwm2m/block_transfer/prj.conf index ea874ac5925f696..2b036cf0c8e2483 100644 --- a/tests/net/lib/lwm2m/block_transfer/prj.conf +++ b/tests/net/lib/lwm2m/block_transfer/prj.conf @@ -8,6 +8,7 @@ CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_LWM2M_LOG_ENCODE_BUFFER_ALLOCATIONS=y CONFIG_ZTEST_SHUFFLE=y +CONFIG_ZTEST_REPEAT=y CONFIG_LWM2M=y CONFIG_LWM2M_COAP_BLOCK_TRANSFER=y diff --git a/tests/subsys/ipc/pbuf/prj.conf b/tests/subsys/ipc/pbuf/prj.conf index 3dca34304fca329..039e336da5e32f3 100644 --- a/tests/subsys/ipc/pbuf/prj.conf +++ b/tests/subsys/ipc/pbuf/prj.conf @@ -1,6 +1,7 @@ CONFIG_ZTEST=y CONFIG_ZTRESS=y CONFIG_ZTEST_SHUFFLE=y +CONFIG_ZTEST_REPEAT=y CONFIG_IPC_SERVICE=y CONFIG_IPC_SERVICE_ICMSG=y diff --git a/tests/subsys/modem/backends/uart/prj.conf b/tests/subsys/modem/backends/uart/prj.conf index fd93accbb08a983..349a8efb8ba5b99 100644 --- a/tests/subsys/modem/backends/uart/prj.conf +++ b/tests/subsys/modem/backends/uart/prj.conf @@ -7,4 +7,5 @@ CONFIG_SERIAL=y CONFIG_ZTEST=y CONFIG_LOG=y CONFIG_ZTEST_SHUFFLE=y -CONFIG_ZTEST_SHUFFLE_TEST_REPEAT_COUNT=3 +CONFIG_ZTEST_REPEAT=y +CONFIG_ZTEST_TEST_REPEAT_COUNT=3 diff --git a/tests/ztest/base/prj_verbose_0.conf b/tests/ztest/base/prj_verbose_0.conf index 4a5ace8ad174fee..4aae956442f0ed2 100644 --- a/tests/ztest/base/prj_verbose_0.conf +++ b/tests/ztest/base/prj_verbose_0.conf @@ -6,5 +6,6 @@ CONFIG_TEST_RANDOM_GENERATOR=y CONFIG_TIMER_RANDOM_GENERATOR=y CONFIG_ZTEST_SHUFFLE=y -CONFIG_ZTEST_SHUFFLE_SUITE_REPEAT_COUNT=2 -CONFIG_ZTEST_SHUFFLE_TEST_REPEAT_COUNT=2 +CONFIG_ZTEST_REPEAT=y +CONFIG_ZTEST_SUITE_REPEAT_COUNT=2 +CONFIG_ZTEST_TEST_REPEAT_COUNT=2 diff --git a/tests/ztest/base/prj_verbose_1.conf b/tests/ztest/base/prj_verbose_1.conf index 885394fe91818e3..63c131ce7c74e30 100644 --- a/tests/ztest/base/prj_verbose_1.conf +++ b/tests/ztest/base/prj_verbose_1.conf @@ -2,6 +2,7 @@ CONFIG_ZTEST=y CONFIG_ZTEST_ASSERT_VERBOSE=1 CONFIG_ZTEST_SHUFFLE=y -CONFIG_ZTEST_SHUFFLE_SUITE_REPEAT_COUNT=2 -CONFIG_ZTEST_SHUFFLE_TEST_REPEAT_COUNT=2 +CONFIG_ZTEST_REPEAT=y +CONFIG_ZTEST_SUITE_REPEAT_COUNT=2 +CONFIG_ZTEST_TEST_REPEAT_COUNT=2 CONFIG_ENTROPY_GENERATOR=y diff --git a/tests/ztest/base/src/main.c b/tests/ztest/base/src/main.c index a805fd41af1519e..db5929f996bb61c 100644 --- a/tests/ztest/base/src/main.c +++ b/tests/ztest/base/src/main.c @@ -153,8 +153,8 @@ static void rule_test_teardown(void *data) * after_each function was called. */ zassert_equal(fixture->state, RULE_STATE_AFTER_EACH, "Unexpected state"); -#ifdef CONFIG_ZTEST_SHUFFLE - zassert_equal(fixture->run_count, CONFIG_ZTEST_SHUFFLE_TEST_REPEAT_COUNT); +#ifdef CONFIG_ZTEST_REPEAT + zassert_equal(fixture->run_count, CONFIG_ZTEST_TEST_REPEAT_COUNT); #endif } From b44a1ab9073235deea4695f60daf581de27c671d Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Fri, 13 Sep 2024 14:07:28 -0300 Subject: [PATCH 267/269] boards: arduino_nicla_vision: add camera subsystem initial support on device tree Signed-off-by: Felipe Neves --- boards/arduino/nicla_vision/CMakeLists.txt | 4 + .../arduino_nicla_vision_stm32h747xx_m7.dts | 86 +++++++++++++++++-- .../arduino/nicla_vision/camera_ext_clock.c | 42 +++++++++ boards/arduino/nicla_vision/doc/index.rst | 2 + 4 files changed, 127 insertions(+), 7 deletions(-) create mode 100644 boards/arduino/nicla_vision/CMakeLists.txt create mode 100644 boards/arduino/nicla_vision/camera_ext_clock.c diff --git a/boards/arduino/nicla_vision/CMakeLists.txt b/boards/arduino/nicla_vision/CMakeLists.txt new file mode 100644 index 000000000000000..31b0b2ec5934def --- /dev/null +++ b/boards/arduino/nicla_vision/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright 2024 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_VIDEO camera_ext_clock.c) diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts index ffd72fe9fb71ea9..1fe8d2f96109906 100644 --- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts +++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.dts @@ -22,6 +22,7 @@ zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,code-partition = &slot0_partition; + zephyr,camera = &dcmi; }; sdram1: sdram@c0000000 { @@ -122,13 +123,6 @@ }; }; -&i2c3 { - status = "okay"; - pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pc9>; - pinctrl-names = "default"; - clock-frequency = ; -}; - &spi4 { status = "okay"; pinctrl-0 = <&spi4_nss_pe11 &spi4_sck_pe12 @@ -192,3 +186,81 @@ zephyr_udc0: &usbotg_hs { phys = <&otghs_ulpi_phy>; status = "okay"; }; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pc9>; + pinctrl-names = "default"; + clock-frequency = ; + + gc2145: gc2145@3c { + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + status = "okay"; + + port { + gc2145_ep_out: endpoint { + remote-endpoint = <&dcmi_ep_in>; + }; + }; + + }; +}; + +&dcmi { + pinctrl-0 = <&dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pe0 &dcmi_d3_pe1 + &dcmi_d4_pe4 &dcmi_d5_pd3 &dcmi_d6_pe5 &dcmi_d7_pe6 + &dcmi_pixclk_pa6 &dcmi_hsync_pa4 &dcmi_vsync_pg9>; + + pinctrl-names = "default"; + status = "okay"; + + sensor = <&gc2145>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + capture-rate = <1>; + dmas = <&dma1 0 38 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC | + STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS | + STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>; + + port { + dcmi_ep_in: endpoint { + remote-endpoint = <&gc2145_ep_out>; + }; + }; +}; + +/* The Arduino nicla uses a PWM output to generate the clock for the + * GC2145 sensor, so we need to configure the PWM generator... + */ +&timers3 { + status = "okay"; + st,prescaler = <0>; + + cam_clock_pwm: pwm { + status = "okay"; + pinctrl-0 = <&tim3_ch2_pa7>; + pinctrl-names = "default"; + }; +}; + +&cam_clock_pwm { + /* ...then use the pwmclock node to start the clock generation */ + pwmclock: pwmclock { + status = "okay"; + compatible = "pwm-clock"; + clock-frequency = <0>; + #clock-cells = <1>; + pwms = <&cam_clock_pwm 2 PWM_HZ(10000000) PWM_POLARITY_NORMAL>; + }; +}; + +&dma1 { + status = "okay"; +}; + +&dmamux1 { + status = "okay"; +}; diff --git a/boards/arduino/nicla_vision/camera_ext_clock.c b/boards/arduino/nicla_vision/camera_ext_clock.c new file mode 100644 index 000000000000000..82b3695feb7d038 --- /dev/null +++ b/boards/arduino/nicla_vision/camera_ext_clock.c @@ -0,0 +1,42 @@ +/* + * Copyright 2024 Felipe Neves + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +LOG_MODULE_REGISTER(camera_ext_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL); + +int camera_ext_clock_enable(void) +{ + int ret; + uint32_t rate; + const struct device *cam_ext_clk_dev = DEVICE_DT_GET(DT_NODELABEL(pwmclock)); + + if (!device_is_ready(cam_ext_clk_dev)) { + LOG_ERR("Camera external clock source device is not ready!"); + return -ENODEV; + } + + ret = clock_control_on(cam_ext_clk_dev, (clock_control_subsys_t)0); + if (ret < 0) { + LOG_ERR("Failed to enable camera external clock error: (%d)", ret); + return ret; + } + + ret = clock_control_get_rate(cam_ext_clk_dev, (clock_control_subsys_t)0, &rate); + if (ret < 0) { + LOG_ERR("Failed to get camera external clock rate, error: (%d)", ret); + return ret; + } + + LOG_INF("Camera external clock rate: (%u) Hz", rate); + + return 0; +} + +SYS_INIT(camera_ext_clock_enable, POST_KERNEL, CONFIG_CLOCK_CONTROL_PWM_INIT_PRIORITY); diff --git a/boards/arduino/nicla_vision/doc/index.rst b/boards/arduino/nicla_vision/doc/index.rst index fac12f25fac61d9..73b2d7cd7337e0b 100644 --- a/boards/arduino/nicla_vision/doc/index.rst +++ b/boards/arduino/nicla_vision/doc/index.rst @@ -61,6 +61,8 @@ following hardware features: +-----------+------------+-------------------------------------+ | SPI | on-chip | spi | +-----------+------------+-------------------------------------+ +| DCMI | on-chip | Parallel Camera interface | ++-----------+------------+-------------------------------------+ | IPM | on-chip | virtual mailbox based on HSEM | +-----------+------------+-------------------------------------+ | RADIO | Murata 1DX | WiFi and Bluetooth module | From 97898fe579c3b31c4a38b81af2b7d20bc1fc4454 Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Wed, 18 Sep 2024 16:18:20 -0300 Subject: [PATCH 268/269] drivers: video: gc2145: add resolution support Add VGA and QVGA resolution support to enable usage of gc2145 sensor by smaller ram capable devices. Signed-off-by: Felipe Neves --- drivers/video/gc2145.c | 77 ++++++++++++++++++++++++++++++++---------- 1 file changed, 59 insertions(+), 18 deletions(-) diff --git a/drivers/video/gc2145.c b/drivers/video/gc2145.c index 19404c27e9cf6f7..e6ea122795de9c2 100644 --- a/drivers/video/gc2145.c +++ b/drivers/video/gc2145.c @@ -701,10 +701,19 @@ struct gc2145_data { } static const struct video_format_cap fmts[] = { + GC2145_VIDEO_FORMAT_CAP(320, 240, VIDEO_PIX_FMT_RGB565), /* QVGA */ + GC2145_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565), /* VGA */ GC2145_VIDEO_FORMAT_CAP(1600, 1200, VIDEO_PIX_FMT_RGB565), /* UXGA */ {0}, }; +enum vga_resultions { + QVGA_RESOLUTION = 0, + VGA_RESOLUTION, + UXGA_RESOLUTION, +}; + + static int gc2145_write_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr, uint8_t value) { int ret; @@ -901,28 +910,59 @@ static int gc2145_set_output_format(const struct device *dev, int output_format) return 0; } -static int gc2145_set_resolution(const struct device *dev, uint16_t img_width, uint16_t img_height) +static int gc2145_set_resolution(const struct device *dev, uint16_t img_width, + uint16_t img_height, enum vga_resultions vga_res) { int ret; const struct gc2145_config *cfg = dev->config; - uint16_t win_w = UXGA_HSIZE + 16; - uint16_t win_h = UXGA_VSIZE + 8; - uint16_t c_ratio = 1; - uint16_t r_ratio = 1; - uint16_t x = (((win_w / c_ratio) - UXGA_HSIZE) / 2); - uint16_t y = (((win_h / r_ratio) - UXGA_VSIZE) / 2); - uint16_t win_x = ((UXGA_HSIZE - win_w) / 2); - uint16_t win_y = ((UXGA_VSIZE - win_h) / 2); + uint16_t w = img_width; + uint16_t h = img_height; + uint16_t win_w; + uint16_t win_h; + uint16_t c_ratio; + uint16_t r_ratio; + uint16_t x; + uint16_t y; + uint16_t win_x; + uint16_t win_y; + + /* Add the subsampling factor depending on resolution */ + switch (vga_res) { + case QVGA_RESOLUTION: + win_w = w * 3; + win_h = h * 3; + break; + case VGA_RESOLUTION: + win_w = w * 2; + win_h = h * 2; + break; + case UXGA_RESOLUTION: + win_w = w * 2; + win_h = h * 2; + break; + default: + LOG_ERR("Resolution format not supported!"); + return -EIO; + }; + + /* Calculates the window boundaries to obtain the desired resolution */ + c_ratio = win_w / w; + r_ratio = win_h / h; + x = (((win_w / c_ratio) - w) / 2); + y = (((win_h / r_ratio) - h) / 2); + win_x = ((UXGA_HSIZE - win_w) / 2); + win_y = ((UXGA_VSIZE - win_h) / 2); /* Set readout window first. */ - ret = gc2145_set_window(dev, GC2145_REG_BLANK_WINDOW_BASE, win_x, win_y, win_w, win_h); + ret = gc2145_set_window(dev, GC2145_REG_BLANK_WINDOW_BASE, win_x, win_y, win_w + 16, + win_h + 8); if (ret < 0) { return ret; } /* Set cropping window next. */ - ret = gc2145_set_window(dev, GC2145_REG_WINDOW_BASE, x, y, 1, 1); + ret = gc2145_set_window(dev, GC2145_REG_WINDOW_BASE, x, y, w, h); if (ret < 0) { return ret; } @@ -972,8 +1012,7 @@ static uint8_t gc2145_check_connection(const struct device *dev) } if ((reg_ver_val != GC2145_REV_VAL) || (reg_pid_val != GC2145_PID_VAL)) { - LOG_ERR("failed to detect GC2145 pid: 0x%x rev: 0x%x", reg_pid_val, reg_ver_val); - return -EIO; + LOG_WRN("Unexpected GC2145 pid: 0x%x or rev: 0x%x", reg_pid_val, reg_ver_val); } return 0; @@ -1014,7 +1053,8 @@ static int gc2145_set_fmt(const struct device *dev, enum video_endpoint_id ep, if (fmts[i].width_min == width && fmts[i].height_min == height && fmts[i].pixelformat == fmt->pixelformat) { /* Set window size */ - ret = gc2145_set_resolution(dev, fmt->width, fmt->height); + ret = gc2145_set_resolution(dev, fmt->width, fmt->height, + (enum vga_resultions)i); if (ret < 0) { LOG_ERR("Failed to set the resolution"); } @@ -1105,11 +1145,12 @@ static int gc2145_init(const struct device *dev) gc2145_soft_reset(dev); gc2145_write_all(dev, default_regs, ARRAY_SIZE(default_regs)); - /* set default/init format SVGA RGB565 */ + /* set default/init format QVGA RGB565 */ fmt.pixelformat = VIDEO_PIX_FMT_RGB565; - fmt.width = UXGA_HSIZE; - fmt.height = UXGA_VSIZE; - fmt.pitch = UXGA_HSIZE * 2; + fmt.width = fmts[QVGA_RESOLUTION].width_min; + fmt.height = fmts[QVGA_RESOLUTION].height_min; + fmt.pitch = fmts[QVGA_RESOLUTION].width_min * 2; + ret = gc2145_set_fmt(dev, VIDEO_EP_OUT, &fmt); if (ret) { LOG_ERR("Unable to configure default format"); From a04a9d545e252b70fb327b5d1fc970abb6f3dc4b Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Wed, 18 Sep 2024 16:54:31 -0300 Subject: [PATCH 269/269] samples: drivers: video: add arduino nicla vision As supported board to the video capture sample. Signed-off-by: Felipe Neves --- samples/drivers/video/capture/README.rst | 13 +++++++++++++ .../arduino_nicla_vision_stm32h747xx_m7.conf | 15 +++++++++++++++ ...rduino_nicla_vision_stm32h747xx_m7.overlay | 19 +++++++++++++++++++ samples/drivers/video/capture/sample.yaml | 1 + samples/drivers/video/capture/src/main.c | 2 +- 5 files changed, 49 insertions(+), 1 deletion(-) create mode 100644 samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.conf create mode 100644 samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.overlay diff --git a/samples/drivers/video/capture/README.rst b/samples/drivers/video/capture/README.rst index eace71ecff06229..225a622eacc8cb9 100644 --- a/samples/drivers/video/capture/README.rst +++ b/samples/drivers/video/capture/README.rst @@ -24,6 +24,9 @@ Supported camera modules on some i.MX RT boards can be found below. - :ref:`mimxrt1170_evk` - `OV5640 camera module`_ +Also :ref:`arduino_nicla_vision` can be used in this sample as capture device, in that case +The user can transfer the captured frames through on board USB. + Wiring ****** @@ -35,6 +38,8 @@ On :ref:`mimxrt1170_evk`, the OV5640 camera module should be plugged into the J2 camera connector. A USB cable should be connected from a host to the micro USB debug connector (J11) in order to get console output via the daplink interface. +For :ref:`arduino_nicla_vision` there is no extra wiring required. + Building and Running ******************** @@ -56,6 +61,14 @@ For :ref:`mimxrt1170_evk`, build this sample application with the following comm :goals: build :compact: +For :ref:`arduino_nicla_vision`, build this sample application with the following commands: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/video/capture + :board: arduino_nicla_vision/stm32h747xx/m7 + :goals: build + :compact: + For testing purpose without the need of any real video capture and/or display hardwares, a video software pattern generator is supported by the above build commands without specifying the shields. diff --git a/samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.conf b/samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.conf new file mode 100644 index 000000000000000..6ae5e7da478a6ca --- /dev/null +++ b/samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.conf @@ -0,0 +1,15 @@ +CONFIG_VIDEO_BUFFER_POOL_NUM_MAX=1 +CONFIG_VIDEO_BUFFER_POOL_SZ_MAX=160000 +CONFIG_DMA=y + +# Arduino Nicla Vision has easy access to the USB console +# So use it to check the log messages +CONFIG_USB_DEVICE_STACK=y +CONFIG_USB_WORKQUEUE_STACK_SIZE=8192 +CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=y +CONFIG_MAIN_STACK_SIZE=4096 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_LINE_CTRL=y diff --git a/samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.overlay b/samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.overlay new file mode 100644 index 000000000000000..6485c095e435766 --- /dev/null +++ b/samples/drivers/video/capture/boards/arduino_nicla_vision_stm32h747xx_m7.overlay @@ -0,0 +1,19 @@ +/* + * Copyright 2024 Felipe Neves + * + * SPDX-License-Identifier: Apache-2.0 + */ +/ { + chosen { + zephyr,console = &cdc_acm_uart0; + zephyr,shell-uart = &cdc_acm_uart0; + zephyr,cdc-acm-uart0 = &cdc_acm_uart0; + }; +}; + +zephyr_udc0: &usbotg_hs { + status = "okay"; + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; +}; diff --git a/samples/drivers/video/capture/sample.yaml b/samples/drivers/video/capture/sample.yaml index 34eaffdec69c42e..882796cf674bbc4 100644 --- a/samples/drivers/video/capture/sample.yaml +++ b/samples/drivers/video/capture/sample.yaml @@ -11,6 +11,7 @@ tests: - platform:mimxrt1064_evk:SHIELD="dvp_fpc24_mt9m114;rk043fn66hs_ctg" - platform:mimxrt1170_evk/mimxrt1176/cm7:SHIELD="nxp_btb44_ov5640;rk055hdmipi4ma0" platform_allow: + - arduino_nicla_vision/stm32h747xx/m7 - mimxrt1064_evk - mimxrt1170_evk/mimxrt1176/cm7 - mm_swiftio diff --git a/samples/drivers/video/capture/src/main.c b/samples/drivers/video/capture/src/main.c index 862dff287f7aa5e..d04d0de0954d627 100644 --- a/samples/drivers/video/capture/src/main.c +++ b/samples/drivers/video/capture/src/main.c @@ -75,7 +75,7 @@ static inline void video_display_frame(const struct device *const display_dev, int main(void) { - struct video_buffer *buffers[2], *vbuf; + struct video_buffer *buffers[CONFIG_VIDEO_BUFFER_POOL_NUM_MAX], *vbuf; struct video_format fmt; struct video_caps caps; unsigned int frame = 0;