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LucasTamborcarlescufi
LucasTambor
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carlescufi
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drivers: esp32: update to hal_espressif v5.1
Modify necessary drivers to meet updated hal. Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com> Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
1 parent 37f9958 commit fe57a12

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20 files changed

+660
-479
lines changed

20 files changed

+660
-479
lines changed

‎drivers/adc/adc_esp32.c‎

Lines changed: 8 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -10,42 +10,27 @@
1010
#include <hal/adc_hal.h>
1111
#include <hal/adc_types.h>
1212
#include <esp_adc_cal.h>
13-
#include <esp_heap_caps.h>
13+
#include <esp_private/periph_ctrl.h>
1414

1515
#include <zephyr/kernel.h>
1616
#include <zephyr/device.h>
1717
#include <zephyr/drivers/adc.h>
18-
#include "driver/periph_ctrl.h"
1918

2019
#include <zephyr/logging/log.h>
2120
LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL);
2221

23-
#if CONFIG_SOC_SERIES_ESP32
24-
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF
2522
#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH
2623
#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH
2724

25+
#if CONFIG_SOC_SERIES_ESP32
26+
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF
2827
/* Due to significant measurement discrepancy in higher voltage range, we
2928
* clip the value instead of yet another correction. The IDF implementation
3029
* for ESP32-S2 is doing it, so we copy that approach in Zephyr driver
3130
*/
3231
#define ADC_CLIP_MVOLT_11DB 2550
33-
34-
#elif CONFIG_SOC_SERIES_ESP32S2
35-
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP
36-
#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH
37-
#define ADC_RESOLUTION_MAX SOC_ADC_MAX_BITWIDTH
38-
39-
#elif CONFIG_SOC_SERIES_ESP32C3
32+
#else
4033
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP
41-
#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH
42-
#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH
43-
44-
#elif CONFIG_SOC_SERIES_ESP32S3
45-
#define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP_FIT
46-
#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH
47-
#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH
48-
4934
#endif
5035

5136
/* Convert resolution in bits to esp32 enum values */
@@ -64,9 +49,9 @@ struct adc_esp32_conf {
6449
};
6550

6651
struct adc_esp32_data {
67-
adc_atten_t attenuation[ADC_CHANNEL_MAX];
68-
uint8_t resolution[ADC_CHANNEL_MAX];
69-
esp_adc_cal_characteristics_t chars[ADC_CHANNEL_MAX];
52+
adc_atten_t attenuation[SOC_ADC_MAX_CHANNEL_NUM];
53+
uint8_t resolution[SOC_ADC_MAX_CHANNEL_NUM];
54+
esp_adc_cal_characteristics_t chars[SOC_ADC_MAX_CHANNEL_NUM];
7055
uint16_t meas_ref_internal;
7156
uint16_t *buffer;
7257
uint16_t *buffer_repeat;
@@ -334,7 +319,7 @@ static const struct adc_driver_api api_esp32_driver_api = {
334319
#define ESP32_ADC_INIT(inst) \
335320
\
336321
static const struct adc_esp32_conf adc_esp32_conf_##inst = { \
337-
.unit = DT_PROP(DT_DRV_INST(inst), unit), \
322+
.unit = DT_PROP(DT_DRV_INST(inst), unit) - 1, \
338323
.channel_count = DT_PROP(DT_DRV_INST(inst), channel_count), \
339324
}; \
340325
\

‎drivers/clock_control/clock_control_esp32.c‎

Lines changed: 36 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -14,38 +14,40 @@
1414
#undef CPU_RESET_REASON
1515
#define CPU_RESET_REASON SW_CPU_RESET
1616
#include <zephyr/dt-bindings/clock/esp32_clock.h>
17-
#include "esp32/rom/rtc.h"
18-
#include "soc/dport_reg.h"
17+
#include <esp32/rom/rtc.h>
18+
#include <soc/dport_reg.h>
1919
#elif defined(CONFIG_SOC_SERIES_ESP32S2)
2020
#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
2121
#include <zephyr/dt-bindings/clock/esp32s2_clock.h>
22-
#include "esp32s2/rom/rtc.h"
23-
#include "soc/dport_reg.h"
22+
#include <esp32s2/rom/rtc.h>
23+
#include <soc/dport_reg.h>
2424
#elif defined(CONFIG_SOC_SERIES_ESP32S3)
2525
#define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
2626
#include <zephyr/dt-bindings/clock/esp32s3_clock.h>
27-
#include "esp32s3/rom/rtc.h"
28-
#include "soc/dport_reg.h"
29-
#include "esp32s3/clk.h"
27+
#include <esp32s3/rom/rtc.h>
28+
#include <soc/dport_reg.h>
3029
#elif CONFIG_SOC_SERIES_ESP32C3
3130
#define DT_CPU_COMPAT espressif_riscv
3231
#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
33-
#include "esp32c3/rom/rtc.h"
32+
#include <esp32c3/rom/rtc.h>
3433
#include <soc/soc_caps.h>
3534
#include <soc/soc.h>
3635
#include <soc/rtc.h>
3736
#endif /* CONFIG_SOC_SERIES_ESP32xx */
3837

39-
#include "esp_rom_sys.h"
38+
#include <esp_rom_sys.h>
39+
#include <esp_rom_uart.h>
4040
#include <soc/rtc.h>
4141
#include <soc/i2s_reg.h>
4242
#include <soc/apb_ctrl_reg.h>
4343
#include <soc/timer_group_reg.h>
4444
#include <hal/clk_gate_ll.h>
4545
#include <soc.h>
4646
#include <zephyr/drivers/clock_control.h>
47-
#include <driver/periph_ctrl.h>
48-
#include <hal/cpu_hal.h>
47+
#include <esp_private/periph_ctrl.h>
48+
#include <esp_private/esp_clk.h>
49+
#include <esp_cpu.h>
50+
#include <esp_rom_caps.h>
4951

5052
struct esp32_clock_config {
5153
int clk_src_sel;
@@ -54,21 +56,6 @@ struct esp32_clock_config {
5456
int xtal_div;
5557
};
5658

57-
static uint8_t const xtal_freq[] = {
58-
#if defined(CONFIG_SOC_SERIES_ESP32) || \
59-
defined(CONFIG_SOC_SERIES_ESP32S3)
60-
[ESP32_CLK_XTAL_24M] = 24,
61-
[ESP32_CLK_XTAL_26M] = 26,
62-
[ESP32_CLK_XTAL_40M] = 40,
63-
[ESP32_CLK_XTAL_AUTO] = 0
64-
#elif defined(CONFIG_SOC_SERIES_ESP32S2)
65-
[ESP32_CLK_XTAL_40M] = 40,
66-
#elif defined(CONFIG_SOC_SERIES_ESP32C3)
67-
[ESP32_CLK_XTAL_32M] = 32,
68-
[ESP32_CLK_XTAL_40M] = 40,
69-
#endif
70-
};
71-
7259
static int clock_control_esp32_on(const struct device *dev,
7360
clock_control_subsys_t sys)
7461
{
@@ -377,7 +364,7 @@ static void esp32_clock_perip_init(void)
377364

378365
wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
379366
SYSTEM_WIFI_CLK_BT_EN_M |
380-
SYSTEM_WIFI_CLK_UNUSED_BIT5 |
367+
SYSTEM_WIFI_CLK_I2C_CLK_EN |
381368
SYSTEM_WIFI_CLK_UNUSED_BIT12 |
382369
SYSTEM_WIFI_CLK_SDIO_HOST_EN;
383370
}
@@ -424,8 +411,14 @@ static void esp32_clock_perip_init(void)
424411
/* Enable RNG clock. */
425412
periph_module_enable(PERIPH_RNG_MODULE);
426413

427-
esp_rom_uart_tx_wait_idle(0);
428-
esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200);
414+
/* Enable TimerGroup 0 clock to ensure its reference counter will never
415+
* be decremented to 0 during normal operation and preventing it from
416+
* being disabled.
417+
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
418+
* registers (Flashboot protection included) will be reenabled, and some
419+
* seconds later, will trigger an unintended reset.
420+
*/
421+
periph_module_enable(PERIPH_TIMG0_MODULE);
429422
}
430423
#endif /* CONFIG_SOC_SERIES_ESP32S3 */
431424

@@ -472,7 +465,7 @@ static void esp32_clock_perip_init(void)
472465

473466
wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
474467
SYSTEM_WIFI_CLK_BT_EN_M |
475-
SYSTEM_WIFI_CLK_UNUSED_BIT5 |
468+
SYSTEM_WIFI_CLK_I2C_CLK_EN |
476469
SYSTEM_WIFI_CLK_UNUSED_BIT12;
477470
}
478471

@@ -529,10 +522,10 @@ static int clock_control_esp32_init(const struct device *dev)
529522
if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
530523
rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
531524

532-
clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel];
525+
clk_cfg.xtal_freq = cfg->xtal_freq_sel;
533526
clk_cfg.cpu_freq_mhz = cfg->cpu_freq;
534-
clk_cfg.slow_freq = rtc_clk_slow_freq_get();
535-
clk_cfg.fast_freq = rtc_clk_fast_freq_get();
527+
clk_cfg.slow_clk_src = rtc_clk_slow_freq_get();
528+
clk_cfg.fast_clk_src = rtc_clk_fast_freq_get();
536529
rtc_clk_init(clk_cfg);
537530
}
538531

@@ -563,10 +556,19 @@ static int clock_control_esp32_init(const struct device *dev)
563556
rtc_clk_cpu_freq_set_config(&new_config);
564557

565558
/* Re-calculate the ccount to make time calculation correct */
566-
cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz);
559+
esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * new_freq_mhz / old_freq_mhz);
567560

568561
esp32_clock_perip_init();
569562

563+
uint32_t clock_hz = esp_clk_apb_freq();
564+
#if ESP_ROM_UART_CLK_IS_XTAL
565+
clock_hz = esp_clk_xtal_freq();
566+
#endif
567+
esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM);
568+
569+
#if !defined(ESP_CONSOLE_UART_NONE)
570+
esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, clock_hz, ESP_CONSOLE_UART_BAUDRATE);
571+
#endif
570572
return 0;
571573
}
572574

‎drivers/counter/counter_esp32_tmr.c‎

Lines changed: 29 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,11 @@
99
/* Include esp-idf headers first to avoid redefining BIT() macro */
1010
#include <soc/rtc_cntl_reg.h>
1111
#include <soc/timer_group_reg.h>
12-
#include <driver/periph_ctrl.h>
12+
#include <periph_ctrl.h>
13+
#include <driver/timer_types_legacy.h>
1314
#include <soc/periph_defs.h>
14-
#include <hal/timer_types.h>
1515
#include <hal/timer_hal.h>
16+
#include <hal/timer_ll.h>
1617
#include <string.h>
1718
#include <zephyr/drivers/counter.h>
1819
#include <zephyr/spinlock.h>
@@ -80,22 +81,18 @@ static int counter_esp32_init(const struct device *dev)
8081

8182
timer_hal_init(&data->hal_ctx, cfg->group, cfg->index);
8283
data->alarm_cfg.callback = NULL;
83-
timer_hal_intr_disable(&data->hal_ctx);
84-
timer_hal_clear_intr_status(&data->hal_ctx);
85-
timer_hal_set_auto_reload(&data->hal_ctx, cfg->config.auto_reload);
86-
timer_hal_set_divider(&data->hal_ctx, cfg->config.divider);
87-
timer_hal_set_counter_increase(&data->hal_ctx, cfg->config.counter_dir);
88-
timer_hal_set_alarm_enable(&data->hal_ctx, cfg->config.alarm_en);
89-
if (cfg->config.intr_type == TIMER_INTR_LEVEL) {
90-
timer_hal_set_level_int_enable(&data->hal_ctx, true);
91-
}
92-
timer_hal_set_counter_value(&data->hal_ctx, 0);
93-
timer_hal_set_counter_enable(&data->hal_ctx, cfg->config.counter_en);
94-
esp_intr_alloc(cfg->irq_source,
95-
0,
96-
(ISR_HANDLER)counter_esp32_isr,
97-
(void *)dev,
98-
NULL);
84+
timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),
85+
false);
86+
timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));
87+
timer_ll_enable_auto_reload(data->hal_ctx.dev, data->hal_ctx.timer_id,
88+
cfg->config.auto_reload);
89+
timer_ll_set_clock_prescale(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.divider);
90+
timer_ll_set_count_direction(data->hal_ctx.dev, data->hal_ctx.timer_id,
91+
cfg->config.counter_dir);
92+
timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.alarm_en);
93+
timer_ll_set_reload_value(data->hal_ctx.dev, data->hal_ctx.timer_id, 0);
94+
timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, cfg->config.counter_en);
95+
esp_intr_alloc(cfg->irq_source, 0, (ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);
9996
k_spin_unlock(&lock, key);
10097

10198
return 0;
@@ -106,7 +103,7 @@ static int counter_esp32_start(const struct device *dev)
106103
struct counter_esp32_data *data = dev->data;
107104
k_spinlock_key_t key = k_spin_lock(&lock);
108105

109-
timer_hal_set_counter_enable(&data->hal_ctx, TIMER_START);
106+
timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_START);
110107
k_spin_unlock(&lock, key);
111108

112109
return 0;
@@ -117,7 +114,7 @@ static int counter_esp32_stop(const struct device *dev)
117114
struct counter_esp32_data *data = dev->data;
118115
k_spinlock_key_t key = k_spin_lock(&lock);
119116

120-
timer_hal_set_counter_enable(&data->hal_ctx, TIMER_PAUSE);
117+
timer_ll_enable_counter(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_PAUSE);
121118
k_spin_unlock(&lock, key);
122119

123120
return 0;
@@ -128,7 +125,7 @@ static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks)
128125
struct counter_esp32_data *data = dev->data;
129126
k_spinlock_key_t key = k_spin_lock(&lock);
130127

131-
timer_hal_get_counter_value(&data->hal_ctx, (uint64_t *)ticks);
128+
*ticks = timer_ll_get_counter_value(data->hal_ctx.dev, data->hal_ctx.timer_id);
132129
k_spin_unlock(&lock, key);
133130

134131
return 0;
@@ -146,13 +143,15 @@ static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id,
146143
k_spinlock_key_t key = k_spin_lock(&lock);
147144

148145
if ((alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) == 0) {
149-
timer_hal_set_alarm_value(&data->hal_ctx, (now + alarm_cfg->ticks));
146+
timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,
147+
(now + alarm_cfg->ticks));
150148
} else {
151-
timer_hal_set_alarm_value(&data->hal_ctx, alarm_cfg->ticks);
149+
timer_ll_set_alarm_value(data->hal_ctx.dev, data->hal_ctx.timer_id,
150+
alarm_cfg->ticks);
152151
}
153152

154-
timer_hal_intr_enable(&data->hal_ctx);
155-
timer_hal_set_alarm_enable(&data->hal_ctx, TIMER_ALARM_EN);
153+
timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id), true);
154+
timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_EN);
156155
data->alarm_cfg.callback = alarm_cfg->callback;
157156
data->alarm_cfg.user_data = alarm_cfg->user_data;
158157
k_spin_unlock(&lock, key);
@@ -167,8 +166,9 @@ static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id)
167166

168167
k_spinlock_key_t key = k_spin_lock(&lock);
169168

170-
timer_hal_intr_disable(&data->hal_ctx);
171-
timer_hal_set_alarm_enable(&data->hal_ctx, TIMER_ALARM_DIS);
169+
timer_ll_enable_intr(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id),
170+
false);
171+
timer_ll_enable_alarm(data->hal_ctx.dev, data->hal_ctx.timer_id, TIMER_ALARM_DIS);
172172
k_spin_unlock(&lock, key);
173173

174174
return 0;
@@ -190,9 +190,7 @@ static uint32_t counter_esp32_get_pending_int(const struct device *dev)
190190
{
191191
struct counter_esp32_data *data = dev->data;
192192

193-
timer_hal_get_intr_status_reg(&data->hal_ctx);
194-
195-
return 0;
193+
return timer_ll_get_intr_status(data->hal_ctx.dev);
196194
}
197195

198196
static uint32_t counter_esp32_get_top_value(const struct device *dev)
@@ -226,7 +224,7 @@ static void counter_esp32_isr(void *arg)
226224
data->alarm_cfg.callback(dev, 0, now, data->alarm_cfg.user_data);
227225
}
228226

229-
timer_hal_clear_intr_status(&data->hal_ctx);
227+
timer_ll_clear_intr_status(data->hal_ctx.dev, TIMER_LL_EVENT_ALARM(data->hal_ctx.timer_id));
230228
}
231229

232230
#define ESP32_COUNTER_GET_CLK_DIV(idx) \

‎drivers/dac/dac_esp32.c‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,7 @@
1313
#include <hal/rtc_io_types.h>
1414
#include <hal/rtc_io_hal.h>
1515
#include <hal/rtc_io_ll.h>
16-
#include <hal/dac_hal.h>
17-
#include <hal/dac_types.h>
18-
#include "driver/dac_common.h"
16+
#include "driver/dac.h"
1917

2018
#include <zephyr/logging/log.h>
2119
LOG_MODULE_REGISTER(esp32_dac, CONFIG_DAC_LOG_LEVEL);
@@ -41,7 +39,7 @@ static int dac_esp32_channel_setup(const struct device *dev,
4139
{
4240
ARG_UNUSED(dev);
4341

44-
if (channel_cfg->channel_id > DAC_CHANNEL_MAX) {
42+
if (channel_cfg->channel_id > SOC_DAC_CHAN_NUM) {
4543
LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
4644
return -EINVAL;
4745
}
@@ -66,7 +64,7 @@ static int dac_esp32_init(const struct device *dev)
6664
}
6765

6866
if (clock_control_on(cfg->clock_dev,
69-
(clock_control_subsys_t) cfg->clock_subsys) != 0) {
67+
(clock_control_subsys_t) &cfg->clock_subsys) != 0) {
7068
LOG_ERR("DAC clock setup failed (%d)", -EIO);
7169
return -EIO;
7270
}

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