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jimmyzhenashif
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driver: interrupt_controller: nuclei_eclic: fixed interrupt level
CLIC should be the first level interrupt controller because it replaces the basic RISC-V local interrupt. The interrupt level in CLIC controls preemption between IRQs, rather than specifying the number of nested interrupt controllers. Removed CONFIG_MULTI_LEVEL_INTERRUPTS and the incorrect interrupt level. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
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+2
-18
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3 files changed

+2
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drivers/interrupt_controller/Kconfig.clic

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@ config NUCLEI_ECLIC
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bool "Enhanced Core Local Interrupt Controller (ECLIC)"
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default y
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depends on DT_HAS_NUCLEI_ECLIC_ENABLED
8-
select MULTI_LEVEL_INTERRUPTS
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select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING if !RISCV_VECTORED_MODE
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help
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Interrupt controller for Nuclei SoC core.

drivers/interrupt_controller/intc_nuclei_eclic.c

Lines changed: 2 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@
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#include <zephyr/arch/cpu.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/device.h>
15-
#include <zephyr/irq_multilevel.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
@@ -96,14 +95,6 @@ struct CLICCTRL {
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#define ECLIC_CTRL ((volatile struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3)))
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#define ECLIC_CTRL_SIZE (DT_REG_SIZE_BY_IDX(DT_NODELABEL(eclic), 3))
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99-
#if CONFIG_3RD_LEVEL_INTERRUPTS
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#define INTERRUPT_LEVEL 2
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#elif CONFIG_2ND_LEVEL_INTERRUPTS
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#define INTERRUPT_LEVEL 1
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#else
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#define INTERRUPT_LEVEL 0
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#endif
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static uint8_t nlbits;
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static uint8_t intctlbits;
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static uint8_t max_prio;
@@ -150,7 +141,7 @@ int riscv_clic_irq_is_enabled(uint32_t irq)
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void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
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{
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const uint8_t prio = leftalign8(MIN(pri, max_prio), intctlbits);
153-
const uint8_t level = leftalign8(MIN((irq_get_level(irq) - 1), max_level), nlbits);
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const uint8_t level = leftalign8(max_level, nlbits);
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const uint8_t intctrl = (prio | level) | (~intctrl_mask);
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ECLIC_CTRL[irq].INTCTRL = intctrl;
@@ -180,12 +171,9 @@ void riscv_clic_irq_set_pending(uint32_t irq)
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static int nuclei_eclic_init(const struct device *dev)
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{
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/* check hardware support required interrupt levels */
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__ASSERT_NO_MSG(ECLIC_INFO.b.intctlbits >= INTERRUPT_LEVEL);
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ECLIC_MTH.w = 0;
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ECLIC_CFG.w = 0;
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ECLIC_CFG.b.nlbits = INTERRUPT_LEVEL;
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ECLIC_CFG.b.nlbits = 0;
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for (int i = 0; i < ECLIC_CTRL_SIZE; i++) {
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ECLIC_CTRL[i] = (struct CLICCTRL) { 0 };
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}

soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,6 @@ config NUM_IRQS
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default 87 if NUCLEI_ECLIC
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default 16 if !NUCLEI_ECLIC
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config 2ND_LEVEL_INTERRUPTS
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default y
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config ARCH_IRQ_VECTOR_TABLE_ALIGN
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default 512 if NUCLEI_ECLIC
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