soc: microchip: sam: sama7g5: update mmu for udphs

Update mmu region for udphsa and udphsb
Add usb phy clock configuration

Signed-off-by: CHEN Xing <xing.chen@microchip.com>

Author: MCHP-MPU-Solutions-SHA

soc/microchip/sam/sama7g5/soc.c

@@ -65,6 +65,9 @@ static const struct arm_mmu_region mmu_regions[] = {
 		   (MMU_REGION_FLAT_ENTRY("pwm", PWM_BASE_ADDRESS, 0x500,
 					  MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),))
 
+	MMU_REGION_FLAT_ENTRY("rstc", RSTC_BASE_ADDRESS, 0x10,
+			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+
 	MMU_REGION_FLAT_ENTRY("sckc", SCKC_BASE_ADDRESS, 0x4,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
 
@@ -74,10 +77,25 @@ static const struct arm_mmu_region mmu_regions[] = {
 	MMU_REGION_FLAT_ENTRY("sdmmc1", SDMMC1_BASE_ADDRESS, 0x4000,
 			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
 
+	MMU_REGION_FLAT_ENTRY("sfr", SFR_BASE_ADDRESS, 0x4000,
+			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+
 	IF_ENABLED(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(trng)),
 		   (MMU_REGION_FLAT_ENTRY("trng", TRNG_BASE_ADDRESS, 0x100,
 					  MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),))
 
+	IF_ENABLED(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(udphsa)),
+		(MMU_REGION_FLAT_ENTRY("udphsa", UDPHSA_BASE_ADDRESS, 0x400,
+				       MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+		 MMU_REGION_FLAT_ENTRY("udphsa_ram", UDPHS_RAMA_ADDR, 0x100000,
+				       MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),))
+
+	IF_ENABLED(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(udphsb)),
+		(MMU_REGION_FLAT_ENTRY("udphsb", UDPHSB_BASE_ADDRESS, 0x400,
+				       MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+		 MMU_REGION_FLAT_ENTRY("udphsb_ram", UDPHS_RAMB_ADDR, 0x100000,
+				       MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),))
+
 	FOR_EACH_IDX(MMU_REGION_XDMAC_DEFN, (), 0, 1, 2)
 };
 
@@ -149,4 +167,23 @@ void soc_early_init_hook(void)
 				    PMC_PCR_GCLKDIV(4) | PMC_PCR_MCKID(1) |
 				    PMC_PCR_GCLKCSS_ETHPLL | PMC_PCR_PID(ID_GMAC1);
 	}
+
+	/* Enable USB PHYs clock */
+	PMC_REGS->PMC_XTALF = PMC_XTALF_XTALF_F24M;
+	RSTC_REGS->RSTC_GRSTR |= RSTC_GRSTR_USB_RST1_Msk |
+				 RSTC_GRSTR_USB_RST2_Msk |
+				 RSTC_GRSTR_USB_RST3_Msk;
+	SFR_REGS->SFR_UTMI0R[0] |= SFR_UTMI0R_COMMONONN_Msk;
+	SFR_REGS->SFR_UTMI0R[1] |= SFR_UTMI0R_COMMONONN_Msk;
+	SFR_REGS->SFR_UTMI0R[2] |= SFR_UTMI0R_COMMONONN_Msk;
+	if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(udphsa))) {
+		SFR_REGS->SFR_UTMI0R[0] |= SFR_UTMI0R_VBUS_Msk;
+		SFR_REGS->SFR_UTMI0R[0] &= ~SFR_UTMI0R_COMMONONN_Msk;
+		RSTC_REGS->RSTC_GRSTR &= ~RSTC_GRSTR_USB_RST1_Msk;
+	}
+	if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(udphsb))) {
+		SFR_REGS->SFR_UTMI0R[1] |= SFR_UTMI0R_VBUS_Msk;
+		SFR_REGS->SFR_UTMI0R[1] &= ~SFR_UTMI0R_COMMONONN_Msk;
+		RSTC_REGS->RSTC_GRSTR &= ~RSTC_GRSTR_USB_RST2_Msk;
+	}
 }