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boards: lpcxpresso55s36: Support opamp on lpcxpresso55s36
Add opamp node for lpc55S36. Support opamp for lpcxpresso55s36. Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1 parent 01db99c commit b9a7fe7

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4 files changed

+100
-64
lines changed

4 files changed

+100
-64
lines changed

‎boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
* NOTE: File generated by gen_board_pinctrl.py
33
* from LPC55S36.mex
44
*
5-
* Copyright 2022-2023 NXP
5+
* Copyright 2022-2023, 2025 NXP
66
* SPDX-License-Identifier: Apache-2.0
77
*/
88

@@ -47,6 +47,15 @@
4747
};
4848
};
4949

50+
pinmux_opamp0: pinmux_opamp0 {
51+
group0 {
52+
pinmux = <OPAMP0_DP0_PIO0_8>,
53+
<OPAMP0_OUT_PIO1_9>;
54+
slew-rate = "standard";
55+
nxp,analog-mode;
56+
};
57+
};
58+
5059
/* Configures pin routing and optionally pin electrical features. */
5160
pinmux_sctimer_default: pinmux_sctimer_default {
5261
group0 {

‎boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -198,3 +198,9 @@ zephyr_udc0: &usbfs {
198198
pinctrl-0 = <&pinmux_dac0>;
199199
pinctrl-names = "default";
200200
};
201+
202+
&opamp0 {
203+
status = "okay";
204+
pinctrl-0 = <&pinmux_opamp0>;
205+
pinctrl-names = "default";
206+
};

‎dts/arm/nxp/nxp_lpc55S3x_common.dtsi

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2022, 2024 NXP
2+
* Copyright 2022, 2024-2025 NXP
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -303,6 +303,27 @@
303303
clocks = <&syscon MCUX_LPADC1_CLK>;
304304
};
305305

306+
opamp0: opamp@400b4000 {
307+
compatible = "nxp,opamp";
308+
reg = <0x400b4000 0x1000>;
309+
status = "disabled";
310+
mode = "low_noise";
311+
};
312+
313+
opamp1: opamp@400b8000 {
314+
compatible = "nxp,opamp";
315+
reg = <0x400b8000 0x1000>;
316+
status = "disabled";
317+
mode = "low_noise";
318+
};
319+
320+
opamp2: opamp@400bb000 {
321+
compatible = "nxp,opamp";
322+
reg = <0x400bb000 0x1000>;
323+
status = "disabled";
324+
mode = "low_noise";
325+
};
326+
306327
dac0: dac@b2000 {
307328
compatible = "nxp,lpdac";
308329
reg = < 0xb2000 0x1000>;

‎soc/nxp/lpc/lpc55xxx/soc.c

Lines changed: 62 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
/* Copyright 2017, 2019-2024 NXP
1+
/* Copyright 2017, 2019-2025 NXP
22
*
33
* SPDX-License-Identifier: Apache-2.0
44
*/
@@ -30,8 +30,8 @@
3030
#include "usb_phy.h"
3131
#include "usb.h"
3232
#endif
33-
#if defined(CONFIG_SOC_LPC55S36) && (defined(CONFIG_ADC_MCUX_LPADC) \
34-
|| defined(CONFIG_DAC_MCUX_LPDAC))
33+
#if defined(CONFIG_SOC_LPC55S36) && \
34+
(defined(CONFIG_ADC_MCUX_LPADC) || defined(CONFIG_DAC_MCUX_LPDAC))
3535
#include <fsl_vref.h>
3636
#endif
3737

@@ -41,35 +41,31 @@ extern uint32_t SystemCoreClock;
4141
/*Should be in the range of 12MHz to 32MHz */
4242
static uint32_t ExternalClockFrequency;
4343

44-
45-
#define CTIMER_CLOCK_SOURCE(node_id) \
44+
#define CTIMER_CLOCK_SOURCE(node_id) \
4645
TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source))
4746
#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val)
48-
#define TO_CLOCK_ATTACH_ID(inst, val) MUX_A(CM_CTIMERCLKSEL##inst, val)
49-
#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id));
47+
#define TO_CLOCK_ATTACH_ID(inst, val) MUX_A(CM_CTIMERCLKSEL##inst, val)
48+
#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id));
5049

5150
#ifdef CONFIG_INIT_PLL0
5251
const pll_setup_t pll0Setup = {
53-
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(2U) |
54-
SYSCON_PLL0CTRL_SELP(31U),
52+
.pllctrl =
53+
SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(2U) | SYSCON_PLL0CTRL_SELP(31U),
5554
.pllndec = SYSCON_PLL0NDEC_NDIV(125U),
5655
.pllpdec = SYSCON_PLL0PDEC_PDIV(8U),
5756
.pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(3072U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
5857
.pllRate = 24576000U,
59-
.flags = PLL_SETUPFLAG_WAITLOCK
60-
};
58+
.flags = PLL_SETUPFLAG_WAITLOCK};
6159
#endif
6260

6361
#ifdef CONFIG_INIT_PLL1
64-
const pll_setup_t pll1Setup = {
65-
.pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) |
66-
SYSCON_PLL1CTRL_SELP(31U),
67-
.pllndec = SYSCON_PLL1NDEC_NDIV(8U),
68-
.pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
69-
.pllmdec = SYSCON_PLL1MDEC_MDIV(144U),
70-
.pllRate = 144000000U,
71-
.flags = PLL_SETUPFLAG_WAITLOCK
72-
};
62+
const pll_setup_t pll1Setup = {.pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) |
63+
SYSCON_PLL1CTRL_SELP(31U),
64+
.pllndec = SYSCON_PLL1NDEC_NDIV(8U),
65+
.pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
66+
.pllmdec = SYSCON_PLL1MDEC_MDIV(144U),
67+
.pllRate = 144000000U,
68+
.flags = PLL_SETUPFLAG_WAITLOCK};
7369
#endif
7470

7571
/**
@@ -87,8 +83,8 @@ __weak void clock_init(void)
8783
POWER_PowerInit();
8884
#endif
8985

90-
#if defined(CONFIG_SOC_LPC55S06) || defined(CONFIG_SOC_LPC55S16) || \
91-
defined(CONFIG_SOC_LPC55S26) || defined(CONFIG_SOC_LPC55S28) || \
86+
#if defined(CONFIG_SOC_LPC55S06) || defined(CONFIG_SOC_LPC55S16) || \
87+
defined(CONFIG_SOC_LPC55S26) || defined(CONFIG_SOC_LPC55S28) || \
9288
defined(CONFIG_SOC_LPC55S36) || defined(CONFIG_SOC_LPC55S69_CPU0)
9389
/* Set up the clock sources */
9490
/* Configure FRO192M */
@@ -110,7 +106,6 @@ __weak void clock_init(void)
110106
SystemCoreClock = 144000000U;
111107
#endif
112108

113-
114109
/* These functions must be called before increasing to a higher frequency
115110
* Additionally, CONFIG_TRUSTED_EXECUTION_NONSECURE is being used
116111
* since the non-secure SOCs should not have access to the flash
@@ -123,7 +118,6 @@ __weak void clock_init(void)
123118
CLOCK_SetFLASHAccessCyclesForFreq(SystemCoreClock);
124119
#endif /* !CONFIG_TRUSTED_EXECUTION_NONSECURE */
125120

126-
127121
#if defined(CONFIG_INIT_PLL0) || defined(CONFIG_INIT_PLL1)
128122
/* Configure XTAL32M */
129123
ExternalClockFrequency = 16000000U;
@@ -152,7 +146,6 @@ __weak void clock_init(void)
152146

153147
#endif /* CONFIG_SOC_LPC55S06 || !CONFIG_INIT_PLL1 */
154148

155-
156149
#ifdef CONFIG_INIT_PLL0
157150
/* Switch PLL0 clock source selector to XTAL32M */
158151
CLOCK_AttachClk(kEXT_CLK_to_PLL0);
@@ -169,27 +162,26 @@ __weak void clock_init(void)
169162
#endif /* CONFIG_SOC_LPC55S36 */
170163
#endif /* CONFIG_INIT_PLL0 */
171164

172-
173165
/* Set up dividers */
174166
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
175167

176168
/* Enables the clock for the I/O controller.: Enable Clock. */
177169
CLOCK_EnableClock(kCLOCK_Iocon);
178170

179-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_i2c, okay) || \
180-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_spi, okay) || \
171+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_i2c, okay) || \
172+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_spi, okay) || \
181173
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay)
182174
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM0);
183175
#endif
184176

185-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2c, okay) || \
186-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_spi, okay) || \
177+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2c, okay) || \
178+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_spi, okay) || \
187179
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_usart, okay)
188180
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM1);
189181
#endif
190182

191-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay) || \
192-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_spi, okay) || \
183+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay) || \
184+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_spi, okay) || \
193185
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_usart, okay)
194186
#if defined(CONFIG_SOC_LPC55S36)
195187
CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 0U, true);
@@ -198,14 +190,14 @@ __weak void clock_init(void)
198190
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM2);
199191
#endif
200192

201-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2c, okay) || \
202-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_spi, okay) || \
193+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2c, okay) || \
194+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_spi, okay) || \
203195
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_usart, okay)
204196
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3);
205197
#endif
206198

207-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay) || \
208-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_spi, okay) || \
199+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay) || \
200+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_spi, okay) || \
209201
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_usart, okay)
210202
#if defined(CONFIG_SOC_LPC55S36)
211203
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 0U, true);
@@ -214,20 +206,20 @@ __weak void clock_init(void)
214206
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM4);
215207
#endif
216208

217-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_i2c, okay) || \
218-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay) || \
209+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_i2c, okay) || \
210+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay) || \
219211
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_usart, okay)
220212
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM5);
221213
#endif
222214

223-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2c, okay) || \
224-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_spi, okay) || \
215+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2c, okay) || \
216+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_spi, okay) || \
225217
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_usart, okay)
226218
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM6);
227219
#endif
228220

229-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_i2c, okay) || \
230-
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_spi, okay) || \
221+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_i2c, okay) || \
222+
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_spi, okay) || \
231223
DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_usart, okay)
232224
CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM7);
233225
#endif
@@ -347,9 +339,9 @@ __weak void clock_init(void)
347339

348340
#endif
349341

350-
DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
342+
DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
351343

352-
DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
344+
DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
353345

354346
#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay))
355347
#if defined(CONFIG_SOC_LPC55S36)
@@ -374,8 +366,7 @@ DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
374366
CLOCK_AttachClk(kMCAN_DIV_to_MCAN);
375367
#endif
376368

377-
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(sdif), nxp_lpc_sdif, okay) && \
378-
CONFIG_MCUX_SDIF
369+
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(sdif), nxp_lpc_sdif, okay) && CONFIG_MCUX_SDIF
379370
/* attach main clock to SDIF */
380371
CLOCK_AttachClk(kMAIN_CLK_to_SDIO_CLK);
381372
CLOCK_SetClkDiv(kCLOCK_DivSdioClk, 3, true);
@@ -385,21 +376,18 @@ DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
385376

386377
#if defined(CONFIG_SOC_LPC55S36) && defined(CONFIG_PWM)
387378
/* Set the Submodule Clocks for FlexPWM */
388-
SYSCON->PWM0SUBCTL |=
389-
(SYSCON_PWM0SUBCTL_CLK0_EN_MASK | SYSCON_PWM0SUBCTL_CLK1_EN_MASK |
390-
SYSCON_PWM0SUBCTL_CLK2_EN_MASK);
391-
SYSCON->PWM1SUBCTL |=
392-
(SYSCON_PWM1SUBCTL_CLK0_EN_MASK | SYSCON_PWM1SUBCTL_CLK1_EN_MASK |
393-
SYSCON_PWM1SUBCTL_CLK2_EN_MASK);
379+
SYSCON->PWM0SUBCTL |= (SYSCON_PWM0SUBCTL_CLK0_EN_MASK | SYSCON_PWM0SUBCTL_CLK1_EN_MASK |
380+
SYSCON_PWM0SUBCTL_CLK2_EN_MASK);
381+
SYSCON->PWM1SUBCTL |= (SYSCON_PWM1SUBCTL_CLK0_EN_MASK | SYSCON_PWM1SUBCTL_CLK1_EN_MASK |
382+
SYSCON_PWM1SUBCTL_CLK2_EN_MASK);
394383
#endif
395384

396385
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(adc0), nxp_lpc_lpadc, okay)
397386
#if defined(CONFIG_SOC_LPC55S36)
398387
CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 2U, true);
399388
CLOCK_AttachClk(kFRO_HF_to_ADC0);
400389
#else /* not LPC55s36 */
401-
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk,
402-
DT_PROP(DT_NODELABEL(adc0), clk_divider), true);
390+
CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, DT_PROP(DT_NODELABEL(adc0), clk_divider), true);
403391
CLOCK_AttachClk(MUX_A(CM_ADCASYNCCLKSEL, DT_PROP(DT_NODELABEL(adc0), clk_source)));
404392

405393
/* Power up the ADC */
@@ -422,6 +410,23 @@ DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
422410
#endif /* SOC platform */
423411
#endif /* DAC */
424412

413+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(opamp0))
414+
RESET_PeripheralReset(kOPAMP0_RST_SHIFT_RSTn);
415+
CLOCK_EnableClock(kCLOCK_Opamp0);
416+
POWER_DisablePD(kPDRUNCFG_PD_OPAMP0);
417+
#endif
418+
419+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(opamp1))
420+
RESET_PeripheralReset(kOPAMP1_RST_SHIFT_RSTn);
421+
CLOCK_EnableClock(kCLOCK_Opamp1);
422+
POWER_DisablePD(kPDRUNCFG_PD_OPAMP1);
423+
#endif
424+
425+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(opamp2))
426+
RESET_PeripheralReset(kOPAMP2_RST_SHIFT_RSTn);
427+
CLOCK_EnableClock(kCLOCK_Opamp2);
428+
POWER_DisablePD(kPDRUNCFG_PD_OPAMP2);
429+
#endif
425430
}
426431

427432
/**
@@ -455,7 +460,6 @@ void soc_reset_hook(void)
455460
{
456461
SystemInit();
457462

458-
459463
#ifndef CONFIG_LOG_BACKEND_SWO
460464
/*
461465
* SystemInit unconditionally enables the trace clock.
@@ -484,7 +488,6 @@ int _second_core_init(void)
484488
{
485489
int32_t temp;
486490

487-
488491
/* Setup the reset handler pointer (PC) and stack pointer value.
489492
* This is used once the second core runs its startup code.
490493
* The second core first boots from flash (address 0x00000000)
@@ -496,15 +499,12 @@ int _second_core_init(void)
496499
SYSCON->CPUCFG |= SYSCON_CPUCFG_CPU1ENABLE_MASK;
497500

498501
/* Boot source for Core 1 from flash */
499-
SYSCON->CPBOOT = SYSCON_CPBOOT_CPBOOT(DT_REG_ADDR(
500-
DT_CHOSEN(zephyr_code_cpu1_partition)));
502+
SYSCON->CPBOOT = SYSCON_CPBOOT_CPBOOT(DT_REG_ADDR(DT_CHOSEN(zephyr_code_cpu1_partition)));
501503

502504
temp = SYSCON->CPUCTRL;
503505
temp |= 0xc0c48000;
504-
SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK |
505-
SYSCON_CPUCTRL_CPU1CLKEN_MASK;
506-
SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) &
507-
(~SYSCON_CPUCTRL_CPU1RSTEN_MASK);
506+
SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK | SYSCON_CPUCTRL_CPU1CLKEN_MASK;
507+
SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) & (~SYSCON_CPUCTRL_CPU1RSTEN_MASK);
508508

509509
return 0;
510510
}

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