dts: arm: nxp: rt6xx: add SRAM code region

Add SRAM code region definition to RT6xx series SOC. The RT6xx shares
SRAM partitions between the code and data bus, but a default allocation
is chosen by the SOC level devicetree. The user can modify this
allocation by changing the base address and size of the sram_code and
sram0 regions in their board devicetree.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>

Author: danieldegrasse

dts/arm/nxp/nxp_rt6xx.dtsi

@@ -8,8 +8,9 @@
 
 / {
 	soc {
-		sram: sram@30018000 {
-			ranges = <0x20180000 0x30180000 0x300000>;
+		sram: sram@30000000 {
+			ranges = <0x0 0x10000000 0x500000
+				0x20000000 0x30000000 0x500000>;
 		};
 
 		peripheral: peripheral@50000000 {

dts/arm/nxp/nxp_rt6xx_common.dtsi

@@ -54,6 +54,20 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	/* RT6XX SRAM partitions are shared
+	 * between code and data. Boards can
+	 * override the reg properties of either sram0 or sram_code nodes to
+	 * change the balance of SRAM allocation.
+	 *
+	 * Note that the sram code region starts at an offset of 0x1B000,
+	 * as the boot ROM will not load code before 0x1C000. The first
+	 * 0x1000 of the image will contain the boot header.
+	 */
+	sram_code: memory@1b000 {
+		compatible = "mmio-sram";
+		reg = <0x1b000 DT_SIZE_K(1428)>;
+	};
+
 	sram0: memory@20180000 {
 		compatible = "mmio-sram";
 		reg = <0x20180000 DT_SIZE_K(3072)>;

dts/arm/nxp/nxp_rt6xx_ns.dtsi

@@ -8,8 +8,9 @@
 
 / {
 	soc {
-		sram: sram@20180000 {
-			ranges = <0x20180000 0x20180000 0x300000>;
+		sram: sram@20000000 {
+			ranges = <0x0 0x0 0x500000
+				0x20000000 0x20000000 0x500000>;
 		};
 
 		peripheral: peripheral@40000000 {