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abonislawskicarlescufi
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drivers: dai: add ALH dai driver
The ALH is an intermediary device, which acts as a hub and provides an abstracted support for numerous sound interfaces (e.g. SoundWire). Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
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‎drivers/dai/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory_ifdef(CONFIG_DAI_INTEL_SSP intel/ssp)
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add_subdirectory_ifdef(CONFIG_DAI_INTEL_ALH intel/alh)

‎drivers/dai/Kconfig‎

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@@ -26,5 +26,6 @@ source "subsys/logging/Kconfig.template.log_config"
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comment "Device Drivers"
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source "drivers/dai/intel/ssp/Kconfig.ssp"
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source "drivers/dai/intel/alh/Kconfig.alh"
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endif # DAI

‎drivers/dai/intel/alh/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources(alh.c)
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zephyr_library_compile_options(-std=gnu99)

‎drivers/dai/intel/alh/Kconfig.alh‎

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# SOF ALH configuration options
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# Copyright (c) 2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_INTEL_ALH_DAI := intel,alh-dai
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config DAI_INTEL_ALH
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bool "Intel ALH driver for Dai interface"
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default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ALH_DAI))
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select DMA
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help
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Select this to enable Intel ALH driver.
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The ALH is an intermediary device, which acts as a hub and provides an
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abstracted support for numerous sound interfaces (e.g. SoundWire).
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if DAI_INTEL_ALH
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config DAI_ALH_HAS_OWNERSHIP
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bool "Intel ALH driver has ownership"
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help
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Select this to enable programming HW ownership
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endif

‎drivers/dai/intel/alh/alh.c‎

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/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/logging/log.h>
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#define DT_DRV_COMPAT intel_alh_dai
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#define LOG_DOMAIN dai_intel_alh
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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#include "alh.h"
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/* Digital Audio interface formatting */
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static int dai_alh_set_config_tplg(struct dai_intel_alh *dp, const void *spec_config)
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{
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struct dai_intel_alh_pdata *alh = dai_get_drvdata(dp);
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const struct dai_intel_ipc3_alh_params *config = spec_config;
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if (config->channels && config->rate) {
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alh->params.channels = config->channels;
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alh->params.rate = config->rate;
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LOG_INF("%s channels %d rate %d", __func__, config->channels, config->rate);
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}
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alh->params.stream_id = config->stream_id;
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return 0;
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}
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static int dai_alh_set_config_blob(struct dai_intel_alh *dp, const void *spec_config)
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{
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struct dai_intel_alh_pdata *alh = dai_get_drvdata(dp);
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const struct dai_intel_ipc4_alh_configuration_blob *blob = spec_config;
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const struct ipc4_alh_multi_gtw_cfg *alh_cfg = &blob->alh_cfg;
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alh->params.channels = ALH_CHANNELS_DEFAULT;
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alh->params.rate = ALH_RATE_DEFAULT;
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/* the LSB 8bits are for stream id */
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alh->params.stream_id = alh_cfg->mapping[0].alh_id & 0xff;
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return 0;
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}
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static int dai_alh_trigger(const struct device *dev, enum dai_dir dir,
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enum dai_trigger_cmd cmd)
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{
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LOG_DBG("cmd %d", cmd);
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return 0;
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}
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static void alh_claim_ownership(void)
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{
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#if CONFIG_DAI_ALH_HAS_OWNERSHIP
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uint32_t ALHASCTL = DT_INST_PROP_BY_IDX(0, reg, 0);
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uint32_t ALHCSCTL = DT_INST_PROP_BY_IDX(0, reg, 1);
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sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0x3), ALHASCTL);
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sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0x3), ALHCSCTL);
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#endif
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}
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static void alh_release_ownership(void)
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{
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#if CONFIG_DAI_ALH_HAS_OWNERSHIP
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uint32_t ALHASCTL = DT_INST_PROP_BY_IDX(0, reg, 0);
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uint32_t ALHCSCTL = DT_INST_PROP_BY_IDX(0, reg, 1);
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sys_write32(sys_read32(ALHASCTL) | ALHASCTL_OSEL(0), ALHASCTL);
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sys_write32(sys_read32(ALHCSCTL) | ALHASCTL_OSEL(0), ALHCSCTL);
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#endif
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}
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static const struct dai_config *dai_alh_config_get(const struct device *dev, enum dai_dir dir)
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{
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struct dai_config *params = (struct dai_config *)dev->config;
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struct dai_intel_alh *dp = (struct dai_intel_alh *)dev->data;
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struct dai_intel_alh_pdata *alh = dai_get_drvdata(dp);
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params->rate = alh->params.rate;
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params->channels = alh->params.channels;
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params->word_size = ALH_WORD_SIZE_DEFAULT;
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return params;
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}
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static int dai_alh_config_set(const struct device *dev, const struct dai_config *cfg,
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const void *bespoke_cfg)
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{
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struct dai_intel_alh *dp = (struct dai_intel_alh *)dev->data;
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LOG_DBG("%s", __func__);
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if (cfg->type == DAI_INTEL_ALH) {
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return dai_alh_set_config_tplg(dp, bespoke_cfg);
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} else {
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return dai_alh_set_config_blob(dp, bespoke_cfg);
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}
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}
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static const struct dai_properties *dai_alh_get_properties(const struct device *dev,
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enum dai_dir dir, int stream_id)
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{
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struct dai_intel_alh *dp = (struct dai_intel_alh *)dev->data;
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struct dai_intel_alh_pdata *alh = dai_get_drvdata(dp);
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struct dai_properties *prop = &alh->props;
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uint32_t offset = dir == DAI_DIR_PLAYBACK ?
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ALH_TXDA_OFFSET : ALH_RXDA_OFFSET;
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prop->fifo_address = dai_base(dp) + offset + ALH_STREAM_OFFSET * stream_id;
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prop->dma_hs_id = alh_handshake_map[stream_id];
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prop->stream_id = alh->params.stream_id;
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LOG_DBG("dai_index %u", dp->index);
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LOG_DBG("fifo %u", prop->fifo_address);
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LOG_DBG("handshake %u", prop->dma_hs_id);
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return prop;
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}
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static int dai_alh_probe(const struct device *dev)
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{
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struct dai_intel_alh *dp = (struct dai_intel_alh *)dev->data;
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k_spinlock_key_t key;
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LOG_DBG("%s", __func__);
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key = k_spin_lock(&dp->lock);
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if (dp->sref == 0) {
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alh_claim_ownership();
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}
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dp->sref++;
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k_spin_unlock(&dp->lock, key);
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return 0;
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}
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static int dai_alh_remove(const struct device *dev)
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{
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struct dai_intel_alh *dp = (struct dai_intel_alh *)dev->data;
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k_spinlock_key_t key;
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LOG_DBG("%s", __func__);
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key = k_spin_lock(&dp->lock);
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if (--dp->sref == 0) {
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alh_release_ownership();
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}
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k_spin_unlock(&dp->lock, key);
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return 0;
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}
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static int alh_init(const struct device *dev)
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{
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return 0;
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}
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static const struct dai_driver_api dai_intel_alh_api_funcs = {
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.probe = dai_alh_probe,
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.remove = dai_alh_remove,
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.config_set = dai_alh_config_set,
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.config_get = dai_alh_config_get,
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.trigger = dai_alh_trigger,
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.get_properties = dai_alh_get_properties,
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};
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#define DAI_INTEL_ALH_DEVICE_INIT(n) \
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static struct dai_config dai_intel_alh_config_##n; \
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static struct dai_intel_alh dai_intel_alh_data_##n = { \
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.index = (n / DAI_NUM_ALH_BI_DIR_LINKS_GROUP) << 8 | \
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(n % DAI_NUM_ALH_BI_DIR_LINKS_GROUP), \
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.plat_data = { \
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.base = DT_INST_PROP_BY_IDX(n, reg, 0), \
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.fifo_depth[DAI_DIR_PLAYBACK] = ALH_GPDMA_BURST_LENGTH, \
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.fifo_depth[DAI_DIR_CAPTURE] = ALH_GPDMA_BURST_LENGTH, \
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}, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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alh_init, NULL, \
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&dai_intel_alh_data_##n, \
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&dai_intel_alh_config_##n, \
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POST_KERNEL, 32, \
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&dai_intel_alh_api_funcs);
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DT_INST_FOREACH_STATUS_OKAY(DAI_INTEL_ALH_DEVICE_INIT)

‎drivers/dai/intel/alh/alh.h‎

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/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INTEL_DAI_DRIVER_ALH_H__
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#define __INTEL_DAI_DRIVER_ALH_H__
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#include <stdint.h>
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#include <zephyr/drivers/dai.h>
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#include "alh_map.h"
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#define DAI_NUM_ALH_BI_DIR_LINKS_GROUP 4
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#define ALH_STREAM_OFFSET 0x4
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#define IPC4_ALH_MAX_NUMBER_OF_GTW 16
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#define IPC4_ALH_DAI_INDEX_OFFSET 7
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#define ALH_GPDMA_BURST_LENGTH 4
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#define ALH_SET_BITS(b_hi, b_lo, x) \
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(((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
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#define ALHASCTL_OSEL(x) ALH_SET_BITS(25, 24, x)
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#define dai_get_drvdata(dai) &dai->priv_data
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#define dai_base(dai) dai->plat_data.base
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#define DAI_DIR_PLAYBACK 0
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#define DAI_DIR_CAPTURE 1
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#define ALH_CHANNELS_DEFAULT 2
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#define ALH_RATE_DEFAULT 48000
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#define ALH_WORD_SIZE_DEFAULT 32
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#if CONFIG_INTEL_ADSP_CAVS
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#define ALH_TXDA_OFFSET 0x400
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#define ALH_RXDA_OFFSET 0x500
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#else
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#define ALH_TXDA_OFFSET 0
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#define ALH_RXDA_OFFSET 0x100
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#endif
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union dai_intel_ipc4_gateway_attributes {
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/**< Raw value */
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uint32_t dw;
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/**< Access to the fields */
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struct {
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/**< Gateway data requested in low power memory. */
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uint32_t lp_buffer_alloc : 1;
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/**< Gateway data requested in register file memory. */
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uint32_t alloc_from_reg_file : 1;
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/**< Reserved field */
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uint32_t _rsvd : 30;
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} bits; /**<< Bits */
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} __packed;
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/* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
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struct dai_intel_ipc3_alh_params {
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uint32_t reserved0;
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uint32_t stream_id;
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uint32_t rate;
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uint32_t channels;
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/* reserved for future use */
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uint32_t reserved[13];
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} __packed;
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struct ipc4_alh_multi_gtw_cfg {
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/* Number of single channels (valid items in mapping array). */
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uint32_t count;
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/* Single to multi aggregation mapping item. */
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struct {
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/* Vindex of a single ALH channel aggregated. */
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uint32_t alh_id;
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/* Channel mask */
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uint32_t channel_mask;
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} mapping[IPC4_ALH_MAX_NUMBER_OF_GTW]; /* < Mapping items */
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} __packed;
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struct dai_intel_ipc4_alh_configuration_blob {
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union dai_intel_ipc4_gateway_attributes gtw_attributes;
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struct ipc4_alh_multi_gtw_cfg alh_cfg;
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} __packed;
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struct dai_intel_alh_plat_data {
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uint32_t base;
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uint32_t fifo_depth[2];
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};
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struct dai_intel_alh_pdata {
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struct dai_config config;
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struct dai_properties props;
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struct dai_intel_ipc3_alh_params params;
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};
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struct dai_intel_alh {
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uint32_t index; /**< index */
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struct k_spinlock lock; /**< locking mechanism */
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int sref; /**< simple ref counter, guarded by lock */
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struct dai_intel_alh_plat_data plat_data;
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struct dai_intel_alh_pdata priv_data;
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};
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#endif

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