dts: arm: st: add SMBus devices

Add SMBus devices to all SoCs which have either
a st,stm32-i2c-v1 or st,stm32-i2c-v2.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>

Author: benediktibk

dts/arm/st/c0/stm32c0.dtsi

@@ -343,6 +343,14 @@
 		io-channels = <&adc1 10>;
 		status = "disabled";
 	};
+
+	smbus1: smbus1 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c1>;
+		status = "disabled";
+	};
 };
 
 &nvic {

dts/arm/st/f0/stm32f0.dtsi

@@ -364,6 +364,14 @@
 		io-channels = <&adc1 17>;
 		status = "disabled";
 	};
+
+	smbus1: smbus1 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c1>;
+		status = "disabled";
+	};
 };
 
 &nvic {

dts/arm/st/f0/stm32f030X8.dtsi

@@ -77,4 +77,12 @@
 			};
 		};
 	};
+
+	smbus2: smbus2 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c2>;
+		status = "disabled";
+	};
 };

dts/arm/st/f0/stm32f051.dtsi

@@ -77,4 +77,12 @@
 			#io-channel-cells = <1>;
 		};
 	};
+
+	smbus2: smbus2 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c2>;
+		status = "disabled";
+	};
 };

dts/arm/st/f0/stm32f070Xb.dtsi

@@ -87,4 +87,12 @@
 			status = "disabled";
 		};
 	};
+
+	smbus2: smbus2 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c2>;
+		status = "disabled";
+	};
 };

dts/arm/st/f1/stm32f1.dtsi

@@ -362,6 +362,22 @@
 		v25 = <1430>;
 		ntc;
 	};
+
+	smbus1: smbus1 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c1>;
+		status = "disabled";
+	};
+
+	smbus2: smbus2 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c2>;
+		status = "disabled";
+	};
 };
 
 &nvic {

dts/arm/st/f2/stm32f2.dtsi

@@ -713,6 +713,30 @@
 		compatible = "usb-nop-xceiv";
 		#phy-cells = <0>;
 	};
+
+	smbus1: smbus1 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c1>;
+		status = "disabled";
+	};
+
+	smbus2: smbus2 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c2>;
+		status = "disabled";
+	};
+
+	smbus3: smbus3 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c3>;
+		status = "disabled";
+	};
 };
 
 &nvic {

dts/arm/st/f3/stm32f3.dtsi

@@ -463,6 +463,14 @@
 		compatible = "usb-nop-xceiv";
 		#phy-cells = <0>;
 	};
+
+	smbus1: smbus1 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c1>;
+		status = "disabled";
+	};
 };
 
 &nvic {

dts/arm/st/f3/stm32f302.dtsi

@@ -117,4 +117,20 @@
 			st,adc-sequencer = <FULLY_CONFIGURABLE>;
 		};
 	};
+
+	smbus2: smbus2 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c2>;
+		status = "disabled";
+	};
+
+	smbus3: smbus3 {
+		compatible = "st,stm32-smbus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c = <&i2c3>;
+		status = "disabled";
+	};
 };

dts/arm/st/f3/stm32f302Xc.dtsi

@@ -49,3 +49,4 @@
 };
 
 /delete-node/ &i2c3;
+/delete-node/ &smbus3;