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drivers: pinctrl Addition of pic32cxsg pin control
Addition of pic32cxsg pin control including yaml, bindings, Kconfig, Signed-off-by: Michael D Sherwood <michael.sherwood@microchip.com>
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‎drivers/pinctrl/CMakeLists.txt‎

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@@ -22,6 +22,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM pinctrl_sam.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM_PIO4 pinctrl_sam_pio4.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_PIC32CXSG pinctrl_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_PORT pinctrl_nxp_port.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)

‎drivers/pinctrl/Kconfig‎

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@@ -50,6 +50,7 @@ source "drivers/pinctrl/Kconfig.mspm0"
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source "drivers/pinctrl/Kconfig.rpi_pico"
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source "drivers/pinctrl/Kconfig.sam"
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source "drivers/pinctrl/Kconfig.sam0"
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source "drivers/pinctrl/Kconfig.pic32cxsg"
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source "drivers/pinctrl/Kconfig.stm32"
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source "drivers/pinctrl/Kconfig.nxp_port"
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source "drivers/pinctrl/Kconfig.xec"

‎drivers/pinctrl/Kconfig.pic32cxsg‎

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# Copyright (c) 2024, Microchip
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_PIC32CXSG
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bool "Microchip PIC32CXSG pin controller driver"
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default y
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depends on DT_HAS_MICROCHIP_PIC32CXSG_PINCTRL_ENABLED
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help
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Microchip pin controller driver is used on PIC32CXSG SoC series

‎dts/arm/microchip/pic32c/pic32cx_sg/pic32cxsg.dtsi‎

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};
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pinctrl: pinctrl@41008000 {
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compatible = "atmel,sam0-pinctrl";
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ranges = <0x41008000 0x41008000 0x200>;
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#address-cells = <1>;
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#size-cells = <1>;

‎dts/bindings/pinctrl/microchip,pic32cxsg-pinctrl.yaml‎

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# Copyright (c) 2024 Microchip
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Microchip PIC32CXSG Pinctrl container node
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The Microchip PIC32CXSG pin controller is a singleton node responsible for controlling
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pin function selection and pin properties. For example, you can use this node
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to route SERCOM0 as UART were RX to pin PAD1 and enable the pull-up resistor
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on the pin.
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The node has the 'pinctrl' node label set in your SoC's devicetree, so you can
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modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the 'pinctrl'
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node, as shown in this example:
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/** You can put this in places like a <board>-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/** include pre-defined combinations for the SoC variant used by the board */
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#include <dt-bindings/pinctrl/microchip_pic32cxsg_pinctrl.h>
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&pinctrl {
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/* configuration for the usart0 "default" state */
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sercom0_uart_default: sercom0_uart_default {
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/* group 1 */
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group1 {
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/* configure PA6 as USART0 TX and PA8 as USART0 CTS */
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pinmux = <PA5D_SERCOM0_PAD1>, <PA6D_SERCOM0_PAD2>;
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};
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/* group 2 */
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group2 {
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/* configure PA5 as USART0 RX and PA7 as USART0 RTS */
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pinmux = <PA4D_SERCOM0_PAD0>, <PA7D_SERCOM0_PAD3>;
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/* both PA5 and PA7 have pull-up enabled */
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bias-pull-up;
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};
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};
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};
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The 'usart0_default' child node encodes the pin configurations for a
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particular state of a device; in this case, the default (that is, active)
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state.
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As shown, pin configurations are organized in groups within each child node.
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Each group can specify a list of pin function selections in the 'pinmux'
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property.
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A group can also specify shared pin properties common to all the specified
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pins, such as the 'bias-pull-up' property in group 2. Here is a list of
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supported standard pin properties:
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- bias-pull-up: Enable pull-up resistor.
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- bias-pull-down: Enable pull-down resistor.
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- drive-strength: Increase sink current.
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- input-enable: Enable input on pin.
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- output-enable: Enable output on a pin without actively driving it.
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To link pin configurations with a device, use a pinctrl-N property for some
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number N, like this example you could place in your board's DTS file:
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#include "board-pinctrl.dtsi"
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&usart0 {
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pinctrl-0 = <&usart0_default>;
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pinctrl-names = "default";
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};
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compatible: "microchip,pic32cxsg-pinctrl"
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include: base.yaml
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properties:
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 1
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child-binding:
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description: |
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Each child node defines the configuration for a particular state.
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child-binding:
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description: |
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The grandchild nodes group pins that share the pic32cxsg pin configuration.
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-pull-up
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- bias-pull-down
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- drive-strength
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- input-enable
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- output-enable
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properties:
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pinmux:
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required: true
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type: array
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description: |
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An array of pins sharing the pic32cxsg group properties. The pins should
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be defined using pre-defined macros or, alternatively, using the
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SAM_PINCTRL utility macros depending on the pinmux model used by the
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SoC series.
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drive-strength:
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enum:
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- 0
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- 1
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default: 0
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description: |
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The drive strength controls the output driver strength of an I/O pin
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configured as an output.
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0: Pin drive strength is set to normal drive strength.
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1: Pin drive strength is set to stronger drive strength.

‎dts/bindings/pinctrl/microchip,pic32cxsg-pinmux.yaml‎

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description: Microchip PIC32CXSG PINMUX
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compatible: "microchip,pic32cxsg-pinmux"
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include: base.yaml
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properties:
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reg:
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required: true
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pinmux-cells:
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- pin
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- function

‎include/zephyr/drivers/pinctrl/pinctrl_soc_pic32cxsg_common.h‎

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/*
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* Copyright (c) 2024 Microchip
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* Microchip PIC32CXSG SoC specific helpers for pinctrl driver
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_PIC32CXSG_COMMON_H_
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#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_PIC32CXSG_COMMON_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#include <dt-bindings/pinctrl/microchip_pic32cxsg_pinctrl.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @cond INTERNAL_HIDDEN */
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/** @brief Type for PIC32CXSG pin.
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*
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* Bits:
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* - 0-15: PIC32CXSG pinmux bit field (@ref SAM_PINMUX).
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* - 16-21: Pin flags bit field (@ref PIC32CXSG_PINFLAGS).
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* - 22-31: Reserved.
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*/
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typedef uint32_t pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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/* (CONFIG_SOC_FAMILY_MICROCHIP_PIC32CXSG) */
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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((DT_PROP_BY_IDX(node_id, prop, idx) << SAM_PINCTRL_PINMUX_POS) | \
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(DT_PROP(node_id, bias_pull_up) << SAM_PINCTRL_PULLUP_POS) | \
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(DT_PROP(node_id, bias_pull_down) << SAM_PINCTRL_PULLDOWN_POS) | \
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(DT_PROP(node_id, input_enable) << SAM_PINCTRL_INPUTENABLE_POS) | \
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(DT_PROP(node_id, output_enable) << SAM_PINCTRL_OUTPUTENABLE_POS) | \
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(DT_ENUM_IDX(node_id, drive_strength) << SAM_PINCTRL_DRIVESTRENGTH_POS)),
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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/**
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* @brief Pin flags/attributes
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* @anchor PIC32CXSG_PINFLAGS
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*
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* @{
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*/
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#define SAM_PINCTRL_FLAGS_DEFAULT (0U)
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#define SAM_PINCTRL_FLAGS_POS (0U)
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#define SAM_PINCTRL_FLAGS_MASK (0x3F << SAM_PINCTRL_FLAGS_POS)
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#define SAM_PINCTRL_FLAG_MASK (1U)
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#define SAM_PINCTRL_PULLUP_POS (SAM_PINCTRL_FLAGS_POS)
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#define SAM_PINCTRL_PULLUP (1U << SAM_PINCTRL_PULLUP_POS)
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#define SAM_PINCTRL_PULLDOWN_POS (SAM_PINCTRL_PULLUP_POS + 1U)
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#define SAM_PINCTRL_PULLDOWN (1U << SAM_PINCTRL_PULLDOWN_POS)
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#define SAM_PINCTRL_OPENDRAIN_POS (SAM_PINCTRL_PULLDOWN_POS + 1U)
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#define SAM_PINCTRL_OPENDRAIN (1U << SAM_PINCTRL_OPENDRAIN_POS)
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#define SAM_PINCTRL_INPUTENABLE_POS (SAM_PINCTRL_OPENDRAIN_POS + 1U)
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#define SAM_PINCTRL_INPUTENABLE (1U << SAM_PINCTRL_INPUTENABLE_POS)
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#define SAM_PINCTRL_OUTPUTENABLE_POS (SAM_PINCTRL_INPUTENABLE_POS + 1U)
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#define SAM_PINCTRL_OUTPUTENABLE (1U << SAM_PINCTRL_OUTPUTENABLE_POS)
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#define SAM_PINCTRL_DRIVESTRENGTH_POS (SAM_PINCTRL_OUTPUTENABLE_POS + 1U)
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#define SAM_PINCTRL_DRIVESTRENGTH (1U << SAM_PINCTRL_DRIVESTRENGTH_POS)
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/** @} */
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/**
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* Obtain Flag value from pinctrl_soc_pin_t configuration.
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*
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* @param pincfg pinctrl_soc_pin_t bit field value.
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* @param pos attribute/flags bit position (@ref PIC32CXSG_PINFLAGS).
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*/
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#define SAM_PINCTRL_FLAG_GET(pincfg, pos) (((pincfg) >> pos) & SAM_PINCTRL_FLAG_MASK)
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#define SAM_PINCTRL_FLAGS_GET(pincfg) (((pincfg) >> SAM_PINCTRL_FLAGS_POS) & SAM_PINCTRL_FLAGS_MASK)
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_PIC32CXSG_COMMON_H_ */

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