dts/bindings: clocks: Add stm32wl-rcc and fix stm32wb-pll-clock

Add binding fro stm32wl-rcc.yaml that derivates from stm32wb-rcc.
Additionally update stm32wb-pll-clock.yaml to be used as well
for stm32wl series and add missing div-m property.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>

Author: erwango

dts/bindings/clock/st,stm32wb-pll-clock.yaml

@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32WB PLL node.
+  STM32WB and STM32WL PLL node.
 
   It can be used to describe 2 different PLLs: PLL, PLLSAI1.
   Only main PLL is supported for now.
@@ -20,7 +20,9 @@ description: |
 
       with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
 
-  The PLL output frequency must not exceed 64 MHz.
+  The PLL output frequency must not exceed:
+          - 64 MHz on STM32WB
+          - 62 MHz on STM32WL
 
 compatible: "st,stm32wb-pll-clock"
 
@@ -33,6 +35,13 @@ properties:
     clocks:
       required: true
 
+    div-m:
+      type: int
+      required: true
+      description: |
+          Main PLL division factor for PLL input clock
+          Valid range: 1 - 8
+
     mul-n:
       type: int
       required: true

dts/bindings/clock/st,stm32wl-rcc.yaml

@@ -0,0 +1,36 @@
+# Copyright (c) 2021, Linaro ltd
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32WL Reset and Clock controller node.
+  For more description confere st,stm32-rcc.yaml
+
+compatible: "st,stm32wl-rcc"
+
+include:
+  - name: st,stm32wb-rcc.yaml
+    property-blocklist:
+      - ahb4-prescaler
+
+properties:
+    ahb3-prescaler:
+      type: int
+      required: false
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+        - 256
+        - 512
+      description: |
+          HCLK3 shared prescaler (AHB3, Flash memory, SRAM1 and SRAM2).
+          (A.K.A SHDHPRE)
+
+clock-cells:
+  - bus
+  - bits