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| 1 | +# Copyright (c) 2024 Microchip |
| 2 | +# SPDX-License-Identifier: Apache-2.0 |
| 3 | + |
| 4 | +description: Microchip PIC32CXSG SERCOM UART driver |
| 5 | + |
| 6 | +compatible: "microchip,pic32cxsg-uart" |
| 7 | + |
| 8 | +include: |
| 9 | + - name: uart-controller.yaml |
| 10 | + - name: pinctrl-device.yaml |
| 11 | + - name: atmel,assigned-clocks.yaml |
| 12 | + |
| 13 | +properties: |
| 14 | + reg: |
| 15 | + required: true |
| 16 | + |
| 17 | + interrupts: |
| 18 | + required: true |
| 19 | + |
| 20 | + clocks: |
| 21 | + required: true |
| 22 | + |
| 23 | + clock-names: |
| 24 | + required: true |
| 25 | + |
| 26 | + atmel,assigned-clocks: |
| 27 | + required: true |
| 28 | + |
| 29 | + atmel,assigned-clock-names: |
| 30 | + required: true |
| 31 | + |
| 32 | + rxpo: |
| 33 | + type: int |
| 34 | + required: true |
| 35 | + description: | |
| 36 | + Receive Data Pinout. An enumeration with the following values: |
| 37 | +
|
| 38 | + +-------+---------------+ |
| 39 | + | Value | RX Pin | |
| 40 | + +-------+---------------+ |
| 41 | + | 0 | SERCOM_PAD[0] | |
| 42 | + +-------+---------------+ |
| 43 | + | 1 | SERCOM_PAD[1] | |
| 44 | + +-------+---------------+ |
| 45 | + | 2 | SERCOM_PAD[2] | |
| 46 | + +-------+---------------+ |
| 47 | + | 3 | SERCOM_PAD[3] | |
| 48 | + +-------+---------------+ |
| 49 | +
|
| 50 | +
|
| 51 | + txpo: |
| 52 | + type: int |
| 53 | + required: true |
| 54 | + description: | |
| 55 | + Transmit Data Pinout. An enumeration with values that depend on the |
| 56 | + hardware being used. This controls both the transmit pins and if |
| 57 | + hardware flow control is used. |
| 58 | +
|
| 59 | + PIC32CXSG: |
| 60 | +
|
| 61 | + +-------+---------------+---------------+---------------+ |
| 62 | + | Value | TX Pin | RTS | CTS | |
| 63 | + +-------+---------------+---------------+---------------+ |
| 64 | + | 0 | SERCOM_PAD[0] | N/A | N/A | |
| 65 | + +-------+---------------+---------------+---------------+ |
| 66 | + | 1 | Reserved | |
| 67 | + +-------+---------------+---------------+---------------+ |
| 68 | + | 2 | SERCOM_PAD[0] | SERCOM_PAD[2] | SERCOM_PAD[3] | |
| 69 | + +-------+---------------+---------------+---------------+ |
| 70 | + | 3 | SERCOM_PAD[0] | SERCOM_PAD[2] | N/A | |
| 71 | + +-------+---------------+---------------+---------------+ |
| 72 | +
|
| 73 | +
|
| 74 | + collision-detection: |
| 75 | + type: boolean |
| 76 | + description: Enable collision detection for half-duplex mode. |
| 77 | + |
| 78 | + dmas: |
| 79 | + description: | |
| 80 | + Optional TX & RX dma specifiers. Each specifier will have a phandle |
| 81 | + reference to the dmac controller, the channel number, and peripheral |
| 82 | + trigger source. |
| 83 | +
|
| 84 | + For example dmas for TX, RX on SERCOM3 |
| 85 | + dmas = <&dmac 0 0xb>, <&dmac 0 0xa>; |
| 86 | +
|
| 87 | + dma-names: |
| 88 | + description: | |
| 89 | + Required if the dmas property exists. This should be "tx" and "rx" |
| 90 | + to match the dmas property. |
| 91 | +
|
| 92 | + For example |
| 93 | + dma-names = "tx", "rx"; |
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