diff --git a/drivers/dma/Kconfig.intel_adsp_gpdma b/drivers/dma/Kconfig.intel_adsp_gpdma
index 8488793ae12ab7..a590a3ac277c8a 100644
--- a/drivers/dma/Kconfig.intel_adsp_gpdma
+++ b/drivers/dma/Kconfig.intel_adsp_gpdma
@@ -26,6 +26,11 @@ config DMA_INTEL_ADSP_GPDMA_HAS_LLP
 	  Intel ADSP GPDMA may optionally have a linear link position
 	  feature.
 
+config DMA_INTEL_ADSP_GPDMA_DEBUG
+	bool "Debug dump for IP registers"
+	help
+	  Dump Intel ADSP GPDMA registers for debug
+
 source "drivers/dma/Kconfig.dw_common"
 
 endif # DMA_INTEL_ADSP_GPDMA
diff --git a/drivers/dma/dma_dw_common.h b/drivers/dma/dma_dw_common.h
index 44274f9ef71183..c4b33fac584ec0 100644
--- a/drivers/dma/dma_dw_common.h
+++ b/drivers/dma/dma_dw_common.h
@@ -152,6 +152,10 @@ extern "C" {
 /* min number of elems for config with irq disabled */
 #define DW_DMA_CFG_NO_IRQ_MIN_ELEMS	3
 
+#define DW_DMA_CHANNEL_REGISTER_OFFSET_END	0x50
+#define DW_DMA_IP_REGISTER_OFFSET_END		0x418
+#define DW_DMA_IP_REGISTER_OFFSET_START	0x2C0
+
 /* linked list item address */
 #define DW_DMA_LLI_ADDRESS(lli, dir) \
 	(((dir) == MEMORY_TO_PERIPHERAL) ? ((lli)->sar) : ((lli)->dar))
diff --git a/drivers/dma/dma_intel_adsp_gpdma.c b/drivers/dma/dma_intel_adsp_gpdma.c
index 8310e561d08a38..5d673e36cee135 100644
--- a/drivers/dma/dma_intel_adsp_gpdma.c
+++ b/drivers/dma/dma_intel_adsp_gpdma.c
@@ -51,6 +51,38 @@ struct intel_adsp_gpdma_cfg {
 	uint32_t shim;
 };
 
+#ifdef DMA_INTEL_ADSP_GPDMA_DEBUG
+static void intel_adsp_gpdma_dump_registers(const struct device *dev, uint32_t channel)
+{
+	const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
+	const struct dw_dma_dev_cfg *const dw_cfg = &dev_cfg->dw_cfg;
+	uint32_t cap, ctl, ipptr, llpc, llpl, llpu;
+	int i;
+
+	/* Shims */
+	cap = dw_read(dev_cfg->shim, 0x0);
+	ctl = dw_read(dev_cfg->shim, 0x4);
+	ipptr = dw_read(dev_cfg->shim, 0x8);
+	llpc = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));
+	llpl = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));
+	llpu = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));
+
+	LOG_INF("channel: %d cap %x, ctl %x, ipptr %x, llpc %x, llpl %x, llpu %x",
+		channel, cap, ctl, ipptr, llpc, llpl, llpu);
+
+	/* Channel Register Dump */
+	for (i = 0; i <= DW_DMA_CHANNEL_REGISTER_OFFSET_END; i += 0x8)
+		LOG_INF(" channel register offset: %#x value: %#x\n", chan_reg_offs[i],
+			dw_read(dw_cfg->base, DW_CHAN_OFFSET(channel) + chan_reg_offs[i]));
+
+	/* IP Register Dump */
+	for (i = DW_DMA_CHANNEL_REGISTER_OFFSET_START; i <= DW_DMA_CHANNEL_REGISTER_OFFSET_END;
+	     i += 0x8)
+		LOG_INF(" ip register offset: %#x value: %#x\n", ip_reg_offs[i],
+			dw_read(dw_cfg->base, ip_reg_offs[i]));
+}
+#endif
+
 static void intel_adsp_gpdma_llp_config(const struct device *dev,
 					uint32_t channel, uint32_t dma_slot)
 {