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virt-riscv.dtsi
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virt-riscv.dtsi
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/*
* Copyright (c) 2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* This file is based on:
* qemu-system-riscv32 -machine virt,dumpdtb=virt.dtb -smp 8 -m 256
* dtc virt.dtb > virt.dtsi
*/
/dts-v1/;
/ {
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
compatible = "riscv-virtio";
model = "riscv-virtio,qemu";
flash@20000000 {
bank-width = < 0x04 >;
reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >;
compatible = "cfi-flash";
};
uart0: uart@10000000 {
interrupts = < 0x0a 1 >;
interrupt-parent = < &plic >;
clock-frequency = < 0x384000 >;
reg = < 0x10000000 0x100 >;
compatible = "ns16550";
reg-shift = < 0 >;
};
cpus {
#address-cells = < 0x01 >;
#size-cells = < 0x00 >;
cpu@0 {
device_type = "cpu";
reg = < 0x00 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic0: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@1 {
device_type = "cpu";
reg = < 0x01 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic1: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@2 {
device_type = "cpu";
reg = < 0x02 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic2: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@3 {
device_type = "cpu";
reg = < 0x03 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic3: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@4 {
device_type = "cpu";
reg = < 0x04 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic4: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@5 {
device_type = "cpu";
reg = < 0x05 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic5: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@6 {
device_type = "cpu";
reg = < 0x06 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic6: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
cpu@7 {
device_type = "cpu";
reg = < 0x07 >;
status = "okay";
compatible = "qemu,riscv-virt", "riscv";
hlic7: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
#interrupt-cells = < 0x01 >;
interrupt-controller;
};
};
};
ram0: memory@80000000 {
device_type = "memory";
reg = < 0x80000000 0x10000000 >;
};
soc {
#address-cells = < 0x01 >;
#size-cells = < 0x01 >;
compatible = "simple-bus";
ranges;
plic: interrupt-controller@c000000 {
riscv,max-priority = <7>;
riscv,ndev = < 1024 >;
reg = <0x0c000000 0x04000000>;
interrupts-extended = <
&hlic0 0x0b &hlic0 0x09
&hlic1 0x0b &hlic1 0x09
&hlic2 0x0b &hlic2 0x09
&hlic3 0x0b &hlic3 0x09
&hlic4 0x0b &hlic4 0x09
&hlic5 0x0b &hlic5 0x09
&hlic6 0x0b &hlic6 0x09
&hlic7 0x0b &hlic7 0x09
>;
interrupt-controller;
compatible = "sifive,plic-1.0.0";
#address-cells = < 0x00 >;
#interrupt-cells = < 0x02 >;
};
clint@2000000 {
compatible = "sifive,clint0";
reg = <0x2000000 0x10000>;
interrupts-extended = <&hlic0 0x03 &hlic0 0x07
&hlic1 0x03 &hlic1 0x07
&hlic2 0x03 &hlic2 0x07
&hlic3 0x03 &hlic3 0x07
&hlic4 0x03 &hlic4 0x07
&hlic5 0x03 &hlic5 0x07
&hlic6 0x03 &hlic6 0x07
&hlic7 0x03 &hlic7 0x07>;
};
};
};