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jjsuwa-sys3175jcmvbkbc
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xtensa: Optimize bitwise AND operation with some specific forms of constants
This patch offers several insn-and-split patterns for bitwise AND with register and constant that can be represented as: i. 1's least significant N bits and the others 0's (17 <= N <= 31) ii. 1's most significant N bits and the others 0's (12 <= N <= 31) iii. M 1's sequence of bits and trailing N 0's bits, that cannot fit into a "MOVI Ax, simm12" instruction (1 <= M <= 16, 1 <= N <= 30) And also offers shortcuts for conditional branch if each of the abovementioned operations is (not) equal to zero. gcc/ChangeLog: * config/xtensa/predicates.md (shifted_mask_operand): New predicate. * config/xtensa/xtensa.md (*andsi3_const_pow2_minus_one): New insn-and-split pattern. (*andsi3_const_negative_pow2, *andsi3_const_shifted_mask, *masktrue_const_pow2_minus_one, *masktrue_const_negative_pow2, *masktrue_const_shifted_mask): Ditto.
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‎gcc/config/xtensa/predicates.md

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Original file line numberDiff line numberDiff line change
@@ -52,6 +52,16 @@
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(match_test "xtensa_mask_immediate (INTVAL (op))"))
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(match_operand 0 "register_operand")))
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(define_predicate "shifted_mask_operand"
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(match_code "const_int")
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{
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HOST_WIDE_INT mask = INTVAL (op);
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int shift = ctz_hwi (mask);
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return IN_RANGE (shift, 1, 31)
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&& xtensa_mask_immediate ((uint32_t)mask >> shift);
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})
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(define_predicate "extui_fldsz_operand"
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(and (match_code "const_int")
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(match_test "IN_RANGE (INTVAL (op), 1, 16)")))

‎gcc/config/xtensa/xtensa.md

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Original file line numberDiff line numberDiff line change
@@ -645,6 +645,83 @@
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(set_attr "mode" "SI")
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(set_attr "length" "6")])
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(define_insn_and_split "*andsi3_const_pow2_minus_one"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(and:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")))]
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"IN_RANGE (exact_log2 (INTVAL (operands[2]) + 1), 17, 31)"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(ashift:SI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(lshiftrt:SI (match_dup 0)
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(match_dup 2)))]
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{
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operands[2] = GEN_INT (32 - floor_log2 (INTVAL (operands[2]) + 1));
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}
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set (attr "length")
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(if_then_else (match_test "TARGET_DENSITY
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&& INTVAL (operands[2]) == 0x7FFFFFFF")
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(const_int 5)
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(const_int 6)))])
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(define_insn_and_split "*andsi3_const_negative_pow2"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(and:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i")))]
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"IN_RANGE (exact_log2 (-INTVAL (operands[2])), 12, 31)"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(lshiftrt:SI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(ashift:SI (match_dup 0)
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(match_dup 2)))]
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{
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operands[2] = GEN_INT (floor_log2 (-INTVAL (operands[2])));
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}
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set_attr "length" "6")])
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(define_insn_and_split "*andsi3_const_shifted_mask"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(and:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "shifted_mask_operand" "i")))]
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"! xtensa_simm12b (INTVAL (operands[2]))"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(zero_extract:SI (match_dup 1)
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(match_dup 3)
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(match_dup 4)))
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(set (match_dup 0)
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(ashift:SI (match_dup 0)
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(match_dup 2)))]
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{
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HOST_WIDE_INT mask = INTVAL (operands[2]);
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int shift = ctz_hwi (mask);
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int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1);
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int mask_pos = shift;
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if (BITS_BIG_ENDIAN)
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mask_pos = (32 - (mask_size + shift)) & 0x1f;
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operands[2] = GEN_INT (shift);
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operands[3] = GEN_INT (mask_size);
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operands[4] = GEN_INT (mask_pos);
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}
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[(set_attr "type" "arith")
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(set_attr "mode" "SI")
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(set (attr "length")
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(if_then_else (match_test "TARGET_DENSITY
721+
&& ctz_hwi (INTVAL (operands[2])) == 1")
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(const_int 5)
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(const_int 6)))])
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648725
(define_insn "iorsi3"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(ior:SI (match_operand:SI 1 "register_operand" "%r")
@@ -1649,6 +1726,108 @@
16491726
(set_attr "mode" "none")
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(set_attr "length" "3")])
16511728

1729+
(define_insn_and_split "*masktrue_const_pow2_minus_one"
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[(set (pc)
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(if_then_else (match_operator 3 "boolean_operator"
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[(and:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "const_int_operand" "i"))
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(const_int 0)])
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(label_ref (match_operand 2 "" ""))
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(pc)))]
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"IN_RANGE (exact_log2 (INTVAL (operands[1]) + 1), 17, 31)"
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"#"
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"&& can_create_pseudo_p ()"
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[(set (match_dup 4)
1741+
(ashift:SI (match_dup 0)
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(match_dup 1)))
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(set (pc)
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(if_then_else (match_op_dup 3
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[(match_dup 4)
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(const_int 0)])
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(label_ref (match_dup 2))
1748+
(pc)))]
1749+
{
1750+
operands[1] = GEN_INT (32 - floor_log2 (INTVAL (operands[1]) + 1));
1751+
operands[4] = gen_reg_rtx (SImode);
1752+
}
1753+
[(set_attr "type" "jump")
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(set_attr "mode" "none")
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(set (attr "length")
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(if_then_else (match_test "TARGET_DENSITY
1757+
&& INTVAL (operands[1]) == 0x7FFFFFFF")
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(const_int 5)
1759+
(const_int 6)))])
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1761+
(define_insn_and_split "*masktrue_const_negative_pow2"
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[(set (pc)
1763+
(if_then_else (match_operator 3 "boolean_operator"
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[(and:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "const_int_operand" "i"))
1766+
(const_int 0)])
1767+
(label_ref (match_operand 2 "" ""))
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(pc)))]
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"IN_RANGE (exact_log2 (-INTVAL (operands[1])), 12, 30)"
1770+
"#"
1771+
"&& can_create_pseudo_p ()"
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[(set (match_dup 4)
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(lshiftrt:SI (match_dup 0)
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(match_dup 1)))
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(set (pc)
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(if_then_else (match_op_dup 3
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[(match_dup 4)
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(const_int 0)])
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(label_ref (match_dup 2))
1780+
(pc)))]
1781+
{
1782+
operands[1] = GEN_INT (floor_log2 (-INTVAL (operands[1])));
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operands[4] = gen_reg_rtx (SImode);
1784+
}
1785+
[(set_attr "type" "jump")
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(set_attr "mode" "none")
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(set_attr "length" "6")])
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(define_insn_and_split "*masktrue_const_shifted_mask"
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[(set (pc)
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(if_then_else (match_operator 4 "boolean_operator"
1792+
[(and:SI (match_operand:SI 0 "register_operand" "r")
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(match_operand:SI 1 "shifted_mask_operand" "i"))
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(match_operand:SI 2 "const_int_operand" "i")])
1795+
(label_ref (match_operand 3 "" ""))
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(pc)))]
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"(INTVAL (operands[2]) & ((1 << ctz_hwi (INTVAL (operands[1]))) - 1)) == 0
1798+
&& xtensa_b4const_or_zero ((uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])))"
1799+
"#"
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"&& can_create_pseudo_p ()"
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[(set (match_dup 6)
1802+
(zero_extract:SI (match_dup 0)
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(match_dup 5)
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(match_dup 1)))
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(set (pc)
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(if_then_else (match_op_dup 4
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[(match_dup 6)
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(match_dup 2)])
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(label_ref (match_dup 3))
1810+
(pc)))]
1811+
{
1812+
HOST_WIDE_INT mask = INTVAL (operands[1]);
1813+
int shift = ctz_hwi (mask);
1814+
int mask_size = floor_log2 (((uint32_t)mask >> shift) + 1);
1815+
int mask_pos = shift;
1816+
if (BITS_BIG_ENDIAN)
1817+
mask_pos = (32 - (mask_size + shift)) & 0x1f;
1818+
operands[1] = GEN_INT (mask_pos);
1819+
operands[2] = GEN_INT ((uint32_t)INTVAL (operands[2]) >> shift);
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operands[5] = GEN_INT (mask_size);
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operands[6] = gen_reg_rtx (SImode);
1822+
}
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[(set_attr "type" "jump")
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(set_attr "mode" "none")
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(set (attr "length")
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(if_then_else (match_test "TARGET_DENSITY
1827+
&& (uint32_t)INTVAL (operands[2]) >> ctz_hwi (INTVAL (operands[1])) == 0")
1828+
(const_int 5)
1829+
(const_int 6)))])
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16521831

16531832
;; Zero-overhead looping support.
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