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Execute.vp
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Execute.vp
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`include "data_defs.vp"
module Execute( clock, reset, E_Control, bypass_alu_1, bypass_alu_2, IR, npc, W_Control_in, Mem_Control_in,
VSR1, VSR2, enable_execute, Mem_Bypass_Val, bypass_mem_1, bypass_mem_2,
W_Control_out, Mem_Control_out, NZP, IR_Exec,
aluout, pcout, sr1, sr2, dr, M_Data); // MODIFICATION_RAVI Need in put in the bypass that could
// be either VSR1 or VSR2. Need controls for that as well.
input clock, reset, enable_execute;
input [1:0] W_Control_in;
input Mem_Control_in;
input [5:0] E_Control;
input [15:0] IR;
input [15:0] npc;
input [15:0] VSR1, VSR2, Mem_Bypass_Val;
input bypass_alu_1, bypass_alu_2, bypass_mem_1, bypass_mem_2; //bypass1 and bypass2 allow for the use of bypass values for either VSR1 or VSR2
output [15:0] aluout, pcout;
output [1:0] W_Control_out;
output Mem_Control_out;
output [2:0] NZP;
output [15:0] IR_Exec;
output [2:0] sr1, sr2, dr;
output [15:0] M_Data;
reg [2:0] sr1, sr2, dr;
reg [1:0] W_Control_out;
reg Mem_Control_out;
reg [15:0] M_Data;
wire [15:0] offset11, offset9, offset6, imm5, trapvect8;
wire [1:0] pcselect1, alu_control, alu_control_temp;
wire pcselect2, op2select;
reg [15:0] addrin1, addrin2, aluin1_temp, aluin2_temp;
wire alucarry; // overflow checking not implemented
wire [15:0] VSR1_int, VSR2_int;
wire alu_or_pc;
wire [15:0] aluin1, aluin2;
reg [2:0] NZP;
reg [15:0] IR_Exec;
//assign {IR, VSR1, VSR2}=D_Data; // the D_Data values is going to come in from the register file based on the
// the sr1 and sr2 values sent to the RF from the Execute.
// create the correct sr1 sr2 values for reading the register file
ALU alu (clock, reset, aluin1, aluin2, alu_control, enable_execute, aluout, alucarry);
extension ext (IR, offset11, offset9, offset6, trapvect8, imm5); // IR and trapvect8 are not used for this project
`protected
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`endprotected
endmodule
module extension(ir, offset11, offset9, offset6, trapvect8, imm5);
input [15:0] ir;
output [15:0] offset11, offset9, offset6, trapvect8, imm5;
`protected
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`endprotected
endmodule //extension
module ALU(clock, reset, aluin1, aluin2, alu_control, enable_execute, aluout, alucarry);
input clock, reset;
input [15:0] aluin1, aluin2;
input [1:0] alu_control;
input enable_execute;
output [15:0] aluout;
output alucarry;
reg [15:0] aluout;
reg alucarry;
`protected
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`endprotected
endmodule // ALU