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Create output macro
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@ytausky
ytausky committed Feb 15, 2020
1 parent 8c382a8 commit e04f6d6
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Showing 7 changed files with 251 additions and 148 deletions.
2 changes: 1 addition & 1 deletion src/cpu/instruction.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -580,7 +580,7 @@ impl<'a> RunView<'a, InstructionExecutionState> {
if addr == 0xffff {
self.state.read_ie = true;
}
bus_read(addr)
Some(bus_read(addr))
}

fn alu_op(&self, op: AluOp, lhs: u8, rhs: u8) -> (u8, Flags) {
Expand Down
14 changes: 7 additions & 7 deletions src/cpu/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -187,7 +187,7 @@ impl<'a, T> RunView<'a, T> {
if addr == 0xffff {
self.basic.ie = data & 0x1f
}
bus_write(addr, data)
Some(bus_write(addr, data))
}
}

Expand Down Expand Up @@ -434,18 +434,18 @@ pub enum BusOp {
Write(u8),
}

fn bus_read(addr: u16) -> Option<BusActivity> {
Some(BusActivity {
fn bus_read(addr: u16) -> BusActivity {
BusActivity {
addr,
op: Some(BusOp::Read),
})
}
}

fn bus_write(addr: u16, data: u8) -> Option<BusActivity> {
Some(BusActivity {
fn bus_write(addr: u16, data: u8) -> BusActivity {
BusActivity {
addr,
op: Some(BusOp::Write(data)),
})
}
}

enum RegSelect {
Expand Down
12 changes: 6 additions & 6 deletions src/cpu/tests/alu.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,8 @@ fn test_addition_deref_hl(opcode: &[u8], test_case: &AluTestCase) {
cpu.test_simple_instr(
opcode,
&[
(input!(), bus_read(cpu.data.hl())),
(input!(data: test_case.input.y), None),
(input!(), output!(bus: bus_read(cpu.data.hl()))),
(input!(data: test_case.input.y), output!()),
],
);
assert_eq!(cpu.data.a, test_case.expected.result);
Expand Down Expand Up @@ -436,10 +436,10 @@ fn inc_deref_hl() {
cpu.test_simple_instr(
&[0b00_110_100],
&[
(input!(), bus_read(0x1234)),
(input!(data: 0x01), None),
(input!(), bus_write(0x1234, 0x02)),
(input!(), None),
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x01), output!()),
(input!(), output!(bus: bus_write(0x1234, 0x02))),
(input!(), output!()),
],
);
assert_eq!(cpu.data.f, flags!())
Expand Down
81 changes: 42 additions & 39 deletions src/cpu/tests/branch.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ fn jp_nn() {
cpu.test_opcode(
&[0xc3, 0x34, 0x12],
&[
(input!(), None),
(input!(), None),
(input!(), bus_read(0x1234)),
(input!(data: 0x00), None),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -20,10 +20,10 @@ fn jp_nz_nn_branching() {
cpu.test_opcode(
&[0xc2, 0x34, 0x12],
&[
(input!(), None),
(input!(), None),
(input!(), bus_read(0x1234)),
(input!(data: 0x00), None),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -42,10 +42,10 @@ fn jp_z_nn_branching() {
cpu.test_opcode(
&[0xca, 0x34, 0x12],
&[
(input!(), None),
(input!(), None),
(input!(), bus_read(0x1234)),
(input!(data: 0x00), None),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -62,10 +62,10 @@ fn jp_nc_nn_branching() {
cpu.test_opcode(
&[0xd2, 0x34, 0x12],
&[
(input!(), None),
(input!(), None),
(input!(), bus_read(0x1234)),
(input!(data: 0x00), None),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -84,10 +84,10 @@ fn jp_c_nn_branching() {
cpu.test_opcode(
&[0xda, 0x34, 0x12],
&[
(input!(), None),
(input!(), None),
(input!(), bus_read(0x1234)),
(input!(data: 0x00), None),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -104,16 +104,16 @@ fn jp_c_nn_non_branching_then_ret() {
cpu.test_opcode(
&[0xda, 0x34, 0x12],
&[
(input!(), bus_read(0x0003)),
(input!(data: RET), None),
(input!(), bus_read(0x0000)),
(input!(data: 0x34), None),
(input!(), bus_read(0x0001)),
(input!(data: 0x12), None),
(input!(), None),
(input!(), None),
(input!(), bus_read(0x1234)),
(input!(data: 0x00), None),
(input!(), output!(bus: bus_read(0x0003))),
(input!(data: RET), output!()),
(input!(), output!(bus: bus_read(0x0000))),
(input!(data: 0x34), output!()),
(input!(), output!(bus: bus_read(0x0001))),
(input!(data: 0x12), output!()),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -125,10 +125,10 @@ fn jr_e_min_value() {
cpu.test_opcode(
&[0x18, 0x80],
&[
(input!(), None),
(input!(), None),
(input!(), bus_read(0x0f82)),
(input!(data: 0x00), None),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x0f82))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -140,10 +140,10 @@ fn jr_e_with_carry() {
cpu.test_opcode(
&[0x18, 0x7e],
&[
(input!(), None),
(input!(), None),
(input!(), bus_read(0x1100)),
(input!(data: 0x00), None),
(input!(), output!()),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x1100))),
(input!(data: 0x00), output!()),
],
)
}
Expand All @@ -155,7 +155,10 @@ fn jp_deref_hl() {
cpu.data.l = 0x34;
cpu.test_opcode(
&[0xe9],
&[(input!(), bus_read(0x1234)), (input!(data: 0x00), None)],
&[
(input!(), output!(bus: bus_read(0x1234))),
(input!(data: 0x00), output!()),
],
);
assert_eq!(cpu.data.pc, 0x1235)
}
69 changes: 39 additions & 30 deletions src/cpu/tests/interrupt.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,20 +48,20 @@ fn halt_mode_canceled_and_interrupt_dispatched() {
cpu.data.ime = true;

// Fetch HALT opcode
assert_eq!(cpu.step(&input!()), bus_read(0x0000));
assert_eq!(cpu.step(&input!(data: HALT)), None);
assert_eq!(cpu.step(&input!()), output!(bus: bus_read(0x0000)));
assert_eq!(cpu.step(&input!(data: HALT)), output!());

// Execute HALT
assert_eq!(cpu.step(&input!()), None);
assert_eq!(cpu.step(&input!()), None);
assert_eq!(cpu.step(&input!()), output!());
assert_eq!(cpu.step(&input!()), output!());

// Wait one M-cycle to avoid testing behavior immediately following HALT execution
assert_eq!(cpu.step(&input!()), None);
assert_eq!(cpu.step(&input!()), None);
assert_eq!(cpu.step(&input!()), output!());
assert_eq!(cpu.step(&input!()), output!());

// Request interrupt
assert_eq!(cpu.step(&input!(if: 0x01)), None);
assert_eq!(cpu.step(&input!(if: 0x01)), None);
assert_eq!(cpu.step(&input!(if: 0x01)), output!());
assert_eq!(cpu.step(&input!(if: 0x01)), output!());

cpu.assert_interrupt_dispatch(0x01, 0);
}
Expand All @@ -74,7 +74,10 @@ fn reading_0xffff_returns_ie() {
cpu.data.ie = 0x15;
cpu.test_simple_instr(
&[0xf0, 0xff],
&[(input!(), bus_read(0xffff)), (input!(), None)],
&[
(input!(), output!(bus: bus_read(0xffff))),
(input!(), output!()),
],
);
assert_eq!(cpu.data.a, 0x15)
}
Expand All @@ -88,10 +91,10 @@ fn read_memory_in_same_instruction_after_reading_0xffff() {
cpu.test_simple_instr(
&[POP_BC],
&[
(input!(), bus_read(0xffff)),
(input!(), None),
(input!(), bus_read(0x0000)),
(input!(data: 0x42), None),
(input!(), output!(bus: bus_read(0xffff))),
(input!(), output!()),
(input!(), output!(bus: bus_read(0x0000))),
(input!(data: 0x42), output!()),
],
);
assert_eq!(cpu.data.bc(), 0x4215)
Expand All @@ -104,7 +107,10 @@ fn writing_0xffff_sets_5_lower_bits_of_ie() {
cpu.data.a = 0xff;
cpu.test_simple_instr(
&[0xe0, 0xff],
&[(input!(), bus_write(0xffff, 0xff)), (input!(), None)],
&[
(input!(), output!(bus: bus_write(0xffff, 0xff))),
(input!(), output!()),
],
);
assert_eq!(cpu.data.ie, 0x1f)
}
Expand All @@ -122,38 +128,41 @@ fn writing_0xffff_during_interrupt_dispatch_updates_ie() {
impl Cpu {
fn assert_fetch_and_interrupt_dispatch(&mut self, r#if: u8, n: u16) {
self.data.ime = true;
assert_eq!(self.step(&input!(if: r#if)), bus_read(self.data.pc));
assert_eq!(self.step(&input!(data: NOP, if: r#if)), None);
assert_eq!(
self.step(&input!(if: r#if)),
output!(bus: bus_read(self.data.pc))
);
assert_eq!(self.step(&input!(data: NOP, if: r#if)), output!());
self.assert_interrupt_dispatch(r#if, n)
}

fn assert_interrupt_dispatch(&mut self, r#if: u8, n: u16) {
let pc = self.data.pc;
let sp = self.data.sp;
assert_eq!(self.step(&input!(if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), output!());
assert_eq!(self.step(&input!(if: r#if)), output!());
assert_eq!(self.step(&input!(if: r#if)), output!());
assert_eq!(self.step(&input!(if: r#if)), output!());
assert_eq!(
self.step(&input!(if: r#if)),
bus_write(sp.wrapping_sub(1), high_byte(pc))
output!(bus: bus_write(sp.wrapping_sub(1), high_byte(pc)))
);
assert_eq!(self.step(&input!(if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), output!());
assert_eq!(
self.step(&input!(if: r#if)),
bus_write(sp.wrapping_sub(2), low_byte(pc))
output!(bus: bus_write(sp.wrapping_sub(2), low_byte(pc)))
);
assert_eq!(self.step(&input!(if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), output!());
assert!(!self.data.ime);
assert_eq!(self.step(&input!()), bus_read(0x0040 + 8 * n));
assert_eq!(self.step(&input!(data: 0x00)), None);
assert_eq!(self.step(&input!()), output!(bus: bus_read(0x0040 + 8 * n)));
assert_eq!(self.step(&input!(data: 0x00)), output!());
}

fn assert_no_interrupt_dispatch(&mut self, r#if: u8) {
let pc = self.data.pc;
assert_eq!(self.step(&input!(if: r#if)), bus_read(pc));
assert_eq!(self.step(&input!(data: 0x00, if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), bus_read(pc + 1));
assert_eq!(self.step(&input!(data: 0x00, if: r#if)), None);
assert_eq!(self.step(&input!(if: r#if)), output!(bus: bus_read(pc)));
assert_eq!(self.step(&input!(data: 0x00, if: r#if)), output!());
assert_eq!(self.step(&input!(if: r#if)), output!(bus: bus_read(pc + 1)));
assert_eq!(self.step(&input!(data: 0x00, if: r#if)), output!());
}
}
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