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css.c
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/*
* Channel subsystem base support.
*
* Copyright 2012 IBM Corp.
* Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or (at
* your option) any later version. See the COPYING file in the top-level
* directory.
*/
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
#include "hw/qdev.h"
#include "qemu/bitops.h"
#include "qemu/error-report.h"
#include "exec/address-spaces.h"
#include "cpu.h"
#include "hw/s390x/ioinst.h"
#include "hw/s390x/css.h"
#include "trace.h"
#include "hw/s390x/s390_flic.h"
#include "hw/s390x/s390-virtio-ccw.h"
typedef struct CrwContainer {
CRW crw;
QTAILQ_ENTRY(CrwContainer) sibling;
} CrwContainer;
static const VMStateDescription vmstate_crw = {
.name = "s390_crw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT16(flags, CRW),
VMSTATE_UINT16(rsid, CRW),
VMSTATE_END_OF_LIST()
},
};
static const VMStateDescription vmstate_crw_container = {
.name = "s390_crw_container",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW),
VMSTATE_END_OF_LIST()
},
};
typedef struct ChpInfo {
uint8_t in_use;
uint8_t type;
uint8_t is_virtual;
} ChpInfo;
static const VMStateDescription vmstate_chp_info = {
.name = "s390_chp_info",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(in_use, ChpInfo),
VMSTATE_UINT8(type, ChpInfo),
VMSTATE_UINT8(is_virtual, ChpInfo),
VMSTATE_END_OF_LIST()
}
};
typedef struct SubchSet {
SubchDev *sch[MAX_SCHID + 1];
unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)];
unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)];
} SubchSet;
static const VMStateDescription vmstate_scsw = {
.name = "s390_scsw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT16(flags, SCSW),
VMSTATE_UINT16(ctrl, SCSW),
VMSTATE_UINT32(cpa, SCSW),
VMSTATE_UINT8(dstat, SCSW),
VMSTATE_UINT8(cstat, SCSW),
VMSTATE_UINT16(count, SCSW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_pmcw = {
.name = "s390_pmcw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(intparm, PMCW),
VMSTATE_UINT16(flags, PMCW),
VMSTATE_UINT16(devno, PMCW),
VMSTATE_UINT8(lpm, PMCW),
VMSTATE_UINT8(pnom, PMCW),
VMSTATE_UINT8(lpum, PMCW),
VMSTATE_UINT8(pim, PMCW),
VMSTATE_UINT16(mbi, PMCW),
VMSTATE_UINT8(pom, PMCW),
VMSTATE_UINT8(pam, PMCW),
VMSTATE_UINT8_ARRAY(chpid, PMCW, 8),
VMSTATE_UINT32(chars, PMCW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_schib = {
.name = "s390_schib",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW),
VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW),
VMSTATE_UINT64(mba, SCHIB),
VMSTATE_UINT8_ARRAY(mda, SCHIB, 4),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_ccw1 = {
.name = "s390_ccw1",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(cmd_code, CCW1),
VMSTATE_UINT8(flags, CCW1),
VMSTATE_UINT16(count, CCW1),
VMSTATE_UINT32(cda, CCW1),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_ciw = {
.name = "s390_ciw",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(type, CIW),
VMSTATE_UINT8(command, CIW),
VMSTATE_UINT16(count, CIW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_sense_id = {
.name = "s390_sense_id",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(reserved, SenseId),
VMSTATE_UINT16(cu_type, SenseId),
VMSTATE_UINT8(cu_model, SenseId),
VMSTATE_UINT16(dev_type, SenseId),
VMSTATE_UINT8(dev_model, SenseId),
VMSTATE_UINT8(unused, SenseId),
VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_orb = {
.name = "s390_orb",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(intparm, ORB),
VMSTATE_UINT16(ctrl0, ORB),
VMSTATE_UINT8(lpm, ORB),
VMSTATE_UINT8(ctrl1, ORB),
VMSTATE_UINT32(cpa, ORB),
VMSTATE_END_OF_LIST()
}
};
static bool vmstate_schdev_orb_needed(void *opaque)
{
return css_migration_enabled();
}
static const VMStateDescription vmstate_schdev_orb = {
.name = "s390_subch_dev/orb",
.version_id = 1,
.minimum_version_id = 1,
.needed = vmstate_schdev_orb_needed,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB),
VMSTATE_END_OF_LIST()
}
};
static int subch_dev_post_load(void *opaque, int version_id);
static int subch_dev_pre_save(void *opaque);
const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!"
" Likely reason: some sequences of plug and unplug can break"
" migration for machine versions prior to 2.7 (known design flaw).";
const VMStateDescription vmstate_subch_dev = {
.name = "s390_subch_dev",
.version_id = 1,
.minimum_version_id = 1,
.post_load = subch_dev_post_load,
.pre_save = subch_dev_pre_save,
.fields = (VMStateField[]) {
VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"),
VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"),
VMSTATE_UINT16(migrated_schid, SubchDev),
VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno),
VMSTATE_BOOL(thinint_active, SubchDev),
VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB),
VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32),
VMSTATE_UINT64(channel_prog, SubchDev),
VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1),
VMSTATE_BOOL(last_cmd_valid, SubchDev),
VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId),
VMSTATE_BOOL(ccw_fmt_1, SubchDev),
VMSTATE_UINT8(ccw_no_data_cnt, SubchDev),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * []) {
&vmstate_schdev_orb,
NULL
}
};
typedef struct IndAddrPtrTmp {
IndAddr **parent;
uint64_t addr;
int32_t len;
} IndAddrPtrTmp;
static int post_load_ind_addr(void *opaque, int version_id)
{
IndAddrPtrTmp *ptmp = opaque;
IndAddr **ind_addr = ptmp->parent;
if (ptmp->len != 0) {
*ind_addr = get_indicator(ptmp->addr, ptmp->len);
} else {
*ind_addr = NULL;
}
return 0;
}
static int pre_save_ind_addr(void *opaque)
{
IndAddrPtrTmp *ptmp = opaque;
IndAddr *ind_addr = *(ptmp->parent);
if (ind_addr != NULL) {
ptmp->len = ind_addr->len;
ptmp->addr = ind_addr->addr;
} else {
ptmp->len = 0;
ptmp->addr = 0L;
}
return 0;
}
const VMStateDescription vmstate_ind_addr_tmp = {
.name = "s390_ind_addr_tmp",
.pre_save = pre_save_ind_addr,
.post_load = post_load_ind_addr,
.fields = (VMStateField[]) {
VMSTATE_INT32(len, IndAddrPtrTmp),
VMSTATE_UINT64(addr, IndAddrPtrTmp),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_ind_addr = {
.name = "s390_ind_addr_tmp",
.fields = (VMStateField[]) {
VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp),
VMSTATE_END_OF_LIST()
}
};
typedef struct CssImage {
SubchSet *sch_set[MAX_SSID + 1];
ChpInfo chpids[MAX_CHPID + 1];
} CssImage;
static const VMStateDescription vmstate_css_img = {
.name = "s390_css_img",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
/* Subchannel sets have no relevant state. */
VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0,
vmstate_chp_info, ChpInfo),
VMSTATE_END_OF_LIST()
}
};
typedef struct IoAdapter {
uint32_t id;
uint8_t type;
uint8_t isc;
uint8_t flags;
} IoAdapter;
typedef struct ChannelSubSys {
QTAILQ_HEAD(, CrwContainer) pending_crws;
bool sei_pending;
bool do_crw_mchk;
bool crws_lost;
uint8_t max_cssid;
uint8_t max_ssid;
bool chnmon_active;
uint64_t chnmon_area;
CssImage *css[MAX_CSSID + 1];
uint8_t default_cssid;
/* don't migrate, see css_register_io_adapters */
IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1];
/* don't migrate, see get_indicator and IndAddrPtrTmp */
QTAILQ_HEAD(, IndAddr) indicator_addresses;
} ChannelSubSys;
static const VMStateDescription vmstate_css = {
.name = "s390_css",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container,
CrwContainer, sibling),
VMSTATE_BOOL(sei_pending, ChannelSubSys),
VMSTATE_BOOL(do_crw_mchk, ChannelSubSys),
VMSTATE_BOOL(crws_lost, ChannelSubSys),
/* These were kind of migrated by virtio */
VMSTATE_UINT8(max_cssid, ChannelSubSys),
VMSTATE_UINT8(max_ssid, ChannelSubSys),
VMSTATE_BOOL(chnmon_active, ChannelSubSys),
VMSTATE_UINT64(chnmon_area, ChannelSubSys),
VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1,
0, vmstate_css_img, CssImage),
VMSTATE_UINT8(default_cssid, ChannelSubSys),
VMSTATE_END_OF_LIST()
}
};
static ChannelSubSys channel_subsys = {
.pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws),
.do_crw_mchk = true,
.sei_pending = false,
.do_crw_mchk = true,
.crws_lost = false,
.chnmon_active = false,
.indicator_addresses =
QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses),
};
static int subch_dev_pre_save(void *opaque)
{
SubchDev *s = opaque;
/* Prepare remote_schid for save */
s->migrated_schid = s->schid;
return 0;
}
static int subch_dev_post_load(void *opaque, int version_id)
{
SubchDev *s = opaque;
/* Re-assign the subchannel to remote_schid if necessary */
if (s->migrated_schid != s->schid) {
if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) {
/*
* Cleanup the slot before moving to s->migrated_schid provided
* it still belongs to us, i.e. it was not changed by previous
* invocation of this function.
*/
css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL);
}
/* It's OK to re-assign without a prior de-assign. */
s->schid = s->migrated_schid;
css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s);
}
if (css_migration_enabled()) {
/* No compat voodoo to do ;) */
return 0;
}
/*
* Hack alert. If we don't migrate the channel subsystem status
* we still need to find out if the guest enabled mss/mcss-e.
* If the subchannel is enabled, it certainly was able to access it,
* so adjust the max_ssid/max_cssid values for relevant ssid/cssid
* values. This is not watertight, but better than nothing.
*/
if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) {
if (s->ssid) {
channel_subsys.max_ssid = MAX_SSID;
}
if (s->cssid != channel_subsys.default_cssid) {
channel_subsys.max_cssid = MAX_CSSID;
}
}
return 0;
}
void css_register_vmstate(void)
{
vmstate_register(NULL, 0, &vmstate_css, &channel_subsys);
}
IndAddr *get_indicator(hwaddr ind_addr, int len)
{
IndAddr *indicator;
QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) {
if (indicator->addr == ind_addr) {
indicator->refcnt++;
return indicator;
}
}
indicator = g_new0(IndAddr, 1);
indicator->addr = ind_addr;
indicator->len = len;
indicator->refcnt = 1;
QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses,
indicator, sibling);
return indicator;
}
static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr,
bool do_map)
{
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map);
}
void release_indicator(AdapterInfo *adapter, IndAddr *indicator)
{
assert(indicator->refcnt > 0);
indicator->refcnt--;
if (indicator->refcnt > 0) {
return;
}
QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling);
if (indicator->map) {
s390_io_adapter_map(adapter, indicator->map, false);
}
g_free(indicator);
}
int map_indicator(AdapterInfo *adapter, IndAddr *indicator)
{
int ret;
if (indicator->map) {
return 0; /* already mapped is not an error */
}
indicator->map = indicator->addr;
ret = s390_io_adapter_map(adapter, indicator->map, true);
if ((ret != 0) && (ret != -ENOSYS)) {
goto out_err;
}
return 0;
out_err:
indicator->map = 0;
return ret;
}
int css_create_css_image(uint8_t cssid, bool default_image)
{
trace_css_new_image(cssid, default_image ? "(default)" : "");
/* 255 is reserved */
if (cssid == 255) {
return -EINVAL;
}
if (channel_subsys.css[cssid]) {
return -EBUSY;
}
channel_subsys.css[cssid] = g_new0(CssImage, 1);
if (default_image) {
channel_subsys.default_cssid = cssid;
}
return 0;
}
uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc)
{
if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC ||
!channel_subsys.io_adapters[type][isc]) {
return -1;
}
return channel_subsys.io_adapters[type][isc]->id;
}
/**
* css_register_io_adapters: Register I/O adapters per ISC during init
*
* @swap: an indication if byte swap is needed.
* @maskable: an indication if the adapter is subject to the mask operation.
* @flags: further characteristics of the adapter.
* e.g. suppressible, an indication if the adapter is subject to AIS.
* @errp: location to store error information.
*/
void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable,
uint8_t flags, Error **errp)
{
uint32_t id;
int ret, isc;
IoAdapter *adapter;
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
/*
* Disallow multiple registrations for the same device type.
* Report an error if registering for an already registered type.
*/
if (channel_subsys.io_adapters[type][0]) {
error_setg(errp, "Adapters for type %d already registered", type);
}
for (isc = 0; isc <= MAX_ISC; isc++) {
id = (type << 3) | isc;
ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags);
if (ret == 0) {
adapter = g_new0(IoAdapter, 1);
adapter->id = id;
adapter->isc = isc;
adapter->type = type;
adapter->flags = flags;
channel_subsys.io_adapters[type][isc] = adapter;
} else {
error_setg_errno(errp, -ret, "Unexpected error %d when "
"registering adapter %d", ret, id);
break;
}
}
/*
* No need to free registered adapters in kvm: kvm will clean up
* when the machine goes away.
*/
if (ret) {
for (isc--; isc >= 0; isc--) {
g_free(channel_subsys.io_adapters[type][isc]);
channel_subsys.io_adapters[type][isc] = NULL;
}
}
}
static void css_clear_io_interrupt(uint16_t subchannel_id,
uint16_t subchannel_nr)
{
Error *err = NULL;
static bool no_clear_irq;
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
int r;
if (unlikely(no_clear_irq)) {
return;
}
r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr);
switch (r) {
case 0:
break;
case -ENOSYS:
no_clear_irq = true;
/*
* Ignore unavailability, as the user can't do anything
* about it anyway.
*/
break;
default:
error_setg_errno(&err, -r, "unexpected error condition");
error_propagate(&error_abort, err);
}
}
static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid)
{
if (channel_subsys.max_cssid > 0) {
return (cssid << 8) | (1 << 3) | (ssid << 1) | 1;
}
return (ssid << 1) | 1;
}
uint16_t css_build_subchannel_id(SubchDev *sch)
{
return css_do_build_subchannel_id(sch->cssid, sch->ssid);
}
void css_inject_io_interrupt(SubchDev *sch)
{
uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
sch->curr_status.pmcw.intparm, isc, "");
s390_io_interrupt(css_build_subchannel_id(sch),
sch->schid,
sch->curr_status.pmcw.intparm,
isc << 27);
}
void css_conditional_io_interrupt(SubchDev *sch)
{
/*
* If the subchannel is not currently status pending, make it pending
* with alert status.
*/
if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) {
uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11;
trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid,
sch->curr_status.pmcw.intparm, isc,
"(unsolicited)");
sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL;
sch->curr_status.scsw.ctrl |=
SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND;
/* Inject an I/O interrupt. */
s390_io_interrupt(css_build_subchannel_id(sch),
sch->schid,
sch->curr_status.pmcw.intparm,
isc << 27);
}
}
int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode)
{
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
int r;
if (env->psw.mask & PSW_MASK_PSTATE) {
r = -PGM_PRIVILEGED;
goto out;
}
trace_css_do_sic(mode, isc);
switch (mode) {
case SIC_IRQ_MODE_ALL:
case SIC_IRQ_MODE_SINGLE:
break;
default:
r = -PGM_OPERAND;
goto out;
}
r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0;
out:
return r;
}
void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc)
{
S390FLICState *fs = s390_get_flic();
S390FLICStateClass *fsc = S390_FLIC_COMMON_GET_CLASS(fs);
uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI;
IoAdapter *adapter = channel_subsys.io_adapters[type][isc];
if (!adapter) {
return;
}
trace_css_adapter_interrupt(isc);
if (fs->ais_supported) {
if (fsc->inject_airq(fs, type, isc, adapter->flags)) {
error_report("Failed to inject airq with AIS supported");
exit(1);
}
} else {
s390_io_interrupt(0, 0, 0, io_int_word);
}
}
static void sch_handle_clear_func(SubchDev *sch)
{
PMCW *p = &sch->curr_status.pmcw;
SCSW *s = &sch->curr_status.scsw;
int path;
/* Path management: In our simple css, we always choose the only path. */
path = 0x80;
/* Reset values prior to 'issuing the clear signal'. */
p->lpum = 0;
p->pom = 0xff;
s->flags &= ~SCSW_FLAGS_MASK_PNO;
/* We always 'attempt to issue the clear signal', and we always succeed. */
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
s->ctrl &= ~SCSW_ACTL_CLEAR_PEND;
s->ctrl |= SCSW_STCTL_STATUS_PEND;
s->dstat = 0;
s->cstat = 0;
p->lpum = path;
}
static void sch_handle_halt_func(SubchDev *sch)
{
PMCW *p = &sch->curr_status.pmcw;
SCSW *s = &sch->curr_status.scsw;
hwaddr curr_ccw = sch->channel_prog;
int path;
/* Path management: In our simple css, we always choose the only path. */
path = 0x80;
/* We always 'attempt to issue the halt signal', and we always succeed. */
sch->channel_prog = 0x0;
sch->last_cmd_valid = false;
s->ctrl &= ~SCSW_ACTL_HALT_PEND;
s->ctrl |= SCSW_STCTL_STATUS_PEND;
if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
!((s->ctrl & SCSW_ACTL_START_PEND) ||
(s->ctrl & SCSW_ACTL_SUSP))) {
s->dstat = SCSW_DSTAT_DEVICE_END;
}
if ((s->ctrl & (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) ||
(s->ctrl & SCSW_ACTL_SUSP)) {
s->cpa = curr_ccw + 8;
}
s->cstat = 0;
p->lpum = path;
}
static void copy_sense_id_to_guest(SenseId *dest, SenseId *src)
{
int i;
dest->reserved = src->reserved;
dest->cu_type = cpu_to_be16(src->cu_type);
dest->cu_model = src->cu_model;
dest->dev_type = cpu_to_be16(src->dev_type);
dest->dev_model = src->dev_model;
dest->unused = src->unused;
for (i = 0; i < ARRAY_SIZE(dest->ciw); i++) {
dest->ciw[i].type = src->ciw[i].type;
dest->ciw[i].command = src->ciw[i].command;
dest->ciw[i].count = cpu_to_be16(src->ciw[i].count);
}
}
static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1)
{
CCW0 tmp0;
CCW1 tmp1;
CCW1 ret;
if (fmt1) {
cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1));
ret.cmd_code = tmp1.cmd_code;
ret.flags = tmp1.flags;
ret.count = be16_to_cpu(tmp1.count);
ret.cda = be32_to_cpu(tmp1.cda);
} else {
cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0));
if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) {
ret.cmd_code = CCW_CMD_TIC;
ret.flags = 0;
ret.count = 0;
} else {
ret.cmd_code = tmp0.cmd_code;
ret.flags = tmp0.flags;
ret.count = be16_to_cpu(tmp0.count);
}
ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16);
}
return ret;
}
/**
* If out of bounds marks the stream broken. If broken returns -EINVAL,
* otherwise the requested length (may be zero)
*/
static inline int cds_check_len(CcwDataStream *cds, int len)
{
if (cds->at_byte + len > cds->count) {
cds->flags |= CDS_F_STREAM_BROKEN;
}
return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len;
}
static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1)
{
return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24));
}
static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len,
CcwDataStreamOp op)
{
int ret;
ret = cds_check_len(cds, len);
if (ret <= 0) {
return ret;
}
if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) {
return -EINVAL; /* channel program check */
}
if (op == CDS_OP_A) {
goto incr;
}
ret = address_space_rw(&address_space_memory, cds->cda,
MEMTXATTRS_UNSPECIFIED, buff, len, op);
if (ret != MEMTX_OK) {
cds->flags |= CDS_F_STREAM_BROKEN;
return -EINVAL;
}
incr:
cds->at_byte += len;
cds->cda += len;
return 0;
}
/* returns values between 1 and bsz, where bsz is a power of 2 */
static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz)
{
return bsz - (cda & (bsz - 1));
}
static inline uint64_t ccw_ida_block_size(uint8_t flags)
{
if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) {
return 1ULL << 12;
}
return 1ULL << 11;
}
static inline int ida_read_next_idaw(CcwDataStream *cds)
{
union {uint64_t fmt2; uint32_t fmt1; } idaw;
int ret;
hwaddr idaw_addr;
bool idaw_fmt2 = cds->flags & CDS_F_C64;
bool ccw_fmt1 = cds->flags & CDS_F_FMT;
if (idaw_fmt2) {
idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw;
if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
return -EINVAL; /* channel program check */
}
ret = address_space_rw(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2,
sizeof(idaw.fmt2), false);
cds->cda = be64_to_cpu(idaw.fmt2);
} else {
idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw;
if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) {
return -EINVAL; /* channel program check */
}
ret = address_space_rw(&address_space_memory, idaw_addr,
MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1,
sizeof(idaw.fmt1), false);
cds->cda = be64_to_cpu(idaw.fmt1);
if (cds->cda & 0x80000000) {
return -EINVAL; /* channel program check */
}
}
++(cds->at_idaw);
if (ret != MEMTX_OK) {
/* assume inaccessible address */
return -EINVAL; /* channel program check */
}
return 0;
}
static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len,
CcwDataStreamOp op)
{
uint64_t bsz = ccw_ida_block_size(cds->flags);
int ret = 0;
uint16_t cont_left, iter_len;
ret = cds_check_len(cds, len);
if (ret <= 0) {
return ret;
}
if (!cds->at_idaw) {
/* read first idaw */
ret = ida_read_next_idaw(cds);
if (ret) {
goto err;
}
cont_left = ida_continuous_left(cds->cda, bsz);
} else {
cont_left = ida_continuous_left(cds->cda, bsz);
if (cont_left == bsz) {
ret = ida_read_next_idaw(cds);
if (ret) {
goto err;
}
if (cds->cda & (bsz - 1)) {
ret = -EINVAL; /* channel program check */
goto err;
}
}
}
do {
iter_len = MIN(len, cont_left);
if (op != CDS_OP_A) {
ret = address_space_rw(&address_space_memory, cds->cda,
MEMTXATTRS_UNSPECIFIED, buff, iter_len, op);
if (ret != MEMTX_OK) {
/* assume inaccessible address */
ret = -EINVAL; /* channel program check */
goto err;
}
}
cds->at_byte += iter_len;
cds->cda += iter_len;
len -= iter_len;
if (!len) {
break;
}
ret = ida_read_next_idaw(cds);
if (ret) {
goto err;
}
cont_left = bsz;
} while (true);
return ret;
err:
cds->flags |= CDS_F_STREAM_BROKEN;
return ret;
}
void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb)
{
/*
* We don't support MIDA (an optional facility) yet and we
* catch this earlier. Just for expressing the precondition.
*/
g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW));
cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) |
(orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) |
(orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) |
(ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0);
cds->count = ccw->count;
cds->cda_orig = ccw->cda;
ccw_dstream_rewind(cds);
if (!(cds->flags & CDS_F_IDA)) {
cds->op_handler = ccw_dstream_rw_noflags;
} else {
cds->op_handler = ccw_dstream_rw_ida;
}
}
static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr,
bool suspend_allowed)
{
int ret;
bool check_len;
int len;
CCW1 ccw;
if (!ccw_addr) {
return -EINVAL; /* channel-program check */
}
/* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */
if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) {
return -EINVAL;
}
/* Translate everything to format-1 ccws - the information is the same. */
ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1);
/* Check for invalid command codes. */
if ((ccw.cmd_code & 0x0f) == 0) {
return -EINVAL;
}
if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) &&
((ccw.cmd_code & 0xf0) != 0)) {
return -EINVAL;
}
if (!sch->ccw_fmt_1 && (ccw.count == 0) &&
(ccw.cmd_code != CCW_CMD_TIC)) {
return -EINVAL;
}
/* We don't support MIDA. */
if (ccw.flags & CCW_FLAG_MIDA) {