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cpqfcTScontrol.c
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/* Copyright 2000, Compaq Computer Corporation
* Fibre Channel Host Bus Adapter
* 64-bit, 66MHz PCI
* Originally developed and tested on:
* (front): [chip] Tachyon TS HPFC-5166A/1.2 L2C1090 ...
* SP# P225CXCBFIEL6T, Rev XC
* SP# 161290-001, Rev XD
* (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* Written by Don Zimmerman
*/
/* These functions control the host bus adapter (HBA) hardware. The main chip
control takes place in the interrupt handler where we process the IMQ
(Inbound Message Queue). The IMQ is Tachyon's way of communicating FC link
events and state information to the driver. The Single Frame Queue (SFQ)
buffers incoming FC frames for processing by the driver. References to
"TL/TS UG" are for:
"HP HPFC-5100/5166 Tachyon TL/TS ICs User Guide", August 16, 1999, 1st Ed.
Hewlitt Packard Manual Part Number 5968-1083E.
*/
#define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
#include <linux/blkdev.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/ioport.h> // request_region() prototype
#include <linux/sched.h>
#include <linux/slab.h> // need "kfree" for ext. S/G pages
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/unistd.h>
#include <asm/io.h> // struct pt_regs for IRQ handler & Port I/O
#include <asm/irq.h>
#include <linux/spinlock.h>
#include "scsi.h"
#include <scsi/scsi_host.h> // Scsi_Host definition for INT handler
#include "cpqfcTSchip.h"
#include "cpqfcTSstructs.h"
//#define IMQ_DEBUG 1
static void fcParseLinkStatusCounters(TACHYON * fcChip);
static void CpqTsGetSFQEntry(TACHYON * fcChip,
USHORT pi, ULONG * buffr, BOOLEAN UpdateChip);
static void
cpqfc_free_dma_consistent(CPQFCHBA *cpqfcHBAdata)
{
// free up the primary EXCHANGES struct and Link Q
PTACHYON fcChip = &cpqfcHBAdata->fcChip;
if (fcChip->Exchanges != NULL)
pci_free_consistent(cpqfcHBAdata->PciDev, sizeof(FC_EXCHANGES),
fcChip->Exchanges, fcChip->exch_dma_handle);
fcChip->Exchanges = NULL;
if (cpqfcHBAdata->fcLQ != NULL)
pci_free_consistent(cpqfcHBAdata->PciDev, sizeof(FC_LINK_QUE),
cpqfcHBAdata->fcLQ, cpqfcHBAdata->fcLQ_dma_handle);
cpqfcHBAdata->fcLQ = NULL;
}
// Note special requirements for Q alignment! (TL/TS UG pg. 190)
// We place critical index pointers at end of QUE elements to assist
// in non-symbolic (i.e. memory dump) debugging
// opcode defines placement of Queues (e.g. local/external RAM)
int CpqTsCreateTachLiteQues( void* pHBA, int opcode)
{
CPQFCHBA *cpqfcHBAdata = (CPQFCHBA*)pHBA;
PTACHYON fcChip = &cpqfcHBAdata->fcChip;
int iStatus=0;
unsigned long ulAddr;
dma_addr_t ERQdma, IMQdma, SPQdma, SESTdma;
int i;
// NOTE! fcMemManager() will return system virtual addresses.
// System (kernel) virtual addresses, though non-paged, still
// aren't physical addresses. Convert to PHYSICAL_ADDRESS for Tachyon's
// DMA use.
ENTER("CreateTachLiteQues");
// Allocate primary EXCHANGES array...
fcChip->Exchanges = NULL;
cpqfcHBAdata->fcLQ = NULL;
/* printk("Allocating %u for %u Exchanges ",
(ULONG)sizeof(FC_EXCHANGES), TACH_MAX_XID); */
fcChip->Exchanges = pci_alloc_consistent(cpqfcHBAdata->PciDev,
sizeof(FC_EXCHANGES), &fcChip->exch_dma_handle);
/* printk("@ %p\n", fcChip->Exchanges); */
if( fcChip->Exchanges == NULL ) // fatal error!!
{
printk("pci_alloc_consistent failure on Exchanges: fatal error\n");
return -1;
}
// zero out the entire EXCHANGE space
memset( fcChip->Exchanges, 0, sizeof( FC_EXCHANGES));
/* printk("Allocating %u for LinkQ ", (ULONG)sizeof(FC_LINK_QUE)); */
cpqfcHBAdata->fcLQ = pci_alloc_consistent(cpqfcHBAdata->PciDev,
sizeof( FC_LINK_QUE), &cpqfcHBAdata->fcLQ_dma_handle);
/* printk("@ %p (%u elements)\n", cpqfcHBAdata->fcLQ, FC_LINKQ_DEPTH); */
if( cpqfcHBAdata->fcLQ == NULL ) // fatal error!!
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk("pci_alloc_consistent() failure on fc Link Que: fatal error\n");
return -1;
}
// zero out the entire EXCHANGE space
memset( cpqfcHBAdata->fcLQ, 0, sizeof( FC_LINK_QUE));
// Verify that basic Tach I/O registers are not NULL
if( !fcChip->Registers.ReMapMemBase )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk("HBA base address NULL: fatal error\n");
return -1;
}
// Initialize the fcMemManager memory pairs (stores allocated/aligned
// pairs for future freeing)
memset( cpqfcHBAdata->dynamic_mem, 0, sizeof(cpqfcHBAdata->dynamic_mem));
// Allocate Tach's Exchange Request Queue (each ERQ entry 32 bytes)
fcChip->ERQ = fcMemManager( cpqfcHBAdata->PciDev,
&cpqfcHBAdata->dynamic_mem[0],
sizeof( TachLiteERQ ), 32*(ERQ_LEN), 0L, &ERQdma);
if( !fcChip->ERQ )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk("pci_alloc_consistent/alignment failure on ERQ: fatal error\n");
return -1;
}
fcChip->ERQ->length = ERQ_LEN-1;
ulAddr = (ULONG) ERQdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! ERQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
}
#endif
fcChip->ERQ->base = (ULONG)ulAddr; // copy for quick reference
// Allocate Tach's Inbound Message Queue (32 bytes per entry)
fcChip->IMQ = fcMemManager( cpqfcHBAdata->PciDev,
&cpqfcHBAdata->dynamic_mem[0],
sizeof( TachyonIMQ ), 32*(IMQ_LEN), 0L, &IMQdma );
if( !fcChip->IMQ )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk("pci_alloc_consistent/alignment failure on IMQ: fatal error\n");
return -1;
}
fcChip->IMQ->length = IMQ_LEN-1;
ulAddr = IMQdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! IMQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
}
#endif
fcChip->IMQ->base = (ULONG)ulAddr; // copy for quick reference
// Allocate Tach's Single Frame Queue (64 bytes per entry)
fcChip->SFQ = fcMemManager( cpqfcHBAdata->PciDev,
&cpqfcHBAdata->dynamic_mem[0],
sizeof( TachLiteSFQ ), 64*(SFQ_LEN),0L, &SPQdma );
if( !fcChip->SFQ )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk("pci_alloc_consistent/alignment failure on SFQ: fatal error\n");
return -1;
}
fcChip->SFQ->length = SFQ_LEN-1; // i.e. Que length [# entries -
// min. 32; max. 4096 (0xffff)]
ulAddr = SPQdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! SFQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
}
#endif
fcChip->SFQ->base = (ULONG)ulAddr; // copy for quick reference
// Allocate SCSI Exchange State Table; aligned nearest @sizeof
// power-of-2 boundary
// LIVE DANGEROUSLY! Assume the boundary for SEST mem will
// be on physical page (e.g. 4k) boundary.
/* printk("Allocating %u for TachSEST for %u Exchanges\n",
(ULONG)sizeof(TachSEST), TACH_SEST_LEN); */
fcChip->SEST = fcMemManager( cpqfcHBAdata->PciDev,
&cpqfcHBAdata->dynamic_mem[0],
sizeof(TachSEST), 4, 0L, &SESTdma );
// sizeof(TachSEST), 64*TACH_SEST_LEN, 0L );
if( !fcChip->SEST )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk("pci_alloc_consistent/alignment failure on SEST: fatal error\n");
return -1;
}
for( i=0; i < TACH_SEST_LEN; i++) // for each exchange
fcChip->SEST->sgPages[i] = NULL;
fcChip->SEST->length = TACH_SEST_LEN; // e.g. DON'T subtract one
// (TL/TS UG, pg 153)
ulAddr = SESTdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! SFQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
}
#endif
fcChip->SEST->base = (ULONG)ulAddr; // copy for quick reference
// Now that structures are defined,
// fill in Tachyon chip registers...
// EEEEEEEE EXCHANGE REQUEST QUEUE
writel( fcChip->ERQ->base,
(fcChip->Registers.ReMapMemBase + TL_MEM_ERQ_BASE));
writel( fcChip->ERQ->length,
(fcChip->Registers.ReMapMemBase + TL_MEM_ERQ_LENGTH));
fcChip->ERQ->producerIndex = 0L;
writel( fcChip->ERQ->producerIndex,
(fcChip->Registers.ReMapMemBase + TL_MEM_ERQ_PRODUCER_INDEX));
// NOTE! write consumer index last, since the write
// causes Tachyon to process the other registers
ulAddr = ((unsigned long)&fcChip->ERQ->consumerIndex -
(unsigned long)fcChip->ERQ) + (unsigned long) ERQdma;
// NOTE! Tachyon DMAs to the ERQ consumer Index host
// address; must be correctly aligned
writel( (ULONG)ulAddr,
(fcChip->Registers.ReMapMemBase + TL_MEM_ERQ_CONSUMER_INDEX_ADR));
// IIIIIIIIIIIII INBOUND MESSAGE QUEUE
// Tell Tachyon where the Que starts
// set the Host's pointer for Tachyon to access
/* printk(" cpqfcTS: writing IMQ BASE %Xh ", fcChip->IMQ->base ); */
writel( fcChip->IMQ->base,
(fcChip->Registers.ReMapMemBase + IMQ_BASE));
writel( fcChip->IMQ->length,
(fcChip->Registers.ReMapMemBase + IMQ_LENGTH));
writel( fcChip->IMQ->consumerIndex,
(fcChip->Registers.ReMapMemBase + IMQ_CONSUMER_INDEX));
// NOTE: TachLite DMAs to the producerIndex host address
// must be correctly aligned with address bits 1-0 cleared
// Writing the BASE register clears the PI register, so write it last
ulAddr = ((unsigned long)&fcChip->IMQ->producerIndex -
(unsigned long)fcChip->IMQ) + (unsigned long) IMQdma;
#if BITS_PER_LONG > 32
if( (ulAddr >> 32) )
{
cpqfc_free_dma_consistent(cpqfcHBAdata);
printk(" FATAL! IMQ ptr %p exceeds Tachyon's 32-bit register size\n",
(void*)ulAddr);
return -1; // failed
}
#endif
#if DBG
printk(" PI %Xh\n", (ULONG)ulAddr );
#endif
writel( (ULONG)ulAddr,
(fcChip->Registers.ReMapMemBase + IMQ_PRODUCER_INDEX));
// SSSSSSSSSSSSSSS SINGLE FRAME SEQUENCE
// Tell TachLite where the Que starts
writel( fcChip->SFQ->base,
(fcChip->Registers.ReMapMemBase + TL_MEM_SFQ_BASE));
writel( fcChip->SFQ->length,
(fcChip->Registers.ReMapMemBase + TL_MEM_SFQ_LENGTH));
// tell TachLite where SEST table is & how long
writel( fcChip->SEST->base,
(fcChip->Registers.ReMapMemBase + TL_MEM_SEST_BASE));
/* printk(" cpqfcTS: SEST %p(virt): Wrote base %Xh @ %p\n",
fcChip->SEST, fcChip->SEST->base,
fcChip->Registers.ReMapMemBase + TL_MEM_SEST_BASE); */
writel( fcChip->SEST->length,
(fcChip->Registers.ReMapMemBase + TL_MEM_SEST_LENGTH));
writel( (TL_EXT_SG_PAGE_COUNT-1),
(fcChip->Registers.ReMapMemBase + TL_MEM_SEST_SG_PAGE));
LEAVE("CreateTachLiteQues");
return iStatus;
}
// function to return TachLite to Power On state
// 1st - reset tachyon ('SOFT' reset)
// others - future
int CpqTsResetTachLite(void *pHBA, int type)
{
CPQFCHBA *cpqfcHBAdata = (CPQFCHBA*)pHBA;
PTACHYON fcChip = &cpqfcHBAdata->fcChip;
ULONG ulBuff, i;
int ret_status=0; // def. success
ENTER("ResetTach");
switch(type)
{
case CLEAR_FCPORTS:
// in case he was running previously, mask Tach's interrupt
writeb( 0, (fcChip->Registers.ReMapMemBase + IINTEN));
// de-allocate mem for any Logged in ports
// (e.g., our module is unloading)
// search the forward linked list, de-allocating
// the memory we allocated when the port was initially logged in
{
PFC_LOGGEDIN_PORT pLoggedInPort = fcChip->fcPorts.pNextPort;
PFC_LOGGEDIN_PORT ptr;
// printk("checking for allocated LoggedInPorts...\n");
while( pLoggedInPort )
{
ptr = pLoggedInPort;
pLoggedInPort = ptr->pNextPort;
// printk("kfree(%p) on FC LoggedInPort port_id 0x%06lX\n",
// ptr, ptr->port_id);
kfree( ptr );
}
}
// (continue resetting hardware...)
case 1: // RESTART Tachyon (power-up state)
// in case he was running previously, mask Tach's interrupt
writeb( 0, (fcChip->Registers.ReMapMemBase + IINTEN));
// turn OFF laser (NOTE: laser is turned
// off during reset, because GPIO4 is cleared
// to 0 by reset action - see TLUM, sec 7.22)
// However, CPQ 64-bit HBAs have a "health
// circuit" which keeps laser ON for a brief
// period after it is turned off ( < 1s)
fcChip->LaserControl( fcChip->Registers.ReMapMemBase, 0);
// soft reset timing constraints require:
// 1. set RST to 1
// 2. read SOFTRST register
// (128 times per R. Callison code)
// 3. clear PCI ints
// 4. clear RST to 0
writel( 0xff000001L,
(fcChip->Registers.ReMapMemBase + TL_MEM_SOFTRST));
for( i=0; i<128; i++)
ulBuff = readl( fcChip->Registers.ReMapMemBase + TL_MEM_SOFTRST);
// clear the soft reset
for( i=0; i<8; i++)
writel( 0, (fcChip->Registers.ReMapMemBase + TL_MEM_SOFTRST));
// clear out our copy of Tach regs,
// because they must be invalid now,
// since TachLite reset all his regs.
CpqTsDestroyTachLiteQues(cpqfcHBAdata,0); // remove Host-based Que structs
cpqfcTSClearLinkStatusCounters(fcChip); // clear our s/w accumulators
// lower bits give GBIC info
fcChip->Registers.TYstatus.value =
readl( fcChip->Registers.TYstatus.address );
break;
/*
case 2: // freeze SCSI
case 3: // reset Outbound command que (ERQ)
case 4: // unfreeze OSM (Outbound Seq. Man.) 'er'
case 5: // report status
break;
*/
default:
ret_status = -1; // invalid option passed to RESET function
break;
}
LEAVE("ResetTach");
return ret_status;
}
// 'addrBase' is IOBaseU for both TachLite and (older) Tachyon
int CpqTsLaserControl( void* addrBase, int opcode )
{
ULONG dwBuff;
dwBuff = readl((addrBase + TL_MEM_TACH_CONTROL) ); // read TL Control reg
// (change only bit 4)
if( opcode == 1)
dwBuff |= ~0xffffffefL; // set - ON
else
dwBuff &= 0xffffffefL; // clear - OFF
writel( dwBuff, (addrBase + TL_MEM_TACH_CONTROL)); // write TL Control reg
return 0;
}
// Use controller's "Options" field to determine loopback mode (if any)
// internal loopback (silicon - no GBIC)
// external loopback (GBIC - no FC loop)
// no loopback: L_PORT, external cable from GBIC required
int CpqTsInitializeFrameManager( void *pChip, int opcode)
{
PTACHYON fcChip;
int iStatus;
ULONG wwnLo, wwnHi; // for readback verification
ENTER("InitializeFrameManager");
fcChip = (PTACHYON)pChip;
if( !fcChip->Registers.ReMapMemBase ) // undefined controller?
return -1;
// TL/TS UG, pg. 184
// 0x0065 = 100ms for RT_TOV
// 0x01f5 = 500ms for ED_TOV
// 0x07D1 = 2000ms
fcChip->Registers.ed_tov.value = 0x006507D1;
writel( fcChip->Registers.ed_tov.value,
(fcChip->Registers.ed_tov.address));
// Set LP_TOV to the FC-AL2 specified 2 secs.
// TL/TS UG, pg. 185
writel( 0x07d00010, fcChip->Registers.ReMapMemBase +TL_MEM_FM_TIMEOUT2);
// Now try to read the WWN from the adapter's NVRAM
iStatus = CpqTsReadWriteWWN( fcChip, 1); // '1' for READ
if( iStatus ) // NVRAM read failed?
{
printk(" WARNING! HBA NVRAM WWN read failed - make alias\n");
// make up a WWN. If NULL or duplicated on loop, FC loop may hang!
fcChip->Registers.wwn_hi = (__u32)jiffies;
fcChip->Registers.wwn_hi |= 0x50000000L;
fcChip->Registers.wwn_lo = 0x44556677L;
}
writel( fcChip->Registers.wwn_hi,
fcChip->Registers.ReMapMemBase + TL_MEM_FM_WWN_HI);
writel( fcChip->Registers.wwn_lo,
fcChip->Registers.ReMapMemBase + TL_MEM_FM_WWN_LO);
// readback for verification:
wwnHi = readl( fcChip->Registers.ReMapMemBase + TL_MEM_FM_WWN_HI );
wwnLo = readl( fcChip->Registers.ReMapMemBase + TL_MEM_FM_WWN_LO);
// test for correct chip register WRITE/READ
DEBUG_PCI( printk(" WWN %08X%08X\n",
fcChip->Registers.wwn_hi, fcChip->Registers.wwn_lo ) );
if( wwnHi != fcChip->Registers.wwn_hi ||
wwnLo != fcChip->Registers.wwn_lo )
{
printk( "cpqfcTS: WorldWideName register load failed\n");
return -1; // FAILED!
}
// set Frame Manager Initialize command
fcChip->Registers.FMcontrol.value = 0x06;
// Note: for test/debug purposes, we may use "Hard" address,
// but we completely support "soft" addressing, including
// dynamically changing our address.
if( fcChip->Options.intLoopback == 1 ) // internal loopback
fcChip->Registers.FMconfig.value = 0x0f002080L;
else if( fcChip->Options.extLoopback == 1 ) // internal loopback
fcChip->Registers.FMconfig.value = 0x0f004080L;
else // L_Port
fcChip->Registers.FMconfig.value = 0x55000100L; // hard address (55h start)
// fcChip->Registers.FMconfig.value = 0x01000080L; // soft address (can't pick)
// fcChip->Registers.FMconfig.value = 0x55000100L; // hard address (55h start)
// write config to FM
if( !fcChip->Options.intLoopback && !fcChip->Options.extLoopback )
// (also need LASER for real LOOP)
fcChip->LaserControl( fcChip->Registers.ReMapMemBase, 1); // turn on LASER
writel( fcChip->Registers.FMconfig.value,
fcChip->Registers.FMconfig.address);
// issue INITIALIZE command to FM - ACTION!
writel( fcChip->Registers.FMcontrol.value,
fcChip->Registers.FMcontrol.address);
LEAVE("InitializeFrameManager");
return 0;
}
// This "look ahead" function examines the IMQ for occurrence of
// "type". Returns 1 if found, 0 if not.
static int PeekIMQEntry( PTACHYON fcChip, ULONG type)
{
ULONG CI = fcChip->IMQ->consumerIndex;
ULONG PI = fcChip->IMQ->producerIndex; // snapshot of IMQ indexes
while( CI != PI )
{ // proceed with search
if( (++CI) >= IMQ_LEN ) CI = 0; // rollover check
switch( type )
{
case ELS_LILP_FRAME:
{
// first, we need to find an Inbound Completion message,
// If we find it, check the incoming frame payload (1st word)
// for LILP frame
if( (fcChip->IMQ->QEntry[CI].type & 0x1FF) == 0x104 )
{
TachFCHDR_GCMND* fchs;
#error This is too much stack
ULONG ulFibreFrame[2048/4]; // max DWORDS in incoming FC Frame
USHORT SFQpi = (USHORT)(fcChip->IMQ->QEntry[CI].word[0] & 0x0fffL);
CpqTsGetSFQEntry( fcChip,
SFQpi, // SFQ producer ndx
ulFibreFrame, // contiguous dest. buffer
FALSE); // DON'T update chip--this is a "lookahead"
fchs = (TachFCHDR_GCMND*)&ulFibreFrame;
if( fchs->pl[0] == ELS_LILP_FRAME)
{
return 1; // found the LILP frame!
}
else
{
// keep looking...
}
}
}
break;
case OUTBOUND_COMPLETION:
if( (fcChip->IMQ->QEntry[CI].type & 0x1FF) == 0x00 )
{
// any OCM errors?
if( fcChip->IMQ->QEntry[CI].word[2] & 0x7a000000L )
return 1; // found OCM error
}
break;
default:
break;
}
}
return 0; // failed to find "type"
}
static void SetTachTOV( CPQFCHBA* cpqfcHBAdata)
{
PTACHYON fcChip = &cpqfcHBAdata->fcChip;
// TL/TS UG, pg. 184
// 0x0065 = 100ms for RT_TOV
// 0x01f5 = 500ms for ED_TOV
// 0x07d1 = 2000ms for ED_TOV
// SANMark Level 1 requires an "initialization backoff"
// (See "SANMark Test Suite Level 1":
// initialization_timeout.fcal.SANMark-1.fc)
// We have to use 2sec, 24sec, then 128sec when login/
// port discovery processes fail to complete.
// when port discovery completes (logins done), we set
// ED_TOV to 500ms -- this is the normal operational case
// On the first Link Down, we'll move to 2 secs (7D1 ms)
if( (fcChip->Registers.ed_tov.value &0xFFFF) <= 0x1f5)
fcChip->Registers.ed_tov.value = 0x006507D1;
// If we get another LST after we moved TOV to 2 sec,
// increase to 24 seconds (5DC1 ms) per SANMark!
else if( (fcChip->Registers.ed_tov.value &0xFFFF) <= 0x7D1)
fcChip->Registers.ed_tov.value = 0x00655DC1;
// If we get still another LST, set the max TOV (Tachyon
// has only 16 bits for ms timer, so the max is 65.5 sec)
else if( (fcChip->Registers.ed_tov.value &0xFFFF) <= 0x5DC1)
fcChip->Registers.ed_tov.value = 0x0065FFFF;
writel( fcChip->Registers.ed_tov.value,
(fcChip->Registers.ed_tov.address));
// keep the same 2sec LP_TOV
writel( 0x07D00010, fcChip->Registers.ReMapMemBase +TL_MEM_FM_TIMEOUT2);
}
// The IMQ is an array with IMQ_LEN length, each element (QEntry)
// with eight 32-bit words. Tachyon PRODUCES a QEntry with each
// message it wants to send to the host. The host CONSUMES IMQ entries
// This function copies the current
// (or oldest not-yet-processed) QEntry to
// the caller, clears/ re-enables the interrupt, and updates the
// (Host) Consumer Index.
// Return value:
// 0 message processed, none remain (producer and consumer
// indexes match)
// 1 message processed, more messages remain
// -1 no message processed - none were available to process
// Remarks:
// TL/TS UG specifices that the following actions for
// INTA_L handling:
// 1. read PCI Interrupt Status register (0xff)
// 2. all IMQ messages should be processed before writing the
// IMQ consumer index.
int CpqTsProcessIMQEntry(void *host)
{
struct Scsi_Host *HostAdapter = (struct Scsi_Host *)host;
CPQFCHBA *cpqfcHBAdata = (CPQFCHBA *)HostAdapter->hostdata;
PTACHYON fcChip = &cpqfcHBAdata->fcChip;
FC_EXCHANGES *Exchanges = fcChip->Exchanges;
int iStatus;
USHORT i, RPCset, DPCset;
ULONG x_ID;
ULONG ulBuff, dwStatus;
TachFCHDR_GCMND* fchs;
#error This is too much stack
ULONG ulFibreFrame[2048/4]; // max number of DWORDS in incoming Fibre Frame
UCHAR ucInboundMessageType; // Inbound CM, dword 3 "type" field
ENTER("ProcessIMQEntry");
// check TachLite's IMQ producer index -
// is a new message waiting for us?
// equal indexes means empty que
if( fcChip->IMQ->producerIndex != fcChip->IMQ->consumerIndex )
{ // need to process message
#ifdef IMQ_DEBUG
printk("PI %X, CI %X type: %X\n",
fcChip->IMQ->producerIndex,fcChip->IMQ->consumerIndex,
fcChip->IMQ->QEntry[fcChip->IMQ->consumerIndex].type);
#endif
// Examine Completion Messages in IMQ
// what CM_Type?
switch( (UCHAR)(fcChip->IMQ->QEntry[fcChip->IMQ->consumerIndex].type
& 0xffL) )
{
case OUTBOUND_COMPLETION:
// Remarks:
// x_IDs (OX_ID, RX_ID) are partitioned by SEST entries
// (starting at 0), and SFS entries (starting at
// SEST_LEN -- outside the SEST space).
// Psuedo code:
// x_ID (OX_ID or RX_ID) from message is Trans_ID or SEST index
// range check - x_ID
// if x_ID outside 'Transactions' length, error - exit
// if any OCM error, copy error status to Exchange slot
// if FCP ASSIST transaction (x_ID within SEST),
// call fcComplete (to App)
// ...
ulBuff = fcChip->IMQ->QEntry[fcChip->IMQ->consumerIndex].word[1];
x_ID = ulBuff & 0x7fffL; // lower 14 bits SEST_Index/Trans_ID
// Range check CM OX/RX_ID value...
if( x_ID < TACH_MAX_XID ) // don't go beyond array space
{
if( ulBuff & 0x20000000L ) // RPC -Response Phase Complete?
RPCset = 1; // (SEST transactions only)
else
RPCset = 0;
if( ulBuff & 0x40000000L ) // DPC -Data Phase Complete?
DPCset = 1; // (SEST transactions only)
else
DPCset = 0;
// set the status for this Outbound transaction's ID
dwStatus = 0L;
if( ulBuff & 0x10000000L ) // SPE? (SEST Programming Error)
dwStatus |= SESTPROG_ERR;
ulBuff = fcChip->IMQ->QEntry[fcChip->IMQ->consumerIndex].word[2];
if( ulBuff & 0x7a000000L ) // any other errs?
{
if( ulBuff & 0x40000000L )
dwStatus |= INV_ENTRY;
if( ulBuff & 0x20000000L )
dwStatus |= FRAME_TO; // FTO
if( ulBuff & 0x10000000L )
dwStatus |= HOSTPROG_ERR;
if( ulBuff & 0x08000000L )
dwStatus |= LINKFAIL_TX;
if( ulBuff & 0x02000000L )
dwStatus |= ABORTSEQ_NOTIFY; // ASN
}
if( dwStatus ) // any errors?
{
// set the Outbound Completion status
Exchanges->fcExchange[ x_ID ].status |= dwStatus;
// if this Outbound frame was for a SEST entry, automatically
// reque it in the case of LINKFAIL (it will restart on PDISC)
if( x_ID < TACH_SEST_LEN )
{
printk(" #OCM error %Xh x_ID %X# ",
dwStatus, x_ID);
Exchanges->fcExchange[x_ID].timeOut = 30000; // seconds default
// We Q ABTS for each exchange.
// NOTE: We can get FRAME_TO on bad alpa (device gone). Since
// bad alpa is reported before FRAME_TO, examine the status
// flags to see if the device is removed. If so, DON'T
// post an ABTS, since it will be terminated by the bad alpa
// message.
if( dwStatus & FRAME_TO ) // check for device removed...
{
if( !(Exchanges->fcExchange[x_ID].status & DEVICE_REMOVED) )
{
// presumes device is still there: send ABTS.
cpqfcTSPutLinkQue( cpqfcHBAdata, BLS_ABTS, &x_ID);
}
}
else // Abort all other errors
{
cpqfcTSPutLinkQue( cpqfcHBAdata, BLS_ABTS, &x_ID);
}
// if the HPE bit is set, we have to CLose the LOOP
// (see TL/TS UG, pg. 239)
if( dwStatus &= HOSTPROG_ERR )
// set CL bit (see TL/TS UG, pg. 172)
writel( 4, fcChip->Registers.FMcontrol.address);
}
}
// NOTE: we don't necessarily care about ALL completion messages...
// SCSI resp. complete OR
if( ((x_ID < TACH_SEST_LEN) && RPCset)||
(x_ID >= TACH_SEST_LEN) ) // non-SCSI command
{
// exchange done; complete to upper levels with status
// (if necessary) and free the exchange slot
if( x_ID >= TACH_SEST_LEN ) // Link Service Outbound frame?
// A Request or Reply has been sent
{ // signal waiting WorkerThread
up( cpqfcHBAdata->TYOBcomplete); // frame is OUT of Tach
// WorkerThread will complete Xchng
}
else // X_ID is for FCP assist (SEST)
{
// TBD (target mode)
// fcCompleteExchange( fcChip, x_ID); // TRE completed
}
}
}
else // ERROR CONDITION! bogus x_ID in completion message
{
printk(" ProcessIMQ (OBCM) x_id out of range %Xh\n", x_ID);
}
// Load the Frame Manager's error counters. We check them here
// because presumably the link is up and healthy enough for the
// counters to be meaningful (i.e., don't check them while loop
// is initializing).
fcChip->Registers.FMLinkStatus1.value = // get TL's counter
readl(fcChip->Registers.FMLinkStatus1.address);
fcChip->Registers.FMLinkStatus2.value = // get TL's counter
readl(fcChip->Registers.FMLinkStatus2.address);
fcParseLinkStatusCounters( fcChip); // load into 6 s/w accumulators
break;
case ERROR_IDLE_COMPLETION: // TachLite Error Idle...
// We usually get this when the link goes down during heavy traffic.
// For now, presume that if SEST Exchanges are open, we will
// get this as our cue to INVALIDATE all SEST entries
// (and we OWN all the SEST entries).
// See TL/TS UG, pg. 53
for( x_ID = 0; x_ID < TACH_SEST_LEN; x_ID++)
{
// Does this VALid SEST entry need to be invalidated for Abort?
fcChip->SEST->u[ x_ID].IWE.Hdr_Len &= 0x7FFFFFFF;
}
CpqTsUnFreezeTachlite( fcChip, 2); // unfreeze Tachyon, if Link OK
break;
case INBOUND_SFS_COMPLETION: //0x04
// NOTE! we must process this SFQ message to avoid SFQ filling
// up and stopping TachLite. Incoming commands are placed here,
// as well as 'unknown' frames (e.g. LIP loop position data)
// write this CM's producer index to global...
// TL/TS UG, pg 234:
// Type: 0 - reserved
// 1 - Unassisted FCP
// 2 - BAD FCP
// 3 - Unkown Frame
// 4-F reserved
fcChip->SFQ->producerIndex = (USHORT)
(fcChip->IMQ->QEntry[fcChip->IMQ->consumerIndex].word[0] & 0x0fffL);
ucInboundMessageType = 0; // default to useless frame
// we can only process two Types: 1, Unassisted FCP, and 3, Unknown
// Also, we aren't interested in processing frame fragments
// so don't Que anything with 'LKF' bit set
if( !(fcChip->IMQ->QEntry[fcChip->IMQ->consumerIndex].word[2]
& 0x40000000) ) // 'LKF' link failure bit clear?
{
ucInboundMessageType = (UCHAR) // ICM DWord3, "Type"
(fcChip->IMQ->QEntry[fcChip->IMQ->consumerIndex].word[2] & 0x0fL);
}
else
{
fcChip->fcStats.linkFailRX++;
// printk("LKF (link failure) bit set on inbound message\n");
}
// clears SFQ entry from Tachyon buffer; copies to contiguous ulBuff
CpqTsGetSFQEntry(
fcChip, // i.e. this Device Object
(USHORT)fcChip->SFQ->producerIndex, // SFQ producer ndx
ulFibreFrame, TRUE); // contiguous destination buffer, update chip
// analyze the incoming frame outside the INT handler...
// (i.e., Worker)
if( ucInboundMessageType == 1 )
{
fchs = (TachFCHDR_GCMND*)ulFibreFrame; // cast to examine IB frame
// don't fill up our Q with garbage - only accept FCP-CMND
// or XRDY frames
if( (fchs->d_id & 0xFF000000) == 0x06000000 ) // CMND
{
// someone sent us a SCSI command
// fcPutScsiQue( cpqfcHBAdata,
// SFQ_UNASSISTED_FCP, ulFibreFrame);
}
else if( ((fchs->d_id & 0xFF000000) == 0x07000000) || // RSP (status)
(fchs->d_id & 0xFF000000) == 0x05000000 ) // XRDY
{
ULONG x_ID;
// Unfortunately, ABTS requires a Freeze on the chip so
// we can modify the shared memory SEST. When frozen,
// any received Exchange frames cannot be processed by
// Tachyon, so they will be dumped in here. It is too
// complex to attempt the reconstruct these frames in
// the correct Exchange context, so we simply seek to
// find status or transfer ready frames, and cause the
// exchange to complete with errors before the timeout
// expires. We use a Linux Scsi Cmnd result code that
// causes immediate retry.
// Do we have an open exchange that matches this s_id
// and ox_id?
for( x_ID = 0; x_ID < TACH_SEST_LEN; x_ID++)
{
if( (fchs->s_id & 0xFFFFFF) ==
(Exchanges->fcExchange[x_ID].fchs.d_id & 0xFFFFFF)
&&
(fchs->ox_rx_id & 0xFFFF0000) ==
(Exchanges->fcExchange[x_ID].fchs.ox_rx_id & 0xFFFF0000) )
{
// printk(" #R/X frame x_ID %08X# ", fchs->ox_rx_id );
// simulate the anticipated error - since the
// SEST was frozen, frames were lost...
Exchanges->fcExchange[ x_ID ].status |= SFQ_FRAME;
// presumes device is still there: send ABTS.
cpqfcTSPutLinkQue( cpqfcHBAdata, BLS_ABTS, &x_ID);
break; // done