From b2932f495ce6a7c37a0d3897e96950e558ebeb25 Mon Sep 17 00:00:00 2001 From: Fabian Albert Date: Thu, 5 Dec 2019 21:11:54 +0100 Subject: [PATCH 1/5] removed newlines in verilog parse files --- tests/hdl_parser/hdl_parser_verilog.cpp | 970 ++++++++++++------------ 1 file changed, 485 insertions(+), 485 deletions(-) diff --git a/tests/hdl_parser/hdl_parser_verilog.cpp b/tests/hdl_parser/hdl_parser_verilog.cpp index 499fdc470dd..1bca284d0c2 100644 --- a/tests/hdl_parser/hdl_parser_verilog.cpp +++ b/tests/hdl_parser/hdl_parser_verilog.cpp @@ -54,30 +54,30 @@ TEST_F(hdl_parser_verilog_test, check_main_example) { TEST_START { - std::stringstream input("module top (\n" - " global_in,\n" - " global_out, \n" - " global_inout\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " input global_inout ;\n" - " wire net_0 ;\n" - " wire net_1 ;\n" - "INV gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (net_0 )\n" - " ) ;\n" - "AND2 gate_1 (\n" - " .\\I0 (global_in ),\n" - " .\\I1 (global_inout ),\n" - " .\\O (net_1 )\n" - " ) ;\n" - "AND3 gate_2 (\n" - " .\\I0 (net_0 ),\n" - " .\\I1 (net_1 ),\n" - " .\\O (global_out )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_in," + " global_out, " + " global_inout" + " ) ;" + " input global_in ;" + " output global_out ;" + " input global_inout ;" + " wire net_0 ;" + " wire net_1 ;" + "INV gate_0 (" + " .\\I (global_in )," + " .\\O (net_0 )" + " ) ;" + "AND2 gate_1 (" + " .\\I0 (global_in )," + " .\\I1 (global_inout )," + " .\\O (net_1 )" + " ) ;" + "AND3 gate_2 (" + " .\\I0 (net_0 )," + " .\\I1 (net_1 )," + " .\\O (global_out )" + " ) ;" "endmodule"); hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -145,7 +145,7 @@ TEST_F(hdl_parser_verilog_test, check_main_example) } /** - * The same test, as the main example, but use white spaces of different types (' ','\n','\t') in various locations (or remove some unnecessary ones) + * The same test, as the main example, but use white spaces of different types (' ','','\t') in various locations (or remove some unnecessary ones) * * Functions: parse */ @@ -154,26 +154,26 @@ TEST_F(hdl_parser_verilog_test, check_whitespace_chaos) { TEST_START { - std::stringstream input("module top (\n" - " global_in, \n" + std::stringstream input("module top (" + " global_in, " " global_out, " - "global_inout\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " input global_inout ;\n" - " wire net_0; wire net_1 ;\n" - "\n" - "INV gate_0 (\n" - " .\\I \t (global_in),\n" - " .\\O \n" - "(net_0)\n" - " ) ;\n" - "AND2 gate_1 (\n" - " .\\I0 (global_in ),\n" - ".\\I1 (global_inout ), .\\O (net_1 )\n" - " ) ;\n" - "AND3 gate_2 (.\\I0 ( net_0 ), .\\I1 (net_1 ),.\\O (global_out));\n" + "global_inout" + " ) ;" + " input global_in ;" + " output global_out ;" + " input global_inout ;" + " wire net_0; wire net_1 ;" + "" + "INV gate_0 (" + " .\\I \t (global_in)," + " .\\O " + "(net_0)" + " ) ;" + "AND2 gate_1 (" + " .\\I0 (global_in )," + ".\\I1 (global_inout ), .\\O (net_1 )" + " ) ;" + "AND3 gate_2 (.\\I0 ( net_0 ), .\\I1 (net_1 ),.\\O (global_out));" "endmodule"); hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -252,7 +252,7 @@ TEST_F(hdl_parser_verilog_test, check_comment_detection){ { // Testing all comment types with attributes std::stringstream input; - input << "/*here comes a module*/ module top (\n" + input << "/*here comes a module*/ module top ( \n" " global_in,\n" " global_out\n" " ) ;\n" @@ -277,7 +277,7 @@ TEST_F(hdl_parser_verilog_test, check_comment_detection){ " .\\I (global_in ),\n" " .\\O (global_out )\n" " ) ;\n" - "endmodule"; + "endmodule\n"; test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -332,24 +332,24 @@ TEST_F(hdl_parser_verilog_test, check_generic_map){ TEST_START { // Store an instance of all possible data types in one gate - std::stringstream input("module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - "INV #(\n" - ".key_integer(1234),\n" // no prefix => integer (stored in hex) - ".key_floating_point(1.234),\n" - ".key_string(\"test_string\"),\n" - ".key_bit_vector_hex('habc),\n" // All values are 'ABC' in hex - ".key_bit_vector_dec('d2748),\n" - ".key_bit_vector_oct('o5274),\n" - ".key_bit_vector_bin('b101010111100)) \n" - "gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (global_out )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + "INV #(" + ".key_integer(1234)," // no prefix => integer (stored in hex) + ".key_floating_point(1.234)," + ".key_string(\"test_string\")," + ".key_bit_vector_hex('habc)," // All values are 'ABC' in hex + ".key_bit_vector_dec('d2748)," + ".key_bit_vector_oct('o5274)," + ".key_bit_vector_bin('b101010111100)) " + "gate_0 (" + " .\\I (global_in )," + " .\\O (global_out )" + " ) ;" "endmodule"); test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -390,31 +390,31 @@ TEST_F(hdl_parser_verilog_test, check_vector_bounds){ TEST_START { // Use a net vector of size 3 - std::stringstream input("module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire [1:3] net_vec ;\n" - "AND3 gate_0 (\n" - " .\\I0 (net_vec[1] ),\n" - " .\\I1 (net_vec[2] ),\n" - " .\\I2 (net_vec[3] ),\n" - " .\\O (global_out )\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I (global_in ),\n" - " .\\O (net_vec[1] )\n" - ") ;\n" - "INV gate_2 (\n" - " .\\I (global_in ),\n" - " .\\O (net_vec[2] )\n" - ") ;\n" - "INV gate_3 (\n" - " .\\I (global_in ),\n" - " .\\O (net_vec[3] )\n" - ") ;\n" + std::stringstream input("module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + " wire [1:3] net_vec ;" + "AND3 gate_0 (" + " .\\I0 (net_vec[1] )," + " .\\I1 (net_vec[2] )," + " .\\I2 (net_vec[3] )," + " .\\O (global_out )" + " ) ;" + "INV gate_1 (" + " .\\I (global_in )," + " .\\O (net_vec[1] )" + ") ;" + "INV gate_2 (" + " .\\I (global_in )," + " .\\O (net_vec[2] )" + ") ;" + "INV gate_3 (" + " .\\I (global_in )," + " .\\O (net_vec[3] )" + ") ;" "endmodule"); test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -449,36 +449,36 @@ TEST_F(hdl_parser_verilog_test, check_vector_bounds){ } { // Declare multiple wire vectors in one line - std::stringstream input("module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire [0:1] net_vec_0, net_vec_1 ;\n" - "AND4 gate_0 (\n" - " .\\I0 (net_vec_0[0] ),\n" - " .\\I1 (net_vec_0[1] ),\n" - " .\\I2 (net_vec_1[0] ),\n" - " .\\I3 (net_vec_1[1] ),\n" - " .\\O (global_out )\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I (global_in ),\n" - " .\\O (net_vec_0[0] )\n" - ") ;\n" - "INV gate_2 (\n" - " .\\I (global_in ),\n" - " .\\O (net_vec_0[1] )\n" - ") ;\n" - "INV gate_3 (\n" - " .\\I (global_in ),\n" - " .\\O (net_vec_1[0] )\n" - ") ;\n" - "INV gate_4 (\n" - " .\\I (global_in ),\n" - " .\\O (net_vec_1[1] )\n" - ") ;\n" + std::stringstream input("module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + " wire [0:1] net_vec_0, net_vec_1 ;" + "AND4 gate_0 (" + " .\\I0 (net_vec_0[0] )," + " .\\I1 (net_vec_0[1] )," + " .\\I2 (net_vec_1[0] )," + " .\\I3 (net_vec_1[1] )," + " .\\O (global_out )" + " ) ;" + "INV gate_1 (" + " .\\I (global_in )," + " .\\O (net_vec_0[0] )" + ") ;" + "INV gate_2 (" + " .\\I (global_in )," + " .\\O (net_vec_0[1] )" + ") ;" + "INV gate_3 (" + " .\\I (global_in )," + " .\\O (net_vec_1[0] )" + ") ;" + "INV gate_4 (" + " .\\I (global_in )," + " .\\O (net_vec_1[1] )" + ") ;" "endmodule"); test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -527,29 +527,29 @@ TEST_F(hdl_parser_verilog_test, check_assign) * | * '---=| gate_2 |=------ */ - std::stringstream input("module top (\n" - " global_in,\n" - " global_out_0,\n" - " global_out_1\n" - " ) ;\n" - " input global_in ;\n" - " output global_out_0 ;\n" - " output global_out_1 ;\n" - " wire net_0;\n" - " wire net_1;\n" - " assign net_1 = net_0 ;\n" - "INV gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O ( net_0 )\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I ( net_0 ),\n" - " .\\O ( global_out_0 )\n" - " ) ;\n" - "INV gate_2 (\n" - " .\\I ( net_1 ),\n" - " .\\O ( global_out_1 )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_in," + " global_out_0," + " global_out_1" + " ) ;" + " input global_in ;" + " output global_out_0 ;" + " output global_out_1 ;" + " wire net_0;" + " wire net_1;" + " assign net_1 = net_0 ;" + "INV gate_0 (" + " .\\I (global_in )," + " .\\O ( net_0 )" + " ) ;" + "INV gate_1 (" + " .\\I ( net_0 )," + " .\\O ( global_out_0 )" + " ) ;" + "INV gate_2 (" + " .\\I ( net_1 )," + " .\\O ( global_out_1 )" + " ) ;" "endmodule"); test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -603,8 +603,8 @@ TEST_F(hdl_parser_verilog_test, check_assign) // 2^(dim) gates (with one pin) must be created to connect all assigned wires for (u64 i = 0; i < (1 << dim); i++){ - global_out_list_module << " global_out_" << i << ",\n"; - global_out_list << " output global_out_" << i << ";\n"; + global_out_list_module << " global_out_" << i << ","; + global_out_list << " output global_out_" << i << ";"; std::bitset<64> i_bs(i); @@ -613,26 +613,26 @@ TEST_F(hdl_parser_verilog_test, check_assign) brackets << "[" << (i_bs[j] ? "1":"0") << "]"; } - gate_list << "INV in_gate_"<< i <<" (\n" - " .\\I (global_in ),\n" - " .\\O ( net_slave_vector" << brackets.str() << ")\n" - " ) ;\n"; - gate_list << "INV out_gate_"<< i <<" (\n" - " .\\I (net_slave_vector" << brackets.str() << "),\n" - " .\\O ( global_out_" << i << ")\n" - " ) ;\n"; + gate_list << "INV in_gate_"<< i <<" (" + " .\\I (global_in )," + " .\\O ( net_slave_vector" << brackets.str() << ")" + " ) ;"; + gate_list << "INV out_gate_"<< i <<" (" + " .\\I (net_slave_vector" << brackets.str() << ")," + " .\\O ( global_out_" << i << ")" + " ) ;"; } std::stringstream input; - input << "module top (\n" - " global_in,\n" + input << "module top (" + " global_in," << global_out_list_module.str() - << " );\n" - " input global_in ;\n" + << " );" + " input global_in ;" << global_out_list.str() - << " wire " << dim_decl << " net_slave_vector;\n" - << " wire [0:"<< ((1 << dim)-1) <<"] net_master_vector;\n" - << " assign net_slave_vector = net_master_vector;\n" // <- !!! + << " wire " << dim_decl << " net_slave_vector;" + << " wire [0:"<< ((1 << dim)-1) <<"] net_master_vector;" + << " assign net_slave_vector = net_master_vector;" // <- !!! << gate_list.str() << "endmodule"; @@ -670,19 +670,19 @@ TEST_F(hdl_parser_verilog_test, check_assign) /*{ // NOTE: fails with map::at (l. 635) // Assign constants ('b0 and 'b1) - std::stringstream input("module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire [0:3] bit_vector ;\n" - " assign bit_vector = 4'hA ;\n" - "\n" - " INV test_gate (\n" - " .\\I (bit_vector[0] ),\n" - " .\\O (global_out )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + " wire [0:3] bit_vector ;" + " assign bit_vector = 4'hA ;" + "" + " INV test_gate (" + " .\\I (bit_vector[0] )," + " .\\O (global_out )" + " ) ;" "endmodule"); //test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -705,45 +705,45 @@ TEST_F(hdl_parser_verilog_test, check_assign) /*{ // NOTE: fails currently (bc for example .\I(0) (single_net) is interpreted as "I" => "0")(wrong escaped?) // Assign constants a set of wires (single AND vectors) to a vector - std::stringstream input("module top (\n" - " global_out_0,\n" - " global_out_1,\n" - " global_out_2\n" - " ) ;\n" - " output global_out_0 ;\n" - " output global_out_1 ;\n" - " output global_out_2 ;\n" - "\n" - " wire single_net ;\n" - " wire [0:2][0:2] 2_d_vector_0;\n" - " wire [0:2][0:1] 2_d_vector_1;\n" - " wire [0:15] big_vector;\n" - " wire [0:11] net_vector_master;\n" - " assign {single_net, big_vector[3], big_vector[0:1], 2_d_vector_0[0:1][0:1], 2_d_vector_1[1:0][0:1]} = net_vector_master;\n" - "\n" - "GATE_4^1_IN_1^0_OUT test_gate_0 (\n" - " .\\I(0) (single_net ),\n" - " .\\I(1) (big_vector[3] ),\n" - " .\\I(2) (big_vector[0] ),\n" - " .\\I(3) (big_vector[1] ),\n" - " .\\O (global_out_0 )\n" - " ) ;\n" - "\n" - "GATE_4^1_IN_1^0_OUT test_gate_1 (\n" - " .\\I(0) (2_d_vector_0[0][0] ),\n" - " .\\I(1) (2_d_vector_0[0][1] ),\n" - " .\\I(2) (2_d_vector_0[1][0] ),\n" - " .\\I(3) (2_d_vector_0[1][1] ),\n" - " .\\O (global_out_1 )\n" - " ) ;\n" - "// Not sure...\n" - "GATE_4^1_IN_1^0_OUT test_gate_2 (\n" - " .\\I(0) (2_d_vector_1[1][0] ),\n" - " .\\I(1) (2_d_vector_1[1][0] ),\n" - " .\\I(2) (2_d_vector_1[0][1] ),\n" - " .\\I(3) (2_d_vector_1[0][1] ),\n" - " .\\O (global_out_2 )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_out_0," + " global_out_1," + " global_out_2" + " ) ;" + " output global_out_0 ;" + " output global_out_1 ;" + " output global_out_2 ;" + "" + " wire single_net ;" + " wire [0:2][0:2] 2_d_vector_0;" + " wire [0:2][0:1] 2_d_vector_1;" + " wire [0:15] big_vector;" + " wire [0:11] net_vector_master;" + " assign {single_net, big_vector[3], big_vector[0:1], 2_d_vector_0[0:1][0:1], 2_d_vector_1[1:0][0:1]} = net_vector_master;" + "" + "GATE_4^1_IN_1^0_OUT test_gate_0 (" + " .\\I(0) (single_net )," + " .\\I(1) (big_vector[3] )," + " .\\I(2) (big_vector[0] )," + " .\\I(3) (big_vector[1] )," + " .\\O (global_out_0 )" + " ) ;" + "" + "GATE_4^1_IN_1^0_OUT test_gate_1 (" + " .\\I(0) (2_d_vector_0[0][0] )," + " .\\I(1) (2_d_vector_0[0][1] )," + " .\\I(2) (2_d_vector_0[1][0] )," + " .\\I(3) (2_d_vector_0[1][1] )," + " .\\O (global_out_1 )" + " ) ;" + "// Not sure..." + "GATE_4^1_IN_1^0_OUT test_gate_2 (" + " .\\I(0) (2_d_vector_1[1][0] )," + " .\\I(1) (2_d_vector_1[1][0] )," + " .\\I(2) (2_d_vector_1[0][1] )," + " .\\I(3) (2_d_vector_1[0][1] )," + " .\\O (global_out_2 )" + " ) ;" "endmodule"); //test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -763,22 +763,22 @@ TEST_F(hdl_parser_verilog_test, check_assign) }*/ { // NOTE: stoi failure (l.978) - // Testing assignments, where escaped identifiers are used (e.g. \net[1:3][2:3] stands for a net, literally named "net[1:3][2:3]") - - std::stringstream input("module top (\n" - " global_out\n" - ") ;\n" - " output global_out ;\n" - " wire \\escaped_net_range[0:3] ;\n" - " wire [0:3] escaped_net_range ;\n" - " wire \\escaped_net[0] ;\n" - " wire [0:1] net_vector_master ;\n" - " assign { \\escaped_net_range[0:3] , \\escaped_net[0] } = net_vector_master;\n" - " AND2 test_gate (\n" - " .\\I0 ( \\escaped_net_range[0:3] ),\n" - " .\\I1 ( \\escaped_net[0] ),\n" - " .\\O (global_out )\n" - " ) ;\n" + // Testing assignments, where escaped identifiers are used (e.g. et[1:3][2:3] stands for a net, literally named "net[1:3][2:3]") + + std::stringstream input("module top (" + " global_out" + ") ;" + " output global_out ;" + " wire \\escaped_net_range[0:3] ;" + " wire [0:3] escaped_net_range ;" + " wire \\escaped_net[0] ;" + " wire [0:1] net_vector_master ;" + " assign { \\escaped_net_range[0:3] , \\escaped_net[0] } = net_vector_master;" + " AND2 test_gate (" + " .\\I0 ( \\escaped_net_range[0:3] )," + " .\\I1 ( \\escaped_net[0] )," + " .\\O (global_out )" + " ) ;" "endmodule"); hdl_parser_verilog verilog_parser(input); @@ -802,13 +802,13 @@ TEST_F(hdl_parser_verilog_test, check_global_gnd_vcc_gates) TEST_START { // Testing the usage of a global VCC gate (gate type 'VCC' is global VCC gate in our test gate library) - std::stringstream input("module top (\n" - " global_out\n" - " ) ;\n" - " output global_out ;\n" - "VCC gate_0 (\n" - " .\\O (global_out )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_out" + " ) ;" + " output global_out ;" + "VCC gate_0 (" + " .\\O (global_out )" + " ) ;" "endmodule"); test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -831,13 +831,13 @@ TEST_F(hdl_parser_verilog_test, check_global_gnd_vcc_gates) } { // Testing the usage of a global GND gate (gate type 'GND' is global GND gate in our test gate library) - std::stringstream input("module top (\n" - " global_out\n" - " ) ;\n" - " output global_out ;\n" - "GND gate_0 (\n" - " .\\O (global_out )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_out" + " ) ;" + " output global_out ;" + "GND gate_0 (" + " .\\O (global_out )" + " ) ;" "endmodule"); test_def::capture_stdout(); hdl_parser_verilog verilog_parser(input); @@ -882,43 +882,43 @@ TEST_F(hdl_parser_verilog_test, check_multiple_entities) * '---------------------------------------------' */ // NOTE: Data propagation? - std::stringstream input("module ENT_CHILD (\n" - " child_in,\n" - " child_out\n" - " ) ;\n" - " input child_in ;\n" - " output child_out ;\n" - " wire net_0_child ;\n" - "INV gate_0_child (\n" - " .\\I (child_in ),\n" - " .\\O (net_0_child )\n" - " ) ;\n" - "INV gate_1_child (\n" - " .\\I (net_0_child ),\n" - " .\\O (child_out )\n" - " ) ;\n" - "endmodule\n" + std::stringstream input("module ENT_CHILD (" + " child_in," + " child_out" + " ) ;" + " input child_in ;" + " output child_out ;" + " wire net_0_child ;" + "INV gate_0_child (" + " .\\I (child_in )," + " .\\O (net_0_child )" + " ) ;" + "INV gate_1_child (" + " .\\I (net_0_child )," + " .\\O (child_out )" + " ) ;" + "endmodule" "\n" - "module ENT_TO (\n" - " net_global_in,\n" - " net_global_out\n" - " ) ;\n" - " input net_global_in ;\n" - " output net_global_out ;\n" - " wire net_0 ;\n" - " wire net_1 ;\n" - "INV gate_0 (\n" - " .\\I (net_global_in ),\n" - " .\\O (net_0 )\n" - " ) ;\n" - "ENT_CHILD child_mod (\n" - " .\\child_in (net_0 ),\n" - " .\\child_out (net_1 )\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I (net_1 ), \n" - " .\\O (net_global_out )\n" - " ) ;\n" + "module ENT_TO (" + " net_global_in," + " net_global_out" + " ) ;" + " input net_global_in ;" + " output net_global_out ;" + " wire net_0 ;" + " wire net_1 ;" + "INV gate_0 (" + " .\\I (net_global_in )," + " .\\O (net_0 )" + " ) ;" + "ENT_CHILD child_mod (" + " .\\child_in (net_0 )," + " .\\child_out (net_1 )" + " ) ;" + "INV gate_1 (" + " .\\I (net_1 ), " + " .\\O (net_global_out )" + " ) ;" "endmodule"); hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -983,62 +983,62 @@ TEST_F(hdl_parser_verilog_test, check_multiple_entities) // Testing the correct build of the module hierarchy. Moreover the correct substitution of gate and net names, // which would be added twice (because an entity can be used multiple times) is tested as well. - std::stringstream input("module ENT_CHILD_TWO (\n" - " I_c2,\n" - " O_c2\n" - " ) ;\n" - " input I_c2 ;\n" - " output O_c2 ;\n" - "INV gate_child_two (\n" - " .\\I (I_c2 ),\n" - " .\\O (O_c2 )\n" - " ) ;\n" - "endmodule\n" + std::stringstream input("module ENT_CHILD_TWO (" + " I_c2," + " O_c2" + " ) ;" + " input I_c2 ;" + " output O_c2 ;" + "INV gate_child_two (" + " .\\I (I_c2 )," + " .\\O (O_c2 )" + " ) ;" + "endmodule" "\n" - "module ENT_CHILD_ONE (\n" - " I_c1,\n" - " O_c1\n" - " ) ;\n" - " input I_c1 ;\n" - " output O_c1 ;\n" - " wire net_child_0 ;\n" - " wire net_child_1 ;\n" - "ENT_CHILD_TWO gate_0_ent_two (\n" - " .\\I_c2 (I_c1 ),\n" - " .\\O_c2 (net_child_0 )\n" - " ) ;\n" - "ENT_CHILD_TWO gate_1_ent_two (\n" - " .\\I_c2 (net_child_0 ),\n" - " .\\O_c2 (net_child_1 )\n" - " ) ;\n" - "INV gate_child_one (\n" - " .\\I (net_child_1 ),\n" - " .\\O (O_c1 )\n" - " ) ;\n" - "endmodule\n" + "module ENT_CHILD_ONE (" + " I_c1," + " O_c1" + " ) ;" + " input I_c1 ;" + " output O_c1 ;" + " wire net_child_0 ;" + " wire net_child_1 ;" + "ENT_CHILD_TWO gate_0_ent_two (" + " .\\I_c2 (I_c1 )," + " .\\O_c2 (net_child_0 )" + " ) ;" + "ENT_CHILD_TWO gate_1_ent_two (" + " .\\I_c2 (net_child_0 )," + " .\\O_c2 (net_child_1 )" + " ) ;" + "INV gate_child_one (" + " .\\I (net_child_1 )," + " .\\O (O_c1 )" + " ) ;" + "endmodule" "\n" - "module ENT_TOP (\n" - " net_global_in,\n" - " net_global_out\n" - " ) ;\n" - " input net_global_in ;\n" - " output net_global_out ;\n" - " wire net_0 ;\n" - " wire net_1 ;\n" - "ENT_CHILD_ONE #(\n" - " .child_one_mod_key(1234)\n" - ") child_one_mod (\n" - " .\\I_c1 (net_global_in ),\n" - " .\\O_c1 (net_0 )\n" - " ) ;\n" - "ENT_CHILD_TWO child_two_mod (\n" - " .\\I_c2 (net_0 ),\n" - " .\\O_c2 (net_1 )\n" - " ) ;\n" - "INV gate_top (\n" - " .\\I (net_1 ),\n" - " .\\O (net_global_out )\n" - " ) ;\n" + "module ENT_TOP (" + " net_global_in," + " net_global_out" + " ) ;" + " input net_global_in ;" + " output net_global_out ;" + " wire net_0 ;" + " wire net_1 ;" + "ENT_CHILD_ONE #(" + " .child_one_mod_key(1234)" + ") child_one_mod (" + " .\\I_c1 (net_global_in )," + " .\\O_c1 (net_0 )" + " ) ;" + "ENT_CHILD_TWO child_two_mod (" + " .\\I_c2 (net_0 )," + " .\\O_c2 (net_1 )" + " ) ;" + "INV gate_top (" + " .\\I (net_1 )," + " .\\O (net_global_out )" + " ) ;" "endmodule"); hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1110,20 +1110,20 @@ TEST_F(hdl_parser_verilog_test, check_zero_and_one_nets) { // Port map gets multiple nets std::stringstream input; - input << "module top (\n" - " global_out_0,\n" - " global_out_1 \n" - " ) ;\n" - " output global_out_0 ;\n" - " output global_out_1 ;\n" - "INV gate_0 (\n" - " .\\I ('b0 ),\n" + input << "module top (" + " global_out_0," + " global_out_1 " + " ) ;" + " output global_out_0 ;" + " output global_out_1 ;" + "INV gate_0 (" + " .\\I ('b0 )," " .\\O (global_out_0)" - " ) ;\n" - "INV gate_1 (\n" - " .\\I ('b1 ),\n" + " ) ;" + "INV gate_1 (" + " .\\I ('b1 )," " .\\O (global_out_1)" - " ) ;\n" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1162,16 +1162,16 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // The passed gate library name is unknown NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - "INV gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (global_out )\n" - " ) ;\n" + input << "module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + "INV gate_0 (" + " .\\I (global_in )," + " .\\O (global_out )" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse("unknown_gate_lib"); @@ -1181,16 +1181,16 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // The module has no identifier NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - "INV gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (global_out )\n" - " ) ;\n" + input << "module (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + "INV gate_0 (" + " .\\I (global_in )," + " .\\O (global_out )" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1209,14 +1209,14 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // one side of the direct assignment is empty NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire signal_0 ;\n" - " assign signal_0 = ;\n" + input << "module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + " wire signal_0 ;" + " assign signal_0 = ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1226,19 +1226,19 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // The two sides of assignment do not have the same width NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire [0:4] signal_vec_0 ;\n" - " wire [0:4] signal_vec_1 ;\n" - " assign signal_vec_0[0:3] = signal_vec_0[0:4];\n" - "INV gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (global_out )\n" - " ) ;\n" + input << "module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + " wire [0:4] signal_vec_0 ;" + " wire [0:4] signal_vec_1 ;" + " assign signal_vec_0[0:3] = signal_vec_0[0:4];" + "INV gate_0 (" + " .\\I (global_in )," + " .\\O (global_out )" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1248,27 +1248,27 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // Having a cyclic module hierarchy (NOTE: Infinite Loop) NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module ENT_0 (\n" - " IE0,\n" - " OE0 \n" - " ) ;\n" - " input IE0 ;\n" - " output OE0 ;\n" - "ENT_1 gate_0 (\n" - " .\\IE1 (IE0 ),\n" - " .\\OE1 (OE0 )\n" - " ) ;\n" - "endmodule\n" - "module ENT_1 (\n" - " IE1,\n" - " OE1 \n" - " ) ;\n" - " input IE1 ;\n" - " output OE1 ;\n" - "ENT_0 gate_0 (\n" - " .\\IE0 (IE1 ),\n" - " .\\OE0 (OE1 )\n" - " ) ;\n" + input << "module ENT_0 (" + " IE0," + " OE0 " + " ) ;" + " input IE0 ;" + " output OE0 ;" + "ENT_1 gate_0 (" + " .\\IE1 (IE0 )," + " .\\OE1 (OE0 )" + " ) ;" + "endmodule" + "module ENT_1 (" + " IE1," + " OE1 " + " ) ;" + " input IE1 ;" + " output OE1 ;" + "ENT_0 gate_0 (" + " .\\IE0 (IE1 )," + " .\\OE0 (OE1 )" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1278,24 +1278,24 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // Having a cyclic assignment hierarchy NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module top (\n" - " global_in,\n" - " global_out \n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire net_0;\n" - " wire net_1;\n" - " assign net_0 = net_1;\n" - " assign net_1 = net_0;\n" - "INV gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (net_0 )\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I (net_1 ),\n" - " .\\O (global_out )\n" - " ) ;\n" + input << "module top (" + " global_in," + " global_out " + " ) ;" + " input global_in ;" + " output global_out ;" + " wire net_0;" + " wire net_1;" + " assign net_0 = net_1;" + " assign net_1 = net_0;" + "INV gate_0 (" + " .\\I (global_in )," + " .\\O (net_0 )" + " ) ;" + "INV gate_1 (" + " .\\I (net_1 )," + " .\\O (global_out )" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1305,20 +1305,20 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // Port map gets multiple nets NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module top (\n" - " global_in,\n" - " global_out \n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire net_0;\n" - "INV gate_0 (\n" - " .\\I ({global_in, net_0} )\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I (net_0 ),\n" - " .\\O (global_out )\n" - " ) ;\n" + input << "module top (" + " global_in," + " global_out " + " ) ;" + " input global_in ;" + " output global_out ;" + " wire net_0;" + "INV gate_0 (" + " .\\I ({global_in, net_0} )" + " ) ;" + "INV gate_1 (" + " .\\I (net_0 )," + " .\\O (global_out )" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1328,20 +1328,20 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) // Port name is unknown NO_COUT_TEST_BLOCK; std::stringstream input; - input << "module top (\n" - " global_in,\n" - " global_out \n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire net_0;\n" - "INV gate_0 (\n" - " .\\UNKNOWN_PORT_NAME (net_0)\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I (net_0 ),\n" - " .\\O (global_out )\n" - " ) ;\n" + input << "module top (" + " global_in," + " global_out " + " ) ;" + " input global_in ;" + " output global_out ;" + " wire net_0;" + "INV gate_0 (" + " .\\UNKNOWN_PORT_NAME (net_0)" + " ) ;" + "INV gate_1 (" + " .\\I (net_0 )," + " .\\O (global_out )" + " ) ;" "endmodule"; hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1350,18 +1350,18 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) { // Store an unknown data type NO_COUT_TEST_BLOCK; - std::stringstream input("module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - "INV #(\n" - ".key_unknown(#Unkn0wn!)) \n" - "gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (global_out )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + "INV #(" + ".key_unknown(#Unkn0wn!)) " + "gate_0 (" + " .\\I (global_in )," + " .\\O (global_out )" + " ) ;" "endmodule"); hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); @@ -1370,28 +1370,28 @@ TEST_F(hdl_parser_verilog_test, check_invalid_input) { // Assign one net to another, but booth are connected to different source gates NO_COUT_TEST_BLOCK; - std::stringstream input("module top (\n" - " global_in,\n" - " global_out\n" - " ) ;\n" - " input global_in ;\n" - " output global_out ;\n" - " wire net_0 ;\n" - " wire net_1 ;\n" - " assign net_0 = net_1 ;\n" - "INV gate_0 (\n" - " .\\I (global_in ),\n" - " .\\O (net_0 )\n" - " ) ;\n" - "INV gate_1 (\n" - " .\\I (global_in ),\n" - " .\\O (net_1 )\n" - " ) ;\n" - "AND2 gate_1 (\n" - " .\\I0 (net_0 ),\n" - " .\\I1 (net_1 ),\n" - " .\\O (global_out )\n" - " ) ;\n" + std::stringstream input("module top (" + " global_in," + " global_out" + " ) ;" + " input global_in ;" + " output global_out ;" + " wire net_0 ;" + " wire net_1 ;" + " assign net_0 = net_1 ;" + "INV gate_0 (" + " .\\I (global_in )," + " .\\O (net_0 )" + " ) ;" + "INV gate_1 (" + " .\\I (global_in )," + " .\\O (net_1 )" + " ) ;" + "AND2 gate_1 (" + " .\\I0 (net_0 )," + " .\\I1 (net_1 )," + " .\\O (global_out )" + " ) ;" "endmodule"); hdl_parser_verilog verilog_parser(input); std::shared_ptr nl = verilog_parser.parse(g_lib_name); From 3dfdebe292cbc7dcd103d563f75e06427d80c63f Mon Sep 17 00:00:00 2001 From: Fabian Albert Date: Thu, 5 Dec 2019 22:58:22 +0100 Subject: [PATCH 2/5] updated vhdl parser test --- tests/hdl_parser/hdl_parser_vhdl.cpp | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/tests/hdl_parser/hdl_parser_vhdl.cpp b/tests/hdl_parser/hdl_parser_vhdl.cpp index 572814c1542..8b5fe4d44e2 100644 --- a/tests/hdl_parser/hdl_parser_vhdl.cpp +++ b/tests/hdl_parser/hdl_parser_vhdl.cpp @@ -934,23 +934,23 @@ TEST_F(hdl_parser_vhdl_test, check_port_assignment) { "begin\n" " gate_0 : GATE_2^2_IN_2^2_OUT\n" " port map (\n" - " I(0, 1) => net_0\n" // <- connect I(0,1) to net_0 + " I(0,1) => net_0\n" // <- connect I(0,1) to net_0 " );\n" "end STRUCTURE;"); - test_def::capture_stdout(); + //test_def::capture_stdout(); hdl_parser_vhdl vhdl_parser(input); std::shared_ptr nl = vhdl_parser.parse(temp_lib_name); if (nl == nullptr) { - std::cout << test_def::get_captured_stdout(); + //std::cout << test_def::get_captured_stdout(); } else { - test_def::get_captured_stdout(); + //test_def::get_captured_stdout(); } ASSERT_NE(nl, nullptr); ASSERT_FALSE(nl->get_gates("GATE_2^2_IN_2^2_OUT", "gate_0").empty()); std::shared_ptr gate_0 = *(nl->get_gates("GATE_2^2_IN_2^2_OUT", "gate_0").begin()); - std::shared_ptr net_i_0 = gate_0->get_fan_in_net("I(0, 1)"); + std::shared_ptr net_i_0 = gate_0->get_fan_in_net("I(0,1)"); ASSERT_NE(net_i_0, nullptr); EXPECT_EQ(net_i_0->get_name(), "net_0"); }*/ @@ -1043,7 +1043,7 @@ TEST_F(hdl_parser_vhdl_test, check_port_assignment) { ASSERT_NE(net_2, nullptr); EXPECT_EQ(net_2->get_name(), "l_vec(2)"); }*/ - /*{ + { // Connect a vector of output pins with a vector of nets, but using downto statements std::stringstream input("-- Device\t: device_name\n" "entity TEST_Comp is\n" @@ -1083,7 +1083,7 @@ TEST_F(hdl_parser_vhdl_test, check_port_assignment) { std::shared_ptr net_2 = gate_0->get_fan_out_net("O(3)"); ASSERT_NE(net_2, nullptr); EXPECT_EQ(net_2->get_name(), "l_vec(2)"); - }*/ + } /*{ // Connect a vector of output pins with a vector of nets, but using a mix of to and downto statements std::stringstream input("-- Device\t: device_name\n" @@ -1126,7 +1126,7 @@ TEST_F(hdl_parser_vhdl_test, check_port_assignment) { EXPECT_EQ(net_2->get_name(), "l_vec(1)"); }*/ // NEGATIVE - /*{ + { // The range of the vectors does not match in size std::stringstream input("-- Device\t: device_name\n" "entity TEST_Comp is\n" @@ -1158,8 +1158,8 @@ TEST_F(hdl_parser_vhdl_test, check_port_assignment) { std::shared_ptr gate_0 = *(nl->get_gates("GATE_4^1_IN_4^1_OUT" ,"gate_0").begin()); EXPECT_EQ(gate_0->get_fan_out_nets().size(), 0); - }*/ - /*{ + } + { // The right side does no match any vector format std::stringstream input("-- Device\t: device_name\n" "entity TEST_Comp is\n" @@ -1191,14 +1191,14 @@ TEST_F(hdl_parser_vhdl_test, check_port_assignment) { EXPECT_EQ(gate_0->get_fan_in_nets().size(), 0); - }*/ + } remove_temp_gate_lib(); TEST_END } /** * Testing the usage of components, which should define new gate types with custom input/output/inout pins. - * ISSUE: l.98: "end component " needs a SPACE at the end... + * (currently unsupported...) * * Functions: parse */ From a5479a02f36ab5542227d47de274828d36687162 Mon Sep 17 00:00:00 2001 From: Fabian Albert Date: Thu, 12 Dec 2019 18:29:31 +0100 Subject: [PATCH 3/5] moved filter functions in netlist_test_utils --- tests/hdl_parser/hdl_parser_verilog.cpp | 21 ---- tests/hdl_parser/hdl_parser_vhdl.cpp | 19 --- tests/hdl_writer/hdl_writer_verilog.cpp | 24 ++-- tests/hdl_writer/hdl_writer_vhdl.cpp | 108 +++++++++--------- tests/netlist/gate.cpp | 10 -- tests/netlist/module.cpp | 26 ++--- tests/netlist/netlist.cpp | 15 --- tests/netlist/netlist_factory.cpp | 4 +- tests/test_utils/include/netlist_test_utils.h | 84 ++++++++++++++ tests/test_utils/src/netlist_test_utils.cpp | 42 +++++++ 10 files changed, 201 insertions(+), 152 deletions(-) diff --git a/tests/hdl_parser/hdl_parser_verilog.cpp b/tests/hdl_parser/hdl_parser_verilog.cpp index 0672d249c2b..7cd617b6986 100644 --- a/tests/hdl_parser/hdl_parser_verilog.cpp +++ b/tests/hdl_parser/hdl_parser_verilog.cpp @@ -29,27 +29,6 @@ class hdl_parser_verilog_test : public ::testing::Test } }; -static std::function&)> net_name_filter(const std::string& name){ - return [name](auto& n){return n->get_name() == name;}; -} - -static std::function&)> gate_name_filter(const std::string& name){ - return [name](auto& g){return g->get_name() == name;}; -} - -static std::function&)> gate_type_filter(const std::string& type){ - return [type](auto& g){return g->get_type()->get_name() == type;}; -} - -static std::function&)> gate_filter(const std::string& type, const std::string& name){ - return [name, type](auto& g){return g->get_name() == name && g->get_type()->get_name() == type;}; -} - -static std::function endpoint_type_filter(const std::string& type){ - return [type](auto& ep){return ep.gate->get_type()->get_name() == type;}; -} - - /* net_0 * .--= INV (0) =------. * global_in | '-= global_out diff --git a/tests/hdl_parser/hdl_parser_vhdl.cpp b/tests/hdl_parser/hdl_parser_vhdl.cpp index d4b398cf287..2696793d541 100644 --- a/tests/hdl_parser/hdl_parser_vhdl.cpp +++ b/tests/hdl_parser/hdl_parser_vhdl.cpp @@ -27,25 +27,6 @@ class hdl_parser_vhdl_test : public ::testing::Test } }; - -static std::function&)> net_name_filter(const std::string& name){ - return [name](auto& n){return n->get_name() == name;}; -} - -static std::function&)> gate_name_filter(const std::string& name){ - return [name](auto& g){return g->get_name() == name;}; -} - -static std::function&)> gate_type_filter(const std::string& type){ - return [type](auto& g){return g->get_type()->get_name() == type;}; -} - -static std::function&)> gate_filter(const std::string& type, const std::string& name){ - return [name, type](auto& g){return g->get_name() == name && g->get_type()->get_name() == type;}; -} - - - /* net_0 * .--= INV (0) =----. * global_in | '-= global_out diff --git a/tests/hdl_writer/hdl_writer_verilog.cpp b/tests/hdl_writer/hdl_writer_verilog.cpp index 0265004356c..c425165cc7a 100644 --- a/tests/hdl_writer/hdl_writer_verilog.cpp +++ b/tests/hdl_writer/hdl_writer_verilog.cpp @@ -62,10 +62,6 @@ class hdl_writer_verilog_test : public ::testing::Test } }; -static std::function&)> name_filter(const std::string& name){ - return [name](auto& g){return g->get_name() == name;}; -} - /** * Testing to write a given netlist in a sstream and parses it after, with * the hdl_parse_verilog. @@ -573,16 +569,16 @@ TEST_F(hdl_writer_verilog_test, check_special_net_names) { test_def::get_captured_stdout(); // Check if the gate_name is translated correctly - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_0" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_1" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_2" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_3" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_4" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_5" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_6" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_7" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_8" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("GATE_9" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_0" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_1" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_2" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_3" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_4" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_5" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_6" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_7" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_8" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("GATE_9" + GATE_SUFFIX)).empty()); } TEST_END } diff --git a/tests/hdl_writer/hdl_writer_vhdl.cpp b/tests/hdl_writer/hdl_writer_vhdl.cpp index 08b40b86e95..4459dff6ab5 100644 --- a/tests/hdl_writer/hdl_writer_vhdl.cpp +++ b/tests/hdl_writer/hdl_writer_vhdl.cpp @@ -16,7 +16,7 @@ using namespace test_utils; class hdl_writer_vhdl_test : public ::testing::Test { protected: - const std::string GATE_SUFFIX = ""; + const std::string GATE_SUFFIX = ""; virtual void SetUp() { NO_COUT_BLOCK; @@ -28,10 +28,6 @@ class hdl_writer_vhdl_test : public ::testing::Test } }; -static std::function&)> name_filter(const std::string& name){ - return [name](auto& g){return g->get_name() == name;}; -} - /** * Testing to write a given netlist in a sstream and parses it after, with * the hdl_parser_vhdl. @@ -621,16 +617,16 @@ TEST_F(hdl_writer_vhdl_test, check_special_net_names) { test_def::get_captured_stdout(); // Check if the gate_name is translated correctly - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_0" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_1" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_2" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_3" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_4" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_5" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_6" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_7" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("gate_8" + GATE_SUFFIX)).empty()); - EXPECT_FALSE(parsed_nl->get_gates(name_filter("GATE_9" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_0" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_1" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_2" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_3" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_4" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_5" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_6" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_7" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("gate_8" + GATE_SUFFIX)).empty()); + EXPECT_FALSE(parsed_nl->get_gates(gate_name_filter("GATE_9" + GATE_SUFFIX)).empty()); } TEST_END } @@ -693,47 +689,47 @@ TEST_F(hdl_writer_vhdl_test, check_gate_net_name_collision) { * * Functions: write, parse */ - /* +/* TEST_F(hdl_writer_vhdl_test, check_digit_net_name) { - TEST_START - { - // Add a gate to the netlist and store some data - std::shared_ptr nl = create_empty_netlist(0); - - std::shared_ptr test_gate = nl->create_gate( MIN_GATE_ID+0, "INV", "gate_net_name"); - std::shared_ptr test_net_0 = nl->create_net( MIN_NET_ID+0, "0"); - std::shared_ptr test_net_1 = nl->create_net( MIN_NET_ID+1, "1"); - - test_net_0->add_dst(test_gate, "I"); - test_net_1->set_src(test_gate, "O"); - - // Write and parse the netlist now - test_def::capture_stdout(); - std::stringstream parser_input; - hdl_writer_vhdl vhdl_writer(parser_input); - - // Writes the netlist in the sstream - bool writer_suc = vhdl_writer.write(nl); - if (!writer_suc) { - std::cout << test_def::get_captured_stdout() << std::endl; - } - ASSERT_TRUE(writer_suc); - - hdl_parser_vhdl vhdl_parser(parser_input); - // Parse the .vhdl file - std::shared_ptr parsed_nl = vhdl_parser.parse(g_lib_name); - - if (parsed_nl == nullptr) { - std::cout << test_def::get_captured_stdout() << std::endl; - } - ASSERT_NE(parsed_nl, nullptr); - test_def::get_captured_stdout(); - - // Check if the gate name was added a "_inst" - EXPECT_NE(get_net_by_subname(parsed_nl, "gate_net_name"), nullptr); - EXPECT_NE(get_gate_by_subname(parsed_nl, "gate_net_name_inst"), nullptr); - - } - TEST_END + TEST_START + { + // Add a gate to the netlist and store some data + std::shared_ptr nl = create_empty_netlist(0); + + std::shared_ptr test_gate = nl->create_gate( MIN_GATE_ID+0, "INV", "gate_net_name"); + std::shared_ptr test_net_0 = nl->create_net( MIN_NET_ID+0, "0"); + std::shared_ptr test_net_1 = nl->create_net( MIN_NET_ID+1, "1"); + + test_net_0->add_dst(test_gate, "I"); + test_net_1->set_src(test_gate, "O"); + + // Write and parse the netlist now + test_def::capture_stdout(); + std::stringstream parser_input; + hdl_writer_vhdl vhdl_writer(parser_input); + + // Writes the netlist in the sstream + bool writer_suc = vhdl_writer.write(nl); + if (!writer_suc) { + std::cout << test_def::get_captured_stdout() << std::endl; + } + ASSERT_TRUE(writer_suc); + + hdl_parser_vhdl vhdl_parser(parser_input); + // Parse the .vhdl file + std::shared_ptr parsed_nl = vhdl_parser.parse(g_lib_name); + + if (parsed_nl == nullptr) { + std::cout << test_def::get_captured_stdout() << std::endl; + } + ASSERT_NE(parsed_nl, nullptr); + test_def::get_captured_stdout(); + + // Check if the gate name was added a "_inst" + EXPECT_NE(get_net_by_subname(parsed_nl, "gate_net_name"), nullptr); + EXPECT_NE(get_gate_by_subname(parsed_nl, "gate_net_name_inst"), nullptr); + + } + TEST_END }*/ diff --git a/tests/netlist/gate.cpp b/tests/netlist/gate.cpp index 11a11e7ed21..6068fd01f54 100644 --- a/tests/netlist/gate.cpp +++ b/tests/netlist/gate.cpp @@ -27,16 +27,6 @@ class gate_test : public ::testing::Test }; -static std::function type_filter(const std::string& type){ - return [type](auto&, auto& ep){return ep.gate->get_type()->get_name() == type;}; -} -static std::function endpoint_pin_filter(const std::string& pin){ - return [pin](auto&, auto& ep){return ep.pin_type == pin;}; -} -static std::function starting_pin_filter(const std::string& pin){ - return [pin](auto& starting_pin, auto&){return starting_pin == pin;}; -} - /** * Testing the constructor as well as the copy constructor of the gate * diff --git a/tests/netlist/module.cpp b/tests/netlist/module.cpp index c1a9f0e8e71..991c996d425 100644 --- a/tests/netlist/module.cpp +++ b/tests/netlist/module.cpp @@ -26,12 +26,6 @@ class module_test : public ::testing::Test } }; - -static std::function&)> name_filter(const std::string& name){ - return [name](auto& m){return m->get_name() == name;}; -} - - /** * Testing the access on the id, the type and the stored netlist after calling the constructor * @@ -112,9 +106,9 @@ TEST_F(module_test, check_set_parent_module){ m_0->set_parent_module(m_1); EXPECT_EQ(m_0->get_parent_module(), m_1); - EXPECT_FALSE(m_1->get_submodules(name_filter("test_module_0"),false).empty()); - EXPECT_FALSE(m_1->get_submodules(name_filter("test_module_2"),true).empty()); - EXPECT_FALSE(m_1->get_submodules(name_filter("test_module_3"),true).empty()); + EXPECT_FALSE(m_1->get_submodules(module_name_filter("test_module_0"),false).empty()); + EXPECT_FALSE(m_1->get_submodules(module_name_filter("test_module_2"),true).empty()); + EXPECT_FALSE(m_1->get_submodules(module_name_filter("test_module_3"),true).empty()); } { /* Hang m_0 to one of its childs (m_1). m_1 should be connected to the top_module afterwards @@ -659,7 +653,7 @@ TEST_F(module_test, check_get_submodules){ std::shared_ptr m_3 = nl->create_module(MIN_MODULE_ID+3, "odd_module", m_1); ASSERT_NE(m_3, nullptr); { - // Testing the access on submodules (no name_filter, not recursive) + // Testing the access on submodules (no module_name_filter, not recursive) { // Submodules of TOP_MODULE; std::set> exp_result = {m_0, m_1}; @@ -677,21 +671,21 @@ TEST_F(module_test, check_get_submodules){ } } { - // Testing the access on submodules (name_filter set, not recursive) + // Testing the access on submodules (module_name_filter set, not recursive) { // Submodules of TOP_MODULE; std::set> exp_result = {m_0}; - EXPECT_EQ(tm->get_submodules(name_filter("even_module"), false), exp_result); + EXPECT_EQ(tm->get_submodules(module_name_filter("even_module"), false), exp_result); } { // Submodules of MODULE_1; std::set> exp_result = {m_2}; - EXPECT_EQ(m_1->get_submodules(name_filter("even_module"), false), exp_result); + EXPECT_EQ(m_1->get_submodules(module_name_filter("even_module"), false), exp_result); } { // Submodules of TOP_MODULE (name does not exists); std::set> exp_result = {}; - EXPECT_EQ(tm->get_submodules(name_filter("non_existing_name"), false), exp_result); + EXPECT_EQ(tm->get_submodules(module_name_filter("non_existing_name"), false), exp_result); } } { @@ -702,9 +696,9 @@ TEST_F(module_test, check_get_submodules){ EXPECT_EQ(tm->get_submodules(nullptr, true), exp_result); } { - // Submodules of TOP_MODULE (with name_filter); + // Submodules of TOP_MODULE (with module_name_filter); std::set> exp_result = {m_0,m_2}; - EXPECT_EQ(tm->get_submodules(name_filter("even_module"), true), exp_result); + EXPECT_EQ(tm->get_submodules(module_name_filter("even_module"), true), exp_result); } { // Submodules of MODULE_0 diff --git a/tests/netlist/netlist.cpp b/tests/netlist/netlist.cpp index 27430504c98..2d92c9cf863 100644 --- a/tests/netlist/netlist.cpp +++ b/tests/netlist/netlist.cpp @@ -26,21 +26,6 @@ class netlist_test : public ::testing::Test } }; - - -static std::function&)> net_name_filter(const std::string& name){ - return [name](auto& n){return n->get_name() == name;}; -} - -static std::function&)> gate_name_filter(const std::string& name){ - return [name](auto& g){return g->get_name() == name;}; -} - -static std::function&)> gate_type_filter(const std::string& type){ - return [type](auto& g){return g->get_type()->get_name() == type;}; -} - - /** * Testing the get_shared function which returns a shared_ptr on itselves * diff --git a/tests/netlist/netlist_factory.cpp b/tests/netlist/netlist_factory.cpp index 051c1c59c9c..81345dc3dd3 100644 --- a/tests/netlist/netlist_factory.cpp +++ b/tests/netlist/netlist_factory.cpp @@ -16,7 +16,7 @@ * any errors, it can be an issue of the vhdl parser as well... */ - +#ifdef FIXME using namespace test_utils; @@ -319,3 +319,5 @@ TEST_F(netlist_factory_test, check_create_netlist_by_program_args) TEST_END } + +#endif FIXME \ No newline at end of file diff --git a/tests/test_utils/include/netlist_test_utils.h b/tests/test_utils/include/netlist_test_utils.h index 17913958618..41f9da388aa 100644 --- a/tests/test_utils/include/netlist_test_utils.h +++ b/tests/test_utils/include/netlist_test_utils.h @@ -351,6 +351,90 @@ namespace test_utils bool netlists_are_equal(const std::shared_ptr nl_0, const std::shared_ptr nl_1, const bool ignore_id = false, const bool ignore_name = false); + // ===== Filter Factory Functions (used in module::get_gates, netlist::get_nets, moduleget_submodules, gate::get_sucessors, gate::get_predecessors) ===== + + // +++ Module Filter +++ + + /** + * Filter returns true for modules with the name 'name' + * + * @param name - the name of the modules the filter is searching for + * @return the std::function object of the filter function + */ + std::function&)> module_name_filter(const std::string& name); + + // +++ Gate Filter +++ + + /** + * Filter only returns true, if the gate is of type 'type' AND has the name 'name' + * + * @param type - the type of the gates the filter is searching for + * @param name - the name of the gates the filter is searching for + * @return the std::function object of the filter function + */ + std::function&)> gate_filter(const std::string& type, const std::string& name); + + /** + * Filter returns true for gates with the name 'name' + * + * @param name - the name of the gates the filter is searching for + * @return the std::function object of the filter function + */ + std::function&)> gate_name_filter(const std::string& name); + + /** + * Filter returns true for gates of type 'type' + * + * @param type - the type of the gates the filter is searching for + * @return the std::function object of the filter function + */ + std::function&)> gate_type_filter(const std::string& type); + + // +++ Net Filter +++ + + /** + * Filter returns true for nets with the name 'name' + * + * @param name - the name of the nets the filter is searching for + * @return the std::function object of the filter function + */ + std::function&)> net_name_filter(const std::string& name); + + // +++ Endpoint Filter +++ + + /** + * Filter returns true, if the type of the gate, the endpoint is connected to, is of type 'type' + * + * @param type - the type of the gates the filter is searching for + * @return the std::function object of the filter function + */ + std::function endpoint_type_filter(const std::string& type); + + /** + * Filter returns true, for all connected endpoint (of adjacent gates) of type 'pin' + * + * @param type - the type of the endpoints the filter is searching for + * @return the std::function object of the filter function + */ + std::function endpoint_pin_filter(const std::string& pin); + + /** + * Filter returns true for all endpoints, that are connected to the pin of pintype 'pin' of the calling gate + * + * @param pin - the pin of the gate, calling the get_predecessors/sucesseors function + * @return the std::function object of the filter function + */ + std::function starting_pin_filter(const std::string& pin); + + /** + * Filter returns true for all endpoints of adjacent gates of gate type 'type' + * + * @param type - the type of adjacent gates, the filter is searching for + * @return the std::function object of the filter function + */ + std::function type_filter(const std::string& type); + + } // namespace test_utils diff --git a/tests/test_utils/src/netlist_test_utils.cpp b/tests/test_utils/src/netlist_test_utils.cpp index f2665cc0e39..73dcb722aba 100644 --- a/tests/test_utils/src/netlist_test_utils.cpp +++ b/tests/test_utils/src/netlist_test_utils.cpp @@ -675,6 +675,48 @@ bool test_utils::modules_are_equal(const std::shared_ptr m_0, const std: return true; }*/ +// Filter Functions + +std::function&)> test_utils::module_name_filter(const std::string& name){ + return [name](auto& m){return m->get_name() == name;}; +} + +std::function&)> test_utils::gate_filter(const std::string& type, const std::string& name){ + return [name, type](auto& g){return g->get_name() == name && g->get_type()->get_name() == type;}; +} + +std::function&)> test_utils::gate_name_filter(const std::string& name){ + return [name](auto& g){return g->get_name() == name;}; +} + +std::function&)> test_utils::gate_type_filter(const std::string& type){ + return [type](auto& g){return g->get_type()->get_name() == type;}; +} + +std::function&)> test_utils::net_name_filter(const std::string& name){ + return [name](auto& n){return n->get_name() == name;}; +} + +std::function test_utils::endpoint_type_filter(const std::string& type){ + return [type](auto& ep){return ep.gate->get_type()->get_name() == type;}; +} + +std::function test_utils::endpoint_pin_filter(const std::string& pin){ + return [pin](auto&, auto& ep){return ep.pin_type == pin;}; +} +std::function test_utils::starting_pin_filter(const std::string& pin){ + return [pin](auto& starting_pin, auto&){return starting_pin == pin;}; +} + +std::function test_utils::type_filter(const std::string& type){ + return [type](auto&, auto& ep){return ep.gate->get_type()->get_name() == type;}; +} + + + + + + From 27c36eba82cc11e1a3d390756872350ded5bb142 Mon Sep 17 00:00:00 2001 From: Fabian Albert Date: Thu, 12 Dec 2019 18:39:58 +0100 Subject: [PATCH 4/5] repaired test plugin + temporarily removed plugin manager tests --- tests/core/plugin_manager.cpp | 5 ++--- .../test_plugin/include/factory_test_plugin.h | 7 +++++-- .../test_plugin/include/plugin_test_plugin.h | 20 +++---------------- .../test_plugin/src/factory_test_plugin.cpp | 7 +++++-- .../test_plugin/src/plugin_test_plugin.cpp | 12 +++++------ 5 files changed, 21 insertions(+), 30 deletions(-) diff --git a/tests/core/plugin_manager.cpp b/tests/core/plugin_manager.cpp index 83a478dd5c6..40d860c811e 100644 --- a/tests/core/plugin_manager.cpp +++ b/tests/core/plugin_manager.cpp @@ -5,7 +5,6 @@ #include #include - #ifdef FIXME using std::cout; @@ -328,7 +327,7 @@ TEST_F(plugin_manager_test, check_cli_plugin_options) * * Functions: get_plugin_factory */ -TEST_F(plugin_manager_test, check_get_plugin_factory) +/*TEST_F(plugin_manager_test, check_get_plugin_factory) { TEST_START // ######################## @@ -366,7 +365,7 @@ TEST_F(plugin_manager_test, check_get_plugin_factory) TEST_END } - +*/ /** * Testing the get_plugin_instance function * diff --git a/tests/core/test_plugin/include/factory_test_plugin.h b/tests/core/test_plugin/include/factory_test_plugin.h index edd4aef5fff..9c6a434bbc5 100644 --- a/tests/core/test_plugin/include/factory_test_plugin.h +++ b/tests/core/test_plugin/include/factory_test_plugin.h @@ -1,7 +1,9 @@ #ifndef HAL_FACTORY_TEST_PLUGIN_H #define HAL_FACTORY_TEST_PLUGIN_H -/* FIXME + +#ifdef REMOVE_ME + #include "core/interface_factory.h" class PLUGIN_API factory_test_plugin : public i_factory @@ -16,6 +18,7 @@ class PLUGIN_API factory_test_plugin : public i_factory }; extern "C" PLUGIN_API i_factory* get_factory(); -*/ + +#endif // REMOVE_ME #endif //HAL_FACTORY_TEST_PLUGIN_H diff --git a/tests/core/test_plugin/include/plugin_test_plugin.h b/tests/core/test_plugin/include/plugin_test_plugin.h index 54200c5bf7f..8a9fa0378ab 100644 --- a/tests/core/test_plugin/include/plugin_test_plugin.h +++ b/tests/core/test_plugin/include/plugin_test_plugin.h @@ -1,16 +1,7 @@ -// -// Created by ubuntu on 9/28/19. -// #ifndef HAL_PLUGIN_TEST_PLUGIN_H #define HAL_PLUGIN_TEST_PLUGIN_H - -#include "core/interface_base.h" - -//#include - -#include #include "core/interface_cli.h" #include "core/interface_base.h" @@ -19,7 +10,6 @@ class netlist; class gate; class net; -#ifdef FIXME class PLUGIN_API plugin_test_plugin : virtual public i_cli { @@ -35,17 +25,14 @@ class PLUGIN_API plugin_test_plugin : virtual public i_cli */ /** interface implementation: i_base */ - std::string get_name() override; - - /** interface implementation: i_base */ - std::string get_version() override; + std::string get_name() const override; /** interface implementation: i_base */ - std::set get_type() override; + std::string get_version() const override; /** interface implementation: i_cli */ - program_options get_cli_options() override; + program_options get_cli_options() const override; @@ -53,6 +40,5 @@ class PLUGIN_API plugin_test_plugin : virtual public i_cli bool handle_cli_call(std::shared_ptr nl, program_arguments& args) override; }; -#endif // FIXME #endif //HAL_PLUGIN_TEST_PLUGIN_H diff --git a/tests/core/test_plugin/src/factory_test_plugin.cpp b/tests/core/test_plugin/src/factory_test_plugin.cpp index 0392ddea64f..1a18ed660af 100644 --- a/tests/core/test_plugin/src/factory_test_plugin.cpp +++ b/tests/core/test_plugin/src/factory_test_plugin.cpp @@ -1,6 +1,8 @@ #include "factory_test_plugin.h" #include "plugin_test_plugin.h" -/* FIXME + +#ifdef REMOVE_ME + std::shared_ptr factory_test_plugin::get_plugin_instance() { return std::dynamic_pointer_cast(std::make_shared()); @@ -11,4 +13,5 @@ extern i_factory* get_factory() static factory_test_plugin* factory = new factory_test_plugin(); return (i_factory*)factory; } -*/ \ No newline at end of file + +#endif // REMOVE_ME diff --git a/tests/core/test_plugin/src/plugin_test_plugin.cpp b/tests/core/test_plugin/src/plugin_test_plugin.cpp index e6611127fab..2f548a07216 100644 --- a/tests/core/test_plugin/src/plugin_test_plugin.cpp +++ b/tests/core/test_plugin/src/plugin_test_plugin.cpp @@ -1,23 +1,24 @@ #include "plugin_test_plugin.h" #include "core/log.h" -/* FIXME -std::string plugin_test_plugin::get_name() + +std::string plugin_test_plugin::get_name() const { return std::string("test_plugin"); } -std::string plugin_test_plugin::get_version() +std::string plugin_test_plugin::get_version() const { return std::string("1.2.3"); } + /* std::set plugin_test_plugin::get_type() { return std::set{interface_type::base, interface_type::cli}; -} +}*/ -program_options plugin_test_plugin::get_cli_options() +program_options plugin_test_plugin::get_cli_options() const { program_options description; description.add("--option_one", "option_one_description"); @@ -31,4 +32,3 @@ bool plugin_test_plugin::handle_cli_call(std::shared_ptr nl, program_ar UNUSED(args); return true; } -*/ \ No newline at end of file From 36b4567849be5e22f86d6820a5b7788cf86826c6 Mon Sep 17 00:00:00 2001 From: Fabian Albert Date: Thu, 12 Dec 2019 19:30:18 +0100 Subject: [PATCH 5/5] added tests for gate locations + the module::contains_module funciton --- tests/netlist/gate.cpp | 48 ++++++++ tests/netlist/module.cpp | 247 ++++----------------------------------- 2 files changed, 69 insertions(+), 226 deletions(-) diff --git a/tests/netlist/gate.cpp b/tests/netlist/gate.cpp index 6068fd01f54..1226d39f5c9 100644 --- a/tests/netlist/gate.cpp +++ b/tests/netlist/gate.cpp @@ -622,3 +622,51 @@ TEST_F(gate_test, check_get_module) TEST_END } +/** + * Testing storage and access of gate locations + * + * Functions: get_location_x, get_location_y, get_location, has_location, set_location_x, set_location_y, set_location + */ +TEST_F(gate_test, check_location_storage) +{ + TEST_START + { + // Create a gate with a location and change it afterwards + std::shared_ptr nl = create_empty_netlist(); + std::shared_ptr test_gate = nl->create_gate(MIN_GATE_ID+0, get_gate_type_by_name("INV"), "test_gate", 1.11f, 2.22f); + EXPECT_EQ(test_gate->get_location_x(), 1.11f); + EXPECT_EQ(test_gate->get_location_y(), 2.22f); + EXPECT_EQ(test_gate->get_location(), std::make_pair(1.11f, 2.22f)); + // -- set a new x location + test_gate->set_location_x(3.33f); + EXPECT_EQ(test_gate->get_location(), std::make_pair(3.33f, 2.22f)); + // -- set a new y location + test_gate->set_location_y(4.44f); + EXPECT_EQ(test_gate->get_location(), std::make_pair(3.33f, 4.44f)); + // -- set a new location + test_gate->set_location(std::make_pair(5.55f, 6.66f)); + EXPECT_EQ(test_gate->get_location(), std::make_pair(5.55f, 6.66f)); + // -- set the same location again + test_gate->set_location(std::make_pair(5.55f, 6.66f)); + EXPECT_EQ(test_gate->get_location(), std::make_pair(5.55f, 6.66f)); + } + { + // Test the has_location function + std::shared_ptr nl = create_empty_netlist(); + std::shared_ptr test_gate = nl->create_gate(MIN_GATE_ID+0, get_gate_type_by_name("INV"), "test_gate", 1.11f, 2.22f); + // -- both coordinates are >= 0 + test_gate->set_location(std::make_pair(1.11f, 2.22f)); + EXPECT_TRUE(test_gate->has_location()); + test_gate->set_location(std::make_pair(0.0f, 0.0f)); + EXPECT_TRUE(test_gate->has_location()); + // -- not both coordinates are >= 0 + test_gate->set_location(std::make_pair(-1.11f, 2.22f)); + EXPECT_FALSE(test_gate->has_location()); + test_gate->set_location(std::make_pair(1.11f, -2.22f)); + EXPECT_FALSE(test_gate->has_location()); + test_gate->set_location(std::make_pair(-1.11f, -2.22f)); + EXPECT_FALSE(test_gate->has_location()); + } + TEST_END +} + diff --git a/tests/netlist/module.cpp b/tests/netlist/module.cpp index 991c996d425..0466722b236 100644 --- a/tests/netlist/module.cpp +++ b/tests/netlist/module.cpp @@ -400,231 +400,7 @@ TEST_F(module_test, check_get_gate_by_id){ } /** - * Testing the contains_net function - * - * Functions: contains_net - */ -/*TEST_F(module_test, check_contains_net){ - TEST_START - // POSITIVE - { - // Check a net, that is part of the module (not recursive) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - //m_0->assign_net(net_0); - - EXPECT_TRUE(m_0->contains_net(net_0)); - } - { - // Check a net, that isn't part of the module (not recursive) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - - EXPECT_FALSE(m_0->contains_net(net_0)); - } - { - // Check a net, that isn't part of the module, but of a submodule (not recursive) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr submodule = nl->create_module(MIN_MODULE_ID+1, "test_module", m_0); - ASSERT_NE(submodule, nullptr); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - submodule->assign_net(net_0); - - EXPECT_FALSE(m_0->contains_net(net_0)); - } - { - // Check a net, that isn't part of the module, but of a submodule (recursive) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr submodule = nl->create_module(MIN_MODULE_ID+1, "test_module", m_0); - ASSERT_NE(submodule, nullptr); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - submodule->assign_net(net_0); - - EXPECT_TRUE(m_0->contains_net(net_0, true)); - } - TEST_END -}*/ - -/** - * Testing the addition of nets to the module. Verify the addition by call the - * get_nets function and the contains_net and get_nets function - * - * Functions: assign_net - */ -/*TEST_F(module_test, check_assign_net){ - TEST_START - { - // Add some nets to the module - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - std::shared_ptr net_1 = nl->create_net(MIN_NET_ID+1, "net_1"); - // this net is not part of the module - std::shared_ptr net_not_in_m = nl->create_net(MIN_NET_ID+2, "net_not_in_m"); - - // Add net_0 and net_1 to a module - std::shared_ptr test_module = nl->create_module(MIN_MODULE_ID+1, "test module", nl->get_top_module()); - test_module->assign_net(net_0); - test_module->assign_net(net_1); - - std::set> expRes = {net_0, net_1}; - - EXPECT_EQ(test_module->get_nets(), expRes); - } - { - NO_COUT_TEST_BLOCK; - // Add the same net twice to the module - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - - // Add net_0 twice - std::shared_ptr test_module = nl->create_module(MIN_MODULE_ID+0, "test module", nl->get_top_module()); - test_module->assign_net(net_0); - test_module->assign_net(net_0); - - std::set> expRes = { - net_0, - }; - - EXPECT_EQ(test_module->get_nets(), expRes); - EXPECT_TRUE(test_module->contains_net(net_0)); - } - { - // Insert a net owned by a submodule - NO_COUT_TEST_BLOCK; - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - - std::shared_ptr test_module = nl->create_module(MIN_MODULE_ID+0, "test module", nl->get_top_module()); - std::shared_ptr submodule = nl->create_module(MIN_MODULE_ID+1, "submodule", test_module); - submodule->assign_net(net_0); - ASSERT_TRUE(submodule->contains_net(net_0)); - ASSERT_FALSE(test_module->contains_net(net_0)); - - test_module->assign_net(net_0); - - std::set> expRes = { - net_0 - }; - - EXPECT_EQ(test_module->get_nets(), expRes); - EXPECT_FALSE(submodule->contains_net(net_0)); - } - - // NEGATIVE - { - // Net is a nullptr - NO_COUT_TEST_BLOCK; - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr test_module = nl->create_module(MIN_MODULE_ID+0, "test module", nl->get_top_module()); - test_module->assign_net(nullptr); - EXPECT_TRUE(test_module->get_nets().empty()); - } - - TEST_END -}*/ - -/** - * Testing the deletion of nets from modules - * - * Functions: remove_net - */ -/*TEST_F(module_test, check_remove_net){ - TEST_START - { - // Delete a net from a module (net owned by the modules) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - m_0->assign_net(net_0); - - ASSERT_TRUE(m_0->contains_net(net_0)); - m_0->remove_net(net_0); - EXPECT_FALSE(m_0->contains_net(net_0)); - } - { - // Try to delete a net from a module (net owned by another module) - NO_COUT_TEST_BLOCK; - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr m_other = nl->create_module(MIN_MODULE_ID+1, "other_test_module", nl->get_top_module()); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - m_other->assign_net(net_0); - - m_0->remove_net(net_0); - EXPECT_FALSE(m_0->contains_net(net_0)); - EXPECT_TRUE(m_other->contains_net(net_0)); - } - // NEGATIVE - { - // Try to delete a net from the top-module (should change nothing) - NO_COUT_TEST_BLOCK; - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr net_0 = nl->create_net(MIN_NET_ID+0, "net_0"); - std::shared_ptr tm = nl->get_top_module(); - - ASSERT_TRUE(tm->contains_net(net_0)); - tm->remove_net(net_0); - EXPECT_TRUE(tm->contains_net(net_0)); - } - { - // Try to delete a nullptr (should not crash) - NO_COUT_TEST_BLOCK; - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - - m_0->remove_net(nullptr); - } - TEST_END -}*/ - -/** - * Testing the get_net_by_id function - * - * Functions: get_net_by_id - */ -/*TEST_F(module_test, check_get_net_by_id){ - TEST_START - // POSITIVE - { - // get a net by its id (net owned by module)(not recursive) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr net_123 = nl->create_net(MIN_NET_ID+123, "net_123"); - m_0->assign_net(net_123); - - ASSERT_TRUE(m_0->contains_net(net_123)); - EXPECT_EQ(m_0->get_net_by_id(MIN_NET_ID+123), net_123); - } - { - // get a net by its id (not owned by a submodule)(not recursive) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr submodule = nl->create_module(MIN_MODULE_ID+1, "other_module", m_0); - std::shared_ptr net_123 = nl->create_net(MIN_NET_ID+123, "net_123"); - submodule->assign_net(net_123); - - EXPECT_EQ(m_0->get_net_by_id(MIN_NET_ID+123), nullptr); - } - { - // get a net by its id (not owned by a submodule)(recursive) - std::shared_ptr nl = create_empty_netlist(); - std::shared_ptr m_0 = nl->create_module(MIN_MODULE_ID+0, "test_module", nl->get_top_module()); - std::shared_ptr submodule = nl->create_module(MIN_MODULE_ID+1, "other_module", m_0); - std::shared_ptr net_123 = nl->create_net(MIN_NET_ID+123, "net_123"); - submodule->assign_net(net_123); - - EXPECT_EQ(m_0->get_net_by_id(MIN_NET_ID+123, true), net_123); - } - TEST_END -}*/ - - -/** - * Testing the access on submodules. Therefore we build up a module tree like this: + * Testing the access on submodules as well as the contains module function. Therefore we build up a module tree like this: * * .----> MODULE_0 * | @@ -636,7 +412,7 @@ TEST_F(module_test, check_get_gate_by_id){ * * (Remark: MODULE_0 and MODULE_2 are both named "even_module", while MODULE_1 and MODULE_3 are named "odd_module") * - * Functions: get_submodules + * Functions: get_submodules, contains_module */ TEST_F(module_test, check_get_submodules){ TEST_START @@ -658,6 +434,10 @@ TEST_F(module_test, check_get_submodules){ // Submodules of TOP_MODULE; std::set> exp_result = {m_0, m_1}; EXPECT_EQ(tm->get_submodules(nullptr, false), exp_result); + EXPECT_TRUE(tm->contains_module(m_0, false)); + EXPECT_TRUE(tm->contains_module(m_1, false)); + EXPECT_FALSE(tm->contains_module(m_2, false)); + EXPECT_FALSE(tm->contains_module(m_3, false)); } { // Submodules of MODULE_1; @@ -694,6 +474,10 @@ TEST_F(module_test, check_get_submodules){ // Submodules of TOP_MODULE; std::set> exp_result = {m_0,m_1,m_2,m_3}; EXPECT_EQ(tm->get_submodules(nullptr, true), exp_result); + EXPECT_TRUE(tm->contains_module(m_0, true)); + EXPECT_TRUE(tm->contains_module(m_1, true)); + EXPECT_TRUE(tm->contains_module(m_2, true)); + EXPECT_TRUE(tm->contains_module(m_3, true)); } { // Submodules of TOP_MODULE (with module_name_filter); @@ -706,6 +490,16 @@ TEST_F(module_test, check_get_submodules){ EXPECT_EQ(m_0->get_submodules(nullptr, true), exp_result); } } + { + // Testing edge cases of contains_module + + // -- the passed module is a nullptr + EXPECT_FALSE(tm->contains_module(nullptr, false)); + // -- the calling module is a leave + EXPECT_FALSE(m_2->contains_module(tm, false)); + // -- the passed module is the same as the calling one + EXPECT_FALSE(m_2->contains_module(m_2, false)); + } TEST_END } @@ -797,3 +591,4 @@ TEST_F(module_test, check_get_input_nets){ TEST_END } +