xfsmart
diff --git a/‎example/Arista_7132LB/fpga_25g/README.md renamed to ‎example/DCS7132LB/fpga_25g/README.md b/‎example/Arista_7132LB/fpga_25g/README.md renamed to ‎example/DCS7132LB/fpga_25g/README.md
diff --git a/‎example/Arista_7132LB/fpga_25g/common/vivado.mk renamed to ‎example/DCS7132LB/fpga_25g/common/vivado.mk b/‎example/Arista_7132LB/fpga_25g/common/vivado.mk renamed to ‎example/DCS7132LB/fpga_25g/common/vivado.mk
diff --git a/‎example/Arista_7132LB/fpga_25g/fpga.xdc renamed to ‎example/DCS7132LB/fpga_25g/fpga.xdc b/‎example/Arista_7132LB/fpga_25g/fpga.xdc renamed to ‎example/DCS7132LB/fpga_25g/fpga.xdc
diff --git a/‎example/Arista_7132LB/fpga_25g/fpga/Makefile renamed to ‎example/DCS7132LB/fpga_25g/fpga/Makefile b/‎example/Arista_7132LB/fpga_25g/fpga/Makefile renamed to ‎example/DCS7132LB/fpga_25g/fpga/Makefile
diff --git a/‎example/Arista_7132LB/fpga_25g/fpga/config.tcl renamed to ‎example/DCS7132LB/fpga_25g/fpga/config.tcl b/‎example/Arista_7132LB/fpga_25g/fpga/config.tcl renamed to ‎example/DCS7132LB/fpga_25g/fpga/config.tcl
diff --git a/‎example/Arista_7132LB/fpga_25g/fpga_10g/Makefile renamed to ‎example/DCS7132LB/fpga_25g/fpga_10g/Makefile b/‎example/Arista_7132LB/fpga_25g/fpga_10g/Makefile renamed to ‎example/DCS7132LB/fpga_25g/fpga_10g/Makefile
diff --git a/‎example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl renamed to ‎example/DCS7132LB/fpga_25g/fpga_10g/config.tcl b/‎example/Arista_7132LB/fpga_25g/fpga_10g/config.tcl renamed to ‎example/DCS7132LB/fpga_25g/fpga_10g/config.tcl
diff --git a/‎example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl renamed to ‎example/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl b/‎example/Arista_7132LB/fpga_25g/ip/eth_xcvr_gt.tcl renamed to ‎example/DCS7132LB/fpga_25g/ip/eth_xcvr_gt.tcl
diff --git a/‎example/Arista_7132LB/fpga_25g/lib/eth renamed to ‎example/DCS7132LB/fpga_25g/lib/eth b/‎example/Arista_7132LB/fpga_25g/lib/eth renamed to ‎example/DCS7132LB/fpga_25g/lib/eth
diff --git a/‎example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/‎example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
diff --git a/‎example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/‎example/Arista_7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
diff --git a/‎example/Arista_7132LB/fpga_25g/rtl/fpga.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/fpga.v b/‎example/Arista_7132LB/fpga_25g/rtl/fpga.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/fpga.v
diff --git a/‎example/Arista_7132LB/fpga_25g/rtl/fpga_core.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/fpga_core.v b/‎example/Arista_7132LB/fpga_25g/rtl/fpga_core.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/fpga_core.v
diff --git a/‎example/Arista_7132LB/fpga_25g/rtl/sync_signal.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/sync_signal.v b/‎example/Arista_7132LB/fpga_25g/rtl/sync_signal.v renamed to ‎example/DCS7132LB/fpga_25g/rtl/sync_signal.v
diff --git a/‎example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile renamed to ‎example/DCS7132LB/fpga_25g/tb/fpga_core/Makefile b/‎example/Arista_7132LB/fpga_25g/tb/fpga_core/Makefile renamed to ‎example/DCS7132LB/fpga_25g/tb/fpga_core/Makefile
diff --git a/‎example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py renamed to ‎example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py b/‎example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py renamed to ‎example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.py
diff --git a/‎example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v renamed to ‎example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v b/‎example/Arista_7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v renamed to ‎example/DCS7132LB/fpga_25g/tb/fpga_core/test_fpga_core.v