[x64] Move all sequences in same compilation unit

Currently, sequences are in separate compilation units, but their
constructors all share the same unordered_map, which is in one of the
compilation unit.

Due to that, when compiling using GCC with LTO enabled, the constructor of
some units is called before the constructor of the unit with the map, also
called 'Static Initialization Order Fiasco'
(see: https://en.cppreference.com/w/cpp/language/siof). Thus, the
map is not initialized, which causes a division-by-zero error (SIGFPE).

Fix this by converting the files that contain specific sequences to be
includable in the main file. This way all sequences are in the same
compilation unit and guarantees the map is initialized.

Author: amessier

src/xenia/cpu/backend/x64/x64_seq_control.cc renamed to src/xenia/cpu/backend/x64/x64_seq_control.inc

@@ -2,24 +2,12 @@
  ******************************************************************************
  * Xenia : Xbox 360 Emulator Research Project                                 *
  ******************************************************************************
- * Copyright 2018 Xenia Developers. All rights reserved.                      *
+ * Copyright 2022 Xenia Developers. All rights reserved.                      *
  * Released under the BSD license - see LICENSE in the root for more details. *
  ******************************************************************************
  */
 
-#include "xenia/cpu/backend/x64/x64_sequences.h"
-
-#include <algorithm>
-#include <cstring>
-
-#include "xenia/cpu/backend/x64/x64_op.h"
-
-namespace xe {
-namespace cpu {
-namespace backend {
-namespace x64 {
-
-volatile int anchor_control = 0;
+// NOTICE: This file is #included in x64_sequences.cc
 
 // ============================================================================
 // OPCODE_DEBUG_BREAK
@@ -546,8 +534,3 @@ struct BRANCH_FALSE_F64
 EMITTER_OPCODE_TABLE(OPCODE_BRANCH_FALSE, BRANCH_FALSE_I8, BRANCH_FALSE_I16,
                      BRANCH_FALSE_I32, BRANCH_FALSE_I64, BRANCH_FALSE_F32,
                      BRANCH_FALSE_F64);
-
-}  // namespace x64
-}  // namespace backend
-}  // namespace cpu
-}  // namespace xe

src/xenia/cpu/backend/x64/x64_seq_memory.cc renamed to src/xenia/cpu/backend/x64/x64_seq_memory.inc

@@ -2,26 +2,12 @@
  ******************************************************************************
  * Xenia : Xbox 360 Emulator Research Project                                 *
  ******************************************************************************
- * Copyright 2018 Xenia Developers. All rights reserved.                      *
+ * Copyright 2022 Xenia Developers. All rights reserved.                      *
  * Released under the BSD license - see LICENSE in the root for more details. *
  ******************************************************************************
  */
 
-#include "xenia/cpu/backend/x64/x64_sequences.h"
-
-#include <algorithm>
-#include <cstring>
-
-#include "xenia/base/memory.h"
-#include "xenia/cpu/backend/x64/x64_op.h"
-#include "xenia/cpu/backend/x64/x64_tracers.h"
-
-namespace xe {
-namespace cpu {
-namespace backend {
-namespace x64 {
-
-volatile int anchor_memory = 0;
+// NOTICE: This file is #included in x64_sequences.cc
 
 // Note: all types are always aligned in the context.
 RegExp ComputeContextAddress(X64Emitter& e, const OffsetOp& offset) {
@@ -1169,8 +1155,3 @@ struct MEMSET_I64_I8_I64
   }
 };
 EMITTER_OPCODE_TABLE(OPCODE_MEMSET, MEMSET_I64_I8_I64);
-
-}  // namespace x64
-}  // namespace backend
-}  // namespace cpu
-}  // namespace xe

src/xenia/cpu/backend/x64/x64_seq_vector.cc renamed to src/xenia/cpu/backend/x64/x64_seq_vector.inc

@@ -7,22 +7,7 @@
  ******************************************************************************
  */
 
-#include "xenia/cpu/backend/x64/x64_sequences.h"
-
-#include <algorithm>
-#include <cstring>
-
-#include "xenia/cpu/backend/x64/x64_op.h"
-
-// For OPCODE_PACK/OPCODE_UNPACK
-#include "third_party/half/include/half.hpp"
-
-namespace xe {
-namespace cpu {
-namespace backend {
-namespace x64 {
-
-volatile int anchor_vector = 0;
+// NOTICE: This file is #included in x64_sequences.cc
 
 // ============================================================================
 // OPCODE_VECTOR_CONVERT_I2F
@@ -2684,8 +2669,3 @@ struct UNPACK : Sequence<UNPACK, I<OPCODE_UNPACK, V128Op, V128Op>> {
   }
 };
 EMITTER_OPCODE_TABLE(OPCODE_UNPACK, UNPACK);
-
-}  // namespace x64
-}  // namespace backend
-}  // namespace cpu
-}  // namespace xe

src/xenia/cpu/backend/x64/x64_sequences.cc

@@ -38,6 +38,9 @@
 #include "xenia/cpu/hir/hir_builder.h"
 #include "xenia/cpu/processor.h"
 
+// For OPCODE_PACK/OPCODE_UNPACK
+#include "third_party/half/include/half.hpp"
+
 namespace xe {
 namespace cpu {
 namespace backend {
@@ -54,6 +57,23 @@ using xe::cpu::hir::Instr;
 typedef bool (*SequenceSelectFn)(X64Emitter&, const Instr*);
 std::unordered_map<uint32_t, SequenceSelectFn> sequence_table;
 
+template <typename T>
+bool Register() {
+  sequence_table.insert({T::head_key(), T::Select});
+  return true;
+}
+
+template <typename T, typename Tn, typename... Ts>
+static bool Register() {
+  bool b = true;
+  b = b && Register<T>();          // Call the above function
+  b = b && Register<Tn, Ts...>();  // Call ourself again (recursively)
+  return b;
+}
+
+#define EMITTER_OPCODE_TABLE(name, ...) \
+  const auto X64_INSTR_##name = Register<__VA_ARGS__>();
+
 // ============================================================================
 // OPCODE_COMMENT
 // ============================================================================
@@ -3299,15 +3319,9 @@ struct SET_ROUNDING_MODE_I32
 };
 EMITTER_OPCODE_TABLE(OPCODE_SET_ROUNDING_MODE, SET_ROUNDING_MODE_I32);
 
-// Include anchors to other sequence sources so they get included in the build.
-extern volatile int anchor_control;
-static int anchor_control_dest = anchor_control;
-
-extern volatile int anchor_memory;
-static int anchor_memory_dest = anchor_memory;
-
-extern volatile int anchor_vector;
-static int anchor_vector_dest = anchor_vector;
+#include "x64_seq_control.inc"
+#include "x64_seq_memory.inc"
+#include "x64_seq_vector.inc"
 
 bool SelectSequence(X64Emitter* e, const Instr* i, const Instr** new_tail) {
   const InstrKey key(i);

src/xenia/cpu/backend/x64/x64_sequences.h

@@ -2,7 +2,7 @@
  ******************************************************************************
  * Xenia : Xbox 360 Emulator Research Project                                 *
  ******************************************************************************
- * Copyright 2014 Ben Vanik. All rights reserved.                             *
+ * Copyright 2022 Ben Vanik. All rights reserved.                             *
  * Released under the BSD license - see LICENSE in the root for more details. *
  ******************************************************************************
  */
@@ -12,34 +12,13 @@
 
 #include "xenia/cpu/hir/instr.h"
 
-#include <unordered_map>
-
 namespace xe {
 namespace cpu {
 namespace backend {
 namespace x64 {
 
 class X64Emitter;
 
-typedef bool (*SequenceSelectFn)(X64Emitter&, const hir::Instr*);
-extern std::unordered_map<uint32_t, SequenceSelectFn> sequence_table;
-
-template <typename T>
-bool Register() {
-  sequence_table.insert({T::head_key(), T::Select});
-  return true;
-}
-
-template <typename T, typename Tn, typename... Ts>
-static bool Register() {
-  bool b = true;
-  b = b && Register<T>();          // Call the above function
-  b = b && Register<Tn, Ts...>();  // Call ourself again (recursively)
-  return b;
-}
-#define EMITTER_OPCODE_TABLE(name, ...) \
-  const auto X64_INSTR_##name = Register<__VA_ARGS__>();
-
 bool SelectSequence(X64Emitter* e, const hir::Instr* i,
                     const hir::Instr** new_tail);