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.gitmodules
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[submodule "adder/Digital_Adders_Verilog"]
path = 01_adder/01_32bit_adders
url = https://github.com/Ams0x57/Digital_Adders_Verilog
[submodule "multiplier/Fixed-Floating-Point-Adder-Multiplier"]
path = 02_multiplier/Fixed-Floating-Point-Adder-Multiplier
url = https://github.com/suoglu/Fixed-Floating-Point-Adder-Multiplier.git
[submodule "hybrid/Verilog-Projects"]
path = 0x_hybrid/Verilog-Projects
url = https://github.com/nxbyte/Verilog-Projects.git
[submodule "hybrid/Computer-Architecture"]
path = 0x_hybrid/Computer-Architecture
url = https://github.com/princeofpython/Computer-Architecture.git
[submodule "hybrid/32-Verilog-Mini-Projects"]
path = 0x_hybrid/32-Verilog-Mini-Projects
url = https://github.com/sudhamshu091/32-Verilog-Mini-Projects
[submodule "fpu/fpu"]
path = 04_fpu/fpu
url = https://github.com/dawsonjon/fpu.git
[submodule "fpu/riscv-fpu"]
path = 04_fpu/riscv-fpu
url = https://github.com/taneroksuz/riscv-fpu.git
[submodule "core/rocket"]
path = 06_core/rocket
url = https://github.com/bigzz/rocket.git
[submodule "bus/axi"]
path = 07_bus/03_pulp_axi
url = https://github.com/pulp-platform/axi.git
[submodule "bus/apb"]
path = 07_bus/04_pulp_apb
url = https://github.com/pulp-platform/apb.git
[submodule "bus/AMBA_AXI_AHB_APB"]
path = 07_bus/01_amba_study
url = https://github.com/adki/AMBA_AXI_AHB_APB
[submodule "cache/Verilog-caches"]
path = 05_cache/Verilog-caches
url = https://github.com/airin711/Verilog-caches.git
[submodule "cache/4-way-set-associative-cache-verilog"]
path = 05_cache/4-way-set-associative-cache-verilog
url = https://github.com/rajshadow/4-way-set-associative-cache-verilog.git
[submodule "cache/iob-cache"]
path = 05_cache/iob-cache
url = https://github.com/IObundle/iob-cache.git
[submodule "cache/esp-caches"]
path = 05_cache/esp-caches
url = https://github.com/sld-columbia/esp-caches.git
[submodule "cache/block-inclusivecache-sifive"]
path = 05_cache/block-inclusivecache-sifive
url = https://github.com/sifive/block-inclusivecache-sifive.git
[submodule "cache/L2_tcdm_hybrid_interco"]
path = 05_cache/L2_tcdm_hybrid_interco
url = https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
[submodule "alu/alu-8bit"]
path = 03_alu/alu-8bit
url = https://github.com/gupta-utkarsh/alu-8bit.git
[submodule "alu/Floating-Point-ALU-in-Verilog"]
path = 03_alu/Floating-Point-ALU-in-Verilog
url = https://github.com/nishthaparashar/Floating-Point-ALU-in-Verilog.git
[submodule "soc/rocket-chip"]
path = 08_soc/rocket-chip
url = https://github.com/chipsalliance/rocket-chip.git
[submodule "soc/riscv-mini"]
path = 08_soc/riscv-mini
url = https://github.com/ucb-bar/riscv-mini
[submodule "07_bus/gen_amba_2021"]
path = 07_bus/02_gen_amba
url = https://github.com/adki/gen_amba_2021.git