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marine_hud_sprite_inst.v
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marine_hud_sprite_inst.v
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// Copyright (C) 2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details.
// Generated by Quartus Prime Version 18.1 (Build Build 625 09/12/2018)
// Created on Sat Dec 03 17:20:06 2022
marine_hud_sprite marine_hud_sprite_inst
(
.read_address(read_address_sig) , // input [13:0] read_address_sig
.Clk(Clk_sig) , // input Clk_sig
.data_Out(data_Out_sig) // output [4:0] data_Out_sig
);