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<title>: Memory Management Status Registers</title>
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<b class="current">Memory Management Status Registers</b>
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<div><h2 id="a0000000025">2.11 Memory Management Status Registers</h2>
<p>In addition to the segmentation registers, on the PDP11/40 there are two memory management status registers: </p><dl class="description">
<dt>SR0</dt>
<dd><p>contains abort error flags and other essential information for the operating system. In particular memory management is enabled when bit 0 of SR0 is on; </p></dd>
<dt>SR2</dt>
<dd><p>is loaded with the 16 bit virtual address at the beginning of each instruction fetch. </p></dd>
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