[RISCV] Clear kill flags for FalseReg in foldVMergeToMask

Or we can't pass the MachineVerifier because of using a killed virtual
register.

This was found when backporting llvm#170070 to 21.x branch.

Author: wangpc-pp

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -834,6 +834,8 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
     MRI->constrainRegClass(
         MO.getReg(), True.getRegClassConstraint(MO.getOperandNo(), TII, TRI));
   }
+  // We should clear the IsKill flag since we have an use now.
+  MRI->clearKillFlags(FalseReg);
   MI.eraseFromParent();
 
   return true;

llvm/test/CodeGen/RISCV/rvv/vmerge-peephole.mir

@@ -157,7 +157,7 @@ body: |
     ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vmv0 = COPY [[PseudoVLM_V_B32_2]]
     ; CHECK-NEXT: [[PseudoVMERGE_VIM_M1_1:%[0-9]+]]:vrnov0 = PseudoVMERGE_VIM_M1 $noreg, [[PseudoVMV_V_I_M1_]], 1, killed [[COPY5]], -1, 5 /* e32 */
     ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1 $noreg, [[PseudoVMERGE_VIM_M1_]], [[PseudoVMERGE_VIM_M1_1]], -1, 5 /* e32 */, 3 /* ta, ma */
-    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vrnov0 = COPY killed [[PseudoVADD_VV_M1_]]
+    ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vrnov0 = COPY [[PseudoVADD_VV_M1_]]
     ; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 $noreg, [[PseudoVMERGE_VIM_M1_]], [[PseudoVMERGE_VIM_M1_1]], -1, 5 /* e32 */, 3 /* ta, ma */
     ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vmv0 = COPY [[PseudoVLM_V_B32_1]]
     ; CHECK-NEXT: [[PseudoVOR_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVOR_VV_M1_MASK [[PseudoVADD_VV_M1_]], [[COPY6]], killed [[COPY4]], [[COPY7]], -1, 5 /* e32 */, 1 /* ta, mu */