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Added reference benchmark project for Gowin IDE
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-14
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10 files changed

+92
-14
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‎benchmark_projects/gowin_benchmark/.gitignore

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#------------------------------------------------------------------------------
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# .gitignore for Gowin IDE
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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# INFO ------------------------------------------------------------------------
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# rename the file to ".gitignore" and place into your Gowin project directory
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#
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# junk files
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*.gprj.user
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impl/gwsynthesis/*.html
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impl/gwsynthesis/*.xml
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impl/gwsynthesis/*.log
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impl/gwsynthesis/*.vg
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# junk directories
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/impl/pnr
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/impl/temp
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‎benchmark_projects/gowin_benchmark/clean_gowin.bat

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@echo off
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rem ------------------------------------------------------------------------------
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rem clean_gowin.bat
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rem published as part of https://github.com/pConst/basic_verilog
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rem Konstantin Pavlov, pavlovconst@gmail.com
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rem ------------------------------------------------------------------------------
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rem Use this file as a boilerplate for your custom clean script
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rem for Gowin IDE projects
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rem preserving .\impl\gwsynthesis\test.prj file
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del /s /f /q .\impl\gwsynthesis\*.html
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del /s /f /q .\impl\gwsynthesis\*.xml
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del /s /f /q .\impl\gwsynthesis\*.log
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del /s /f /q .\impl\gwsynthesis\*.vg
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del /s /f /q .\impl\pnr\*
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rmdir /s /q .\impl\pnr\
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del /s /f /q .\impl\temp\*
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rmdir /s /q .\impl\temp\
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del /s /f /q .*.gprj.user
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pause
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goto :eof
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‎benchmark_projects/gowin_benchmark/gowin_benchmark.gprj

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<FileList>
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<File path="src/dynamic_delay.sv" type="file.verilog" enable="1"/>
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<File path="src/main.sv" type="file.verilog" enable="1"/>
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<File path="src/gowin_benchmark.cst" type="file.cst" enable="1"/>
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<File path="src/timing.sdc" type="file.sdc" enable="1"/>
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</FileList>
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</Project>

‎benchmark_projects/gowin_benchmark/gowin_benchmark.gprj.user

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<UserConfig>
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<Version>1.0</Version>
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<FlowState>
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<Process ID="Synthesis" State="2"/>
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<Process ID="Pnr" State="2"/>
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<Process ID="Gao" State="2"/>
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<Process ID="Synthesis" State="4"/>
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<Process ID="Pnr" State="4"/>
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<Process ID="Gao" State="4"/>
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<Process ID="Rtl_Gao" State="2"/>
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</FlowState>
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<ResultFileList>
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<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/gowin_benchmark.vg"/>
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<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/gowin_benchmark.fs"/>
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<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/gowin_benchmark.pin.html"/>
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<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/gowin_benchmark.power.html"/>
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<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/gowin_benchmark.rpt.html"/>
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<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/gowin_benchmark.tr.html"/>
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<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/gowin_benchmark_syn.rpt.html"/>
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<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/gowin_benchmark_syn_rsc.xml"/>
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</ResultFileList>
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<Ui>000000ff00000001fd00000002000000000000010000000282fc0200000001fc00000035000002820000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000140fc0100000001fc00000000000007800000000000fffffffaffffffff0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff00000000000000000000067c0000028200000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000</Ui>
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<Ui>000000ff00000001fd00000002000000000000010000000280fc0200000001fc00000037000002800000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f006300650073007303fffffeeb0000003c0000010000000269fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000140fc0100000001fc00000000000007800000000000fffffffaffffffff0100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000000000000000fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff00000000000000000000067c0000028000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000</Ui>
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</UserConfig>

‎benchmark_projects/gowin_benchmark/impl/gwsynthesis/gowin_benchmark.prj

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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-55C" package="PBGA1156" speed="7" partNumber="GW2A-LV55PG1156C7/I6"/>
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<FileList>
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<File path="J:\basic_verilog\benchmark_projects\gowin_benchmark\src\dynamic_delay.sv" type="verilog"/>
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<File path="J:\basic_verilog\benchmark_projects\gowin_benchmark\src\main.sv" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="dsp_balance" value="0"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="J:\basic_verilog\benchmark_projects\gowin_benchmark\impl\gwsynthesis\gowin_benchmark.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="1"/>
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<Option type="top_module" value="main"/>
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<Option type="verilog_language" value="sysv-2017"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>

‎benchmark_projects/gowin_benchmark/impl/project_process_config.json

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{
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"Allow_Duplicate_Modules" : false,
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"Annotated_Properties_for_Analyst" : true,
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"BACKGROUND_PROGRAMMING" : false,
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"BACKGROUND_PROGRAMMING" : "off",
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"COMPRESS" : false,
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"CRC_CHECK" : true,
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"Clock_Conversion" : true,
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"Generate_Post_Place_File" : false,
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"Generate_SDF_File" : false,
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"GwSyn_Loop_Limit" : 2000,
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"HOTBOOT" : false,
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"I2C" : false,
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"I2C_SLAVE_ADDR" : "00",
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"Implicit_Initial_Value_Support" : false,
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"IncludePath" : [
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],
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"Incremental_Compile" : "",
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"Initialize_Primitives" : false,
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"JTAG" : false,
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"MODE_IO" : false,
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"Number_of_Critical_Paths" : "",
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"Number_of_Start/End_Points" : "",
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"OUTPUT_BASE_NAME" : "gowin_benchmark",
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"POWER_ON_RESET" : false,
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"PRINT_BSRAM_VALUE" : true,
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"PROGRAM_DONE_BYPASS" : false,
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"Pipelining" : true,
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"PlaceInRegToIob" : true,
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"PlaceIoRegToIob" : true,
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"PlaceOutRegToIob" : true,
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"Place_Option" : "0",
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"Place_register_to_IOB" : true,
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"Process_Configuration_Verion" : "1.0",
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"Promote_Physical_Constraint_Warning_to_Error" : false,
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"Push_Tristates" : true,
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"Verilog_Standard" : "Vlg_Std_Sysv2017",
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"WAKE_UP" : "0",
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"Write_Vendor_Constraint_File" : true,
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"dsp_balance" : false
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"dsp_balance" : false,
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"show_all_warnings" : false
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}

‎benchmark_projects/gowin_benchmark/src/dynamic_delay.sv

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//--------------------------------------------------------------------------------
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// dynamic_delay.v
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// dynamic_delay.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//--------------------------------------------------------------------------------
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‎benchmark_projects/gowin_benchmark/src/gowin_benchmark.cst

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‎benchmark_projects/gowin_benchmark/src/main.sv

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//------------------------------------------------------------------------------
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// main.sv
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// published as part of https://github.com/pConst/basic_verilog
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// Konstantin Pavlov, pavlovconst@gmail.com
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//------------------------------------------------------------------------------
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// INFO ------------------------------------------------------------------------
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// Vivado benchmark project
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// Gowin benchmark project
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//
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// This project uses dynamic_delay.sv module to model both high-register count and
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// combinational-intensive design. See "Messages" tab for TOTAL time

‎benchmark_projects/gowin_benchmark/src/timing.sdc

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#------------------------------------------------------------------------------
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# timing.sdc
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# published as part of https://github.com/pConst/basic_verilog
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# Konstantin Pavlov, pavlovconst@gmail.com
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#------------------------------------------------------------------------------
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