[Bug] variables driven in multiple processes / assignment statements

[nblei]

module double_use
(
    clk : input logic,
)
{
    var a: logic;

    assign a = 1'bx;
    always_comb { a = 1'b0; }
    always_comb { a = 1'b1; }
    always_ff (clk) { a = 1'b0; }
    assign a = 1'bz;
}

Veryl emits:

module double_use_double_use (
    input logic clk
);
    logic a;

    assign a = 1'bx;
    always_comb begin
        a = 1'b0;
    end
    always_comb begin
        a = 1'b1;
    end
    always_ff @ (posedge clk) begin
        a <= 1'b0;
    end
    assign a = 1'bz;
endmodule

I think there is currently a lack of a mechanism to check if a variable is already being driven.