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This repository contains all the Verilog codes and their testbenches that I have compiled as a part of my academic journey in Electronics and Communication Engineering.

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varunram2001/VerliogCodes

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10's Complement Generator
10's Complement Generator
 
 
16:1 Multiplexer
16:1 Multiplexer
 
 
1:16 Demultiplexer
1:16 Demultiplexer
 
 
1:4 Demultiplexer
1:4 Demultiplexer
 
 
1:8 Demultiplexer
1:8 Demultiplexer
 
 
2 to 4 Decoder
2 to 4 Decoder
 
 
2's Complement Generator
2's Complement Generator
 
 
3 to 8 Decoder
3 to 8 Decoder
 
 
4 BIT SIPO Register
4 BIT SIPO Register
 
 
4 bit PIPO Register
4 bit PIPO Register
 
 
4 bit PISO register
4 bit PISO register
 
 
4 bit SISO register
4 bit SISO register
 
 
4 bit Wallace Tree Multiplier
4 bit Wallace Tree Multiplier
 
 
4 to 16 Decoder
4 to 16 Decoder
 
 
4-bit Comparator
4-bit Comparator
 
 
4-bit Counter
4-bit Counter
 
 
4:1 Multiplexer
4:1 Multiplexer
 
 
7 Segment Display
7 Segment Display
 
 
8 bit Adder
8 bit Adder
 
 
8 but PIPO Register
8 but PIPO Register
 
 
8-bit Booth Multiplier
8-bit Booth Multiplier
 
 
8:1 Multiplexer
8:1 Multiplexer
 
 
9's Complement Generator
9's Complement Generator
 
 
BCD to 7 Segment Decoder
BCD to 7 Segment Decoder
 
 
Barrel Shifter
Barrel Shifter
 
 
Binary to One Hot Coder
Binary to One Hot Coder
 
 
Bit Reversal Circuit
Bit Reversal Circuit
 
 
Braun Array Multiplier
Braun Array Multiplier
 
 
Carry Look Ahead Adder
Carry Look Ahead Adder
 
 
D Flip Flop
D Flip Flop
 
 
Decade Counter
Decade Counter
 
 
Dual Port RAM Design
Dual Port RAM Design
 
 
Full Adder
Full Adder
 
 
Full Wave Rectifier Signal Generator
Full Wave Rectifier Signal Generator
 
 
Gray to Binary Code Convertor
Gray to Binary Code Convertor
 
 
Half Adder
Half Adder
 
 
Half Wave Rectifier Signal Generator
Half Wave Rectifier Signal Generator
 
 
JK Flip Flop
JK Flip Flop
 
 
Johnson Counter
Johnson Counter
 
 
Logic Gate - AND Gate
Logic Gate - AND Gate
 
 
Logic Gate - NAND Gate
Logic Gate - NAND Gate
 
 
Logic Gate - NOR Gate
Logic Gate - NOR Gate
 
 
Logic Gate - NOT Gate
Logic Gate - NOT Gate
 
 
Logic Gate - OR Gate
Logic Gate - OR Gate
 
 
Logic Gate - XNOR Gate
Logic Gate - XNOR Gate
 
 
Logic Gate - XOR Gate
Logic Gate - XOR Gate
 
 
MAC (Multiplier and Accumulator) Circuit
MAC (Multiplier and Accumulator) Circuit
 
 
MOD 4 DOWN Counter
MOD 4 DOWN Counter
 
 
MOD 4 UP Counter
MOD 4 UP Counter
 
 
MOD 8 DOWN Counter
MOD 8 DOWN Counter
 
 
MOD 8 UP Counter
MOD 8 UP Counter
 
 
Mealey State Machine
Mealey State Machine
 
 
Moore State Machine
Moore State Machine
 
 
Negative Edge Detector
Negative Edge Detector
 
 
Overlapping Sequence Detector
Overlapping Sequence Detector
 
 
Positive Edge Detector
Positive Edge Detector
 
 
Ring Counter
Ring Counter
 
 
Ripple Carry Adder
Ripple Carry Adder
 
 
SR Flip Flop
SR Flip Flop
 
 
Single Port RAM Design
Single Port RAM Design
 
 
T flip flop
T flip flop
 
 
README.md
README.md
 
 
dataset.asdb
dataset.asdb
 
 
design.sv
design.sv
 
 

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VerliogCodes

This repository contains all the Verilog codes that I'm compiling as a part of my academic journey in Electronics and Communication Engineering.

The circuit diagrams for the respective folders will be added soon.

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This repository contains all the Verilog codes and their testbenches that I have compiled as a part of my academic journey in Electronics and Communication Engineering.

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verilog verilog-hdl

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