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sim-outorder.c
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/*
* sim-outorder.c - sample out-of-order issue perf simulator implementation
*
* This file is a part of the SimpleScalar tool suite written by
* Todd M. Austin as a part of the Multiscalar Research Project.
*
* The tool suite is currently maintained by Doug Burger and Todd M. Austin.
*
* Copyright (C) 1994, 1995, 1996, 1997, 1998 by Todd M. Austin
*
* This source file is distributed "as is" in the hope that it will be
* useful. The tool set comes with no warranty, and no author or
* distributor accepts any responsibility for the consequences of its
* use.
*
* Everyone is granted permission to copy, modify and redistribute
* this tool set under the following conditions:
*
* This source code is distributed for non-commercial use only.
* Please contact the maintainer for restrictions applying to
* commercial use.
*
* Permission is granted to anyone to make or distribute copies
* of this source code, either as received or modified, in any
* medium, provided that all copyright notices, permission and
* nonwarranty notices are preserved, and that the distributor
* grants the recipient permission for further redistribution as
* permitted by this document.
*
* Permission is granted to distribute this file in compiled
* or executable form under the same conditions that apply for
* source code, provided that either:
*
* A. it is accompanied by the corresponding machine-readable
* source code,
* B. it is accompanied by a written offer, with no time limit,
* to give anyone a machine-readable copy of the corresponding
* source code in return for reimbursement of the cost of
* distribution. This written offer must permit verbatim
* duplication by anyone, or
* C. it is distributed by someone who received only the
* executable form, and is accompanied by a copy of the
* written offer of source code that they received concurrently.
*
* In other words, you are welcome to use, share and improve this
* source file. You are forbidden to forbid anyone else to use, share
* and improve what you give them.
*
* INTERNET: dburger@cs.wisc.edu
* US Mail: 1210 W. Dayton Street, Madison, WI 53706
*
*
* Revision 1.1.1.1 2000/05/26 15:18:58 taustin
* SimpleScalar Tool Set
*
*
* Revision 1.7 1999/12/31 18:50:38 taustin
* quad_t naming conflicts removed
* added retirement tracing to sim-outorder (enable with -v)
* speculative execution should now be deterministic (uninit bugs fixed...)
* sim-outorder now stops after sim_num_insn
*
* Revision 1.6 1999/12/13 18:46:40 taustin
* cross endian execution support added
*
* Revision 1.5 1998/08/27 16:27:48 taustin
* implemented host interface description in host.h
* added target interface support
* added support for register and memory contexts
* instruction predecoding moved to loader module
* Alpha target support added
* added support for qword's
* added fault support
* added option ("-max:inst") to limit number of instructions analyzed
* explicit BTB sizing option added to branch predictors, use
* "-btb" option to configure BTB
* added queue statistics for IFQ, RUU, and LSQ; all terms of Little's
* law are measured and reports; also, measures fraction of cycles
* in which queue is full
* added fast forward option ("-fastfwd") that skips a specified number
* of instructions (using functional simulation) before starting timing
* simulation
* sim-outorder speculative loads no longer allocate memory pages,
* this significantly reduces memory requirements for programs with
* lots of mispeculation (e.g., cc1)
* branch predictor updates can now optionally occur in ID, WB,
* or CT
* added target-dependent myprintf() support
* fixed speculative qword store bug (missing most significant word)
* sim-outorder now computes correct result when non-speculative register
* operand is first defined speculative within the same inst
* speculative fault handling simplified
* dead variable "no_ea_dep" removed
*
* Revision 1.4 1997/04/16 22:10:23 taustin
* added -commit:width support (from kskadron)
* fixed "bad l2 D-cache parms" fatal string
*
* Revision 1.3 1997/03/11 17:17:06 taustin
* updated copyright
* `-pcstat' option support added
* long/int tweaks made for ALPHA target support
* better defaults defined for caches/TLBs
* "mstate" command supported added for DLite!
* supported added for non-GNU C compilers
* buglet fixed in speculative trace generation
* multi-level cache hierarchy now supported
* two-level predictor supported added
* I/D-TLB supported added
* many comments added
* options package supported added
* stats package support added
* resource configuration options extended
* pipetrace support added
* DLite! support added
* writeback throttling now supported
* decode and issue B/W now decoupled
* new and improved (and more precise) memory scheduler added
* cruft for TLB paper removed
*
* Revision 1.1 1996/12/05 18:52:32 taustin
* Initial revision
*
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <signal.h>
#include "host.h"
#include "misc.h"
#include "machine.h"
#include "regs.h"
#include "memory.h"
#include "cache.h"
#include "loader.h"
#include "syscall.h"
#include "bpred.h"
#include "resource.h"
#include "bitmap.h"
#include "options.h"
#include "eval.h"
#include "stats.h"
#include "ptrace.h"
#include "dlite.h"
#include "sim.h"
/* added for Wattch */
#include "power.h"
/* Leakage: includes */
#include "cache_leak_ctrl.h"
#include "leakage.h"
#define DLITE_SUPPORT
#if defined(GLOBAL_LRU)
void setup_lru_status(struct cache_t *cp);
#endif /* defined(GLOBAL_LRU) */
extern int print_total_access();
#ifndef decayed_cache
#define decayed_cache cache_dl1
#endif
/*********************************************************************************
*********************************************************************************/
int b_in_dispatch = FALSE;
float step_increase, step_decrease;
extern int update_cache_stats();
extern int update_cache_decay();
int b_decay_enabled = FALSE;
int b_decay_profile_enabled = FALSE;
int global_counter_max, local_counter_max;
int slow_counter, fast_counter;
int sample_interval;
unsigned int skip_start;
md_addr_t cur_pc;
int global_LRU_off_ratio; /* turn off % of the LRU cache lines */
/*********************************************************************************
*********************************************************************************/
/*
* This file implements a very detailed out-of-order issue superscalar
* processor with a two-level memory system and speculative execution support.
* This simulator is a performance simulator, tracking the latency of all
* pipeline operations.
*/
/*
* simulator options
*/
/* simulated registers */
static struct regs_t regs;
/* simulated memory */
static struct mem_t *mem = NULL;
/* maximum number of inst's to execute */
static unsigned int max_insts;
/* number of insts skipped before timing starts */
static unsigned int fastfwd_count;
/* pipeline trace range and output filename */
static int ptrace_nelt = 0;
static char *ptrace_opts[2];
/* instruction fetch queue size (in insts) */
static int ruu_ifq_size;
/* extra branch mis-prediction latency */
static int ruu_branch_penalty;
/* speed of front-end of machine relative to execution core */
static int fetch_speed;
/* branch predictor type {nottaken|taken|perfect|bimod|2lev} */
static char *pred_type;
/* bimodal predictor config (<table_size>) */
static int bimod_nelt = 1;
int bimod_config[1] =
{ /* bimod tbl size */4096 };
/* 2-level predictor config (<l1size> <l2size> <hist_size> <xor>) */
static int twolev_nelt = 4;
int twolev_config[4] =
{ /* l1size */1024, /* l2size */1024, /* hist */10, /* xor */FALSE};
/* combining predictor config (<meta_table_size> */
static int comb_nelt = 1;
int comb_config[1] =
{ /* meta_table_size */4096 };
/* return address stack (RAS) size */
int ras_size = 32;
/* BTB predictor config (<num_sets> <associativity>) */
static int btb_nelt = 2;
int btb_config[2] =
{ /* nsets */1024, /* assoc */4 };
/* instruction decode B/W (insts/cycle) */
int ruu_decode_width;
/* instruction issue B/W (insts/cycle) */
int ruu_issue_width;
/* run pipeline with in-order issue */
static int ruu_inorder_issue;
/* issue instructions down wrong execution paths */
static int ruu_include_spec = TRUE;
/* instruction commit B/W (insts/cycle) */
int ruu_commit_width;
/* register update unit (RUU) size */
int RUU_size = 8;
/* load/store queue (LSQ) size */
int LSQ_size = 4;
/* l1 data cache config, i.e., {<config>|none} */
static char *cache_dl1_opt;
/* l1 data cache hit latency (in cycles) */
static int cache_dl1_lat;
/* l2 data cache config, i.e., {<config>|none} */
static char *cache_dl2_opt;
/* l2 data cache hit latency (in cycles) */
static int cache_dl2_lat;
/* l1 instruction cache config, i.e., {<config>|dl1|dl2|none} */
static char *cache_il1_opt;
/* l1 instruction cache hit latency (in cycles) */
static int cache_il1_lat;
/* l2 instruction cache config, i.e., {<config>|dl1|dl2|none} */
static char *cache_il2_opt;
/* l2 instruction cache hit latency (in cycles) */
static int cache_il2_lat;
/* flush caches on system calls */
static int flush_on_syscalls;
/* convert 64-bit inst addresses to 32-bit inst equivalents */
static int compress_icache_addrs;
/* memory access latency (<first_chunk> <inter_chunk>) */
static int mem_nelt = 2;
static int mem_lat[2] =
{ /* lat to first chunk */97, /* lat between remaining chunks */1 };
/* memory access bus width (in bytes) */
static int mem_bus_width;
/* instruction TLB config, i.e., {<config>|none} */
static char *itlb_opt;
/* data TLB config, i.e., {<config>|none} */
static char *dtlb_opt;
/* inst/data TLB miss latency (in cycles) */
static int tlb_miss_lat;
/* total number of integer ALU's available */
int res_ialu;
/* total number of integer multiplier/dividers available */
static int res_imult;
/* total number of memory system ports available (to CPU) */
int res_memport;
/* total number of floating point ALU's available */
int res_fpalu;
/* total number of floating point multiplier/dividers available */
int res_fpmult;
/* options for Wattch */
int data_width = 64;
/* static power model results */
extern power_result_type power;
/* counters added for Wattch */
counter_t rename_access=0;
counter_t bpred_access=0;
counter_t window_access=0;
counter_t lsq_access=0;
counter_t regfile_access=0;
counter_t icache_access=0;
counter_t dcache_access=0;
counter_t dcache2_access=0;
counter_t alu_access=0;
counter_t ialu_access=0;
counter_t falu_access=0;
counter_t resultbus_access=0;
counter_t window_preg_access=0;
counter_t window_selection_access=0;
counter_t window_wakeup_access=0;
counter_t lsq_store_data_access=0;
counter_t lsq_load_data_access=0;
counter_t lsq_preg_access=0;
counter_t lsq_wakeup_access=0;
counter_t window_total_pop_count_cycle=0;
counter_t window_num_pop_count_cycle=0;
counter_t lsq_total_pop_count_cycle=0;
counter_t lsq_num_pop_count_cycle=0;
counter_t regfile_total_pop_count_cycle=0;
counter_t regfile_num_pop_count_cycle=0;
counter_t resultbus_total_pop_count_cycle=0;
counter_t resultbus_num_pop_count_cycle=0;
/* text-based stat profiles */
#define MAX_PCSTAT_VARS 8
static int pcstat_nelt = 0;
static char *pcstat_vars[MAX_PCSTAT_VARS];
/* convert 64-bit inst text addresses to 32-bit inst equivalents */
#ifdef TARGET_PISA
#define IACOMPRESS(A) \
(compress_icache_addrs ? ((((A) - ld_text_base) >> 1) + ld_text_base) : (A))
#define ISCOMPRESS(SZ) \
(compress_icache_addrs ? ((SZ) >> 1) : (SZ))
#else /* !TARGET_PISA */
#define IACOMPRESS(A) (A)
#define ISCOMPRESS(SZ) (SZ)
#endif /* TARGET_PISA */
/* operate in backward-compatible bugs mode (for testing only) */
static int bugcompat_mode;
/*
* functional unit resource configuration
*/
/* resource pool indices, NOTE: update these if you change FU_CONFIG */
#define FU_IALU_INDEX 0
#define FU_IMULT_INDEX 1
#define FU_MEMPORT_INDEX 2
#define FU_FPALU_INDEX 3
#define FU_FPMULT_INDEX 4
/* resource pool definition, NOTE: update FU_*_INDEX defs if you change this */
struct res_desc fu_config[] = {
{
"integer-ALU",
4,
0,
{
{ IntALU, 1, 1 }
}
},
{
"integer-MULT/DIV",
1,
0,
{
{ IntMULT, 3, 1 },
{ IntDIV, 20, 19 }
}
},
{
"memory-port",
2,
0,
{
{ RdPort, 1, 1 },
{ WrPort, 1, 1 }
}
},
{
"FP-adder",
4,
0,
{
{ FloatADD, 2, 1 },
{ FloatCMP, 2, 1 },
{ FloatCVT, 2, 1 }
}
},
{
"FP-MULT/DIV",
1,
0,
{
{ FloatMULT, 4, 1 },
{ FloatDIV, 12, 12 },
{ FloatSQRT, 24, 24 }
}
},
};
/*
* simulator stats
*/
/* SLIP variable */
static counter_t sim_slip = 0;
/* total number of instructions executed */
static counter_t sim_total_insn = 0;
/* total number of memory references committed */
static counter_t sim_num_refs = 0;
/* total number of memory references executed */
static counter_t sim_total_refs = 0;
/* total number of loads committed */
static counter_t sim_num_loads = 0;
/* total number of loads executed */
static counter_t sim_total_loads = 0;
/* total number of branches committed */
static counter_t sim_num_branches = 0;
/* total number of branches executed */
static counter_t sim_total_branches = 0;
/* cycle counter */
tick_t sim_cycle = 0;
/* occupancy counters */
static counter_t IFQ_count; /* cumulative IFQ occupancy */
static counter_t IFQ_fcount; /* cumulative IFQ full count */
static counter_t RUU_count; /* cumulative RUU occupancy */
static counter_t RUU_fcount; /* cumulative RUU full count */
static counter_t LSQ_count; /* cumulative LSQ occupancy */
static counter_t LSQ_fcount; /* cumulative LSQ full count */
/* total non-speculative bogus addresses seen (debug var) */
static counter_t sim_invalid_addrs;
/*
* simulator state variables
*/
/* instruction sequence counter, used to assign unique id's to insts */
static unsigned int inst_seq = 0;
/* pipetrace instruction sequence counter */
static unsigned int ptrace_seq = 0;
/* speculation mode, non-zero when mis-speculating, i.e., executing
instructions down the wrong path, thus state recovery will eventually have
to occur that resets processor register and memory state back to the last
precise state */
static int spec_mode = FALSE;
/* cycles until fetch issue resumes */
static unsigned ruu_fetch_issue_delay = 0;
/* perfect prediction enabled */
static int pred_perfect = FALSE;
/* speculative bpred-update enabled */
static char *bpred_spec_opt;
static enum { spec_ID, spec_WB, spec_CT } bpred_spec_update;
/* level 1 instruction cache, entry level instruction cache */
struct cache_t *cache_il1;
/* level 1 instruction cache */
struct cache_t *cache_il2;
/* level 1 data cache, entry level data cache */
struct cache_t *cache_dl1;
/* level 2 data cache */
struct cache_t *cache_dl2;
/* instruction TLB */
struct cache_t *itlb;
/* data TLB */
struct cache_t *dtlb;
/* branch predictor */
static struct bpred_t *pred;
/* functional unit resource pool */
static struct res_pool *fu_pool = NULL;
/* text-based stat profiles */
static struct stat_stat_t *pcstat_stats[MAX_PCSTAT_VARS];
static counter_t pcstat_lastvals[MAX_PCSTAT_VARS];
static struct stat_stat_t *pcstat_sdists[MAX_PCSTAT_VARS];
/* wedge all stat values into a counter_t */
#define STATVAL(STAT) \
((STAT)->sc == sc_int \
? (counter_t)*((STAT)->variant.for_int.var) \
: ((STAT)->sc == sc_uint \
? (counter_t)*((STAT)->variant.for_uint.var) \
: ((STAT)->sc == sc_counter \
? *((STAT)->variant.for_counter.var) \
: (panic("bad stat class"), 0))))
/*********************************************************************************
*********************************************************************************/
void reg_options_decay(struct opt_odb_t *odb)
{
opt_reg_float(odb, "-step:increase", "increase step.",
&step_increase, 2.0, /* print */TRUE, /* default format */NULL);
opt_reg_float(odb, "-step:decrease", "decrease step.",
&step_decrease, 2.0, /* print */TRUE, /* default format */NULL);
opt_reg_int(odb, "-global:counter",
"global counter limit",
&global_counter_max, /* default */8192,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-local:counter",
"local counter limit",
&local_counter_max, /* default */3,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-slow:counter",
"slow counter limit",
&slow_counter, /* default */0,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-fast:counter",
"fast counter limit",
&fast_counter, /* default */0,
/* print */TRUE, /* format */NULL);
opt_reg_uint(odb, "-skip:start",
"ignore start cycles",
&skip_start, /* default */0,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-sample:interval",
"sample interval",
&sample_interval, /* default */100,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-global:LRU",
"off ratio of global LRU scheme",
&global_LRU_off_ratio, /* default */0,
/* print */TRUE, /* format */NULL);
}/* reg_options */
/*********************************************************************************
*********************************************************************************/
/* memory access latency, assumed to not cross a page boundary */
static unsigned int /* total latency of access */
mem_access_latency(int blk_sz) /* block size accessed */
{
int chunks = (blk_sz + (mem_bus_width - 1)) / mem_bus_width;
assert(chunks > 0);
return (/* first chunk latency */mem_lat[0] +
(/* remainder chunk latency */mem_lat[1] * (chunks - 1)));
}
/*
* cache miss handlers
*/
/* l1 data cache l1 block miss handler function */
static unsigned int /* latency of block access */
dl1_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
md_addr_t baddr, /* block address to access */
int bsize, /* size of block to access */
struct cache_blk_t *blk, /* ptr to block in upper level */
tick_t now) /* time of access */
{
unsigned int lat;
if (cache_dl2)
{
/* access next level of data cache hierarchy */
lat = cache_access(cache_dl2, cmd, baddr, NULL, bsize,
/* now */now, /* pudata */NULL, /* repl addr */NULL);
/* Wattch -- Dcache2 access */
dcache2_access++;
if (cmd == Read)
return lat;
else
{
/* FIXME: unlimited write buffers */
return 0;
}
}
else
{
/* access main memory */
if (cmd == Read)
return mem_access_latency(bsize);
else
{
/* FIXME: unlimited write buffers */
return 0;
}
}
}
/* l2 data cache block miss handler function */
static unsigned int /* latency of block access */
dl2_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
md_addr_t baddr, /* block address to access */
int bsize, /* size of block to access */
struct cache_blk_t *blk, /* ptr to block in upper level */
tick_t now) /* time of access */
{
/* Wattch -- main memory access -- Wattch-FIXME (offchip) */
/* this is a miss to the lowest level, so access main memory */
if (cmd == Read)
return mem_access_latency(bsize);
else
{
/* FIXME: unlimited write buffers */
return 0;
}
}
/* l1 inst cache l1 block miss handler function */
static unsigned int /* latency of block access */
il1_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
md_addr_t baddr, /* block address to access */
int bsize, /* size of block to access */
struct cache_blk_t *blk, /* ptr to block in upper level */
tick_t now) /* time of access */
{
unsigned int lat;
if (cache_il2)
{
/* access next level of inst cache hierarchy */
lat = cache_access(cache_il2, cmd, baddr, NULL, bsize,
/* now */now, /* pudata */NULL, /* repl addr */NULL);
/* Wattch -- Dcache2 access */
dcache2_access++;
if (cmd == Read)
return lat;
else
panic("writes to instruction memory not supported");
}
else
{
/* access main memory */
if (cmd == Read)
return mem_access_latency(bsize);
else
panic("writes to instruction memory not supported");
}
}
/* l2 inst cache block miss handler function */
static unsigned int /* latency of block access */
il2_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
md_addr_t baddr, /* block address to access */
int bsize, /* size of block to access */
struct cache_blk_t *blk, /* ptr to block in upper level */
tick_t now) /* time of access */
{
/* Wattch -- main memory access -- Wattch-FIXME (offchip) */
/* this is a miss to the lowest level, so access main memory */
if (cmd == Read)
return mem_access_latency(bsize);
else
panic("writes to instruction memory not supported");
}
/*
* TLB miss handlers
*/
/* inst cache block miss handler function */
static unsigned int /* latency of block access */
itlb_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
md_addr_t baddr, /* block address to access */
int bsize, /* size of block to access */
struct cache_blk_t *blk, /* ptr to block in upper level */
tick_t now) /* time of access */
{
md_addr_t *phy_page_ptr = (md_addr_t *)blk->user_data;
/* no real memory access, however, should have user data space attached */
assert(phy_page_ptr);
/* fake translation, for now... */
*phy_page_ptr = 0;
/* return tlb miss latency */
return tlb_miss_lat;
}
/* data cache block miss handler function */
static unsigned int /* latency of block access */
dtlb_access_fn(enum mem_cmd cmd, /* access cmd, Read or Write */
md_addr_t baddr, /* block address to access */
int bsize, /* size of block to access */
struct cache_blk_t *blk, /* ptr to block in upper level */
tick_t now) /* time of access */
{
md_addr_t *phy_page_ptr = (md_addr_t *)blk->user_data;
/* no real memory access, however, should have user data space attached */
assert(phy_page_ptr);
/* fake translation, for now... */
*phy_page_ptr = 0;
/* return tlb miss latency */
return tlb_miss_lat;
}
/* register simulator-specific options */
void
sim_reg_options(struct opt_odb_t *odb)
{
opt_reg_header(odb,
"sim-outorder: This simulator implements a very detailed out-of-order issue\n"
"superscalar processor with a two-level memory system and speculative\n"
"execution support. This simulator is a performance simulator, tracking the\n"
"latency of all pipeline operations.\n"
);
/* instruction limit */
opt_reg_uint(odb, "-max:inst", "maximum number of inst's to execute",
&max_insts, /* default */0,
/* print */TRUE, /* format */NULL);
/* trace options */
opt_reg_uint(odb, "-fastfwd", "number of insts skipped before timing starts",
&fastfwd_count, /* default */0,
/* print */TRUE, /* format */NULL);
opt_reg_string_list(odb, "-ptrace",
"generate pipetrace, i.e., <fname|stdout|stderr> <range>",
ptrace_opts, /* arr_sz */2, &ptrace_nelt, /* default */NULL,
/* !print */FALSE, /* format */NULL, /* !accrue */FALSE);
opt_reg_note(odb,
" Pipetrace range arguments are formatted as follows:\n"
"\n"
" {{@|#}<start>}:{{@|#|+}<end>}\n"
"\n"
" Both ends of the range are optional, if neither are specified, the entire\n"
" execution is traced. Ranges that start with a `@' designate an address\n"
" range to be traced, those that start with an `#' designate a cycle count\n"
" range. All other range values represent an instruction count range. The\n"
" second argument, if specified with a `+', indicates a value relative\n"
" to the first argument, e.g., 1000:+100 == 1000:1100. Program symbols may\n"
" be used in all contexts.\n"
"\n"
" Examples: -ptrace FOO.trc #0:#1000\n"
" -ptrace BAR.trc @2000:\n"
" -ptrace BLAH.trc :1500\n"
" -ptrace UXXE.trc :\n"
" -ptrace FOOBAR.trc @main:+278\n"
);
/* ifetch options */
opt_reg_int(odb, "-fetch:ifqsize", "instruction fetch queue size (in insts)",
&ruu_ifq_size, /* default */8,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-fetch:mplat", "extra branch mis-prediction latency",
&ruu_branch_penalty, /* default */2,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-fetch:speed",
"speed of front-end of machine relative to execution core",
&fetch_speed, /* default */1,
/* print */TRUE, /* format */NULL);
/* branch predictor options */
opt_reg_note(odb,
" Branch predictor configuration examples for 2-level predictor:\n"
" Configurations: N, M, W, X\n"
" N # entries in first level (# of shift register(s))\n"
" W width of shift register(s)\n"
" M # entries in 2nd level (# of counters, or other FSM)\n"
" X (yes-1/no-0) xor history and address for 2nd level index\n"
" Sample predictors:\n"
" GAg : 1, W, 2^W, 0\n"
" GAp : 1, W, M (M > 2^W), 0\n"
" PAg : N, W, 2^W, 0\n"
" PAp : N, W, M (M == 2^(N+W)), 0\n"
" gshare : 1, W, 2^W, 1\n"
" Predictor `comb' combines a bimodal and a 2-level predictor.\n"
);
opt_reg_string(odb, "-bpred",
"branch predictor type {nottaken|taken|perfect|bimod|2lev|comb}",
&pred_type, /* default */"comb",
/* print */TRUE, /* format */NULL);
opt_reg_int_list(odb, "-bpred:bimod",
"bimodal predictor config (<table size>)",
bimod_config, bimod_nelt, &bimod_nelt,
/* default */bimod_config,
/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
opt_reg_int_list(odb, "-bpred:2lev",
"2-level predictor config "
"(<l1size> <l2size> <hist_size> <xor>)",
twolev_config, twolev_nelt, &twolev_nelt,
/* default */twolev_config,
/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
opt_reg_int_list(odb, "-bpred:comb",
"combining predictor config (<meta_table_size>)",
comb_config, comb_nelt, &comb_nelt,
/* default */comb_config,
/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
opt_reg_int(odb, "-bpred:ras",
"return address stack size (0 for no return stack)",
&ras_size, /* default */ras_size,
/* print */TRUE, /* format */NULL);
opt_reg_int_list(odb, "-bpred:btb",
"BTB config (<num_sets> <associativity>)",
btb_config, btb_nelt, &btb_nelt,
/* default */btb_config,
/* print */TRUE, /* format */NULL, /* !accrue */FALSE);
opt_reg_string(odb, "-bpred:spec_update",
"speculative predictors update in {ID|WB} (default non-spec)",
&bpred_spec_opt, /* default */NULL,
/* print */TRUE, /* format */NULL);
/* next miss predictor options */
opt_reg_note(odb,
" Next miss predictor configuration examples for 2-level predictor:\n"
" Configurations: N, M, W, X\n"
" N # entries in first level (# of shift register(s))\n"
" W width of shift register(s)\n"
" M # entries in 2nd level (# of counters, or other FSM)\n"
" X (yes-1/no-0) xor history and address for 2nd level index\n"
" Sample predictors:\n"
" GAg : 1, W, 2^W, 0\n"
" GAp : 1, W, M (M > 2^W), 0\n"
" PAg : N, W, 2^W, 0\n"
" PAp : N, W, M (M == 2^(N+W)), 0\n"
" gshare : 1, W, 2^W, 1\n"
" Predictor `comb' combines a bimodal and a 2-level predictor.\n"
);
/* decode options */
opt_reg_int(odb, "-decode:width",
"instruction decode B/W (insts/cycle)",
&ruu_decode_width, /* default */4,
/* print */TRUE, /* format */NULL);
/* issue options */
opt_reg_int(odb, "-issue:width",
"instruction issue B/W (insts/cycle)",
&ruu_issue_width, /* default */4,
/* print */TRUE, /* format */NULL);
opt_reg_flag(odb, "-issue:inorder", "run pipeline with in-order issue",
&ruu_inorder_issue, /* default */FALSE,
/* print */TRUE, /* format */NULL);
opt_reg_flag(odb, "-issue:wrongpath",
"issue instructions down wrong execution paths",
&ruu_include_spec, /* default */TRUE,
/* print */TRUE, /* format */NULL);
/* commit options */
opt_reg_int(odb, "-commit:width",
"instruction commit B/W (insts/cycle)",
&ruu_commit_width, /* default */4,
/* print */TRUE, /* format */NULL);
/* register scheduler options */
opt_reg_int(odb, "-ruu:size",
"register update unit (RUU) size",
&RUU_size, /* default */80,
/* print */TRUE, /* format */NULL);
/* memory scheduler options */
opt_reg_int(odb, "-lsq:size",
"load/store queue (LSQ) size",
&LSQ_size, /* default */40,
/* print */TRUE, /* format */NULL);
/* cache options */
opt_reg_string(odb, "-cache:dl1",
"l1 data cache config, i.e., {<config>|none}",
&cache_dl1_opt, "dl1:1024:32:1:l",