-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathleakinit.c
2255 lines (1709 loc) · 70.9 KB
/
leakinit.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/* ***************************************************************
The following is the license agreement for all components in this
archive with exceptions listed in Section II.
I. LICENSE
Copyright (c)2003 Dharmesh Parikh, Yan Zhang, Karthik Sankaranarayanan, Kevin Skadron, and
Mircea R. Stan. All rights reserved.
Permission is hereby granted, without written agreement and without
license or royalty fees, to use, copy, modify, and distribute this
software and its documentation for any purpose, provided that the
above copyright notice and the following four paragraphs appear in all
copies of this software, whether in binary form or not.
IN NO EVENT SHALL THE AUTHORS, THE UNIVERSITY OF VIRGINIA, OR THE
STATE OF VIRGINIA BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE
OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THEY HAVE BEEN ADVISED
OF THE POSSIBILITY OF SUCH DAMAGE.
THE AUTHORS, THE UNIVERSITY OF VIRGINIA, AND THE STATE OF VIRGINIA
SPECIFICALLY DISCLAIM ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND
THE AUTHORS HAVE NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT,
UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
NEITHER THE NAME OF ANY VIRGINIA ENTITY NOR THE NAMES OF THE
CONTRIBUTORS MAY BE USED TO ENDORSE OR PROMOTE PRODUCTS
DERIVED FROM THIS SOFTWARE WITHOUT SPECIFIC PRIOR WRITTEN
PERMISSION.
If you use this software or a modified version of it, please cite the
following paper or an appropriate updated version by the same authors:
Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. R. Stan. "HotLeakage: An
Architectural, Temperature-Aware Model of Subthreshold and Gate
Leakage". University of Virginia Dept. of Computer Science
Tech. Report CS-2003-05, Mar. 2003.
II. EXCEPTIONS
SimpleScalar
------------
SimpleScalar simulators, tools, and functions are held under license by
SimpleScalar LLC. SimpleScalar is licensed under the following terms.
SimpleScalar Tool Suite
(c)1994-2001 Todd M. Austin, Ph.D. and SimpleScalar, LLC
All Rights Reserved.
THIS IS A LEGAL DOCUMENT
BY USING SIMPLESCALAR,
YOU ARE AGREEING TO THESE TERMS AND CONDITIONS.
No portion of this work may be used by any commercial entity, or
for any commercial purpose, without the prior, written permission
of SimpleScalar, LLC (info@simplescalar.com). Nonprofit and
noncommercial use is permitted as described below.
1. SimpleScalar is provided AS IS, with no warranty of any kind,
express or implied. The user of the program accepts full
responsibility for the application of the program and the use of any
results.
2. Nonprofit and noncommercial use is encouraged. SimpleScalar
may be downloaded, compiled, executed, copied, and modified
solely for nonprofit, educational, noncommercial research, and
noncommercial scholarship purposes provided that this notice in its
entirety accompanies all copies. Copies of the modified software
can be delivered to persons who use it solely for nonprofit,
educational, noncommercial research, and noncommercial
scholarship purposes provided that this notice in its entirety
accompanies all copies.
3. ALL COMMERCIAL USE, AND ALL USE BY FOR PROFIT
ENTITIES, IS EXPRESSLY PROHIBITED WITHOUT A LICENSE
FROM SIMPLESCALAR, LLC (info@simplescalar.com).
4. No nonprofit user may place any restrictions on the use of this
software, including as modified by the user, by any other authorized
user.
5. Noncommercial and nonprofit users may distribute copies of
SimpleScalar in compiled or executable form as set forth in Section
2, provided that either: (A) it is accompanied by the corresponding
machine-readable source code, or (B) it is accompanied by a
written offer, with no time limit, to give anyone a machine-readable
copy of the corresponding source code in return for reimbursement
of the cost of distribution. This written offer must permit verbatim
duplication by anyone, or (C) it is distributed by someone who
received only the executable form, and is accompanied by a copy of
the written offer of source code.
6. SimpleScalar was developed by Todd M. Austin, Ph.D. The tool
suite is currently maintained by SimpleScalar LLC
(info@simplescalar.com). US Mail: 2395 Timbercrest Court, Ann
Arbor, MI 48105.
Copyright (c)1994-2001 by Todd M. Austin, Ph.D. and SimpleScalar, LLC.
Wattch
------
Wattch is a microarchitectural power model built on top of
simplescalar. At the time this document was written, there were no
licensing restrictions on Wattch itself, but users should check the Wattch homepage at
http://www.ee.princeton.edu/~dbrooks/wattch-form.html
Wattch is built on SimpleScalar and CACTI and hence is still subject to the
licensing terms associated with those software releases.
CACTI
-----
CACTI is subject to the following licensing terms.
Copyright 1994 Digital Equipment Corporation and Steve Wilton, All
Rights Reserved
Permission to use, copy, and modify this software and its documentation is
hereby granted only under the following terms and conditions. Both the
above copyright notice and this permission notice must appear in all copies
of the software, derivative works or modified versions, and any portions
thereof, and both notices must appear in supporting documentation.
Users of this software agree to the terms and conditions set forth herein,
and hereby grant back to Digital a non-exclusive, unrestricted, royalty-
free right and license under any changes, enhancements or extensions
made to the core functions of the software, including but not limited to
those affording compatibility with other hardware or software
environments, but excluding applications which incorporate this software.
Users further agree to use their best efforts to return to Digital any
such changes, enhancements or extensions that they make and inform Digital
of noteworthy uses of this software. Correspondence should be provided
to Digital at:
Director of Licensing
Western Research Laboratory
Digital Equipment Corporation
100 Hamilton Avenue
Palo Alto, California 94301
This software may be distributed (but not offered for sale or transferred
for compensation) to third parties, provided such third parties agree to
abide by the terms and conditions of this notice.
THE SOFTWARE IS PROVIDED "AS IS" AND DIGITAL EQUIPMENT CORP. DISCLAIMS ALL
WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL DIGITAL EQUIPMENT
CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
OF THIS SOFTWARE
Cache Decay
-----------
Our functions to implement various forms of cache leakage control are
based on the original cache-decay codebase provided by Zhigang Hu and
Margaret Martonosi of Princeton University and Stefanos Kaxiras of
Agere Corp. This code consists chiefly of the functions
update_cache_stats(), update_cache_decay(),
update_cache_block_stats_when_hit(),
update_cache_block_stats_when_miss(), and various other changes in
sim-outorder.c and cache.c. These Princeton/Agere modifications are
subject to the following license terms:
This software is provided subject to the following terms and
conditions, which you should read carefully before using the
software. Using this software indicates your acceptance of these terms
and conditions. If you do not agree with these terms and conditions,
do not use the software.
Copyright (c) 2002,2003 Agere Systems
All rights reserved.
Redistribution and use in source or binary forms, with or
without modifications, are permitted provided that the
following conditions are met:
- Redistributions of source code must retain the above
copyright notice, this list of conditions and the
following Disclaimer in comments in the code as well as
in the documentation and/or other materials provided with
the distribution.
- Redistributions in binary form must reproduce the above
copyright notice, this list of conditions and the following
Disclaimer in the documentation and/or other materials
provided with the distribution.
- Neither the name of Agere Systems nor the names of the
contributors may be used to endorse or promote products
derived from this software without specific prior written
permission.
Disclaimer:
THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
WARRANTIES, INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE ARE DISCLAIMED. ANY USE, MODIFICATION OR DISTRIBUTION OF
THIS SOFTWARE IS SOLELY AT THE USER'S OWN RISK. IN NO EVENT SHALL
AGERE SYSTEMS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED
TO, CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*************************************************************** */
/*
*
* Revision 0.91
* HotLeakage Leakage Modeling Tool
* Leakage power calculation for the TAG arrays
of all the caches fixed (With feedback from Ruchira Sasanka)
* Leakage power for copmarators and mux-drivers
fixed for all the caches.
*
*/
#include <math.h>
#include "leakage.h"
#include "power.h"
#include "options.h"
#include "misc.h"
extern double GEN_POWER_FACTOR ;
extern double CSCALE; /* wire capacitance scaling factor */
extern double RSCALE ;/* wire resistance scaling factor */
extern double LSCALE ; /* length (feature) scaling factor */
extern double ASCALE ; /* area scaling factor */
extern double VSCALE ; /* voltage scaling factor */
extern double VTSCALE ; /* threshold voltage scaling factor */
extern double SSCALE ; /* sense voltage scaling factor */
extern double TECH_LENGTH ; /* TECH LENGTH */
extern double Mhz ;
extern double GEN_POWER_SCALE ;
/*
* CMOS 0.8um model parameters
* - from Appendix II of Cacti tech report
*/
/* corresponds to 8um of m3 @ 225ff/um */
extern double Cwordmetal ;
/*extern double Corresponds to 16um of m2 @ 275ff/um */
extern double Cbitmetal ;
/* corresponds to 1um of m2 @ 275ff/um */
extern double Cmetal ;
extern double CM3metal ;
extern double CM2metal ;
/* Cmetal 1.222e-15 */
/* fF/um2 at 1.5V */
extern double Cndiffarea ; /* FIXME: ??? */
/* fF/um2 at 1.5V */
extern double Cpdiffarea ; /* FIXME: ??? */
/* fF/um at 1.5V */
extern double Cndiffside ; /* in general this does not scale */
/* fF/um at 1.5V */
extern double Cpdiffside ; /* in general this does not scale */
/* fF/um at 1.5V */
extern double Cndiffovlp ; /* FIXME: by depth??? */
/* fF/um at 1.5V */
extern double Cpdiffovlp ; /* FIXME: by depth??? */
/* fF/um assuming 25% Miller effect */
extern double Cnoxideovlp ; /* FIXME: by depth??? */
/* fF/um assuming 25% Miller effect */
extern double Cpoxideovlp ; /* FIXME: by depth??? */
/* um */
extern double Leff ;
/* fF/um2 */
extern double Cgate ; /* FIXME: ??? */
/* fF/um2 */
extern double Cgatepass ; /* FIXME: ??? */
/* note that the value ofextern double Cgatepass will be different depending on
whether or not the source and drain are at different potentials or
the same potential. The two values were averaged */
/* fF/um */
extern double Cpolywire ;
/* ohms*um of channel width */
extern double Rnchannelstatic ;
/* ohms*um of channel width */
extern double Rpchannelstatic ;
extern double Rnchannelon ;
extern double Rpchannelon;
/* corresponds to 16um of m2 @ 48mO/sq */
extern double Rbitmetal ;
/* corresponds to 8um of m3 @ 24mO/sq */
extern double Rwordmetal;
extern double Vdd ;
/* other stuff (from tech report, appendix 1) */
extern double Period ;
extern double krise ;
extern double tsensedata ;
extern double tsensetag ;
extern double tfalldata;
extern double tfalltag;
extern double Vbitpre ;
extern double Vt ;
extern double Vbitsense ;
extern double AF ;
extern double POPCOUNT_AF ;
/* Threshold voltages (as a proportion of Vdd)
If you don't know them, set all values to 0.5 */
extern double VSINV ;
extern double VTHINV100x60 ; /* inverter with p00,n0 */
extern double VTHNAND60x90 ; /* nand with p=60 and three n=90 */
extern double VTHNOR12x4x1 ; /* nor with p=12, n=4, 1 input */
extern double VTHNOR12x4x2 ; /* nor with p=12, n=4, 2 inputs */
extern double VTHNOR12x4x3 ; /* nor with p=12, n=4, 3 inputs */
extern double VTHNOR12x4x4 ; /* nor with p=12, n=4, 4 inputs */
extern double VTHOUTDRINV ;
extern double VTHOUTDRNOR ;
extern double VTHOUTDRNAND ;
extern double VTHOUTDRIVE ;
extern double VTHCOMPINV ;
extern double VTHMUXDRV1 ;
extern double VTHMUXDRV2 ;
extern double VTHMUXDRV3 ;
extern double VTHEVALINV ;
extern double VTHSENSEEXTDRV ;
/* transistor widths in um (as described in tech report, appendix 1) */
extern double Wdecdrivep ;
extern double Wdecdriven ;
extern double Wdec3to8n ;
extern double Wdec3to8p ;
extern double WdecNORn ;
extern double WdecNORp ;
extern double Wdecinvn ;
extern double Wdecinvp ;
extern double Wworddrivemax ;
extern double Wmemcella ;
extern double Wmemcellr ;
extern double Wmemcellw ;
extern double Wmemcellbscale ; /* means 2x bigger than Wmemcella */
extern double Wbitpreequ ;
extern double Wbitmuxn ;
extern double WsenseQ1to4 ;
extern double Wcompinvp1 ;
extern double Wcompinvn1 ;
extern double Wcompinvp2 ;
extern double Wcompinvn2 ;
extern double Wcompinvp3 ;
extern double Wcompinvn3 ;
extern double Wevalinvp ;
extern double Wevalinvn ;
extern double Wcompn ;
extern double Wcompp ;
extern double Wcomppreequ ;
extern double Wmuxdrv12n ;
extern double Wmuxdrv12p ;
extern double WmuxdrvNANDn ;
extern double WmuxdrvNANDp ;
extern double WmuxdrvNORn ;
extern double WmuxdrvNORp ;
extern double Wmuxdrv3n ;
extern double Wmuxdrv3p ;
extern double Woutdrvseln ;
extern double Woutdrvselp ;
extern double Woutdrvnandn ;
extern double Woutdrvnandp ;
extern double Woutdrvnorn ;
extern double Woutdrvnorp ;
extern double Woutdrivern ;
extern double Woutdriverp ;
extern double Wcompcellpd2 ;
extern double Wcompdrivern ;
extern double Wcompdriverp ;
extern double Wcomparen2 ;
extern double Wcomparen1 ;
extern double Wmatchpchg ;
extern double Wmatchinvn ;
extern double Wmatchinvp ;
extern double Wmatchnandn ;
extern double Wmatchnandp ;
extern double Wmatchnorn ;
extern double Wmatchnorp ;
extern double WSelORn ;
extern double WSelORprequ ;
extern double WSelPn ;
extern double WSelPp ;
extern double WSelEnn ;
extern double WSelEnp ;
extern double Wsenseextdrv1p ;
extern double Wsenseextdrv1n ;
extern double Wsenseextdrv2p ;
extern double Wsenseextdrv2n ;
/* bit width of RAM cell in um */
extern double BitWidth ;
/* bit height of RAM cell in um */
extern double BitHeight ;
extern double Cout ;
/* Sizing of cells and spacings */
extern double RatCellHeight ;
extern double RatCellWidth ;
extern double RatShiftRegWidth ;
extern double RatNumShift ;
extern double BitlineSpacing ;
extern double WordlineSpacing ;
extern double RegCellHeight ;
extern double RegCellWidth ;
extern double CamCellHeight ;
extern double CamCellWidth ;
extern double MatchlineSpacing ;
extern double TaglineSpacing ;
/* ALU POWER NUMBERS for .18um 733Mhz */
/* normalize to cap from W */
extern double NORMALIZE_SCALE ;
/* normalize .18um cap to other gen's cap, then xPowerfactor */
extern double POWER_SCALE ;
extern double I_ADD ;
extern double I_ADD32 ;
extern double I_MULT16 ;
extern double I_SHIFT ;
extern double I_LOGIC ;
extern double F_ADD ;
extern double F_MULT ;
extern double I_ADD_CLOCK ;
extern double I_MULT_CLOCK ;
extern double I_SHIFT_CLOCK ;
extern double I_LOGIC_CLOCK ;
extern double F_ADD_CLOCK ;
extern double F_MULT_CLOCK ;
/* HotLeakage */
/*
* options for Leakage
*/
double tech_length0;
double M0n ; /* Zero Bias Mobility for N-Type */
double M0p ; /* Zero Bias Mobility for P-Type */
double Tox ;
double Cox ; /* Gate Oxide Capacitance per unit area */
double Vnoff0 ; /* Empirically Determined Model Parameter for N-Type */
/* FIX ME */
double Vpoff0 ; /* Empirically Determined Model Parameter for P-Type */
double Nfix ; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) */
double Pfix ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) */
double Vthn ; /* In the equation Voff = Vnoff0 +Nfix*(Vth0-Vthn) */
double Vthp ; /* In the equation Voff = Vpoff0 +Pfix*(Vth0-Vthp) */
double Vnthx ; /* In the Equation Vth = Vth0 +Vnthx*(T-300) */
double Vpthx ; /* In the Equation Vth = Vth0 +Vpthx*(T-300) */
double Vdd_init ; /* Default Vdd. Can be Changed in leakage.c */
double Volt0 ;
double Na ; /* Empirical param for the Vdd fit */
double Nb ; /* Empirical param for the Vdd fit */
double Pa ; /* Empirical param for the Vdd fit */
double Pb ; /* Empirical param for the Vdd fit */
double NEta ; /* Sub-threshold Swing Co-efficient N-Type */
double PEta ; /* Sub-threshold Swing Co-efficient P-Type */
double Kdesign_3in_nand ;
double Kdesign_2in_nand_outdrv ;
double Kdesign_2in_nor_outdrv ;
double Kdesign_2in_nor_mux_driver ;
double Kdesign_comparator ;
double Kdesign_sensamp ;
double Kdesign_ireg_readbitline ;
double Kdesigp_ireg_readbitline ;
double Kndesign_3in_nand ;
double in3_nandn_t_slope ;
double in3_nandn_vdd_slope ;
double Kpdesign_3in_nand ;
double in3_nandp_t_slope ;
double in3_nandp_vdd_slope ;
double Kndesign_2in_nand_outdrv ;
double in2_nandn_outdrv_t_slope ;
double in2_nandn_outdrv_vdd_slope ;
double Kpdesign_2in_nand_outdrv ;
double in2_nandp_outdrv_t_slope ;
double in2_nandp_outdrv_vdd_slope ;
/* NOR gate of decoder*/
double Kndesign_4in_nor_decoder ;
double in4_norn_decoder_t_slope ;
double in4_norn_decoder_vdd_slope;
double Kpdesign_4in_nor_decoder ;
double in4_norp_decoder_t_slope;
double in4_norp_decoder_vdd_slope ;
double Kndesign_3in_nor_decoder ;
double in3_norn_decoder_t_slope ;
double in3_norn_decoder_vdd_slope ;
double Kpdesign_3in_nor_decoder ;
double in3_norp_decoder_t_slope ;
double in3_norp_decoder_vdd_slope ;
double Kndesign_2in_nor_decoder ;
double in2_norn_decoder_t_slope;
double in2_norn_decoder_vdd_slope ;
double Kpdesign_2in_nor_decoder ;
double in2_norp_decoder_t_slope ;
double in2_norp_decoder_vdd_slope ;
double Kndesign_2in_nor_mux_driver ;
double in2_norn_mux_driver_t_slope ;
double in2_norn_mux_driver_vdd_slope ;
double Kpdesign_2in_nor_mux_driver ;
double in2_norp_mux_driver_t_slope ;
double in2_norp_mux_driver_vdd_slope ;
double Kndesign_2in_nor_outdrv ;
double in2_norn_outdrv_t_slope ;
double in2_norn_outdrv_vdd_slope;
double Kpdesign_2in_nor_outdrv ;
double in2_norp_outdrv_t_slope ;
double in2_norp_outdrv_vdd_slope ;
double Kndesign_comparator ;
double Kpdesign_comparator ;
double Kndesign_sensamp ;
double Kpdesign_sensamp ;
double Kndesign_ireg_readbitline ;
double Kpdesigp_ireg_readbitline ;
/* gate Vss */
double Vth0_gate_vss ;
double aspect_gate_vss;
/*drowsy cache*/
double Vdd_low ;
/*RBB*/
double k1_body_n ;
double k1_body_p ;
double vfi ;
double VSB_NMOS ;
double VSB_PMOS ;
/* dual VT*/
double Vt_cell_nmos_high ;
double Vt_cell_pmos_high ;
double Vt_bit_nmos_low ;
double Vt_bit_pmos_low ;
/* Gate lekage for 70nm */
double nmos_unit_leakage ;
double a_nmos_vdd ;
double b_nmos_t;
double c_nmos_tox;
double pmos_unit_leakage;
double a_pmos_vdd ;
double b_pmos_t ;
double c_pmos_tox ;
double L_nmos_d ; /* Adjusting Factor for Length */
double Tox_nmos_e ; /* Adjusting Factor for Tox */
double L_pmos_d ; /* Adjusting Factor for Length */
double Tox_pmos_e ; /* Adjusting Factor for Tox */
/* level 1 instruction cache, entry level instruction cache */
extern struct cache_t *cache_il1;
/* level 2 instruction cache */
extern struct cache_t *cache_il2;
/* level 1 data cache, entry level data cache */
extern struct cache_t *cache_dl1;
/* level 2 data cache */
extern struct cache_t *cache_dl2;
extern leakage_power_type leakage_power;
/* instruction issue B/W (insts/cycle) */
extern int ruu_issue_width;
/* Technology Length */
extern char *TECH_FACTOR;
/* Tox Given */
double Tox_User;
/* Tox variation */
double Tox_Std;
/* Vdd Variation */
double Vdd_Std;
/* Tech Length Variation */
double Tech_Std;
/* Threshold Voltage Nmos Variation */
double Vthn_Std;
/* Threshold Voltage Pmos Variation */
double Vthp_Std;
/* Number of Samples to be Generated for the Box-Mueller Method */
int No_of_Samples;
/* Aspect Ratio Ireg Access Cell N */
double aspect_ratio_access_ireg_cell_N;
/* Aspect Ratio Ireg Cell N */
double aspect_ratio_ireg_cell_l2_N;
/* Aspect Ratio Ireg Cell P */
double aspect_ratio_ireg_cell_l3_P;
/* Aspect Ratio Ram Access Cell N */
double aspect_ratio_access_ram_cell_N;
/* Aspect Ratio Ram Cell N */
double aspect_ratio_ram_cell_l2_N;
/* Aspect Ratio Ram Cell P */
double aspect_ratio_ram_cell_l3_P;
/* Aspect Ratio Decoder Inverter P */
double aspect_ratio_decoder_inverter_P;
/* Aspect Ratio Decoder Inverter N */
double aspect_ratio_decoder_inverter_N;
/* Aspect Ratio of Comparator Inverter4 N */
double aspect_ratio_comparator_inverter4_N;
/* Aspect Ratio of Comparator Inverter4 P */
double aspect_ratio_comparator_inverter4_P;
/* Aspect Ratio of Comparator Inverter3 N */
double aspect_ratio_comparator_inverter3_N;
/* Aspect Ratio of Comparator Inverter3 P */
double aspect_ratio_comparator_inverter3_P;
/* Aspect Ratio of Comparator Inverter2 N */
double aspect_ratio_comparator_inverter2_N;
/* Aspect Ratio of Comparator Inverter2 P */
double aspect_ratio_comparator_inverter2_P;
/* Aspect Ratio of Comparator Inverter1 N */
double aspect_ratio_comparator_inverter1_N;
/* Aspect Ratio of Comparator Inverter4 P */
double aspect_ratio_comparator_inverter1_P;
/* Aspect Ratio of Comparator Inverter P */
double aspect_ratio_comparator_P;
/* Aspect Ratio of Comparator Inverter N */
double aspect_ratio_comparator_N;
/* Aspect Ratio of MUX DRIVER STAGE 1 N */
double aspect_ratio_muxdrv12_N;
/* Aspect Ratio of MUX DRIVER STAGE 1 P */
double aspect_ratio_muxdrv12_P;
/* Aspect Ratio of MUX DRIVER STAGE 2 N */
double aspect_ratio_muxdrvNOR_N;
/* Aspect Ratio of MUX DRIVER STAGE 1 P */
double aspect_ratio_muxdrvNOR_P;
/* Aspect Ratio of MUX DRIVER STAGE 3 N */
double aspect_ratio_muxdrv3_N;
/* Aspect Ratio of MUX DRIVER STAGE 3 P */
double aspect_ratio_muxdrv3_P;
/* Aspect Ratio of OUTPUT DRIVER STAGE 1 N */
double aspect_ratio_outdrvsel_N;
/* Aspect Ratio of OUTPUT DRIVER STAGE 1 P */
double aspect_ratio_outdrvsel_P;
/* Aspect Ratio of OUTPUT DRIVER NOR N */
double aspect_ratio_outdrvnor_N;
/* Aspect Ratio of OUTPUT DRIVER NOR P */
double aspect_ratio_outdrvnor_P;
/* Aspect Ratio of OUTPUT DRIVER NAND N */
double aspect_ratio_outdrvnand_N;
/* Aspect Ratio of OUTPUT DRIVER NAND P */
double aspect_ratio_outdrvnand_P;
/* Aspect Ratio of OUTPUT DRIVER FINAL STAGE N */
double aspect_ratio_outdriver_N;
/* Aspect Ratio of OUTPUT DRIVER FINAL STAGE P */
double aspect_ratio_outdriver_P;
/* Ports for L1-ICache (both read and write) */
double il1_ports;
/* Ports for L2-ICache (both read and write) */
double il2_ports;
/* Ports for L1-DCache (both read and write) */
double dl1_ports;
/* Ports for L2-DCache (both read and write) */
double dl2_ports;
/* Ports for read Ireg */
double ireg_read_ports;
/* Ports for write Ireg */
double ireg_write_ports;
/* Supply Voltage for L1-ICaches */
double Vdd_I_Reg;
/* Zero Bias Threshold Voltage for Ireg Cell N-Mos */
double Vth0N_Cell_I_Reg;
/* Zero Bias Threshold Voltage for Ireg Cell P-Mos */
double Vth0P_Cell_I_Reg;
/* Zero Bias Threshold Voltage for Ireg Access N-Mos */
double Vth0N_Access_I_Reg;
/* Temperature in Absolute Kelvin for Ireg */
double Tkelvin_I_Reg;
/* Supply Voltage for L1-ICaches */
double Vdd_L1_ICache;
/* Supply Voltage for L1-DCaches */
double Vdd_L1_DCache;
/* Zero Bias Threshold Voltage for L1-ICaches Cell N-Mos */
double Vth0N_Cell_L1_ICache;
/* Zero Bias Threshold Voltage for L1-ICaches Cell P-Mos */
double Vth0P_Cell_L1_ICache;
/* Zero Bias Threshold Voltage for L1-ICaches Access N-Mos */
double Vth0N_Access_L1_ICache;
/* Zero Bias Threshold Voltage for L1-DCaches P-Mos */
double Vth0P_L1_DCache;
/* Zero Bias Threshold Voltage for L1-ICaches P-Mos */
double Vth0P_L1_ICache;
/* Zero Bias Threshold Voltage for L1-DCaches Cell N-Mos */
double Vth0N_Cell_L1_DCache;
/* Zero Bias Threshold Voltage for L1-DCaches Cell P-Mos */
double Vth0P_Cell_L1_DCache;
/* Zero Bias Threshold Voltage for L1-DCaches Access N-Mos */
double Vth0N_Access_L1_DCache;
/* Supply Voltage for L2-ICaches */
double Vdd_L2_ICache;
/* Supply Voltage for L2-DCaches */
double Vdd_L2_DCache;
/* Zero Bias Threshold Voltage for L2-ICaches Access N-Mos */
double Vth0N_Access_L2_ICache;
/* Zero Bias Threshold Voltage for L2-ICaches Cell N-Mos */
double Vth0N_Cell_L2_ICache;
/* Zero Bias Threshold Voltage for L2-ICaches Cell P-Mos */
double Vth0P_Cell_L2_ICache;
/* Zero Bias Threshold Voltage for L2-DCaches P-Mos */
double Vth0P_L2_DCache;
/* Zero Bias Threshold Voltage for L2-ICaches P-Mos */
double Vth0P_L2_ICache;
/* Zero Bias Threshold Voltage for L2-DCaches Cell N-Mos */
double Vth0N_Cell_L2_DCache;
/* Zero Bias Threshold Voltage for L2-DCaches Cell P-Mos */
double Vth0P_Cell_L2_DCache;
/* Zero Bias Threshold Voltage for L2-DCaches Access N-Mos */
double Vth0N_Access_L2_DCache;
/* Temperature in Absolute Kelvin for L1-ICaches */
double Tkelvin_L1_ICache;
/* Temperature in Absolute Kelvin for L1-DCaches */
double Tkelvin_L1_DCache;
/* Temperature in Absolute Kelvin for L2-ICaches */
double Tkelvin_L2_ICache;
/* Temperature in Absolute Kelvin for L2-DCaches */
double Tkelvin_L2_DCache;
void sim_reg_leak_options(struct opt_odb_t *odb)
{
/* HotLeakage */
/* HotLeakage options */
opt_reg_double(odb, "-ireg:read_ports",
"ireg file read ports",
&ireg_read_ports, /* default */(2*ruu_issue_width),
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-ireg:write_ports",
"ireg file write ports",
&ireg_write_ports, /* default */(ruu_issue_width),
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-ireg:temp",
"ireg file temperature in Kelvin ",
&Tkelvin_I_Reg, /* default */300.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-il1:ports",
"l1 instruction cache ports",
&il1_ports, /* default */2.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-il2:ports",
"l2 instruction cache ports",
&il2_ports, /* default */2.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-dl1:ports",
"l1 data cache ports",
&dl1_ports, /* default */2.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-dl2:ports",
"l2 data cache ports",
&dl2_ports, /* default */2.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-il1:temp",
"l1 instruction cache temperature in Kelvin ",
&Tkelvin_L1_ICache, /* default */300.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-il2:temp",
"l2 instruction cache temperature in Kelvin ",
&Tkelvin_L2_ICache, /* default */300.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-dl1:temp",
"l1 data cache temperature in Kelvin ",
&Tkelvin_L1_DCache, /* default */300.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-dl2:temp",
"l2 data cache temperature in Kelvin ",
&Tkelvin_L2_DCache, /* default */300.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-tox:var",
"Tox Std Variation",
&Tox_Std , /* default */0.00 ,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-vdd:var",
"Vdd Std Variation",
&Vdd_Std , /* default */0.00 ,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-length:var",
"Tech Length Std Variation",
&Tech_Std , /* default */0.00 ,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-threshold_n:var",
"Threshold Nmos Variation",
&Vthn_Std , /* default */0.00 ,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-threshold_p:var",
"Threshold Pmos Variation",
&Vthp_Std , /* default */0.00 ,
/* print */TRUE, /* format */NULL);
opt_reg_int(odb, "-samples:boxm",
"samples for box-mueller method",
&No_of_Samples, /* default */10000,
/* print */TRUE, /* format */NULL);
if (!mystricmp(TECH_FACTOR, "TECH_180"))
{
opt_reg_double(odb, "-tox",
"Tox",
&Tox_User, /* default */3.5E-9,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-ireg:voltage",
"ireg file supply voltage ",
&Vdd_I_Reg, /* default */2.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-ireg:threshold_Cell_N",
"ireg file threshold voltage N-Type Cell ",
&Vth0N_Cell_I_Reg, /* default */0.3979,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-ireg:threshold_Cell_P",
"ireg file threshold voltage P-Type Cell ",
&Vth0P_Cell_I_Reg, /* default */0.4659,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-ireg:threshold_Access_N",
"ireg file threshold voltage N-Type Bitline ",
&Vth0N_Access_I_Reg, /* default */0.3979,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-il1:voltage",
"l1 instruction cache supply voltage ",
&Vdd_L1_ICache, /* default */2.0,
/* print */TRUE, /* format */NULL);
opt_reg_double(odb, "-il2:voltage",
"l2 instruction cache supply voltage ",
&Vdd_L2_ICache, /* default */2.0,