|
1 | | -# awesome-opensource-eda |
| 1 | +# awesome-hardware-tools |
| 2 | + |
| 3 | +A curated list of awesome (open source) hardware tools. |
| 4 | + |
| 5 | +* Category |
| 6 | +* Alphabetical (per category) |
| 7 | +* Requirements |
| 8 | + * open source |
| 9 | + * useful (working) |
| 10 | +* Optional, include year of founding in parentheses |
| 11 | +* Up to 3 bullets per company (confirmed company reps only) |
| 12 | +* All entries must be confirmed with repository link |
| 13 | +* Max 80 char line width |
| 14 | + |
| 15 | +## Compilers |
| 16 | + |
| 17 | +* [ACT](https://github.com/asyncvlsi/act) |
| 18 | +* [Amaranth](https://github.com/amaranth-lang/amaranth) |
| 19 | +* [bsc](https://github.com/B-Lang-org/bsc) |
| 20 | +* [Calyx](https://github.com/cucapra/calyx) |
| 21 | +* [Chisel](https://github.com/chipsalliance/chisel3) |
| 22 | +* [Circt](https://github.com/llvm/circt) |
| 23 | +* [Circuitgraph](https://github.com/circuitgraph/circuitgraph) |
| 24 | +* [Clash](https://github.com/clash-lang/clash-compiler) |
| 25 | +* [Cocoon](https://github.com/pku-dasys/cocoon) |
| 26 | +* [Coreir](https://github.com/rdaly525/coreir) |
| 27 | +* [DFiant](https://github.com/DFiantHDL/DFiant) |
| 28 | +* [FIRRTL](https://github.com/chipsalliance/firrtl) |
| 29 | +* [Halide](https://github.com/halide/Halide) |
| 30 | +* [Halide-to-hardware](https://github.com/StanfordAHA/Halide-to-Hardware) |
| 31 | +* [hdlconvertor](https://github.com/Nic30/hdlConvertor) |
| 32 | +* [LiveHD](https://github.com/masc-ucsc/livehd) |
| 33 | +* [LLHD](https://github.com/fabianschuiki/llhd) |
| 34 | +* [Magma](https://github.com/phanrahan/magma/) |
| 35 | +* [Matchlib](https://github.com/NVlabs/matchlib) |
| 36 | +* [MyHDL](https://github.com/myhdl/myhdl) |
| 37 | +* [PandA](https://github.com/ferrandi/PandA-bambu) |
| 38 | +* [PipelineC](https://github.com/JulianKemmerer/PipelineC) |
| 39 | +* [PyGears](https://github.com/bogdanvuk/pygears) |
| 40 | +* [pymtl3](https://github.com/pymtl/pymtl3) |
| 41 | +* [PyRTL](https://github.com/UCSBarchlab/PyRTL) |
| 42 | +* [PyVerilog](https://github.com/PyHDI/Pyverilog) |
| 43 | +* [Rohd](https://github.com/intel/rohd) |
| 44 | +* [silice](https://github.com/sylefeb/Silice) |
| 45 | +* [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL) |
| 46 | +* [Spydrnet](https://github.com/byuccl/spydrnet) |
| 47 | +* [Surelog](https://github.com/chipsalliance/Surelog) |
| 48 | +* [sv-parser](https://github.com/dalance/sv-parser) |
| 49 | +* [sv2v](https://github.com/zachjs/sv2v) |
| 50 | +* [Symbolator](https://github.com/kevinpt/symbolator) |
| 51 | +* [UHDM](https://github.com/chipsalliance/UHDM) |
| 52 | +* [Verible](https://github.com/chipsalliance/verible) |
| 53 | +* [Veriloggen](https://github.com/PyHDI/veriloggen) |
| 54 | +* [Verik](https://github.com/frwang96/verik) |
| 55 | +* [XLS](https://github.com/google/xls) |
| 56 | + |
| 57 | +## Build Systems |
| 58 | + |
| 59 | +* [Bender](https://github.com/pulp-platform/bender) |
| 60 | +* [datc](https://github.com/jinwookjungs/datc_robust_design_flow) |
| 61 | +* [Edalize](https://github.com/olofk/edalize) |
| 62 | +* [Fusesoc](https://github.com/olofk/fusesoc) |
| 63 | +* [Hammer](https://github.com/ucb-bar/hammer) |
| 64 | +* [hwtBuildsystem](https://github.com/Nic30/hwtBuildsystem) |
| 65 | +* [legoHDL](https://github.com/c-rus/legoHDL) |
| 66 | +* [mflowgen](https://github.com/mflowgen/mflowgen) |
| 67 | +* [SiliconCompiler](https://github.com/siliconcompiler/siliconcompiler) |
| 68 | + |
| 69 | +## Formal Verification |
| 70 | + |
| 71 | +* [Boolector](https://github.com/boolector/boolector) |
| 72 | +* [cvc5](https://github.com/cvc5/cvc5) |
| 73 | +* [Pono](https://github.com/upscale-project/pono) |
| 74 | +* [SymbiYosys](https://github.com/YosysHQ/sby) |
| 75 | +* [Z3](https://github.com/Z3Prover/z3) |
| 76 | + |
| 77 | +## Simulators |
| 78 | + |
| 79 | +* [ghdl](https://github.com/ghdl/ghdl) |
| 80 | +* [icarus](https://github.com/steveicarus/iverilog.git) |
| 81 | +* [ngspice](http://ngspice.sourceforge.net/) |
| 82 | +* [Qucs](https://github.com/Qucs/qucs) |
| 83 | +* [Verilator](https://github.com/verilator/verilator) |
| 84 | +* [Xyce](https://github.com/Xyce/Xyce) |
| 85 | + |
| 86 | +## Generators |
| 87 | + |
| 88 | +* [bag](https://github.com/ucb-art/BAG_framework) |
| 89 | +* [ESP](https://github.com/sld-columbia/esp) |
| 90 | +* [FABulous](https://github.com/FPGA-Research-Manchester/FABulous) |
| 91 | +* [FASoC](https://github.com/idea-fasoc/fasoc) |
| 92 | +* [garnet](https://github.com/StanfordAHA/garnet) |
| 93 | +* [gemmini](https://github.com/ucb-bar/gemmini) |
| 94 | +* [lake](https://github.com/StanfordAHA/lake) |
| 95 | +* [LiteX](https://github.com/enjoy-digital/litex) |
| 96 | +* [openfpga](https://github.com/lnis-uofu/OpenFPGA) |
| 97 | +* [prga](https://github.com/PrincetonUniversity/prga) |
| 98 | +* [pymtl3-net](https://github.com/cornell-brg/pymtl3-net) |
| 99 | +* [rggen](https://github.com/rggen/rggen) |
| 100 | +* [Rocket Chip](https://github.com/chipsalliance/rocket-chip) |
| 101 | +* [spiral](https://github.com/spiral-software/spiral-software) |
| 102 | +* [SystemRDL](https://github.com/SystemRDL/systemrdl-compiler) |
| 103 | +* [kaktus2dev](https://github.com/kactus2/kactus2dev) |
| 104 | + |
| 105 | +## Verification |
| 106 | + |
| 107 | +* [anasysmod](https://github.com/sgherbst/anasymod) |
| 108 | +* [Cocotb](https://github.com/cocotb/cocotb) |
| 109 | +* [libsystemctlm-soc](https://github.com/Xilinx/libsystemctlm-soc) |
| 110 | +* [msdsl](https://github.com/sgherbst/msdsl) |
| 111 | +* [pyuvm](https://github.com/pyuvm/pyuvm) |
| 112 | +* [svreal](https://github.com/sgherbst/svreal) |
| 113 | +* [vunit](https://github.com/VUnit/vunit) |
| 114 | + |
| 115 | +## Waveform viewers |
| 116 | + |
| 117 | +* [gtkwave](https://github.com/gtkwave/gtkwave) |
| 118 | +* [ILAng](https://github.com/PrincetonUniversity/ILAng) |
| 119 | +* [Konata](https://github.com/shioyadan/Konata) |
| 120 | +* [simview](https://github.com/pieter3d/simview) |
| 121 | +* [Sootty](https://github.com/Ben1152000/sootty) |
| 122 | +* [wavedrom](https://github.com/wavedrom/wavedrom) |
| 123 | +* [wavedrompy](https://github.com/wallento/wavedrompy) |
| 124 | +* [puselview](https://github.com/sigrokproject/pulseview) |
| 125 | +* [sigrok-cli](https://github.com/sigrokproject/sigrok-cli) |
| 126 | + |
| 127 | +## Schematic Entry |
| 128 | + |
| 129 | +* [xschem](https://github.com/StefanSchippers/xschem) |
| 130 | + |
| 131 | +## Board Design |
| 132 | + |
| 133 | +* [Boardview](https://github.com/whitequark/kicad-boardview) |
| 134 | +* [datasheet-scrubber](https://github.com/idea-fasoc/datasheet-scrubber) |
| 135 | +* [KiCad](https://github.com/KiCad/kicad-source-mirror) |
| 136 | +* [Pinion](https://github.com/yaqwsx/Pinion) |
| 137 | +* [PCBDraw](https://github.com/yaqwsx/PcbDraw) |
| 138 | +* [Pinout](https://github.com/j0ono0/pinout) |
| 139 | +* [Skidl](https://github.com/devbisme/skidl) |
| 140 | + |
| 141 | +## Synthesis |
| 142 | + |
| 143 | +* [ABC](https://github.com/berkeley-abc/abc) |
| 144 | +* [LSOracle](https://github.com/lnis-uofu/LSOracle) |
| 145 | +* [lstools](https://github.com/lsils/lstools-showcase) |
| 146 | +* [mockturtle](https://github.com/lsils/mockturtle) |
| 147 | +* [Yosys](https://github.com/YosysHQ/yosys) |
| 148 | + |
| 149 | +## ASIC Layout |
| 150 | + |
| 151 | +* [Align](https://github.com/ALIGN-analoglayout/ALIGN-public) |
| 152 | +* [DREAMPlace](https://github.com/limbo018/DREAMPlace) |
| 153 | +* [gds3d](https://github.com/trilomix/GDS3D) |
| 154 | +* [gdsfactory](https://github.com/gdsfactory/gdsfactory) |
| 155 | +* [gdstk](https://github.com/heitzmann/gdstk) |
| 156 | +* [gdspy](https://github.com/heitzmann/gdspy) |
| 157 | +* [klayout](https://github.com/KLayout/klayout) |
| 158 | +* [magic](https://github.com/RTimothyEdwards/magic) |
| 159 | +* [magical](https://github.com/magical-eda/MAGICAL) |
| 160 | +* [netgen](https://github.com/RTimothyEdwards/netgen) |
| 161 | +* [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD) |
| 162 | +* [PHIDL](https://github.com/amccaugh/phidl) |
| 163 | + |
| 164 | +## FPGA Layout |
| 165 | + |
| 166 | +* [nextpnr](https://github.com/YosysHQ/nextpnr) |
| 167 | +* [VTR](https://github.com/verilog-to-routing/vtr-verilog-to-routing) |
| 168 | + |
| 169 | +## Benchmark Circuits |
| 170 | + |
| 171 | +* [opdb](https://github.com/PrincetonUniversity/OPDB) |
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