First batch of open source tools

README.md

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-# awesome-opensource-eda
+# awesome-hardware-tools
+
+A curated list of awesome (open source) hardware tools.
+
+* Category
+* Alphabetical (per category)
+* Requirements
+	* open source
+	* useful (working)
+* Optional, include year of founding in parentheses
+* Up to 3 bullets per company (confirmed company reps only)
+* All entries must be confirmed with repository link
+* Max 80 char line width
+
+## Compilers
+
+* [ACT](https://github.com/asyncvlsi/act)
+* [Amaranth](https://github.com/amaranth-lang/amaranth)
+* [bsc](https://github.com/B-Lang-org/bsc)
+* [Calyx](https://github.com/cucapra/calyx)
+* [Chisel](https://github.com/chipsalliance/chisel3)
+* [Circt](https://github.com/llvm/circt)
+* [Circuitgraph](https://github.com/circuitgraph/circuitgraph)
+* [Clash](https://github.com/clash-lang/clash-compiler)
+* [Cocoon](https://github.com/pku-dasys/cocoon)
+* [Coreir](https://github.com/rdaly525/coreir)
+* [DFiant](https://github.com/DFiantHDL/DFiant)
+* [FIRRTL](https://github.com/chipsalliance/firrtl)
+* [Halide](https://github.com/halide/Halide)
+* [Halide-to-hardware](https://github.com/StanfordAHA/Halide-to-Hardware)
+* [hdlconvertor](https://github.com/Nic30/hdlConvertor)
+* [LiveHD](https://github.com/masc-ucsc/livehd)
+* [LLHD](https://github.com/fabianschuiki/llhd)
+* [Magma](https://github.com/phanrahan/magma/)
+* [Matchlib](https://github.com/NVlabs/matchlib)
+* [MyHDL](https://github.com/myhdl/myhdl)
+* [PandA](https://github.com/ferrandi/PandA-bambu)
+* [PipelineC](https://github.com/JulianKemmerer/PipelineC)
+* [PyGears](https://github.com/bogdanvuk/pygears)
+* [pymtl3](https://github.com/pymtl/pymtl3)
+* [PyRTL](https://github.com/UCSBarchlab/PyRTL)
+* [PyVerilog](https://github.com/PyHDI/Pyverilog)
+* [Rohd](https://github.com/intel/rohd)
+* [silice](https://github.com/sylefeb/Silice)
+* [SpinalHDL](https://github.com/SpinalHDL/SpinalHDL)
+* [Spydrnet](https://github.com/byuccl/spydrnet)
+* [Surelog](https://github.com/chipsalliance/Surelog)
+* [sv-parser](https://github.com/dalance/sv-parser)
+* [sv2v](https://github.com/zachjs/sv2v)
+* [Symbolator](https://github.com/kevinpt/symbolator)
+* [UHDM](https://github.com/chipsalliance/UHDM)
+* [Verible](https://github.com/chipsalliance/verible)
+* [Veriloggen](https://github.com/PyHDI/veriloggen)
+* [Verik](https://github.com/frwang96/verik)
+* [XLS](https://github.com/google/xls)
+
+## Build Systems
+
+* [Bender](https://github.com/pulp-platform/bender)
+* [datc](https://github.com/jinwookjungs/datc_robust_design_flow)
+* [Edalize](https://github.com/olofk/edalize)
+* [Fusesoc](https://github.com/olofk/fusesoc)
+* [Hammer](https://github.com/ucb-bar/hammer)
+* [hwtBuildsystem](https://github.com/Nic30/hwtBuildsystem)
+* [legoHDL](https://github.com/c-rus/legoHDL)
+* [mflowgen](https://github.com/mflowgen/mflowgen)
+* [SiliconCompiler](https://github.com/siliconcompiler/siliconcompiler)
+
+## Formal Verification
+
+* [Boolector](https://github.com/boolector/boolector)
+* [cvc5](https://github.com/cvc5/cvc5)
+* [Pono](https://github.com/upscale-project/pono)
+* [SymbiYosys](https://github.com/YosysHQ/sby)
+* [Z3](https://github.com/Z3Prover/z3)
+
+## Simulators
+
+* [ghdl](https://github.com/ghdl/ghdl)
+* [icarus](https://github.com/steveicarus/iverilog.git)
+* [ngspice](http://ngspice.sourceforge.net/)
+* [Qucs](https://github.com/Qucs/qucs)
+* [Verilator](https://github.com/verilator/verilator)
+* [Xyce](https://github.com/Xyce/Xyce)
+
+## Generators
+
+* [bag](https://github.com/ucb-art/BAG_framework)
+* [ESP](https://github.com/sld-columbia/esp)
+* [FABulous](https://github.com/FPGA-Research-Manchester/FABulous)
+* [FASoC](https://github.com/idea-fasoc/fasoc)
+* [garnet](https://github.com/StanfordAHA/garnet)
+* [gemmini](https://github.com/ucb-bar/gemmini)
+* [lake](https://github.com/StanfordAHA/lake)
+* [LiteX](https://github.com/enjoy-digital/litex)
+* [openfpga](https://github.com/lnis-uofu/OpenFPGA)
+* [prga](https://github.com/PrincetonUniversity/prga)
+* [pymtl3-net](https://github.com/cornell-brg/pymtl3-net)
+* [rggen](https://github.com/rggen/rggen)
+* [Rocket Chip](https://github.com/chipsalliance/rocket-chip)
+* [spiral](https://github.com/spiral-software/spiral-software)
+* [SystemRDL](https://github.com/SystemRDL/systemrdl-compiler)
+* [kaktus2dev](https://github.com/kactus2/kactus2dev)
+
+## Verification
+
+* [anasysmod](https://github.com/sgherbst/anasymod)
+* [Cocotb](https://github.com/cocotb/cocotb)
+* [libsystemctlm-soc](https://github.com/Xilinx/libsystemctlm-soc)
+* [msdsl](https://github.com/sgherbst/msdsl)
+* [pyuvm](https://github.com/pyuvm/pyuvm)
+* [svreal](https://github.com/sgherbst/svreal)
+* [vunit](https://github.com/VUnit/vunit)
+
+## Waveform viewers
+
+* [gtkwave](https://github.com/gtkwave/gtkwave)
+* [ILAng](https://github.com/PrincetonUniversity/ILAng)
+* [Konata](https://github.com/shioyadan/Konata)
+* [simview](https://github.com/pieter3d/simview)
+* [Sootty](https://github.com/Ben1152000/sootty)
+* [wavedrom](https://github.com/wavedrom/wavedrom)
+* [wavedrompy](https://github.com/wallento/wavedrompy)
+* [puselview](https://github.com/sigrokproject/pulseview)
+* [sigrok-cli](https://github.com/sigrokproject/sigrok-cli)
+
+## Schematic Entry
+
+* [xschem](https://github.com/StefanSchippers/xschem)
+
+## Board Design
+
+* [Boardview](https://github.com/whitequark/kicad-boardview)
+* [datasheet-scrubber](https://github.com/idea-fasoc/datasheet-scrubber)
+* [KiCad](https://github.com/KiCad/kicad-source-mirror)
+* [Pinion](https://github.com/yaqwsx/Pinion)
+* [PCBDraw](https://github.com/yaqwsx/PcbDraw)
+* [Pinout](https://github.com/j0ono0/pinout)
+* [Skidl](https://github.com/devbisme/skidl)
+
+## Synthesis
+
+* [ABC](https://github.com/berkeley-abc/abc)
+* [LSOracle](https://github.com/lnis-uofu/LSOracle)
+* [lstools](https://github.com/lsils/lstools-showcase)
+* [mockturtle](https://github.com/lsils/mockturtle)
+* [Yosys](https://github.com/YosysHQ/yosys)
+
+## ASIC Layout
+
+* [Align](https://github.com/ALIGN-analoglayout/ALIGN-public)
+* [DREAMPlace](https://github.com/limbo018/DREAMPlace)
+* [gds3d](https://github.com/trilomix/GDS3D)
+* [gdsfactory](https://github.com/gdsfactory/gdsfactory)
+* [gdstk](https://github.com/heitzmann/gdstk)
+* [gdspy](https://github.com/heitzmann/gdspy)
+* [klayout](https://github.com/KLayout/klayout)
+* [magic](https://github.com/RTimothyEdwards/magic)
+* [magical](https://github.com/magical-eda/MAGICAL)
+* [netgen](https://github.com/RTimothyEdwards/netgen)
+* [OpenROAD](https://github.com/The-OpenROAD-Project/OpenROAD)
+* [PHIDL](https://github.com/amccaugh/phidl)
+
+## FPGA Layout
+
+* [nextpnr](https://github.com/YosysHQ/nextpnr)
+* [VTR](https://github.com/verilog-to-routing/vtr-verilog-to-routing)
+
+## Benchmark Circuits
+
+* [opdb](https://github.com/PrincetonUniversity/OPDB)