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7 files changed

+103
-12
lines changed

7 files changed

+103
-12
lines changed

‎compiler-rt/cmake/Modules/AddCompilerRT.cmake

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -158,11 +158,11 @@ function(add_compiler_rt_runtime name type)
158158
set(libnames)
159159
# Until we support this some other way, build compiler-rt runtime without LTO
160160
# to allow non-LTO projects to link with it.
161-
if(COMPILER_RT_HAS_FNO_LTO_FLAG)
162-
set(NO_LTO_FLAGS "-fno-lto")
163-
else()
164-
set(NO_LTO_FLAGS "")
165-
endif()
161+
# if(COMPILER_RT_HAS_FNO_LTO_FLAG)
162+
# set(NO_LTO_FLAGS "-fno-lto")
163+
# else()
164+
# set(NO_LTO_FLAGS "")
165+
# endif()
166166

167167
# By default do not instrument or use profdata for compiler-rt.
168168
set(NO_PGO_FLAGS "")

‎compiler-rt/cmake/builtin-config-ix.cmake

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@ asm(\"cas w0, w1, [x2]\");
3838

3939
set(ARM64 aarch64)
4040
set(ARM32 arm armhf armv6m armv7m armv7em armv7 armv7s armv7k)
41+
set(DPU dpu)
4142
set(HEXAGON hexagon)
4243
set(X86 i386)
4344
set(X86_64 x86_64)
@@ -60,7 +61,7 @@ if(APPLE)
6061
endif()
6162

6263
set(ALL_BUILTIN_SUPPORTED_ARCH
63-
${X86} ${X86_64} ${ARM32} ${ARM64}
64+
${X86} ${X86_64} ${ARM32} ${ARM64} ${DPU}
6465
${HEXAGON} ${MIPS32} ${MIPS64} ${PPC32} ${PPC64}
6566
${RISCV32} ${RISCV64} ${SPARC} ${SPARCV9}
6667
${WASM32} ${WASM64} ${VE})

‎compiler-rt/lib/builtins/CMakeLists.txt

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -94,13 +94,13 @@ set(GENERIC_SOURCES
9494
ffssi2.c
9595
ffsti2.c
9696
fixdfdi.c
97-
fixdfsi.c
97+
# fixdfsi.c
9898
fixdfti.c
9999
fixsfdi.c
100100
fixsfsi.c
101101
fixsfti.c
102102
fixunsdfdi.c
103-
fixunsdfsi.c
103+
# fixunsdfsi.c
104104
fixunsdfti.c
105105
fixunssfdi.c
106106
fixunssfsi.c
@@ -263,6 +263,11 @@ if (NOT MSVC)
263263
)
264264
endif ()
265265

266+
set(dpu_SOURCES
267+
dpu/udivsi3.c
268+
${GENERIC_SOURCES}
269+
)
270+
266271
# Implement extended-precision builtins, assuming long double is 80 bits.
267272
# long double is not 80 bits on Android or MSVC.
268273
set(x86_80_BIT_SOURCES

‎compiler-rt/lib/builtins/dpu/udiv32_stepper.c

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
/* Copyright 2024 UPMEM. All rights reserved.
2+
* Use of this source code is governed by a BSD-style license that can be
3+
* found in the LICENSE file.
4+
*/
5+
6+
#include <stdint.h>
7+
8+
uint64_t __attribute__((used)) __udiv32(uint32_t dividend, uint32_t divider)
9+
{
10+
uint64_t dest;
11+
12+
uint32_t temp0;
13+
uint32_t temp1;
14+
15+
/* clang-format off */
16+
__asm__ volatile(" clz %[temp0], %[divider], max, 1f\n" // %[temp0] = by how many the divider can be shifted on 32-bit
17+
" clz %[temp1], %[dividend]\n" // %[temp1] = number of useless bits of the dividend
18+
" sub %[temp0], %[temp1], %[temp0], gtu, 2f\n" // %[temp0] = the maximal shift to be done
19+
" move %[temp1], %[divider]\n"
20+
" move.u %[dest], %[dividend]\n"
21+
" jump %[temp0], 3f\n" // As we will jump backward relatively to label 3 forward
22+
" div_step %[dest], %[temp1], %[dest], 31\n"
23+
" div_step %[dest], %[temp1], %[dest], 30\n"
24+
" div_step %[dest], %[temp1], %[dest], 29\n"
25+
" div_step %[dest], %[temp1], %[dest], 28\n"
26+
" div_step %[dest], %[temp1], %[dest], 27\n"
27+
" div_step %[dest], %[temp1], %[dest], 26\n"
28+
" div_step %[dest], %[temp1], %[dest], 25\n"
29+
" div_step %[dest], %[temp1], %[dest], 24\n"
30+
" div_step %[dest], %[temp1], %[dest], 23\n"
31+
" div_step %[dest], %[temp1], %[dest], 22\n"
32+
" div_step %[dest], %[temp1], %[dest], 21\n"
33+
" div_step %[dest], %[temp1], %[dest], 20\n"
34+
" div_step %[dest], %[temp1], %[dest], 19\n"
35+
" div_step %[dest], %[temp1], %[dest], 18\n"
36+
" div_step %[dest], %[temp1], %[dest], 17\n"
37+
" div_step %[dest], %[temp1], %[dest], 16\n"
38+
" div_step %[dest], %[temp1], %[dest], 15\n"
39+
" div_step %[dest], %[temp1], %[dest], 14\n"
40+
" div_step %[dest], %[temp1], %[dest], 13\n"
41+
" div_step %[dest], %[temp1], %[dest], 12\n"
42+
" div_step %[dest], %[temp1], %[dest], 11\n"
43+
" div_step %[dest], %[temp1], %[dest], 10\n"
44+
" div_step %[dest], %[temp1], %[dest], 9\n"
45+
" div_step %[dest], %[temp1], %[dest], 8\n"
46+
" div_step %[dest], %[temp1], %[dest], 7\n"
47+
" div_step %[dest], %[temp1], %[dest], 6\n"
48+
" div_step %[dest], %[temp1], %[dest], 5\n"
49+
" div_step %[dest], %[temp1], %[dest], 4\n"
50+
" div_step %[dest], %[temp1], %[dest], 3\n"
51+
" div_step %[dest], %[temp1], %[dest], 2\n"
52+
" div_step %[dest], %[temp1], %[dest], 1\n"
53+
"3:\n"
54+
" div_step %[dest], %[temp1], %[dest], 0\n"
55+
"4:\n"
56+
" jump 5f\n"
57+
"2:\n"
58+
" move.u %[dest], %[dividend], true, 4b\n"
59+
"1:\n"
60+
" fault 2\n"
61+
"5:\n"
62+
: [dest] "=r"(dest), [temp0] "=&r" (temp0), [temp1] "=&r" (temp1)
63+
: [dividend] "r"(dividend), [divider] "r"(divider));
64+
/* clang-format on */
65+
66+
return dest;
67+
}

‎compiler-rt/lib/builtins/dpu/udivsi3.c

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
#include "../int_lib.h"
2+
3+
typedef su_int fixuint_t;
4+
typedef si_int fixint_t;
5+
6+
/* extern void uint64_t __attribute__((used)) __udiv32(uint32_t dividend, uint32_t divider) */
7+
#include "udiv32_stepper.c"
8+
9+
// Returns: a / b
10+
11+
COMPILER_RT_ABI su_int __udivsi3(su_int a, su_int b) {
12+
uint64_t res = __udiv32(a, b);
13+
return (su_int) (res >> 32);
14+
/* return 42; */
15+
}

‎llvm/lib/Target/DPU/DPUTargetLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -89,10 +89,10 @@ DPUTargetLowering::DPUTargetLowering(const TargetMachine &TM, DPUSubtarget &STI)
8989
PredictableSelectIsExpensive = true;
9090
setJumpIsExpensive(false);
9191

92-
setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
93-
setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
94-
setLibcallName(RTLIB::SDIV_I32, "__div32");
95-
setLibcallName(RTLIB::UDIV_I32, "__udiv32");
92+
// setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
93+
// setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
94+
// setLibcallName(RTLIB::SDIV_I32, "__div32");
95+
// setLibcallName(RTLIB::UDIV_I32, "__udiv32");
9696

9797
// Set up the register classes.
9898
addRegisterClass(MVT::i32, &DPU::GP_REGRegClass);

‎llvm/lib/Target/DPU/MCTargetDesc/DPUMCCodeEmitter.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,9 @@ void DPUMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
3636
SmallVectorImpl<MCFixup> &Fixups,
3737
const MCSubtargetInfo &STI) const {
3838
// Get instruction encoding and emit it
39+
// MI.dump();
40+
MI.dump_pretty(dbgs());
41+
dbgs() << "\n";
3942
uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
4043

4144
// Emit bytes in little-endian

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