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Merge pull request #1512 from QDucasse/code_patching
Issues with count for code patching
2 parents 1923c12 + 033e79a commit dfb14e9

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2 files changed

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lines changed

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+121
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‎tests/unit/test_arm64.c

+63-1
Original file line numberDiff line numberDiff line change
@@ -50,4 +50,66 @@ static void test_arm64_until()
5050
OK(uc_close(uc));
5151
}
5252

53-
TEST_LIST = {{"test_arm64_until", test_arm64_until}, {NULL, NULL}};
53+
54+
static void test_arm64_code_patching() {
55+
uc_engine *uc;
56+
char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1
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uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1);
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// zero out x0
59+
uint64_t r_x0 = 0x0;
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OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) -1, 0, 0));
63+
// check value
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OK(uc_reg_read(uc, UC_ARM64_REG_X0, &r_x0));
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TEST_CHECK(r_x0 == 0x1);
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// patch instruction
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char patch_code[] = "\x00\xfc\x1f\x11"; // add w0, w0, 0x7FF
68+
OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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// zero out x0
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r_x0 = 0x0;
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OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(patch_code) -1, 0, 0));
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// check value
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OK(uc_reg_read(uc, UC_ARM64_REG_X0, &r_x0));
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TEST_CHECK(r_x0 != 0x1);
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TEST_CHECK(r_x0 == 0x7ff);
77+
78+
OK(uc_close(uc));
79+
}
80+
81+
// Need to flush the cache before running the emulation after patching
82+
static void test_arm64_code_patching_count() {
83+
uc_engine *uc;
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char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1
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uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1);
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// zero out x0
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uint64_t r_x0 = 0x0;
88+
OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
89+
// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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// check value
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OK(uc_reg_read(uc, UC_ARM64_REG_X0, &r_x0));
93+
TEST_CHECK(r_x0 == 0x1);
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// patch instruction
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char patch_code[] = "\x00\xfc\x1f\x11"; // add w0, w0, 0x7FF
96+
OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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OK(uc_ctl_remove_cache(uc, code_start, code_start + sizeof(patch_code) - 1));
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// zero out x0
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r_x0 = 0x0;
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OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0));
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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// check value
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OK(uc_reg_read(uc, UC_ARM64_REG_X0, &r_x0));
104+
TEST_CHECK(r_x0 != 0x1);
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TEST_CHECK(r_x0 == 0x7ff);
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107+
OK(uc_close(uc));
108+
}
109+
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TEST_LIST = {
111+
{"test_arm64_until", test_arm64_until},
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{"test_arm64_code_patching", test_arm64_code_patching},
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{"test_arm64_code_patching_count", test_arm64_code_patching_count},
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{NULL, NULL}
115+
};

‎tests/unit/test_riscv.c

+58
Original file line numberDiff line numberDiff line change
@@ -372,6 +372,62 @@ static void test_riscv64_fp_move_to_int(void)
372372
uc_close(uc);
373373
}
374374

375+
static void test_riscv64_code_patching() {
376+
uc_engine *uc;
377+
char code[] = "\x93\x82\x12\x00"; // addi t0, t0, 0x1
378+
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
379+
// Zero out t0 and t1
380+
uint64_t r_t0 = 0x0;
381+
OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
382+
// emulate the instruction
383+
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
384+
// check value
385+
OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
386+
TEST_CHECK(r_t0 == 0x1);
387+
// patch instruction
388+
char patch_code[] = "\x93\x82\xf2\x7f"; // addi t0, t0, 0x7FF
389+
OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
390+
// zero out t0
391+
r_t0 = 0x0;
392+
OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
393+
OK(uc_emu_start(uc, code_start, code_start + sizeof(patch_code) -1, 0, 0));
394+
// check value
395+
OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
396+
TEST_CHECK(r_t0 != 0x1);
397+
TEST_CHECK(r_t0 == 0x7ff);
398+
399+
OK(uc_close(uc));
400+
}
401+
402+
// Need to flush the cache before running the emulation after patching
403+
static void test_riscv64_code_patching_count() {
404+
uc_engine *uc;
405+
char code[] = "\x93\x82\x12\x00"; // addi t0, t0, 0x1
406+
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
407+
// Zero out t0 and t1
408+
uint64_t r_t0 = 0x0;
409+
OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
410+
// emulate the instruction
411+
OK(uc_emu_start(uc, code_start, -1, 0, 1));
412+
// check value
413+
OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
414+
TEST_CHECK(r_t0 == 0x1);
415+
// patch instruction
416+
char patch_code[] = "\x93\x82\xf2\x7f"; // addi t0, t0, 0x7FF
417+
OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
418+
OK(uc_ctl_remove_cache(uc, code_start, code_start + sizeof(patch_code) - 1));
419+
// zero out t0
420+
r_t0 = 0x0;
421+
OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
422+
OK(uc_emu_start(uc, code_start, -1, 0, 1));
423+
// check value
424+
OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
425+
TEST_CHECK(r_t0 != 0x1);
426+
TEST_CHECK(r_t0 == 0x7ff);
427+
428+
OK(uc_close(uc));
429+
}
430+
375431
static void test_riscv64_ecall_cb(uc_engine *uc, uint32_t intno, void *data)
376432
{
377433
uc_emu_stop(uc);
@@ -492,4 +548,6 @@ TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop},
492548
{"test_riscv32_mmio_map", test_riscv32_mmio_map},
493549
{"test_riscv64_mmio_map", test_riscv64_mmio_map},
494550
{"test_riscv32_map", test_riscv32_map},
551+
{"test_riscv64_code_patching", test_riscv64_code_patching},
552+
{"test_riscv64_code_patching_count", test_riscv64_code_patching_count},
495553
{NULL, NULL}};

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