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ARTY A7: Add GPIO. Add makefile for vivado
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‎fpga/arty_a7/arty_revb.xdc‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -46,47 +46,47 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { c
4646

4747
##Pmod Header JA
4848

49-
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
50-
#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
51-
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
52-
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
53-
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
54-
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
55-
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
56-
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
49+
set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
50+
set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
51+
set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
52+
set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
53+
set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
54+
set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
55+
set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
56+
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
5757

5858
##Pmod Header JB
5959

60-
#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
61-
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
62-
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
63-
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
64-
#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
65-
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
66-
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
67-
#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
60+
set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
61+
set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
62+
set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
63+
set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
64+
set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
65+
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
66+
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
67+
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
6868

6969
##Pmod Header JC
7070

71-
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
72-
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
73-
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
74-
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
75-
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
76-
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
77-
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
78-
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
71+
set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
72+
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
73+
set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
74+
set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
75+
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
76+
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
77+
set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
78+
set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
7979

8080
##Pmod Header JD
8181

82-
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
83-
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
84-
#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
85-
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
86-
#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
87-
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
88-
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
89-
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
82+
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
83+
set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
84+
set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
85+
set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
86+
set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
87+
set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
88+
set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
89+
set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
9090

9191
##USB-UART Interface
9292

‎fpga/arty_a7/makefile‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
###############################################################################
2+
## Makefile
3+
###############################################################################
4+
PART_NAME = xc7a35ti
5+
PART_PACKAGE = csg324
6+
PART_SPEED = 1L
7+
8+
CPU ?= riscv
9+
10+
# Choice: [rv32i, rv32i_spartan6, rv32im, rv32imsu]
11+
RISCV_CORE ?= rv32im
12+
13+
SRC_DIR = .
14+
SRC_DIR += ../common
15+
SRC_DIR += ../../soc/core_soc/src_v
16+
SRC_DIR += ../../soc/dbg_bridge/src_v
17+
18+
# RISC-V
19+
ifeq ($(CPU),riscv)
20+
SRC_DIR += ../../cpu/riscv/core/$(RISCV_CORE)
21+
SRC_DIR += ../../cpu/riscv/top_tcm_wrapper
22+
EXTRA_VFLAGS += CPU_SELECT_RISCV=1
23+
else
24+
# Cortex M0
25+
SRC_DIR += ../../cpu/cortex_m0/src_v
26+
EXTRA_VFLAGS += CPU_SELECT_ARMV6M=1
27+
endif
28+
29+
include ../common/makefile.fpga_vivado

‎fpga/arty_a7/top.v‎

Lines changed: 52 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,12 @@ module top
1414
,output flash_cs_o
1515
,output flash_si_o
1616
,input flash_so_i
17+
18+
// Pmod Headers
19+
,inout [7:0] ja
20+
,inout [7:0] jb
21+
,inout [7:0] jc
22+
,inout [7:0] jd
1723
);
1824

1925
//-----------------------------------------------------------------
@@ -43,15 +49,30 @@ u_rst
4349
//-----------------------------------------------------------------
4450
// Core
4551
//-----------------------------------------------------------------
46-
wire dbg_txd_w;
47-
wire uart_txd_w;
52+
wire dbg_txd_w;
53+
wire uart_txd_w;
54+
55+
wire spi_clk_w;
56+
wire spi_so_w;
57+
wire spi_si_w;
58+
wire [7:0] spi_cs_w;
4859

49-
wire spi_clk_w;
50-
wire spi_so_w;
51-
wire spi_si_w;
52-
wire [7:0] spi_cs_w;
60+
wire [31:0] gpio_in_w;
61+
wire [31:0] gpio_out_w;
62+
wire [31:0] gpio_out_en_w;
5363

5464
fpga_top
65+
#(
66+
.CLK_FREQ(50000000)
67+
,.BAUDRATE(1000000) // SoC UART baud rate
68+
,.UART_SPEED(1000000) // Debug bridge UART baud (should match BAUDRATE)
69+
,.C_SCK_RATIO(50) // SPI clock divider (SPI_CLK=CLK_FREQ/C_SCK_RATIO)
70+
`ifdef CPU_SELECT_ARMV6M
71+
,.CPU("armv6m") // riscv or armv6m
72+
`else
73+
,.CPU("riscv") // riscv or armv6m
74+
`endif
75+
)
5576
u_top
5677
(
5778
.clk_i(clk)
@@ -68,16 +89,38 @@ u_top
6889
,.spi_miso_i(spi_so_w)
6990
,.spi_cs_o(spi_cs_w)
7091

71-
,.gpio_input_i(32'b0)
72-
,.gpio_output_o()
73-
,.gpio_output_enable_o()
92+
,.gpio_input_i(gpio_in_w)
93+
,.gpio_output_o(gpio_out_w)
94+
,.gpio_output_enable_o(gpio_out_en_w)
7495
);
7596

97+
//-----------------------------------------------------------------
98+
// SPI Flash
99+
//-----------------------------------------------------------------
76100
assign flash_sck_o = spi_clk_w;
77101
assign flash_si_o = spi_si_w;
78102
assign flash_cs_o = spi_cs_w[0];
79103
assign spi_so_w = flash_so_i;
80104

105+
//-----------------------------------------------------------------
106+
// GPIO (PMOD JA=gpio[7:0],...,JD=gpio[31:24])
107+
//-----------------------------------------------------------------
108+
genvar i;
109+
generate
110+
for (i=0; i < 8; i=i+1)
111+
begin
112+
assign ja[i] = gpio_out_en_w[0+i] ? gpio_out_w[0+i] : 1'bz;
113+
assign jb[i] = gpio_out_en_w[8+i] ? gpio_out_w[8+i] : 1'bz;
114+
assign jc[i] = gpio_out_en_w[16+i] ? gpio_out_w[16+i] : 1'bz;
115+
assign jd[i] = gpio_out_en_w[24+i] ? gpio_out_w[24+i] : 1'bz;
116+
117+
assign gpio_in_w[0+i] = ja[i];
118+
assign gpio_in_w[8+i] = jb[i];
119+
assign gpio_in_w[16+i] = jc[i];
120+
assign gpio_in_w[24+i] = jd[i];
121+
end
122+
endgenerate
123+
81124
//-----------------------------------------------------------------
82125
// UART Tx combine
83126
//-----------------------------------------------------------------

‎fpga/common/makefile.fpga_vivado‎

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,124 @@
1+
###############################################################################
2+
## Params
3+
###############################################################################
4+
SRC_DIR ?= ./
5+
EXTRA_VFLAGS ?=
6+
PROJECT_DIR ?= project
7+
PROJECT ?= fpga
8+
9+
PART_NAME ?= xc7a35t
10+
PART_PACKAGE ?= ftg256
11+
PART_SPEED ?= 1
12+
13+
ifeq ($(XILINX_VIVADO),)
14+
$(error "XILINX_VIVADO not set - e.g. export XILINX_VIVADO=/opt/Xilinx/Vivado/2016.3")
15+
endif
16+
17+
TOOL_PATH := $(XILINX_VIVADO)/bin/
18+
19+
FPGA_PART := $(PART_NAME)$(PART_PACKAGE)-$(PART_SPEED)
20+
21+
###############################################################################
22+
# Rules:
23+
###############################################################################
24+
.PRECIOUS: $(PROJECT_DIR)/%.xpr $(PROJECT_DIR)/%.runs/synth_1/%.dcp $(PROJECT_DIR)/%.runs/impl_1/%_routed.dcp $(PROJECT_DIR)/%.bit
25+
26+
all: bitstream
27+
28+
bitstream: $(PROJECT_DIR)/$(PROJECT).bit
29+
30+
clean:
31+
rm -rf $(PROJECT_DIR)
32+
33+
$(PROJECT_DIR):
34+
@mkdir -p $@
35+
36+
###############################################################################
37+
# TCL: Project
38+
###############################################################################
39+
TCL_FILES += $(PROJECT_DIR)/create_project.tcl
40+
$(PROJECT_DIR)/create_project.tcl: | $(PROJECT_DIR)
41+
@echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
42+
@$(foreach _dir,$(SRC_DIR), $(foreach _file,$(wildcard $(_dir)/*.v),echo "add_files -fileset sources_1 $(abspath $(_file)") >> $@;))
43+
@$(foreach _dir,$(SRC_DIR), $(foreach _file,$(wildcard $(_dir)/*.xdc),echo "add_files -fileset constrs_1 $(abspath $(_file)") >> $@;))
44+
@$(foreach _dir,$(SRC_DIR), $(foreach _file,$(wildcard $(_dir)/*.xci),echo "import_ip $(abspath $(_file)") >> $@;))
45+
@echo "set_property verilog_define [list $(EXTRA_VFLAGS)] [get_filesets sources_1]" >> $@
46+
@echo "exit" >> $@
47+
48+
###############################################################################
49+
# TCL: Synth
50+
###############################################################################
51+
TCL_FILES += $(PROJECT_DIR)/run_synth.tcl
52+
$(PROJECT_DIR)/run_synth.tcl: | $(PROJECT_DIR)
53+
@echo "open_project $(PROJECT).xpr" > $@
54+
@echo "reset_run synth_1" >> $@
55+
@echo "launch_runs synth_1" >> $@
56+
@echo "wait_on_run synth_1" >> $@
57+
@echo "exit" >> $@
58+
59+
###############################################################################
60+
# TCL: Implementation
61+
###############################################################################
62+
TCL_FILES += $(PROJECT_DIR)/run_impl.tcl
63+
$(PROJECT_DIR)/run_impl.tcl: | $(PROJECT_DIR)
64+
@echo "open_project $(PROJECT).xpr" > $@
65+
@echo "reset_run impl_1" >> $@
66+
@echo "launch_runs impl_1" >> $@
67+
@echo "wait_on_run impl_1" >> $@
68+
@echo "exit" >> $@
69+
70+
###############################################################################
71+
# TCL: Bitstream
72+
###############################################################################
73+
TCL_FILES += $(PROJECT_DIR)/generate_bit.tcl
74+
$(PROJECT_DIR)/generate_bit.tcl: | $(PROJECT_DIR)
75+
@echo "open_project $(PROJECT).xpr" > $@
76+
@echo "open_run impl_1" >> $@
77+
@echo "write_bitstream -force $(PROJECT).bit" >> $@
78+
@echo "exit" >> $@
79+
80+
###############################################################################
81+
# TCL: Program bitstream
82+
###############################################################################
83+
TCL_FILES += $(PROJECT_DIR)/program.tcl
84+
$(PROJECT_DIR)/program.tcl: | $(PROJECT_DIR)
85+
@echo "open_hw" > $@
86+
@echo "connect_hw_server" >> $@
87+
@echo "open_hw_target" >> $@
88+
@echo "current_hw_device [lindex [get_hw_devices] 0]" >> $@
89+
@echo "refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]" >> $@
90+
@echo "set_property PROBES.FILE {} [lindex [get_hw_devices] 0]" >> $@
91+
@echo "set_property PROGRAM.FILE {$(PROJECT).bit} [lindex [get_hw_devices] 0]" >> $@
92+
@echo "program_hw_devices [lindex [get_hw_devices] 0]" >> $@
93+
@echo "refresh_hw_device [lindex [get_hw_devices] 0]" >> $@
94+
@echo "quit" >> $@
95+
96+
###############################################################################
97+
# Vivado: Create project
98+
###############################################################################
99+
$(PROJECT_DIR)/%.xpr: $(TCL_FILES)
100+
cd $(PROJECT_DIR); $(TOOL_PATH)/vivado -mode batch -source create_project.tcl
101+
102+
###############################################################################
103+
# Vivado: Synthesis
104+
###############################################################################
105+
$(PROJECT_DIR)/%.runs/synth_1/%.dcp: $(PROJECT_DIR)/%.xpr $(PROJECT_DIR)/run_synth.tcl
106+
cd $(PROJECT_DIR); $(TOOL_PATH)/vivado -mode batch -source run_synth.tcl
107+
108+
###############################################################################
109+
# Vivado: Implementation
110+
###############################################################################
111+
$(PROJECT_DIR)/%.runs/impl_1/%_routed.dcp: $(PROJECT_DIR)/%.runs/synth_1/%.dcp $(PROJECT_DIR)/run_impl.tcl
112+
cd $(PROJECT_DIR); $(TOOL_PATH)/vivado -mode batch -source run_impl.tcl
113+
114+
###############################################################################
115+
# Vivado: Create bitstream
116+
###############################################################################
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$(PROJECT_DIR)/%.bit: $(PROJECT_DIR)/%.runs/impl_1/%_routed.dcp $(PROJECT_DIR)/generate_bit.tcl
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cd $(PROJECT_DIR); $(TOOL_PATH)/vivado -mode batch -source generate_bit.tcl
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###############################################################################
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# Vivado: Run bitstream
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###############################################################################
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run:
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cd $(PROJECT_DIR); $(TOOL_PATH)/vivado -mode tcl -source program.tcl

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