Added make target prog_fpga to flash bitfile into SPI flash.

Author: skiphansen

fpga/panologic_g2/Makefile

@@ -4,6 +4,8 @@
 CPU        ?= riscv
 XILINX_ISE ?= /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64
 CABLE 	   ?= jtaghs2
+XC3SPROG_OPTS ?= -c $(CABLE) -v
+XC3SPROG      ?= xc3sprog
 
 # Choice: [rv32i, rv32i_spartan6, rv32im, rv32imsu]
 RISCV_CORE  ?= rv32i_spartan6
@@ -37,8 +39,12 @@ init_and_build: ${CORES_README} all
 
 include ../common/makefile.fpga_ise
 
+BIT_FILE = project/${PROJECT}_routed.bit
 load:
-	xc3sprog -c ${CABLE} project/${PROJECT}_routed.bit
+	$(XC3SPROG) $(XC3SPROG_OPTS) ${BIT_FILE}
+
+prog_fpga:
+	$(XC3SPROG) $(XC3SPROG_OPTS) -Ixc3sprog/$(PART_NAME).bit ${BIT_FILE}
 
 ${CORES_README}:
 	git submodule init