Skip to content

Commit 24c0d6b

Browse files
ultraembeddedultraembedded
committed
Add ISE makefile for minispartan6 board
1 parent b456547 commit 24c0d6b

File tree

3 files changed

+218
-0
lines changed

3 files changed

+218
-0
lines changed

‎fpga/common/makefile.fpga_ise‎

Lines changed: 181 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,181 @@
1+
###############################################################################
2+
## Params
3+
###############################################################################
4+
SRC_DIR ?= .
5+
EXTRA_VFLAGS ?=
6+
PROJECT_DIR ?= project
7+
PROJECT ?= fpga
8+
9+
PART_NAME ?= xc6slx9
10+
PART_PACKAGE ?= tqg144
11+
PART_SPEED ?= 3
12+
13+
TOP_MODULE ?= top
14+
15+
ifeq ($(XILINX_ISE),)
16+
$(error "XILINX_ISE not set - e.g. export XILINX_ISE=/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64")
17+
endif
18+
TOOL_PATH := $(XILINX_ISE)
19+
20+
UCF_FILE ?= fpga.ucf
21+
22+
###############################################################################
23+
# Rules:
24+
###############################################################################
25+
all: bitstream
26+
27+
bitstream: $(PROJECT_DIR)/$(PROJECT)_routed.bit
28+
29+
clean:
30+
rm -rf $(PROJECT_DIR)
31+
32+
$(PROJECT_DIR):
33+
@mkdir -p $@
34+
35+
###############################################################################
36+
# PROJECT.ut
37+
###############################################################################
38+
$(PROJECT_DIR)/$(PROJECT).ut: | $(PROJECT_DIR)
39+
@echo "-w" > $@
40+
@echo "-g DebugBitstream:No" >> $@
41+
@echo "-g Binary:no" >> $@
42+
@echo "-g CRC:Enable" >> $@
43+
@echo "-g ConfigRate:25" >> $@
44+
@echo "-g ProgPin:PullUp" >> $@
45+
@echo "-g DonePin:PullUp" >> $@
46+
@echo "-g TckPin:PullUp" >> $@
47+
@echo "-g TdiPin:PullUp" >> $@
48+
@echo "-g TdoPin:PullUp" >> $@
49+
@echo "-g TmsPin:PullUp" >> $@
50+
@echo "-g UnusedPin:PullDown" >> $@
51+
@echo "-g UserID:0xFFFFFFFF" >> $@
52+
@echo "-g StartUpClk:CClk" >> $@
53+
@echo "-g DONE_cycle:4" >> $@
54+
@echo "-g GTS_cycle:5" >> $@
55+
@echo "-g GWE_cycle:6" >> $@
56+
@echo "-g LCK_cycle:NoWait" >> $@
57+
@echo "-g Security:None" >> $@
58+
@echo "-g DonePipe:No" >> $@
59+
@echo "-g DriveDone:No" >> $@
60+
61+
###############################################################################
62+
# PROJECT.xst
63+
###############################################################################
64+
$(PROJECT_DIR)/$(PROJECT).xst: | $(PROJECT_DIR)
65+
@echo "set -tmpdir \"xst/projnav.tmp\"" > $@
66+
@echo "set -xsthdpdir \"xst\"" >> $@
67+
@echo "run" >> $@
68+
@echo "-ifn $(PROJECT).prj" >> $@
69+
@echo "-ifmt mixed" >> $@
70+
@echo "-ofn $(PROJECT)" >> $@
71+
@echo "-ofmt NGC" >> $@
72+
@echo "-p $(PART_NAME)-$(PART_SPEED)-$(PART_PACKAGE)" >> $@
73+
@echo "-top $(TOP_MODULE)" >> $@
74+
@echo "-opt_mode Speed" >> $@
75+
@echo "-opt_level 2" >> $@
76+
@echo "-iuc NO" >> $@
77+
@echo "-keep_hierarchy No" >> $@
78+
@echo "-netlist_hierarchy As_Optimized" >> $@
79+
@echo "-rtlview Yes" >> $@
80+
@echo "-glob_opt AllClockNets" >> $@
81+
@echo "-read_cores YES" >> $@
82+
@echo "-write_timing_constraints YES" >> $@
83+
@echo "-cross_clock_analysis NO" >> $@
84+
@echo "-hierarchy_separator /" >> $@
85+
@echo "-bus_delimiter <>" >> $@
86+
@echo "-case Maintain" >> $@
87+
@echo "-slice_utilization_ratio 100" >> $@
88+
@echo "-bram_utilization_ratio 100" >> $@
89+
@echo "-fsm_extract YES -fsm_encoding Auto" >> $@
90+
@echo "-safe_implementation No" >> $@
91+
@echo "-fsm_style LUT" >> $@
92+
@echo "-ram_extract Yes" >> $@
93+
@echo "-ram_style Auto" >> $@
94+
@echo "-rom_extract Yes" >> $@
95+
@echo "-shreg_extract YES" >> $@
96+
@echo "-rom_style Auto" >> $@
97+
@echo "-auto_bram_packing NO" >> $@
98+
@echo "-resource_sharing NO" >> $@
99+
@echo "-async_to_sync NO" >> $@
100+
@echo "-mult_style Auto" >> $@
101+
@echo "-iobuf YES" >> $@
102+
@echo "-max_fanout 500" >> $@
103+
@echo "-bufg 24" >> $@
104+
@echo "-register_duplication YES" >> $@
105+
@echo "-register_balancing Yes" >> $@
106+
@echo "-move_first_stage YES" >> $@
107+
@echo "-move_last_stage YES" >> $@
108+
@echo "-optimize_primitives YES" >> $@
109+
@echo "-use_clock_enable Auto" >> $@
110+
@echo "-use_sync_set Auto" >> $@
111+
@echo "-use_sync_reset Auto" >> $@
112+
@echo "-iob Auto" >> $@
113+
@echo "-equivalent_register_removal YES" >> $@
114+
@echo "-slice_utilization_ratio_maxmargin 5" >> $@
115+
@echo "-define {$(EXTRA_VFLAGS)}" >> $@
116+
117+
###############################################################################
118+
# PROJECT.prj
119+
###############################################################################
120+
$(PROJECT_DIR)/$(PROJECT).prj: $(PROJECT_DIR)/$(PROJECT).ut $(PROJECT_DIR)/$(PROJECT).xst
121+
@touch $@
122+
@$(foreach _dir,$(SRC_DIR), $(foreach _file,$(wildcard $(_dir)/*.v),echo "verilog work \"$(abspath $(_file))\"" >> $@;))
123+
124+
###############################################################################
125+
# Rule: Synth
126+
###############################################################################
127+
$(PROJECT_DIR)/$(PROJECT).ngc: $(PROJECT_DIR)/$(PROJECT).prj
128+
@echo "####################################################################"
129+
@echo "# ISE: Synth"
130+
@echo "####################################################################"
131+
@mkdir -p $(PROJECT_DIR)/xst/projnav.tmp/
132+
@cd $(PROJECT_DIR); $(TOOL_PATH)/xst -intstyle ise -ifn $(PROJECT).xst -ofn $(PROJECT).syr
133+
134+
###############################################################################
135+
# Rule: Convert netlist
136+
###############################################################################
137+
$(PROJECT_DIR)/$(PROJECT).ngd: $(PROJECT_DIR)/$(PROJECT).ngc
138+
@echo "####################################################################"
139+
@echo "# ISE: Convert netlist"
140+
@echo "####################################################################"
141+
@cd $(PROJECT_DIR); $(TOOL_PATH)/ngdbuild -intstyle ise -dd _ngo -nt timestamp \
142+
-uc $(abspath $(UCF_FILE)) -p $(PART_NAME)-$(PART_PACKAGE)-$(PART_SPEED) $(PROJECT).ngc $(PROJECT).ngd
143+
144+
###############################################################################
145+
# Rule: Map
146+
###############################################################################
147+
$(PROJECT_DIR)/$(PROJECT).ncd: $(PROJECT_DIR)/$(PROJECT).ngd
148+
@echo "####################################################################"
149+
@echo "# ISE: Map"
150+
@echo "####################################################################"
151+
@cd $(PROJECT_DIR); $(TOOL_PATH)/map -w -intstyle ise -p $(PART_NAME)-$(PART_PACKAGE)-$(PART_SPEED) \
152+
-detail -ir off -ignore_keep_hierarchy -pr b -timing -ol high -logic_opt on \
153+
-o $(PROJECT).ncd $(PROJECT).ngd $(PROJECT).pcf
154+
155+
###############################################################################
156+
# Rule: Place and route
157+
###############################################################################
158+
$(PROJECT_DIR)/$(PROJECT)_routed.ncd: $(PROJECT_DIR)/$(PROJECT).ncd
159+
@echo "####################################################################"
160+
@echo "# ISE: Place and route"
161+
@echo "####################################################################"
162+
@cd $(PROJECT_DIR); $(TOOL_PATH)/par -w -intstyle ise -ol high $(PROJECT).ncd $(PROJECT)_routed.ncd $(PROJECT).pcf
163+
164+
###############################################################################
165+
# Rule: Bitstream
166+
###############################################################################
167+
$(PROJECT_DIR)/$(PROJECT)_routed.bit: $(PROJECT_DIR)/$(PROJECT)_routed.ncd
168+
@echo "####################################################################"
169+
@echo "# ISE: Create bitstream"
170+
@echo "####################################################################"
171+
@cd $(PROJECT_DIR); $(TOOL_PATH)/bitgen -f $(PROJECT).ut $(PROJECT)_routed.ncd
172+
173+
###############################################################################
174+
# Rule: Bitstream -> binary
175+
###############################################################################
176+
$(PROJECT_DIR)/$(PROJECT).bin: $(PROJECT_DIR)/$(PROJECT)_routed.bit
177+
@echo "####################################################################"
178+
@echo "# ISE: Convert bitstream"
179+
@echo "####################################################################"
180+
@cd $(PROJECT_DIR); $(TOOL_PATH)/promgen -u 0x0 $(PROJECT)_routed.bit -p bin -w -b -o $(PROJECT).bin
181+

‎fpga/minispartan6/makefile‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
###############################################################################
2+
## Makefile
3+
###############################################################################
4+
PART_NAME = xc6slx9
5+
PART_PACKAGE = ftg256
6+
PART_SPEED = 3
7+
8+
CPU ?= riscv
9+
10+
# Choice: [rv32i, rv32i_spartan6, rv32im, rv32imsu]
11+
RISCV_CORE ?= rv32i_spartan6
12+
13+
SRC_DIR = .
14+
SRC_DIR += ../common
15+
SRC_DIR += ../../soc/core_soc/src_v
16+
SRC_DIR += ../../soc/dbg_bridge/src_v
17+
18+
# RISC-V
19+
ifeq ($(CPU),riscv)
20+
SRC_DIR += ../../cpu/riscv/core/$(RISCV_CORE)
21+
SRC_DIR += ../../cpu/riscv/top_tcm_wrapper
22+
EXTRA_VFLAGS += CPU_SELECT_RISCV=1
23+
else
24+
# Cortex M0
25+
SRC_DIR += ../../cpu/cortex_m0/src_v
26+
EXTRA_VFLAGS += CPU_SELECT_ARMV6M=1
27+
endif
28+
29+
include ../common/makefile.fpga_ise

‎fpga/minispartan6/top.v‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,14 @@ wire [7:0] spi_cs_w;
4343
fpga_top
4444
#(
4545
.CLK_FREQ(32000000)
46+
,.BAUDRATE(1000000) // SoC UART baud rate
47+
,.UART_SPEED(1000000) // Debug bridge UART baud (should match BAUDRATE)
48+
,.C_SCK_RATIO(50) // SPI clock divider (SPI_CLK=CLK_FREQ/C_SCK_RATIO)
49+
`ifdef CPU_SELECT_ARMV6M
50+
,.CPU("armv6m") // riscv or armv6m
51+
`else
52+
,.CPU("riscv") // riscv or armv6m
53+
`endif
4654
)
4755
u_top
4856
(

0 commit comments

Comments
 (0)