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ShiftRegisterMem should provide also single port SRAM implementation #2

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chick opened this issue Jun 23, 2021 · 1 comment
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ShiftRegisterMem should provide also single port SRAM implementation #2

chick opened this issue Jun 23, 2021 · 1 comment
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@chick
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chick commented Jun 23, 2021

There is a note inside craft/ShiftRegisterMem.scala that ShiftRegisterMem should provide also single port SRAM iplementation but there are some bugs in the current version.
We would need to have this fixed eventually, but perhaps we can try to fix it on our side also.
@chick chick added the bug Something isn't working label Jun 23, 2021
@milovanovic
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This issue is fixed by the corresponding pull request.

@milovanovic milovanovic mentioned this issue Dec 31, 2022
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