Illegal use of tristate value.

[alsrbok]

While I use Synopsys DC to synthesize the system verilog code of Gemmini accelerator, Illegal use of tristate value error happen on CSRFile.sv file.
This is due to following line
wire [15:0] read_mip = {1'bz, 1'bz, io_rocc_interrupt, 1'bz, io_interrupts_meip, 1'bz, reg_mip_seip | io_interrupts_seip, 1'bz, io_interrupts_mtip, 1'bz, reg_mip_stip, 1'bz, io_interrupts_msip, 1'bz, reg_mip_ssip, 1'bz} & 16'h2AAA; // @[CSR.scala:407:10, :473:20, :559:24, :565:57, :569:{22,29}]

What should I do for this line?
As CSRFile.sv is submodule of Rocket.sv, I should handle this error correctly.
Can I chagne 1'bz to 1'b0 or 1'b1?