diff --git a/.gitmodules b/.gitmodules
index b4beb6969b..f50558651b 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -73,9 +73,6 @@
 [submodule "fpga/fpga-shells"]
 	path = fpga/fpga-shells
 	url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git
-[submodule "tools/api-config-chipsalliance"]
-	path = tools/api-config-chipsalliance
-	url = https://github.com/chipsalliance/api-config-chipsalliance.git
 [submodule "tools/rocket-dsp-utils"]
 	path = tools/rocket-dsp-utils
 	url = https://github.com/ucb-bar/rocket-dsp-utils
@@ -121,3 +118,6 @@
 [submodule "generators/mempress"]
 	path = generators/mempress
 	url = https://github.com/ucb-bar/mempress.git
+[submodule "tools/cde"]
+	path = tools/cde
+	url = https://github.com/chipsalliance/cde.git
diff --git a/build.sbt b/build.sbt
index 0f065836a7..24862c4589 100644
--- a/build.sbt
+++ b/build.sbt
@@ -62,7 +62,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
   new Group(test.name, Seq(test), SubProcess(options))
 } toSeq
 
-val chiselVersion = "3.5.5"
+val chiselVersion = "3.5.6"
 
 lazy val chiselSettings = Seq(
   libraryDependencies ++= Seq("edu.berkeley.cs" %% "chisel3" % chiselVersion,
@@ -102,18 +102,8 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
     )
   )
 
-lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
-  .settings(commonSettings)
-  .settings(
-    libraryDependencies ++= Seq(
-      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
-      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
-    )
-  )
-
 lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-  .dependsOn(hardfloat, rocketMacros, rocketConfig)
+  .dependsOn(hardfloat, rocketMacros, cde)
   .settings(commonSettings)
   .settings(chiselSettings)
   .settings(
@@ -246,16 +236,12 @@ lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
       "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
   ))
 
-lazy val `api-config-chipsalliance` = freshProject("api-config-chipsalliance", file("./tools/api-config-chipsalliance"))
-  .settings(
-    commonSettings,
-    libraryDependencies ++= Seq(
-      "org.scalatest" %% "scalatest" % "3.0.+" % "test",
-      "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
-    ))
+lazy val cde = (project in file("tools/cde"))
+  .settings(commonSettings)
+  .settings(Compile / scalaSource := baseDirectory.value / "cde/src/chipsalliance/rocketchip")
 
 lazy val `rocket-dsp-utils` = freshProject("rocket-dsp-utils", file("./tools/rocket-dsp-utils"))
-  .dependsOn(rocketchip, `api-config-chipsalliance`, dsptools)
+  .dependsOn(rocketchip, cde, dsptools)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index b6cd1bb7fe..9f4c6ac571 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit b6cd1bb7fe35bb7a44b6fe5a0d88d1293d7a3bc9
+Subproject commit 9f4c6ac5719b03ded61022dc3767e750872d0535
diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index a88848d0e5..421ba35506 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 package chipyard.fpga.arty
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala
index 4e90e85899..e1743c0b74 100644
--- a/fpga/src/main/scala/arty/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty/HarnessBinders.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.arty
 
 import chisel3._
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 import freechips.rocketchip.jtag.{JTAGIO}
 
 import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
@@ -15,7 +15,7 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
 import chipyard.iobinders.JTAGChipIO
 
 class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
-  (system: HasPeripheryDebugModuleImp, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
+  (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Bool]) => {
     require(ports.size == 2)
 
     withClockAndReset(th.clock_32MHz, th.ck_rst) {
diff --git a/fpga/src/main/scala/arty/IOBinders.scala b/fpga/src/main/scala/arty/IOBinders.scala
index db65675225..da6c7318ee 100644
--- a/fpga/src/main/scala/arty/IOBinders.scala
+++ b/fpga/src/main/scala/arty/IOBinders.scala
@@ -3,12 +3,12 @@ package chipyard.fpga.arty
 import chisel3._
 import chisel3.experimental.{IO}
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug}
 
 import chipyard.iobinders.{ComposeIOBinder}
 
 class WithDebugResetPassthrough extends ComposeIOBinder({
-  (system: HasPeripheryDebugModuleImp) => {
+  (system: HasPeripheryDebug) => {
     // Debug module reset
     val io_ndreset: Bool = IO(Output(Bool())).suggestName("ndreset")
     io_ndreset := system.debug.get.ndreset
diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala
index a3d7fc339f..5e280469da 100644
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.arty
 import chisel3._
 
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 
 import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
 
diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index 0930dbdb2c..673b8b58cd 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -1,7 +1,7 @@
 // See LICENSE for license details.
 package chipyard.fpga.arty100t
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index 5cc1e34834..88ea88af77 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.arty100t
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode, TLBlockDuringReset}
 
 import sifive.fpgashells.shell.xilinx._
diff --git a/fpga/src/main/scala/arty100t/HarnessBinders.scala b/fpga/src/main/scala/arty100t/HarnessBinders.scala
index 3d86f354c2..d9a2df4594 100644
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -2,7 +2,6 @@ package chipyard.fpga.arty100t
 
 import chisel3._
 
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.jtag.{JTAGIO}
 import freechips.rocketchip.subsystem.{PeripheryBusKey}
 import freechips.rocketchip.tilelink.{TLBundle}
diff --git a/fpga/src/main/scala/vc707/Configs.scala b/fpga/src/main/scala/vc707/Configs.scala
index 07a96cfd27..fa08a18477 100644
--- a/fpga/src/main/scala/vc707/Configs.scala
+++ b/fpga/src/main/scala/vc707/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vc707
 
 import sys.process._
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
 import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala
index 924c768e52..94c0ba8ed7 100644
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
 
 import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index 85b6ee24ba..c4f4684e7f 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118
 
 import sys.process._
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
 import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
 import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala
index 250e204090..02669b7919 100644
--- a/fpga/src/main/scala/vcu118/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118
 import chisel3._
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
 
 import sifive.fpgashells.shell._
diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index 9a3cc0d5b6..e46745a82d 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IO}
 
 import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp, BundleBridgeSource}
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.tilelink.{TLClientNode}
 
 import sifive.fpgashells.shell.xilinx._
diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala
index 62c2af3167..bff715dcdc 100644
--- a/fpga/src/main/scala/vcu118/bringup/Configs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -2,7 +2,7 @@ package chipyard.fpga.vcu118.bringup
 
 import math.min
 
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.diplomacy._
diff --git a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
index 43d559f0d6..4b9604f9ab 100644
--- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{attach}
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
 
 import sifive.fpgashells.shell._
diff --git a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
index 5b554f5bcf..c5401d320b 100644
--- a/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
+++ b/fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 2406cb7bb1..c311d84fc4 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -3,7 +3,7 @@ package chipyard.fpga.vcu118.bringup
 import chisel3._
 
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 
diff --git a/generators/boom b/generators/boom
index deae9f7046..0101e2041d 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit deae9f70469336a3787fa7fcc10135ffb93d21d9
+Subproject commit 0101e2041d4a7c11d6b4aff685200aa387fcbc51
diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala
index 184f30f25b..150221b6b9 100644
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -6,7 +6,7 @@ import scala.collection.mutable.{ArrayBuffer}
 
 import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import chipyard.iobinders._
diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala
index 7b663b2455..fffb97d67f 100644
--- a/generators/chipyard/src/main/scala/Cospike.scala
+++ b/generators/chipyard/src/main/scala/Cospike.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.experimental.{IntParam, StringParam, IO}
 import chisel3.util._
 
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.devices.tilelink._
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 2777ba3608..d20bade96d 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.devices.tilelink._
 
 // ------------------------------------
diff --git a/generators/chipyard/src/main/scala/HarnessBinders.scala b/generators/chipyard/src/main/scala/HarnessBinders.scala
index 21dfe5880c..1992bc1ec6 100644
--- a/generators/chipyard/src/main/scala/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/HarnessBinders.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, BaseModule, DataMirror, Direction}
 
-import freechips.rocketchip.config.{Field, Config, Parameters}
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
 import freechips.rocketchip.devices.debug._
diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index 71eef713b6..3eaac60574 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -3,7 +3,7 @@ package chipyard.iobinders
 import chisel3._
 import chisel3.experimental.{Analog, IO, DataMirror}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.jtag.{JTAGIO}
@@ -219,7 +219,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
     def clockBundle = clockSinkNode.get.in.head._1
 
 
-    InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebugModuleImp => {
+    InModuleBody { system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripheryDebug => {
       system.debug.map({ debug =>
         // We never use the PSDIO, so tie it off on-chip
         system.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index c7e5b69d9c..b761144811 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{IntParam, StringParam, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 34175d398a..949a4aa427 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -9,9 +9,9 @@ import chisel3._
 import chisel3.internal.sourceinfo.{SourceInfo}
 
 import freechips.rocketchip.prci._
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug, DebugModuleKey}
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, ExportDebug, DebugModuleKey}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
@@ -47,6 +47,7 @@ trait CanHaveHTIF { this: BaseSubsystem =>
 
 class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
   with HasTiles
+  with HasPeripheryDebug
   with CanHaveHTIF
 {
   def coreMonitorBundles = tiles.map {
diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
index 827b97c000..a6c4b6b3e3 100644
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -7,7 +7,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala
index 240ae5cc91..23bda68036 100644
--- a/generators/chipyard/src/main/scala/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/TestHarness.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.util.{ResetCatchAndSync}
 import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters, ClockSinkParameters, ClockParameters}
 
diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
index a47ae4250b..0e4e33107d 100644
--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -4,7 +4,7 @@ import scala.collection.mutable.{LinkedHashSet}
 
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{XLen, TileParams}
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
 
 /**
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
index 07ae536b2d..c8bad8c4d4 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
index 965beed335..39cb379b87 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupNamePrefixer.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters, Config, Field}
+import org.chipsalliance.cde.config.{Parameters, Config, Field}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 
diff --git a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
index d72b2a7017..121cca24f9 100644
--- a/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
+++ b/generators/chipyard/src/main/scala/clocking/DividerOnlyClockGenerator.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util.ElaborationArtefacts
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
index 0cfc702a12..d2c4f2e5d4 100644
--- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
+++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -4,7 +4,7 @@ import chisel3._
 
 import scala.collection.mutable.{ArrayBuffer}
 
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
index 5ca8d271c9..9b7696fb3f 100644
--- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
index b67371d520..d8243e37c7 100644
--- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.experimental.{Analog, IO}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index b084845ef1..d7e5a8f266 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -1,6 +1,6 @@
 package chipyard.config
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // --------------
 // Chipyard abstract ("base") configuration
diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
index 0de224c964..4c1014038f 100644
--- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // BOOM Configs
diff --git a/generators/chipyard/src/main/scala/config/CVA6Configs.scala b/generators/chipyard/src/main/scala/config/CVA6Configs.scala
index 132a300950..c0d6adb1ef 100644
--- a/generators/chipyard/src/main/scala/config/CVA6Configs.scala
+++ b/generators/chipyard/src/main/scala/config/CVA6Configs.scala
@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // CVA6 Configs
diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
index 8e8c7fe929..206b086b46 100644
--- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // Heterogenous Configs
diff --git a/generators/chipyard/src/main/scala/config/IbexConfigs.scala b/generators/chipyard/src/main/scala/config/IbexConfigs.scala
index 63b7aa5dbf..6d1b6e4e6b 100644
--- a/generators/chipyard/src/main/scala/config/IbexConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/IbexConfigs.scala
@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // ---------------------
 // Ibex Configs
diff --git a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
index fcb4804dd8..8c5aa2e9da 100644
--- a/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ------------------------------
diff --git a/generators/chipyard/src/main/scala/config/NoCConfigs.scala b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
index bd36fe040b..0036e98823 100644
--- a/generators/chipyard/src/main/scala/config/NoCConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 import freechips.rocketchip.subsystem.{SBUS, MBUS}
 
diff --git a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
index 9d0c4132e5..10be8acac8 100644
--- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // A empty config with no cores. Useful for testing
 class NoCoresConfig extends Config(
diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
index d01bcd8dd4..3bb2390d82 100644
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ---------------------------------------------------------
diff --git a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
index 7487a50e8d..4077fcbd69 100644
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // ------------------------------
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index b6677cb1b3..f8b2060090 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // --------------
diff --git a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
index 3eb568ba30..43ad1de3bc 100644
--- a/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketSha3Configs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
 // --------------
diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
index 3679ed076a..24eb1f4d35 100644
--- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala
@@ -2,7 +2,7 @@ package chipyard
 
 import chisel3._
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 class Sodor1StageConfig extends Config(
   // Create a Sodor 1-stage core
diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
index b45245c05c..eb5a9e9d34 100644
--- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 
 // Configs which instantiate a Spike-simulated
 // tile that interacts with the Chipyard SoC
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index 4ab51994a8..605db4d30f 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.rocket.{DCacheParams}
 
 class AbstractTraceGenConfig extends Config(
diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
index c9956b7aaf..e10b3368dc 100644
--- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala
@@ -1,6 +1,6 @@
 package chipyard
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import constellation.channel._
 import constellation.routing._
 import constellation.topology._
diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
index 0c79f6dc0e..7000c81c26 100644
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -4,7 +4,7 @@ import scala.util.matching.Regex
 import chisel3._
 import chisel3.util.{log2Up}
 
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.diplomacy._
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
index ec9ff47c06..7ac7f5699e 100644
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -4,7 +4,7 @@ import scala.util.matching.Regex
 import chisel3._
 import chisel3.util.{log2Up}
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
 import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
 import freechips.rocketchip.stage.phases.TargetDirKey
diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
index 774b23c234..4680eeebf7 100644
--- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
@@ -2,7 +2,7 @@ package chipyard.config
 
 import chisel3._
 
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.diplomacy._
 
diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
index c41e2716e5..40f18d5dc7 100644
--- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
@@ -1,6 +1,6 @@
 package chipyard.config
 
-import freechips.rocketchip.config.{Config}
+import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.subsystem.{SystemBusKey, BankedL2Key, CoherenceManagerWrapper}
 import freechips.rocketchip.diplomacy.{DTSTimebase}
 
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index f19759cb46..56042c3d41 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -2,7 +2,7 @@ package chipyard.config
 
 import chisel3._
 
-import freechips.rocketchip.config.{Field, Parameters, Config}
+import org.chipsalliance.cde.config.{Field, Parameters, Config}
 import freechips.rocketchip.tile._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
diff --git a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
index 2e849c587d..c8b4f82830 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TracegenFragments.scala
@@ -1,6 +1,6 @@
 package chipyard.config
 
-import freechips.rocketchip.config.{Config, Field, Parameters}
+import org.chipsalliance.cde.config.{Config, Field, Parameters}
 import tracegen.{TraceGenSystem}
 import chipyard.{BuildSystem}
 import chipyard.clocking.{HasChipyardPRCI}
diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala
index fe55f28851..bf05ba9c9e 100644
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -5,7 +5,7 @@ import chisel3.util._
 import chisel3.experimental.{IntParam, BaseModule}
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.subsystem.BaseSubsystem
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
 import freechips.rocketchip.tilelink._
diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala
index 5051c37d4a..bb6ecd72a7 100644
--- a/generators/chipyard/src/main/scala/example/InitZero.scala
+++ b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -3,7 +3,7 @@ package chipyard.example
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
 import freechips.rocketchip.tilelink._
 
diff --git a/generators/chipyard/src/main/scala/example/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala
index cafc470f27..1cdddd3225 100644
--- a/generators/chipyard/src/main/scala/example/NodeTypes.scala
+++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala
@@ -1,6 +1,6 @@
 package chipyard.example
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 
diff --git a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
index cda91ffe68..e7a8b0b8ba 100644
--- a/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
+++ b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala
@@ -2,7 +2,7 @@
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink.TLRegisterNode
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index 3d8e1ae108..1a9114b9b4 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -3,7 +3,7 @@ package chipyard.example
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
diff --git a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
index b51e2223bb..9ad23a4c62 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/DspBlocks.scala
@@ -5,7 +5,7 @@ import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
 import freechips.rocketchip.amba.axi4stream._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper._
 import freechips.rocketchip.tilelink._
diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
index f45b318cd7..15dfb99246 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
 import freechips.rocketchip.amba.axi4stream._
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
index c6ffaf42c7..2846277cc9 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import dspblocks._
 import dsptools.numbers._
 import freechips.rocketchip.amba.axi4stream._
-import freechips.rocketchip.config.{Parameters, Field, Config}
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
index 03aa0b5638..2258228e5c 100644
--- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
+++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
@@ -6,7 +6,7 @@ package chipyard.stage.phases
 import scala.util.Try
 import scala.collection.mutable
 
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import chisel3.stage.phases.Elaborate
 import firrtl.AnnotationSeq
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
diff --git a/generators/chipyard/src/main/scala/unittest/TestHarness.scala b/generators/chipyard/src/main/scala/unittest/TestHarness.scala
index 8bb4bbd9fb..a5ca555137 100644
--- a/generators/chipyard/src/main/scala/unittest/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/unittest/TestHarness.scala
@@ -1,7 +1,7 @@
 package chipyard.unittest
 
 import chisel3._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 class TestHarness(implicit val p: Parameters) extends Module {
   val io = IO(new Bundle { val success = Output(Bool()) })
diff --git a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
index 40e991a263..d3281dc194 100644
--- a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
+++ b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala
@@ -1,6 +1,6 @@
 package chipyard.unittest
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts}
 
 class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite {
diff --git a/generators/constellation b/generators/constellation
index 4606ee19b7..e9f1c828ca 160000
--- a/generators/constellation
+++ b/generators/constellation
@@ -1 +1 @@
-Subproject commit 4606ee19b74d32d165b1708ef6f4ee98baa1c50d
+Subproject commit e9f1c828ca5adb4fa46a242cd1798391fc9e6f62
diff --git a/generators/cva6 b/generators/cva6
index 737fd83b82..0011494bb7 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 737fd83b820aea6d615f372a97766b1d390a18d5
+Subproject commit 0011494bb70d2327ab4d6b0258f5073f137927ee
diff --git a/generators/fft-generator b/generators/fft-generator
index a31bd038dd..be8ab768bd 160000
--- a/generators/fft-generator
+++ b/generators/fft-generator
@@ -1 +1 @@
-Subproject commit a31bd038ddf3c941634cb830608edb0bdd6442db
+Subproject commit be8ab768bd15824c69531df632478e4429078b94
diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala
index 4d64a8ad24..4d768da956 100644
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -6,9 +6,9 @@ import chisel3._
 import chisel3.experimental.annotate
 import chisel3.util.experimental.BoringUtils
 
-import freechips.rocketchip.config.{Field, Config, Parameters}
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebug}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{RocketTile}
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index bd35341b56..a62059e318 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -9,7 +9,7 @@ import chisel3.experimental.{IO}
 
 import freechips.rocketchip.prci._
 import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
-import freechips.rocketchip.config.{Field, Config, Parameters}
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
 import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
 
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 2ea848df54..7af98c57a7 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -4,7 +4,7 @@ import java.io.File
 
 import chisel3._
 import chisel3.util.{log2Up}
-import freechips.rocketchip.config.{Parameters, Config}
+import org.chipsalliance.cde.config.{Parameters, Config}
 import freechips.rocketchip.groundtest.TraceGenParams
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
diff --git a/generators/gemmini b/generators/gemmini
index 686cb15dad..11e15ab1c5 160000
--- a/generators/gemmini
+++ b/generators/gemmini
@@ -1 +1 @@
-Subproject commit 686cb15dad756887db62460968bc616392bc4341
+Subproject commit 11e15ab1c5d6dbc3afc4787350b93603062a2e43
diff --git a/generators/hwacha b/generators/hwacha
index e1be8e2a41..d01ca1e7f8 160000
--- a/generators/hwacha
+++ b/generators/hwacha
@@ -1 +1 @@
-Subproject commit e1be8e2a41c6bc2239aed4e23355cf34a224f380
+Subproject commit d01ca1e7f8a3ba3f419509273dfef00e41095f6a
diff --git a/generators/ibex b/generators/ibex
index 626127f229..916fb7a6ff 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 626127f229dd6dc926b7670eb4dd138f32a7940a
+Subproject commit 916fb7a6ff4a65f989279bcc082676a565beee0c
diff --git a/generators/icenet b/generators/icenet
index 90d52a6a84..ce1ec55c1f 160000
--- a/generators/icenet
+++ b/generators/icenet
@@ -1 +1 @@
-Subproject commit 90d52a6a8435c862e6435d04436f587c3b36c8c0
+Subproject commit ce1ec55c1fd9c4339e7c0eec3a82d86041fa5d20
diff --git a/generators/mempress b/generators/mempress
index b9eaedc061..295ae0854a 160000
--- a/generators/mempress
+++ b/generators/mempress
@@ -1 +1 @@
-Subproject commit b9eaedc061adbbe488f4c094f0ddd2177852e11a
+Subproject commit 295ae0854a429182e4a38b120c8771a4e898834e
diff --git a/generators/nvdla b/generators/nvdla
index 2b17011b26..7130a5c0f7 160000
--- a/generators/nvdla
+++ b/generators/nvdla
@@ -1 +1 @@
-Subproject commit 2b17011b266025704b958efeeca2363c0cdd446d
+Subproject commit 7130a5c0f7016cd177ec9cf908a18edd668660d1
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index d6ccc5de5c..c051956d3b 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit d6ccc5de5cf6f07be500a0d1351656bb0c50e4a3
+Subproject commit c051956d3be3269c4ed9fcbb6afe920a6f54fd32
diff --git a/generators/rocket-chip b/generators/rocket-chip
index f5ebf26b36..4fbd2f238d 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit f5ebf26b369922b2924d71e185c473c0385bf54e
+Subproject commit 4fbd2f238db36b2862319e94c2f96d63bd52c98b
diff --git a/generators/sha3 b/generators/sha3
index 8c5d244303..1fa5ef8ae5 160000
--- a/generators/sha3
+++ b/generators/sha3
@@ -1 +1 @@
-Subproject commit 8c5d244303694311c4e63e51915a492491a3f5c7
+Subproject commit 1fa5ef8ae5b67126d709193896e75dba50c5fd28
diff --git a/generators/sifive-blocks b/generators/sifive-blocks
index 4273925fdd..19d42938f2 160000
--- a/generators/sifive-blocks
+++ b/generators/sifive-blocks
@@ -1 +1 @@
-Subproject commit 4273925fdd5d8872d6b6a8dec6cee3330b9a68c7
+Subproject commit 19d42938f27ff480d778e379d0724d8373081377
diff --git a/generators/sifive-cache b/generators/sifive-cache
index 850e12154c..65f8bc26b2 160000
--- a/generators/sifive-cache
+++ b/generators/sifive-cache
@@ -1 +1 @@
-Subproject commit 850e12154c1de6baee9e40094d115e9b85d799b1
+Subproject commit 65f8bc26b2eca4e0167070d6954e7aea2efb26e7
diff --git a/generators/testchipip b/generators/testchipip
index dead693f8f..ee47d2ea20 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit dead693f8f317bfeeb4eb777c4d58c4427fbba31
+Subproject commit ee47d2ea205c7525b21333d3caf835fcd963fa42
diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala
index ac2477a1f9..5d4f02114a 100644
--- a/generators/tracegen/src/main/scala/Configs.scala
+++ b/generators/tracegen/src/main/scala/Configs.scala
@@ -2,7 +2,7 @@ package tracegen
 
 import chisel3._
 import chisel3.util.log2Ceil
-import freechips.rocketchip.config.{Config, Parameters}
+import org.chipsalliance.cde.config.{Config, Parameters}
 import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.BaseConfig
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index fceb0072fb..53d88c6d0d 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -1,9 +1,9 @@
 package tracegen
 
 import chisel3._
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
-import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
+import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple, NullIntSyncSource}
 import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
 import freechips.rocketchip.subsystem._
 import boom.lsu.BoomTraceGenTile
@@ -17,6 +17,7 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
     case t: GroundTestTile => t.statusNode.makeSink()
     case t: BoomTraceGenTile => t.statusNode.makeSink()
   }
+  val debugNode = NullIntSyncSource()
   override lazy val module = new TraceGenSystemModuleImp(this)
 }
 
diff --git a/sims/firesim b/sims/firesim
index 68e5113887..8c85960b93 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 68e5113887d36e87bb6202e7fd1e7e51e786a91b
+Subproject commit 8c85960b939a0090de30a31936981972874d979d
diff --git a/tools/api-config-chipsalliance b/tools/api-config-chipsalliance
deleted file mode 160000
index fd8df1105a..0000000000
--- a/tools/api-config-chipsalliance
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fd8df1105a92065425cd353b6855777e35bd79b4
diff --git a/tools/cde b/tools/cde
new file mode 160000
index 0000000000..384c06b8d4
--- /dev/null
+++ b/tools/cde
@@ -0,0 +1 @@
+Subproject commit 384c06b8d45c8184ca2f3fba2f8e78f79d2c1b51
diff --git a/tools/rocket-dsp-utils b/tools/rocket-dsp-utils
index 46d6ed7798..dcd9eb212a 160000
--- a/tools/rocket-dsp-utils
+++ b/tools/rocket-dsp-utils
@@ -1 +1 @@
-Subproject commit 46d6ed77981ef18789636426cc23f0bd7edc64d9
+Subproject commit dcd9eb212aefd8040cdf9c50adffbbf975422a1d