From af9af69a3f16a3053465d66fe8b387605a23bb4a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 12 Jul 2023 14:13:51 -0700 Subject: [PATCH] UPF Generation --- common.mk | 10 +++++-- docs/VLSI/Advanced-Usage.rst | 10 +++++-- .../src/main/scala/upf/ChipTopUPF.scala | 7 ++--- .../src/main/scala/upf/UPFAspect.scala | 1 - .../chipyard/src/main/scala/upf/UPFGen.scala | 5 ++-- .../src/main/scala/upf/UPFInputs.scala | 29 +++++++++++++++++-- vlsi/Makefile | 5 ---- 7 files changed, 48 insertions(+), 19 deletions(-) diff --git a/common.mk b/common.mk index 7970e68e1e..9e75208bf9 100644 --- a/common.mk +++ b/common.mk @@ -20,7 +20,8 @@ HELP_COMPILATION_VARIABLES += \ " ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_BASE_FIRRTL_OPTIONS = additional options to pass to the Scala FIRRTL compiler" \ -" MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" +" MFC_BASE_LOWERING_OPTIONS = override lowering options to pass to the MLIR FIRRTL compiler" \ +" ASPECTS = additional aspect flows that will be run based on inputted pointers (such as UPF gen)" EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS) EXTRA_SIM_CXXFLAGS ?= @@ -29,6 +30,11 @@ EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW) +ifneq ($(ASPECTS), ) + comma = , + ASPECT_ARGS = $(foreach aspect, $(subst $(comma), , $(ASPECTS)), --with-aspect $(aspect)) +endif + #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ " EXTRA_SIM_FLAGS = additional runtime simulation flags (passed within +permissive)" \ @@ -134,7 +140,7 @@ $(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) --name $(long_name) \ --top-module $(MODEL_PACKAGE).$(MODEL) \ --legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \ - $(UPF_ASPECT) \ + $(ASPECT_ARGS) \ $(EXTRA_CHISEL_OPTIONS)) | tee $(CHISEL_LOG_FILE)) define mfc_extra_anno_contents diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index 62b3c83286..00c3b1d30d 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -109,11 +109,13 @@ The simulation configuration (e.g. binaries) can be edited for your design. See UPF Generation Flow ------------------------------- -To generate UPF for any design, first modify the UPFInputs in generators/chipyard/src/main/scala/upf/UPFInputs.scala to fit your design power specifications. +This VLSI flow experimentally supports generating Chisel-based `UPF `__ files using `Chisel Aspects `__. -This involves filling in the upfInfo list with PowerDomainInput objects representing all the power domains you want in your design, along with specifying hierarchy and domain attributes. +To generate UPF for any design, first modify the ``UPFInputs`` object in ``generators/chipyard/src/main/scala/upf/UPFInputs.scala`` to fit your design power specifications. -The given example in UPFInputs corresponds to a dual-core Rocket config with 3 power domains (1 parent and 2 children). +This involves filling in the ``upfInfo`` list with ``PowerDomainInput`` objects representing all the power domains you want in your design, along with specifying hierarchy and domain attributes. + +The given example in ``UPFInputs`` corresponds to a dual-core Rocket config with 3 power domains (1 parent domain with all uncore modules and 2 children corresponding to the Rocket tiles). To run the flow: @@ -121,3 +123,5 @@ To run the flow: cd chipyard/vlsi make verilog ASPECTS=chipyard.upf.ChipTopUPFAspect + +The output UPF files will be dumped in ``vlsi/generated-src/upf``. diff --git a/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala b/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala index 8d4c6b25dd..f619629738 100644 --- a/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala +++ b/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala @@ -1,14 +1,13 @@ // See LICENSE for license details package chipyard.upf -import chipyard.TestHarness -import freechips.rocketchip.diplomacy.LazyModule - import scala.collection.mutable.ListBuffer - import scalax.collection.mutable.Graph import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._ +import chipyard.TestHarness +import freechips.rocketchip.diplomacy.LazyModule + object ChipTopUPF { def default: UPFFunc.UPFFunction = { diff --git a/generators/chipyard/src/main/scala/upf/UPFAspect.scala b/generators/chipyard/src/main/scala/upf/UPFAspect.scala index 7522adafac..e82d7fe599 100644 --- a/generators/chipyard/src/main/scala/upf/UPFAspect.scala +++ b/generators/chipyard/src/main/scala/upf/UPFAspect.scala @@ -5,7 +5,6 @@ import chisel3.aop.Aspect import firrtl.{AnnotationSeq} import chipyard.TestHarness import freechips.rocketchip.stage.phases.TargetDirKey - import freechips.rocketchip.diplomacy.LazyModule abstract class UPFAspect[T <: TestHarness](upf: UPFFunc.UPFFunction) extends Aspect[T] { diff --git a/generators/chipyard/src/main/scala/upf/UPFGen.scala b/generators/chipyard/src/main/scala/upf/UPFGen.scala index fafc42ac4f..5640ee136e 100644 --- a/generators/chipyard/src/main/scala/upf/UPFGen.scala +++ b/generators/chipyard/src/main/scala/upf/UPFGen.scala @@ -1,13 +1,14 @@ +// See LICENSE for license details package chipyard.upf -import freechips.rocketchip.diplomacy.LazyModule - import java.io.FileWriter import java.nio.file.{Paths, Files} import scala.collection.mutable.ListBuffer import scalax.collection.mutable.Graph import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._ +import freechips.rocketchip.diplomacy.LazyModule + case class PowerDomain (val name: String, val modules: ListBuffer[LazyModule], val isTop: Boolean, val isGated: Boolean, val highVoltage: Double, val lowVoltage: Double) { diff --git a/generators/chipyard/src/main/scala/upf/UPFInputs.scala b/generators/chipyard/src/main/scala/upf/UPFInputs.scala index 31a04451a5..b4137c3342 100644 --- a/generators/chipyard/src/main/scala/upf/UPFInputs.scala +++ b/generators/chipyard/src/main/scala/upf/UPFInputs.scala @@ -1,8 +1,14 @@ +// See LICENSE for license details package chipyard.upf - +// outputs are dumped in vlsi/generated-src/upf object UPFInputs { + /** + * UPF info + * each PowerDomainInput represents a desired power domain + * each input will contain all the necessary info to describe a power domain in UPF, including hierarchy + */ val upfInfo = List( PowerDomainInput(name="PD_top", isTop=true, moduleList=List("DigitalTop"), parentPD="", childrenPDs=List("PD_RocketTile1", "PD_RocketTile2"), @@ -15,7 +21,14 @@ object UPFInputs { isGated=false, highVoltage=3.9, lowVoltage=3.2), ) - // PST info + + /** + * PST info + * experimental Power State Table input, used to gate power domains based on specified power states + * place names of all power domains to be gated in the domains list + * states will map different keywords (arbitrary strings) to a binary on or off (1 or 0) to form a power state + * order of domains in list corresponds to order of values in each states mapping + */ val domains = List("PD_top", "PD_RocketTile1", "PD_RocketTile2") val states = Map( "ON" -> "1, 1, 1", @@ -24,6 +37,18 @@ object UPFInputs { } +/** + * Representation of a power domain used to generate UPF. + * + * @param name name of the power domain. + * @param isTop if the power domain is the top level or not. + * @param moduleList refers to all the Verilog modules belonging to this power domain. Can be module name, instance name, or full path name. + * @param parentPD the name of the parent power domain to this one. + * @param childrenPDs names of all the children power domains to this one. + * @param isGated if the power domain is gated or not. + * @param highVoltage voltage value of the high voltage rail (currently, gated nets have access to high voltage since they are optimized to save power). + * @param lowVoltage voltage value of the low voltage rail (currently, non-gated nets default to the low voltage rail). + */ case class PowerDomainInput(name: String, isTop: Boolean, moduleList: List[String], parentPD: String, childrenPDs: List[String], isGated: Boolean, highVoltage: Double, lowVoltage: Double) diff --git a/vlsi/Makefile b/vlsi/Makefile index c394bc818e..b3901fe65d 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -51,11 +51,6 @@ else OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(TOP) endif -ifneq ($(ASPECTS), ) - comma = , - UPF_ASPECT = $(foreach aspect, $(subst $(comma), , $(ASPECTS)), --with-aspect $(aspect)) -endif - ######################################################################################### # general rules #########################################################################################