diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala
index e3c79f3a7e..281c5917ba 100644
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -104,7 +104,7 @@ object AddIOCells {
 
   /**
    * Add IO cells to a SiFive UART devices and name the IO ports.
-   * @param gpios A Seq of UART port bundles
+   * @param uartPins A Seq of UART port bundles
    * @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references)
    */
   def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = {
@@ -117,7 +117,7 @@ object AddIOCells {
 
   /**
    * Add IO cells to a debug module and name the IO ports.
-   * @param gpios A PSDIO bundle
+   * @param psd A PSDIO bundle
    * @param resetctrlOpt An optional ResetCtrlIO bundle
    * @param debugOpt An optional DebugIO bundle
    * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references)
@@ -312,4 +312,4 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({
   }
 })
 
-}
+} /* end package object */