From f693972e1249aaac5d882d6e55e4eb5a81a99bd0 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:56:01 +0000 Subject: [PATCH 01/14] Start RC bump Bump to pre-merge chipsalliance/rocket-chip#2764 to get it going while picking up the chisel/firrtl bugfixes in 3/1.4.1+ --- build.sbt | 4 ++-- generators/rocket-chip | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/build.sbt b/build.sbt index e80b2a5e3b..c3aa9515c3 100644 --- a/build.sbt +++ b/build.sbt @@ -72,7 +72,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // -- Rocket Chip -- // This needs to stay in sync with the chisel3 and firrtl git submodules -val chiselVersion = "3.4.0" +val chiselVersion = "3.4.1" lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel") lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) @@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies) // keeping scalaVersion in sync with chisel3 to the minor version lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full -val firrtlVersion = "1.4.+" +val firrtlVersion = "1.4.1" lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl") lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4") diff --git a/generators/rocket-chip b/generators/rocket-chip index 577994e38e..a7b016e46e 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e +Subproject commit a7b016e46e22e4fdc013357051e30511f80df082 diff --git a/tools/chisel3 b/tools/chisel3 index d379dca441..58d38f9620 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9 +Subproject commit 58d38f9620e7e91e4668266686484073c0ba7d2e diff --git a/tools/firrtl b/tools/firrtl index 05d047a9be..7756f8f963 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9 +Subproject commit 7756f8f9634b68a1375d2c2ca13abc5742234201 From 95420baccfd1ce26354d6af70a09c7f3b50d448b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 17:57:05 +0000 Subject: [PATCH 02/14] Bump boom for riscv-boom/riscv-boom#508 non-master pre-merge bump --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 4bb6464ff3..1899670ad9 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28 +Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 From c6dfa1d8c5de36bedfc6e3119ae2394fae2ded86 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 18:03:51 +0000 Subject: [PATCH 03/14] Bump testchipip for ucb-bar/testchipip#111 --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 6fbb1b77b9..ca67a843bd 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b +Subproject commit ca67a843bd8f568e205981380c11d321d1bad677 From 5ff5b4e8b7601b461e5d222856ea1a2aaabdab0b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:05:29 +0000 Subject: [PATCH 04/14] Bump sifive-cache for sifive/block-inclusivecache-sifive#18 --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index d4db623ff5..b1160adce0 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0 +Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 From f7a372153acf34416f9c6f9c6a10afb95675ab43 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:00 +0000 Subject: [PATCH 05/14] Bump hwacha for ucb-bar/hwacha#24 --- generators/hwacha | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/hwacha b/generators/hwacha index a354150cb5..62c01f5a88 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588 +Subproject commit 62c01f5a8858aa1b827f0f9372a4392d7b596fca From 022dbf976ff6f389b40a9e058a2406945b88670e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:52:30 +0000 Subject: [PATCH 06/14] Bump boom along in the same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 1899670ad9..ad27160f2a 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1899670ad92e402e7a5d21c13bdf025f546bb779 +Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 From 2ce5f6a40723200761506be0c23042597d1a0045 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 20:54:31 +0000 Subject: [PATCH 07/14] Bump cva6 for ucb-bar/cva6-wrapper#11 --- generators/cva6 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/cva6 b/generators/cva6 index d40a8f5c84..139741a584 160000 --- a/generators/cva6 +++ b/generators/cva6 @@ -1 +1 @@ -Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6 +Subproject commit 139741a584d7e3c0446db592b5d99529bd6cf9fa From a2ce14f8d3528cb2e86c990a35d82655c3f4cc9e Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 21:03:12 +0000 Subject: [PATCH 08/14] Bump sodor for ucb-bar/riscv-sodor#60 --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index cca8a7aa57..8fc516409f 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc +Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485 From cb558b59529a328164e7f96bbcba21629df4fc11 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:20:31 +0000 Subject: [PATCH 09/14] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index ad27160f2a..e250c70fad 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit ad27160f2a6f17bb91c70d570299a066b17255a7 +Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e From a7e6de835ad5c641c516dc310269a0b921e24452 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:22:03 +0000 Subject: [PATCH 10/14] rm *XTypeKey. upstreamed to RC --- .../chipyard/src/main/scala/CustomBusTopologies.scala | 8 -------- 1 file changed, 8 deletions(-) diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala index ee694d2200..0a5c1c30e5 100644 --- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala +++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala @@ -13,14 +13,6 @@ import freechips.rocketchip.subsystem._ // For subsystem/BusTopology.scala -/** - * Keys that serve as a means to define crossing types from a Parameters instance - */ -case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing) -case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) -case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing()) - // Biancolin: This, modified from Henry's email /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */ case class CoherentMulticlockBusTopologyParams( From 72d084da8f8244e29420dfff0a95494d06489562 Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Fri, 18 Dec 2020 23:24:19 +0000 Subject: [PATCH 11/14] update parameter classes for RC additions --- generators/chipyard/src/main/scala/example/TutorialTile.scala | 4 ++++ generators/tracegen/src/main/scala/Tile.scala | 2 ++ 2 files changed, 6 insertions(+) diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala index 23b05f762f..fad51c01fb 100644 --- a/generators/chipyard/src/main/scala/example/TutorialTile.scala +++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala @@ -15,6 +15,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.amba.axi4._ +import freechips.rocketchip.prci.ClockSinkParameters // Example parameter class copied from CVA6, not included in documentation but for compile check only // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure @@ -39,6 +40,7 @@ case class MyCoreParams( val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket val nLocalInterrupts: Int = 0 + val useNMI: Boolean = false val nPMPs: Int = 0 // TODO: Check val pmpGranularity: Int = 4 // copied from Rocket val nBreakpoints: Int = 0 // TODO: Check @@ -51,6 +53,7 @@ case class MyCoreParams( val misaWritable: Boolean = false val haveCFlush: Boolean = false val nL2TLBEntries: Int = 512 // copied from Rocket + val nL2TLBWays: Int = 1 val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket val mtvecWritable: Boolean = true // copied from Rocket val instBits: Int = if (useCompressed) 16 else 32 @@ -83,6 +86,7 @@ case class MyTileParams( val boundaryBuffers: Boolean = false val dcache: Option[DCacheParams] = Some(DCacheParams()) val icache: Option[ICacheParams] = Some(ICacheParams()) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = { new MyTile(this, crossing, lookup) } diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 5ff9af569e..712cffc176 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._ import freechips.rocketchip.subsystem._ import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} +import freechips.rocketchip.prci.ClockSinkParameters class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) @@ -190,6 +191,7 @@ case class BoomTraceGenParams( val blockerCtrlAddr = None val name = None val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId) + val clockSinkParams: ClockSinkParameters = ClockSinkParameters() } class BoomTraceGenTile private( From 29ab6301e0786def4608f7ad3d6456ae36b93c8f Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:15:49 +0000 Subject: [PATCH 12/14] bump sifive-cache for merged sifive/block-inclusivecache-sifive#15 my previous bump duplicated an earlier PR --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index b1160adce0..e3a3000cc1 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit b1160adce09a73df6f5bd40f1e111ab3cefd7300 +Subproject commit e3a3000cc1fd4cdf3a4e638e4d081b8aae94ebf0 From e22350092bdcb11c1f303cf7205eb6caec77efff Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Mon, 21 Dec 2020 18:27:47 +0000 Subject: [PATCH 13/14] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index e250c70fad..75399e3cd9 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit e250c70fade22134fe9dc3347cfb5f608e1ee80e +Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 From 0f47d80edb350ec41d96586d57b886f50882af2b Mon Sep 17 00:00:00 2001 From: Tim Snyder Date: Wed, 23 Dec 2020 15:00:57 +0000 Subject: [PATCH 14/14] bump boom along same PR --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 75399e3cd9..e1a70afed7 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 75399e3cd94e4ad64f007f9d8ba0f39e6ff7ec16 +Subproject commit e1a70afed7de77f6ba9f6e501de71f7f41afc47c