diff --git a/build.sbt b/build.sbt
index e80b2a5e3b..c3aa9515c3 100644
--- a/build.sbt
+++ b/build.sbt
@@ -72,7 +72,7 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
 // -- Rocket Chip --
 
 // This needs to stay in sync with the chisel3 and firrtl git submodules
-val chiselVersion = "3.4.0"
+val chiselVersion = "3.4.1"
 lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel")
 lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion
 lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies)
@@ -81,7 +81,7 @@ lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies)
 //   keeping scalaVersion in sync with chisel3 to the minor version
 lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full
 
-val firrtlVersion = "1.4.+"
+val firrtlVersion = "1.4.1"
 lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl")
 lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion
 val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4")
diff --git a/generators/boom b/generators/boom
index 4bb6464ff3..e1a70afed7 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 4bb6464ff392cf75e9caf8c06bc252b4f1ac8a28
+Subproject commit e1a70afed7de77f6ba9f6e501de71f7f41afc47c
diff --git a/generators/chipyard/src/main/scala/CustomBusTopologies.scala b/generators/chipyard/src/main/scala/CustomBusTopologies.scala
index ee694d2200..0a5c1c30e5 100644
--- a/generators/chipyard/src/main/scala/CustomBusTopologies.scala
+++ b/generators/chipyard/src/main/scala/CustomBusTopologies.scala
@@ -13,14 +13,6 @@ import freechips.rocketchip.subsystem._
 
 // For subsystem/BusTopology.scala
 
-/**
-  * Keys that serve as a means to define crossing types from a Parameters instance
-  */
-case object SbusToMbusXTypeKey extends Field[ClockCrossingType](NoCrossing)
-case object SbusToCbusXTypeKey extends Field[ClockCrossingType](NoCrossing)
-case object CbusToPbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing())
-case object FbusToSbusXTypeKey extends Field[ClockCrossingType](SynchronousCrossing())
-
 // Biancolin: This, modified from Henry's email
 /** Parameterization of a topology containing a banked coherence manager and a bus for attaching memory devices. */
 case class CoherentMulticlockBusTopologyParams(
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index 23b05f762f..fad51c01fb 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -15,6 +15,7 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.prci.ClockSinkParameters
 
 // Example parameter class copied from CVA6, not included in documentation but for compile check only
 // If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
@@ -39,6 +40,7 @@ case class MyCoreParams(
   val mulDiv: Option[MulDivParams] = Some(MulDivParams()) // copied from Rocket
   val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
   val nLocalInterrupts: Int = 0
+  val useNMI: Boolean = false
   val nPMPs: Int = 0 // TODO: Check
   val pmpGranularity: Int = 4 // copied from Rocket
   val nBreakpoints: Int = 0 // TODO: Check
@@ -51,6 +53,7 @@ case class MyCoreParams(
   val misaWritable: Boolean = false
   val haveCFlush: Boolean = false
   val nL2TLBEntries: Int = 512 // copied from Rocket
+  val nL2TLBWays: Int = 1
   val mtvecInit: Option[BigInt] = Some(BigInt(0)) // copied from Rocket
   val mtvecWritable: Boolean = true // copied from Rocket
   val instBits: Int = if (useCompressed) 16 else 32
@@ -83,6 +86,7 @@ case class MyTileParams(
   val boundaryBuffers: Boolean = false
   val dcache: Option[DCacheParams] = Some(DCacheParams())
   val icache: Option[ICacheParams] = Some(ICacheParams())
+  val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
   def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
     new MyTile(this, crossing, lookup)
   }
diff --git a/generators/cva6 b/generators/cva6
index d40a8f5c84..139741a584 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit d40a8f5c844f4169c8e74d3fa05f36286f9e4bb6
+Subproject commit 139741a584d7e3c0446db592b5d99529bd6cf9fa
diff --git a/generators/hwacha b/generators/hwacha
index a354150cb5..62c01f5a88 160000
--- a/generators/hwacha
+++ b/generators/hwacha
@@ -1 +1 @@
-Subproject commit a354150cb50fdc0c0ddd356e37850c8e36e02588
+Subproject commit 62c01f5a8858aa1b827f0f9372a4392d7b596fca
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index cca8a7aa57..8fc516409f 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit cca8a7aa5743b9f9bf25779b87b464187c5c3fbc
+Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 577994e38e..a7b016e46e 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 577994e38e3115cafa3a232b0fc60584aacb996e
+Subproject commit a7b016e46e22e4fdc013357051e30511f80df082
diff --git a/generators/sifive-cache b/generators/sifive-cache
index d4db623ff5..e3a3000cc1 160000
--- a/generators/sifive-cache
+++ b/generators/sifive-cache
@@ -1 +1 @@
-Subproject commit d4db623ff534f775ffc49f59c4a9ef24d5d759d0
+Subproject commit e3a3000cc1fd4cdf3a4e638e4d081b8aae94ebf0
diff --git a/generators/testchipip b/generators/testchipip
index 6fbb1b77b9..ca67a843bd 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 6fbb1b77b90da5e88bfde8e504595a332cca0e0b
+Subproject commit ca67a843bd8f568e205981380c11d321d1bad677
diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala
index 5ff9af569e..712cffc176 100644
--- a/generators/tracegen/src/main/scala/Tile.scala
+++ b/generators/tracegen/src/main/scala/Tile.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.interrupts._
 import freechips.rocketchip.subsystem._
 import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
 import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
+import freechips.rocketchip.prci.ClockSinkParameters
 
 
 class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
@@ -190,6 +191,7 @@ case class BoomTraceGenParams(
   val blockerCtrlAddr = None
   val name = None
   val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId)
+  val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
 }
 
 class BoomTraceGenTile private(
diff --git a/tools/chisel3 b/tools/chisel3
index d379dca441..58d38f9620 160000
--- a/tools/chisel3
+++ b/tools/chisel3
@@ -1 +1 @@
-Subproject commit d379dca4413d4cb08b02165a493faff01f3ddbb9
+Subproject commit 58d38f9620e7e91e4668266686484073c0ba7d2e
diff --git a/tools/firrtl b/tools/firrtl
index 05d047a9be..7756f8f963 160000
--- a/tools/firrtl
+++ b/tools/firrtl
@@ -1 +1 @@
-Subproject commit 05d047a9befda3877f5d8a0a9e1076ffd520ddf9
+Subproject commit 7756f8f9634b68a1375d2c2ca13abc5742234201